March 2021 - U-Boot

[PATCH] rtc: add support for rv3028 rtc
by Heiko Schocher 10 Mar '21

10 Mar '21

add support for rtc3028 rtc from microcrystal. based on linux dirver: commit a38fd8748464: ("Linux 5.12-rc2") Signed-off-by: Heiko Schocher <hs(a)denx.de> --- driver is based on code in linux, but with already corrected weekday usage. linux codes the weekday bitwise, while the weekday register has only 3 valid bits as the app manual [1] says: This register holds the current day of the week. Each value represents one weekday that is assigned by the user. Values will range from 0 to 6 The weekday counter is simply a 3-bit counter which counts up to 6 and then resets to 0. [1] https://www.microcrystal.com/fileadmin/Media/Products/RTC/App.Manual/RV-302… This is not a big problem, as userspace never use weekday. Nevertheless, I will also send an update for the linux driver. Also the nvram can be used for bootcounter purposes. Tested this driver on "PHYTEC phyBOARD-Pollux i.MX8MP" board. azure build: https://dev.azure.com/hs0298/hs/_build/results?buildId=63&view=results drivers/rtc/Kconfig | 6 ++ drivers/rtc/Makefile | 1 + drivers/rtc/rv3028.c | 215 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 222 insertions(+) create mode 100644 drivers/rtc/rv3028.c diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index aa6d90158c..e451308b40 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -95,6 +95,12 @@ config RTC_PCF8563 If you say yes here you get support for the Philips PCF8563 RTC and compatible chips. +config RTC_RV3028 + bool "Enable RV3028 driver" + depends on DM_RTC + help + The MicroCrystal RV3028 is a I2C Real Time Clock (RTC) + config RTC_RV3029 bool "Enable RV3029 driver" depends on DM_RTC diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 6a45a9c874..e7acd76266 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -46,6 +46,7 @@ obj-$(CONFIG_RTC_PCF2127) += pcf2127.o obj-$(CONFIG_RTC_PL031) += pl031.o obj-$(CONFIG_RTC_PT7C4338) += pt7c4338.o obj-$(CONFIG_RTC_RS5C372A) += rs5c372.o +obj-$(CONFIG_RTC_RV3028) += rv3028.o obj-$(CONFIG_RTC_RV3029) += rv3029.o obj-$(CONFIG_RTC_RV8803) += rv8803.o obj-$(CONFIG_RTC_RX8025) += rx8025.o diff --git a/drivers/rtc/rv3028.c b/drivers/rtc/rv3028.c new file mode 100644 index 0000000000..8d8336c5f1 --- /dev/null +++ b/drivers/rtc/rv3028.c @@ -0,0 +1,215 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * RTC driver for the Micro Crystal RV3028 + * + * based on linux driver from + * Copyright (C) 2019 Micro Crystal SA + * + * Alexandre Belloni <alexandre.belloni(a)bootlin.com> + * + */ + +#include <common.h> +#include <command.h> +#include <dm.h> +#include <eeprom.h> +#include <i2c.h> +#include <log.h> +#include <rtc.h> +#include <dm/device_compat.h> +#include <linux/bitops.h> +#include <linux/delay.h> + +#define RV3028_SEC 0x00 +#define RV3028_MIN 0x01 +#define RV3028_HOUR 0x02 +#define RV3028_WDAY 0x03 +#define RV3028_DAY 0x04 +#define RV3028_MONTH 0x05 +#define RV3028_YEAR 0x06 +#define RV3028_ALARM_MIN 0x07 +#define RV3028_ALARM_HOUR 0x08 +#define RV3028_ALARM_DAY 0x09 +#define RV3028_STATUS 0x0E +#define RV3028_CTRL1 0x0F +#define RV3028_CTRL2 0x10 +#define RV3028_EVT_CTRL 0x13 +#define RV3028_TS_COUNT 0x14 +#define RV3028_TS_SEC 0x15 +#define RV3028_RAM1 0x1F +#define RV3028_EEPROM_ADDR 0x25 +#define RV3028_EEPROM_DATA 0x26 +#define RV3028_EEPROM_CMD 0x27 +#define RV3028_CLKOUT 0x35 +#define RV3028_OFFSET 0x36 +#define RV3028_BACKUP 0x37 + +#define RV3028_STATUS_PORF BIT(0) +#define RV3028_STATUS_EVF BIT(1) +#define RV3028_STATUS_AF BIT(2) +#define RV3028_STATUS_TF BIT(3) +#define RV3028_STATUS_UF BIT(4) +#define RV3028_STATUS_BSF BIT(5) +#define RV3028_STATUS_CLKF BIT(6) +#define RV3028_STATUS_EEBUSY BIT(7) + +#define RV3028_CLKOUT_FD_MASK GENMASK(2, 0) +#define RV3028_CLKOUT_PORIE BIT(3) +#define RV3028_CLKOUT_CLKSY BIT(6) +#define RV3028_CLKOUT_CLKOE BIT(7) + +#define RV3028_CTRL1_EERD BIT(3) +#define RV3028_CTRL1_WADA BIT(5) + +#define RV3028_CTRL2_RESET BIT(0) +#define RV3028_CTRL2_12_24 BIT(1) +#define RV3028_CTRL2_EIE BIT(2) +#define RV3028_CTRL2_AIE BIT(3) +#define RV3028_CTRL2_TIE BIT(4) +#define RV3028_CTRL2_UIE BIT(5) +#define RV3028_CTRL2_TSE BIT(7) + +#define RV3028_EVT_CTRL_TSR BIT(2) + +#define RV3028_EEPROM_CMD_UPDATE 0x11 +#define RV3028_EEPROM_CMD_WRITE 0x21 +#define RV3028_EEPROM_CMD_READ 0x22 + +#define RV3028_EEBUSY_POLL 10000 +#define RV3028_EEBUSY_TIMEOUT 100000 + +#define RV3028_BACKUP_TCE BIT(5) +#define RV3028_BACKUP_TCR_MASK GENMASK(1, 0) + +#define OFFSET_STEP_PPT 953674 + +#define RTC_RV3028_LEN 7 + +static int rv3028_rtc_get(struct udevice *dev, struct rtc_time *tm) +{ + u8 regs[RTC_RV3028_LEN]; + u8 status; + int ret; + + ret = dm_i2c_read(dev, RV3028_STATUS, &status, 1); + if (ret < 0) { + printf("%s: error reading RTC status: %x\n", __func__, ret); + return -EIO; + } + + if (status & RV3028_STATUS_PORF) { + printf("Voltage low, data is invalid.\n"); + return -EINVAL; + } + + ret = dm_i2c_read(dev, RV3028_SEC, regs, sizeof(regs)); + if (ret < 0) { + printf("%s: error reading RTC: %x\n", __func__, ret); + return -EIO; + } + + tm->tm_sec = bcd2bin(regs[RV3028_SEC] & 0x7f); + tm->tm_min = bcd2bin(regs[RV3028_MIN] & 0x7f); + tm->tm_hour = bcd2bin(regs[RV3028_HOUR] & 0x3f); + tm->tm_wday = regs[RV3028_WDAY] & 0x7; + tm->tm_mday = bcd2bin(regs[RV3028_DAY] & 0x3f); + tm->tm_mon = bcd2bin(regs[RV3028_MONTH] & 0x1f); + tm->tm_year = bcd2bin(regs[RV3028_YEAR]) + 2000; + tm->tm_yday = 0; + tm->tm_isdst = 0; + + debug("%s: %4d-%02d-%02d (wday=%d) %2d:%02d:%02d\n", + __func__, tm->tm_year, tm->tm_mon, tm->tm_mday, + tm->tm_wday, tm->tm_hour, tm->tm_min, tm->tm_sec); + + return 0; +} + +static int rv3028_rtc_set(struct udevice *dev, const struct rtc_time *tm) +{ + u8 regs[RTC_RV3028_LEN]; + u8 status; + int ret; + + debug("%s: %4d-%02d-%02d (wday=%d( %2d:%02d:%02d\n", + __func__, tm->tm_year, tm->tm_mon, tm->tm_mday, + tm->tm_wday, tm->tm_hour, tm->tm_min, tm->tm_sec); + + if (tm->tm_year < 2000) { + printf("%s: year %d (before 2000) not supported\n", + __func__, tm->tm_year); + return -EINVAL; + } + + regs[RV3028_SEC] = bin2bcd(tm->tm_sec); + regs[RV3028_MIN] = bin2bcd(tm->tm_min); + regs[RV3028_HOUR] = bin2bcd(tm->tm_hour); + regs[RV3028_WDAY] = tm->tm_wday; + regs[RV3028_DAY] = bin2bcd(tm->tm_mday); + regs[RV3028_MONTH] = bin2bcd(tm->tm_mon); + regs[RV3028_YEAR] = bin2bcd(tm->tm_year - 2000); + + ret = dm_i2c_write(dev, RV3028_SEC, regs, sizeof(regs)); + if (ret) { + printf("%s: set rtc error: %d\n", __func__, ret); + return ret; + } + + ret = dm_i2c_read(dev, RV3028_STATUS, &status, 1); + if (ret < 0) { + printf("%s: error reading RTC status: %x\n", __func__, ret); + return -EIO; + } + status |= RV3028_STATUS_PORF; + return dm_i2c_write(dev, RV3028_STATUS, &status, 1); +} + +static int rv3028_rtc_reset(struct udevice *dev) +{ + return 0; +} + +static int rv3028_rtc_read8(struct udevice *dev, unsigned int reg) +{ + u8 data; + int ret; + + ret = dm_i2c_read(dev, reg, &data, sizeof(data)); + return ret < 0 ? ret : data; +} + +static int rv3028_rtc_write8(struct udevice *dev, unsigned int reg, int val) +{ + u8 data = val; + + return dm_i2c_write(dev, reg, &data, 1); +} + +static int rv3028_probe(struct udevice *dev) +{ + i2c_set_chip_flags(dev, DM_I2C_CHIP_RD_ADDRESS | + DM_I2C_CHIP_WR_ADDRESS); + + return 0; +} + +static const struct rtc_ops rv3028_rtc_ops = { + .get = rv3028_rtc_get, + .set = rv3028_rtc_set, + .read8 = rv3028_rtc_read8, + .write8 = rv3028_rtc_write8, + .reset = rv3028_rtc_reset, +}; + +static const struct udevice_id rv3028_rtc_ids[] = { + { .compatible = "microcrystal,rv3028" }, + { } +}; + +U_BOOT_DRIVER(rtc_rv3028) = { + .name = "rtc-rv3028", + .id = UCLASS_RTC, + .probe = rv3028_probe, + .of_match = rv3028_rtc_ids, + .ops = &rv3028_rtc_ops, +}; -- 2.29.2

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Please pull u-boot-x86
by Bin Meng 10 Mar '21

10 Mar '21

Hi Tom, This PR includes the following x86 changes for v2021.04: - Various minor fixes for x86 Azure results: PASS https://dev.azure.com/bmeng/GitHub/_build/results?buildId=337&view=results The following changes since commit 472c5484bca41a477f8b86a263e559f6e992c7f8: Merge tag 'u-boot-amlogic-20210308' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic (2021-03-08 07:41:50 -0500) are available in the git repository at: https://source.denx.de/u-boot/custodians/u-boot-x86 for you to fetch changes up to 736ecc643de4b329e2edcb3207edd58bf7ed0d9d: x86: Select advanced Intel code only if allowed (2021-03-09 09:42:12 +0800) ---------------------------------------------------------------- Heinrich Schuchardt (1): x86: sizeof-array-div error in lpc_common_early_init Simon Glass (3): x86: Fix member check in intel_gnvs x86: Move INTEL_ACPIGEN to arch/x86 x86: Select advanced Intel code only if allowed arch/x86/Kconfig | 24 ++++++++++++++++++++++++ arch/x86/cpu/apollolake/Kconfig | 1 + arch/x86/cpu/intel_common/lpc.c | 2 +- arch/x86/include/asm/intel_gnvs.h | 4 ++++ drivers/core/Kconfig | 9 --------- 5 files changed, 30 insertions(+), 10 deletions(-) Regards, Bin

2 1

[PATCH 1/2] include: configs: am65x_evm: Optimize size of SPL BSS
by Lokesh Vutla 09 Mar '21

09 Mar '21

Current BSS allocation of SPL is as below: $ size spl/u-boot-spl text data bss dec hex filename 132369 7852 1496 141717 22995 spl/u-boot-spl But 20KB is allocated currently for BSS. Reduce it to 3KB and save some space for stack. Signed-off-by: Lokesh Vutla <lokeshvutla(a)ti.com> --- include/configs/am65x_evm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h index b39a5b4ca4..76d73086fb 100644 --- a/include/configs/am65x_evm.h +++ b/include/configs/am65x_evm.h @@ -30,7 +30,7 @@ * our memory footprint. The less we use for BSS the more we have available * for everything else. */ -#define CONFIG_SPL_BSS_MAX_SIZE 0x5000 +#define CONFIG_SPL_BSS_MAX_SIZE 0xc00 /* * Link BSS to be within SPL in a dedicated region located near the top of * the MCU SRAM, this way making it available also before relocation. Note -- 2.30.0

1 1

[PATCH 0/9] stm32: Add Engicam STM32MP1 SoM
by Jagan Teki 09 Mar '21

09 Mar '21

Patch series for Engicam i.Core and MicroGEA SoM and it's associated carrier board dts(i) support. patch 1: for i.Core STM32MP1 SoM dtsi patch 2: i.Core DDR3 config patch 3: for SPL_SPI_LOAD build fix patch 4 - 5: i.Core STM32MP1 with EDIMM2.2 and C.Touch 2.0 carriers. patch 6: for MicroGEA STM32MP1 Micro SoM dtsi patch 7: MicroGEA DDR3 config patch 8 - 9: MicroGEA STM32MP1 with MicroDev 2.0 and 7" OF carriers. Note: dts(i) patches are Linux Mailing list. Any inputs? Jagan. Jagan Teki (9): ARM: dts: stm32: Add Engicam i.Core STM32MP1 SoM ARM: dts: stm32: Add Engicam i.Core STM32MP1 1X4Gb DDR3 ARM: stm32: Imply SPL_SPI_LOAD board: stm32: Add Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit board: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 Micro SoM ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 1X4Gb DDR3 board: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 board board: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 7" OF arch/arm/dts/Makefile | 4 + .../stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi | 119 +++++++++++ ...m32mp15-ddr3-microgea-1x4Gb-1066-binG.dtsi | 121 +++++++++++ ...2mp157a-icore-stm32mp1-ctouch2-u-boot.dtsi | 51 +++++ .../stm32mp157a-icore-stm32mp1-ctouch2.dts | 47 +++++ ...mp157a-icore-stm32mp1-edimm2.2-u-boot.dtsi | 51 +++++ .../stm32mp157a-icore-stm32mp1-edimm2.2.dts | 47 +++++ .../stm32mp157a-icore-stm32mp1-u-boot.dtsi | 146 +++++++++++++ arch/arm/dts/stm32mp157a-icore-stm32mp1.dtsi | 196 ++++++++++++++++++ ...rogea-stm32mp1-microdev2.0-of7-u-boot.dtsi | 51 +++++ ...157a-microgea-stm32mp1-microdev2.0-of7.dts | 154 ++++++++++++++ ...-microgea-stm32mp1-microdev2.0-u-boot.dtsi | 51 +++++ ...32mp157a-microgea-stm32mp1-microdev2.0.dts | 55 +++++ .../stm32mp157a-microgea-stm32mp1-u-boot.dtsi | 118 +++++++++++ .../dts/stm32mp157a-microgea-stm32mp1.dtsi | 148 +++++++++++++ arch/arm/mach-stm32mp/Kconfig | 54 ++++- board/engicam/stm32mp1/Kconfig | 12 ++ board/engicam/stm32mp1/MAINTAINERS | 24 +++ board/engicam/stm32mp1/Makefile | 10 + board/engicam/stm32mp1/spl.c | 48 +++++ board/engicam/stm32mp1/stm32mp1.c | 131 ++++++++++++ ...stm32mp15-icore-stm32mp1-ctouch2_defconfig | 80 +++++++ ...tm32mp15-icore-stm32mp1-edimm2.2_defconfig | 80 +++++++ ...-microgea-stm32mp1-microdev2-of7_defconfig | 80 +++++++ ...mp15-microgea-stm32mp1-microdev2_defconfig | 80 +++++++ 25 files changed, 1957 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi create mode 100644 arch/arm/dts/stm32mp15-ddr3-microgea-1x4Gb-1066-binG.dtsi create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1.dtsi create mode 100644 arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts create mode 100644 arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts create mode 100644 arch/arm/dts/stm32mp157a-microgea-stm32mp1-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp157a-microgea-stm32mp1.dtsi create mode 100644 board/engicam/stm32mp1/Kconfig create mode 100644 board/engicam/stm32mp1/MAINTAINERS create mode 100644 board/engicam/stm32mp1/Makefile create mode 100644 board/engicam/stm32mp1/spl.c create mode 100644 board/engicam/stm32mp1/stm32mp1.c create mode 100644 configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig create mode 100644 configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig create mode 100644 configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig create mode 100644 configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig -- 2.25.1

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[PATCH] usb: ehci-hcd: Add IAA handshake for removing async QH
by Ye Li 09 Mar '21

09 Mar '21

According to EHCI spec, software needs to do handshake with HC for safely removing QH from async list. This handshake is implemented by setting IAAD (Interrupt on Async Advance Doorbell) bit in USB_USBCMD register and poll the IAA (Interrupt on Async Advance bit) in the USB_USBSTS to ensure the HC has released all on-chip state that may potentially reference one of the data structures just removed. Current codes only check active status of the last QTD, but this can't ensure the QH is released from HC. We can meet unrecoverable "EHCI timed out on TD" errors when running SCT tests on USB disk. The USB_ASYNCLISTADDR register is changed to a invalid address when the issue happens. It is fixed after adding the IAA handshake. Signed-off-by: Ye Li <ye.li(a)nxp.com> --- drivers/usb/host/ehci-hcd.c | 25 +++++++++++++++++++++++++ drivers/usb/host/ehci.h | 1 + 2 files changed, 26 insertions(+) diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 8933f60..b52a903 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -346,6 +346,28 @@ static int ehci_disable_async(struct ehci_ctrl *ctrl) return ret; } +static int ehci_iaa_cycle(struct ehci_ctrl *ctrl) +{ + u32 cmd, status; + int ret; + + /* Enable Interrupt on Async Advance Doorbell. */ + cmd = ehci_readl(&ctrl->hcor->or_usbcmd); + cmd |= CMD_IAAD; + ehci_writel(&ctrl->hcor->or_usbcmd, cmd); + + ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_IAA, STS_IAA, + 10 * 1000); /* 10ms timeout */ + if (ret < 0) + printf("EHCI fail timeout STS_IAA set\n"); + + status = ehci_readl(&ctrl->hcor->or_usbsts); + if ((status & STS_IAA)) + ehci_writel(&ctrl->hcor->or_usbsts, STS_IAA); + + return ret; +} + static int ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, int length, struct devrequest *req) @@ -631,6 +653,9 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, flush_dcache_range((unsigned long)&ctrl->qh_list, ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1)); + /* Set IAAD, poll IAA */ + ehci_iaa_cycle(ctrl); + /* * Invalidate the memory area occupied by buffer * Don't try to fix the buffer alignment, if it isn't properly diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h index 8e07554..e9e6f2a5 100644 --- a/drivers/usb/host/ehci.h +++ b/drivers/usb/host/ehci.h @@ -44,6 +44,7 @@ struct ehci_hcor { #define STS_ASS (1 << 15) #define STS_PSS (1 << 14) #define STS_HALT (1 << 12) +#define STS_IAA (1 << 5) uint32_t or_usbintr; #define INTR_UE (1 << 0) /* USB interrupt enable */ #define INTR_UEE (1 << 1) /* USB error interrupt enable */ -- 2.7.4

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bug report : /drivers/pci/pcie_layerscape_rc.c "pcie->ctrl used without being initialised"
by florian.manoel＠siemens.com 09 Mar '21

09 Mar '21

Hi, I would like to report a bug I got, while updating my u-boot version. Configuration : CPU : NXP LS1043a u-boot version : v2020.10 (I didn't see a fix for this issue in the latest u-boot version) What was happening : Function "unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset)" in "/drivers/pci/pcie_layerscape.c" was leading to a panic due to a read at an incorrect address. What was wrong : The address to read at, is extracted from the DTB, in my case, the nodes 'pcie', name 'ctrl' from the 'reg-name' list. This is done in the function "static int ls_pcie_probe(struct udevice *dev)" in "/drivers/pci/pcie_layerscape_rc.c" In some case (mine at least), the DTB doesn't contain the name 'ctrl' in the list 'reg-names' for the pcie nodes, causing 'fdt_get_named_resource()' to return (-1). This (-1) avoid the variable 'pcie->ctrl' to be initialized. This variable is not directly declared but a pointer 'pcie' to a structure ls_pcie is declared instead. Because the value of 'pcie->ctrl' is not initialized, there is a non-zero random value inside that passes the test "if (!pcie->ctrl)" and leads to the panic while given to the ctrl_read() as address to read. How I fixed it : Initialize the value of "pcie->ctrl" to NULL at the beginning of the function ls_pcie_probe() This make the check "if (!pcie->ctrl)" to fail and the variable "pcie->ctrl" is then initialized. How to reproduce it : Not sure... We load a FIT image containing a kernel, ramdisk and a DTB from an NOR memory through a QSPI interface. The checksum are OK. Then, we boot from it using the command 'bootm'. Once the FIT element are loaded, some checks (link) are done on the PCIe and the issue happens here. But, If I start another firmware, using the same DTB, from an eMMC memory. I have no issue at all, "pcie->ctrl" is initialized to NULL directly without need of a fix. Let me know if you want more information. Mit freundlichen Grüßen Florian Manoël Siemens AG Digital Industries Process Automation DI PA DCP R&D 2 Östliche Rheinbrückenstr. 50 76187 Karlsruhe, Deutschland Tel.: +49 721 667-20051 mailto:florian.manoel@siemens.com www.siemens.com Siemens Aktiengesellschaft: Vorsitzender des Aufsichtsrats: Jim Hagemann Snabe; Vorstand: Roland Busch, Vorsitzender; Klaus Helmrich, Cedrik Neike, Matthias Rebellius, Ralf P. Thomas, Judith Wiese; Sitz der Gesellschaft: Berlin und München, Deutschland; Registergericht: Berlin-Charlottenburg, HRB 12300, München, HRB 6684; WEEE-Reg.-Nr. DE 23691322

1 0

request for i.MX8MM Venice test
by Marek Behun 08 Mar '21

08 Mar '21

[sorry for the spam, I accidentally sent this e-mail from my personal address] Hello Tim, you are listed as maintainer of i.MX8MM Venice board in U-Boot. I am currently working on LTO support for U-Boot, and I have encountered a problem with i.MX8MM Venice board: when LTO is enabled, the linking process for SPL does not throw away relocation information, making the resulting SPL image too big for that board. I have added a patch that discards symbols from .rela* section to my patch series, but I would like you to test whether the patch series works for your board and does not break anything. Could you please clone https://github.com/elkablo/u-boot branch lto, build for imx8mm_venice_defconfig and test whether it boots on your board and maybe test some U-Boot commands (disk reads, kernel booting, ...)? If it does not work, could you also please check with current U-Boot master, to see if it got broken with my patches or with something different? Thank you. Marek

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Booting a FIT: The load address of the FDT blob and overlays
by Alex G. 08 Mar '21

08 Mar '21

Hi, I was wondering about the correct load address for a devicetree in FIT. Normally, the dtb can be anywhere in RAM, so it doesn't make sense to force it to a specific address with a 'load =' FIT directive. With bootm, the first overlay, but then fail with with: "Overlayed FDT requires relocation" The reason is that bootm_find_other() will want to apply the overlays with the FDT in-place. This would overwrite the FIT image. But later, in boot_relocate_fdt(), it goes ahead and relocates the FDT anyway. So why not relocate the FDT, and then apply the overlays? I also like the solution when booting FITs with SPL_LOAD_FIT_SIMPLE. In this case, the FDT is placed right after the firmware or OS binary, unless the 'load =' address is given in the FIT. Alex

1 0

[PATCH 0/2] ANATOP regulator driver
by Ying-Chun Liu 08 Mar '21

08 Mar '21

From: "Ying-Chun Liu (PaulLiu)" <paul.liu(a)linaro.org> Anatop is an integrated regulator inside i.MX6 SoC. There are 3 digital regulators which controls PU, CORE (ARM), and SOC. And 3 analog regulators which controls 1P1, 2P5, 3P0 (USB). This patch adds the Anatop regulator driver. Ying-Chun Liu (PaulLiu) (2): power: regulator: add driver for ANATOP regulator doc: device-tree-bindings: regulator: anatop regulator .../regulator/fsl,anatop-regulator.txt | 45 +++ drivers/power/regulator/Kconfig | 10 + drivers/power/regulator/Makefile | 1 + drivers/power/regulator/anatop_regulator.c | 289 ++++++++++++++++++ 4 files changed, 345 insertions(+) create mode 100644 doc/device-tree-bindings/regulator/fsl,anatop-regulator.txt create mode 100644 drivers/power/regulator/anatop_regulator.c -- 2.30.1

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[PULL u-boot] Please pull u-boot-amlogic-20210308
by Neil Armstrong 08 Mar '21

08 Mar '21

Hi Tom, These changes fixes s/treshold/threshold/ in ADC button driver, and adds the missing fdtoverlay_addr_r env variable to make usage of FDT overlay support in PXE boot on Amlogic boards. The CI job is at https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic/pipelines/6696 Thanks, Neil The following changes since commit e4dba4ba6f61e8128be0b4200ca2d8cebf62180b: Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq (2021-03-06 07:25:04 -0500) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic.git u-boot-amlogic-20210308 for you to fetch changes up to 266637db88e37686b160722e183571567c61ad1a: configs: meson64: add fdtoverlay_addr_r (2021-03-08 10:32:35 +0100) ---------------------------------------------------------------- - button: adc: fix treshold typo - configs: meson64: add fdtoverlay_addr_r ---------------------------------------------------------------- Neil Armstrong (2): button: adc: fix treshold typo configs: meson64: add fdtoverlay_addr_r drivers/button/button-adc.c | 14 +++++++------- include/configs/meson64.h | 1 + 2 files changed, 8 insertions(+), 7 deletions(-)

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