March 2021 - U-Boot

[PATCH] net: designware: add DM_MDIO support
by Neil Armstrong 08 Mar '21

08 Mar '21

Add support for DM_MDIO to connect to PHY and expose a MDIO device for the internal MDIO bus in order to dynamically connect to MDIO PHYs with DT with eventual MDIO muxes in between. Signed-off-by: Neil Armstrong <narmstrong(a)baylibre.com> --- drivers/net/designware.c | 93 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 92 insertions(+), 1 deletion(-) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 9dba55adaa..acf3a82828 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -21,7 +21,9 @@ #include <reset.h> #include <asm/cache.h> #include <dm/device_compat.h> +#include <dm/device-internal.h> #include <dm/devres.h> +#include <dm/lists.h> #include <linux/compiler.h> #include <linux/delay.h> #include <linux/err.h> @@ -122,6 +124,55 @@ static int dw_mdio_reset(struct mii_dev *bus) } #endif +#if IS_ENABLED(CONFIG_DM_MDIO) +int designware_eth_mdio_read(struct udevice *mdio_dev, int addr, int devad, int reg) +{ + struct mdio_perdev_priv *pdata = dev_get_uclass_priv(mdio_dev); + + return dw_mdio_read(pdata->mii_bus, addr, devad, reg); +} + +int designware_eth_mdio_write(struct udevice *mdio_dev, int addr, int devad, int reg, u16 val) +{ + struct mdio_perdev_priv *pdata = dev_get_uclass_priv(mdio_dev); + + return dw_mdio_write(pdata->mii_bus, addr, devad, reg, val); +} + +#if CONFIG_IS_ENABLED(DM_GPIO) +int designware_eth_mdio_reset(struct udevice *mdio_dev) +{ + struct mdio_perdev_priv *pdata = dev_get_uclass_priv(mdio_dev); + + return dw_mdio_reset(pdata->mii_bus); +} +#endif + +static const struct mdio_ops designware_eth_mdio_ops = { + .read = designware_eth_mdio_read, + .write = designware_eth_mdio_write, +#if CONFIG_IS_ENABLED(DM_GPIO) + .reset = designware_eth_mdio_reset, +#endif +}; + +static int designware_eth_mdio_probe(struct udevice *dev) +{ + /* Use the priv data of parent */ + dev_set_priv(dev, dev_get_priv(dev->parent)); + + return 0; +} + +U_BOOT_DRIVER(designware_eth_mdio) = { + .name = "eth_designware_mdio", + .id = UCLASS_MDIO, + .probe = designware_eth_mdio_probe, + .ops = &designware_eth_mdio_ops, + .plat_auto = sizeof(struct mdio_perdev_priv), +}; +#endif + static int dw_mdio_init(const char *name, void *priv) { struct mii_dev *bus = mdio_alloc(); @@ -143,6 +194,34 @@ static int dw_mdio_init(const char *name, void *priv) return mdio_register(bus); } +#if IS_ENABLED(CONFIG_DM_MDIO) +static int dw_dm_mdio_init(const char *name, void *priv) +{ + struct udevice *dev = priv; + ofnode node; + int ret; + + ofnode_for_each_subnode(node, dev_ofnode(dev)) { + const char *subnode_name = ofnode_get_name(node); + struct udevice *mdiodev; + + if (strcmp(subnode_name, "mdio")) + continue; + + ret = device_bind_driver_to_node(dev, "eth_designware_mdio", + subnode_name, node, &mdiodev); + if (ret) + debug("%s: not able to bind mdio device node\n", __func__); + + return 0; + } + + printf("%s: mdio node is missing, registering legacy mdio bus", __func__); + + return dw_mdio_init(name, priv); +} +#endif + static void tx_descs_init(struct dw_eth_dev *priv) { struct eth_dma_regs *dma_p = priv->dma_regs_p; @@ -487,7 +566,14 @@ static int _dw_free_pkt(struct dw_eth_dev *priv) static int dw_phy_init(struct dw_eth_dev *priv, void *dev) { struct phy_device *phydev; - int phy_addr = -1, ret; + int ret; + +#if IS_ENABLED(CONFIG_DM_MDIO) && IS_ENABLED(CONFIG_DM_ETH) + phydev = dm_eth_phy_connect(dev); + if (!phydev) + return -ENODEV; +#else + int phy_addr = -1; #ifdef CONFIG_PHY_ADDR phy_addr = CONFIG_PHY_ADDR; @@ -496,6 +582,7 @@ static int dw_phy_init(struct dw_eth_dev *priv, void *dev) phydev = phy_connect(priv->bus, phy_addr, dev, priv->interface); if (!phydev) return -ENODEV; +#endif phydev->supported &= PHY_GBIT_FEATURES; if (priv->max_speed) { @@ -759,7 +846,11 @@ int designware_eth_probe(struct udevice *dev) priv->interface = pdata->phy_interface; priv->max_speed = pdata->max_speed; +#if IS_ENABLED(CONFIG_DM_MDIO) + ret = dw_dm_mdio_init(dev->name, dev); +#else ret = dw_mdio_init(dev->name, dev); +#endif if (ret) { err = ret; goto mdio_err; -- 2.25.1

2 2

[PATCH] net: add Amlogic Meson G12A MDIO MUX driver
by Neil Armstrong 08 Mar '21

08 Mar '21

The Amlogic G12A & compatible SoCs embeds a mux to either communicate with the external PHY or the internal 10/100 PHY. This adds support for this mux as a MDIO MUX device. Signed-off-by: Neil Armstrong <narmstrong(a)baylibre.com> --- drivers/net/Kconfig | 7 ++ drivers/net/Makefile | 1 + drivers/net/mdio_mux_meson_g12a.c | 149 ++++++++++++++++++++++++++++++ 3 files changed, 157 insertions(+) create mode 100644 drivers/net/mdio_mux_meson_g12a.c diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 41fa2fe566..e1d3b26687 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -797,4 +797,11 @@ config MDIO_MUX_MMIOREG This driver is used for MDIO muxes driven by writing to a register in the MMIO physical memory. +config MDIO_MUX_MESON_G12A + bool "MDIO MUX for Amlogic Meson G12A SoCs" + depends on DM_MDIO_MUX + help + This driver is used for the MDIO mux found on the Amlogic G12A & compatible + SoCs. + endif # NETDEVICES diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 511c87c3a5..070ae7662c 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -43,6 +43,7 @@ obj-$(CONFIG_MACB) += macb.o obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o obj-$(CONFIG_MDIO_IPQ4019) += mdio-ipq4019.o obj-$(CONFIG_MDIO_MUX_I2CREG) += mdio_mux_i2creg.o +obj-$(CONFIG_MDIO_MUX_MESON_G12A) += mdio_mux_meson_g12a.o obj-$(CONFIG_MDIO_MUX_MMIOREG) += mdio_mux_mmioreg.o obj-$(CONFIG_MDIO_MUX_SANDBOX) += mdio_mux_sandbox.o obj-$(CONFIG_MPC8XX_FEC) += mpc8xx_fec.o diff --git a/drivers/net/mdio_mux_meson_g12a.c b/drivers/net/mdio_mux_meson_g12a.c new file mode 100644 index 0000000000..b520bf98f0 --- /dev/null +++ b/drivers/net/mdio_mux_meson_g12a.c @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2021 BayLibre, SAS + * Author: Neil Armstrong <narmstrong(a)baylibre.com> + */ + +#include <dm.h> +#include <errno.h> +#include <log.h> +#include <miiphy.h> +#include <asm/io.h> +#include <linux/bitfield.h> + +#define ETH_PLL_STS 0x40 +#define ETH_PLL_CTL0 0x44 +#define PLL_CTL0_LOCK_DIG BIT(30) +#define PLL_CTL0_RST BIT(29) +#define PLL_CTL0_EN BIT(28) +#define PLL_CTL0_SEL BIT(23) +#define PLL_CTL0_N GENMASK(14, 10) +#define PLL_CTL0_M GENMASK(8, 0) +#define PLL_LOCK_TIMEOUT 1000000 +#define PLL_MUX_NUM_PARENT 2 +#define ETH_PLL_CTL1 0x48 +#define ETH_PLL_CTL2 0x4c +#define ETH_PLL_CTL3 0x50 +#define ETH_PLL_CTL4 0x54 +#define ETH_PLL_CTL5 0x58 +#define ETH_PLL_CTL6 0x5c +#define ETH_PLL_CTL7 0x60 + +#define ETH_PHY_CNTL0 0x80 +#define EPHY_G12A_ID 0x33010180 +#define ETH_PHY_CNTL1 0x84 +#define PHY_CNTL1_ST_MODE GENMASK(2, 0) +#define PHY_CNTL1_ST_PHYADD GENMASK(7, 3) +#define EPHY_DFLT_ADD 8 +#define PHY_CNTL1_MII_MODE GENMASK(15, 14) +#define EPHY_MODE_RMII 0x1 +#define PHY_CNTL1_CLK_EN BIT(16) +#define PHY_CNTL1_CLKFREQ BIT(17) +#define PHY_CNTL1_PHY_ENB BIT(18) +#define ETH_PHY_CNTL2 0x88 +#define PHY_CNTL2_USE_INTERNAL BIT(5) +#define PHY_CNTL2_SMI_SRC_MAC BIT(6) +#define PHY_CNTL2_RX_CLK_EPHY BIT(9) + +#define MESON_G12A_MDIO_EXTERNAL_ID 0 +#define MESON_G12A_MDIO_INTERNAL_ID 1 + +struct mdio_mux_meson_g12a_priv { + struct udevice *chip; + phys_addr_t phys; +}; + +static int meson_g12a_ephy_pll_init(struct mdio_mux_meson_g12a_priv *priv) +{ + /* Fire up the PHY PLL */ + writel(0x29c0040a, priv->phys + ETH_PLL_CTL0); + writel(0x927e0000, priv->phys + ETH_PLL_CTL1); + writel(0xac5f49e5, priv->phys + ETH_PLL_CTL2); + writel(0x00000000, priv->phys + ETH_PLL_CTL3); + writel(0x00000000, priv->phys + ETH_PLL_CTL4); + writel(0x20200000, priv->phys + ETH_PLL_CTL5); + writel(0x0000c002, priv->phys + ETH_PLL_CTL6); + writel(0x00000023, priv->phys + ETH_PLL_CTL7); + writel(0x39c0040a, priv->phys + ETH_PLL_CTL0); + writel(0x19c0040a, priv->phys + ETH_PLL_CTL0); + + return 0; +} + +static int meson_g12a_enable_internal_mdio(struct mdio_mux_meson_g12a_priv *priv) +{ + /* Initialize ephy control */ + writel(EPHY_G12A_ID, priv->phys + ETH_PHY_CNTL0); + writel(FIELD_PREP(PHY_CNTL1_ST_MODE, 3) | + FIELD_PREP(PHY_CNTL1_ST_PHYADD, EPHY_DFLT_ADD) | + FIELD_PREP(PHY_CNTL1_MII_MODE, EPHY_MODE_RMII) | + PHY_CNTL1_CLK_EN | + PHY_CNTL1_CLKFREQ | + PHY_CNTL1_PHY_ENB, + priv->phys + ETH_PHY_CNTL1); + writel(PHY_CNTL2_USE_INTERNAL | + PHY_CNTL2_SMI_SRC_MAC | + PHY_CNTL2_RX_CLK_EPHY, + priv->phys + ETH_PHY_CNTL2); + + return 0; +} + +static int meson_g12a_enable_external_mdio(struct mdio_mux_meson_g12a_priv *priv) +{ + /* Reset the mdio bus mux */ + writel(0x0, priv->phys + ETH_PHY_CNTL2); + + return 0; +} + +static int mdio_mux_meson_g12a_select(struct udevice *mux, int cur, int sel) +{ + struct mdio_mux_meson_g12a_priv *priv = dev_get_priv(mux); + + debug("%s: %x -> %x\n", __func__, (u32)cur, (u32)sel); + + /* if last selection didn't change we're good to go */ + if (cur == sel) + return 0; + + switch (sel) { + case MESON_G12A_MDIO_EXTERNAL_ID: + return meson_g12a_enable_external_mdio(priv); + case MESON_G12A_MDIO_INTERNAL_ID: + return meson_g12a_enable_internal_mdio(priv); + default: + return -EINVAL; + } + + return 0; +} + +static const struct mdio_mux_ops mdio_mux_meson_g12a_ops = { + .select = mdio_mux_meson_g12a_select, +}; + +static int mdio_mux_meson_g12a_probe(struct udevice *dev) +{ + struct mdio_mux_meson_g12a_priv *priv = dev_get_priv(dev); + + priv->phys = dev_read_addr(dev); + + meson_g12a_ephy_pll_init(priv); + + return 0; +} + +static const struct udevice_id mdio_mux_meson_g12a_ids[] = { + { .compatible = "amlogic,g12a-mdio-mux" }, + { } +}; + +U_BOOT_DRIVER(mdio_mux_meson_g12a) = { + .name = "mdio_mux_meson_g12a", + .id = UCLASS_MDIO_MUX, + .of_match = mdio_mux_meson_g12a_ids, + .probe = mdio_mux_meson_g12a_probe, + .ops = &mdio_mux_meson_g12a_ops, + .priv_auto = sizeof(struct mdio_mux_meson_g12a_priv), +}; -- 2.25.1

2 2

[PATCH] net: designware: add Amlogic Meson8b & later glue driver
by Neil Armstrong 08 Mar '21

08 Mar '21

This adds a proper glue driver for the Designware DWMAC ethernet MAC IP found in the Amlogic Meson8, GXBB, GXL, GXM, G12A, G12B & SM1 SoCs. This is aimed to replace the static ethernet link setup found on the board init code for the Amlogic SoC based boards. Tested on a libretech-cc (S905x Internal RMII 10/100 PHY) and Khadas VIM3 (A113d with external 10/100/1000 RGMII PHY) to cover the most extreme setups. Signed-off-by: Neil Armstrong <narmstrong(a)baylibre.com> --- drivers/net/Kconfig | 8 ++ drivers/net/Makefile | 1 + drivers/net/dwmac_meson8b.c | 150 ++++++++++++++++++++++++++++++++++++ 3 files changed, 159 insertions(+) create mode 100644 drivers/net/dwmac_meson8b.c diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index e1d3b26687..cf062fad4d 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -271,6 +271,14 @@ config ETH_DESIGNWARE 100Mbit and 1 Gbit operation. You must enable CONFIG_PHYLIB to provide the PHY (physical media interface). +config ETH_DESIGNWARE_MESON8B + bool "Amlogic Meson8b and later glue driver for Synopsys Designware Ethernet MAC" + depends on DM_ETH + select ETH_DESIGNWARE + help + This provides glue layer to use Synopsys Designware Ethernet MAC + present on the Amlogic Meson8b, GX, AXG & G12A SoCs. + config ETH_DESIGNWARE_SOCFPGA select REGMAP select SYSCON diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 070ae7662c..ce7b9e3478 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_CORTINA_NI_ENET) += cortina_ni.o obj-$(CONFIG_CS8900) += cs8900.o obj-$(CONFIG_TULIP) += dc2114x.o obj-$(CONFIG_ETH_DESIGNWARE) += designware.o +obj-$(CONFIG_ETH_DESIGNWARE_MESON8B) += dwmac_meson8b.o obj-$(CONFIG_ETH_DESIGNWARE_SOCFPGA) += dwmac_socfpga.o obj-$(CONFIG_ETH_DESIGNWARE_S700) += dwmac_s700.o obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o diff --git a/drivers/net/dwmac_meson8b.c b/drivers/net/dwmac_meson8b.c new file mode 100644 index 0000000000..c0b6ef4994 --- /dev/null +++ b/drivers/net/dwmac_meson8b.c @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 BayLibre, SAS + */ + +#include <common.h> +#include <asm/io.h> +#include <dm.h> +#include <phy.h> +#include "designware.h" +#include <dm/device_compat.h> +#include <linux/err.h> + +#define ETH_REG_0 0x0 +#define ETH_REG_1 0x4 +#define ETH_REG_2 0x18 +#define ETH_REG_3 0x1c + +#define GX_ETH_REG_0_PHY_INTF BIT(0) +#define GX_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5) +#define GX_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7) +#define GX_ETH_REG_0_PHY_CLK_EN BIT(10) +#define GX_ETH_REG_0_INVERT_RMII_CLK BIT(11) +#define GX_ETH_REG_0_CLK_EN BIT(12) + +#define AXG_ETH_REG_0_PHY_INTF_RGMII BIT(0) +#define AXG_ETH_REG_0_PHY_INTF_RMII BIT(2) +#define AXG_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5) +#define AXG_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7) +#define AXG_ETH_REG_0_PHY_CLK_EN BIT(10) +#define AXG_ETH_REG_0_INVERT_RMII_CLK BIT(11) +#define AXG_ETH_REG_0_CLK_EN BIT(12) + +struct dwmac_meson8b_plat { + struct dw_eth_pdata dw_eth_pdata; + int (*dwmac_setup)(struct udevice *dev, struct eth_pdata *edata); + void *regs; +}; + +static int dwmac_meson8b_of_to_plat(struct udevice *dev) +{ + struct dwmac_meson8b_plat *pdata = dev_get_plat(dev); + + pdata->regs = (void *)dev_read_addr_index(dev, 1); + if ((fdt_addr_t)pdata->regs == FDT_ADDR_T_NONE) + return -EINVAL; + + pdata->dwmac_setup = (void *)dev_get_driver_data(dev); + if (!pdata->dwmac_setup) + return -EINVAL; + + return designware_eth_of_to_plat(dev); +} + +static int dwmac_setup_axg(struct udevice *dev, struct eth_pdata *edata) +{ + struct dwmac_meson8b_plat *plat = dev_get_plat(dev); + + switch (edata->phy_interface) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + /* Set RGMII mode */ + setbits_le32(plat->regs + ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII | + AXG_ETH_REG_0_TX_PHASE(1) | + AXG_ETH_REG_0_TX_RATIO(4) | + AXG_ETH_REG_0_PHY_CLK_EN | + AXG_ETH_REG_0_CLK_EN); + break; + + case PHY_INTERFACE_MODE_RMII: + /* Set RMII mode */ + out_le32(plat->regs + ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RMII | + AXG_ETH_REG_0_INVERT_RMII_CLK | + AXG_ETH_REG_0_CLK_EN); + break; + default: + dev_err(dev, "Unsupported PHY mode\n"); + return -EINVAL; + } + + return 0; +} + +static int dwmac_setup_gx(struct udevice *dev, struct eth_pdata *edata) +{ + struct dwmac_meson8b_plat *plat = dev_get_plat(dev); + + switch (edata->phy_interface) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + /* Set RGMII mode */ + setbits_le32(plat->regs + ETH_REG_0, GX_ETH_REG_0_PHY_INTF | + GX_ETH_REG_0_TX_PHASE(1) | + GX_ETH_REG_0_TX_RATIO(4) | + GX_ETH_REG_0_PHY_CLK_EN | + GX_ETH_REG_0_CLK_EN); + + break; + + case PHY_INTERFACE_MODE_RMII: + /* Set RMII mode */ + out_le32(plat->regs + ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK | + GX_ETH_REG_0_CLK_EN); + + if (!IS_ENABLED(CONFIG_MESON_GXBB)) + writel(0x10110181, plat->regs + ETH_REG_2); + + break; + default: + dev_err(dev, "Unsupported PHY mode\n"); + return -EINVAL; + } + + return 0; +} + +static int dwmac_meson8b_probe(struct udevice *dev) +{ + struct dwmac_meson8b_plat *pdata = dev_get_plat(dev); + struct eth_pdata *edata = &pdata->dw_eth_pdata.eth_pdata; + int ret; + + ret = pdata->dwmac_setup(dev, edata); + if (ret) + return ret; + + return designware_eth_probe(dev); +} + +static const struct udevice_id dwmac_meson8b_ids[] = { + { .compatible = "amlogic,meson-gxbb-dwmac", .data = (ulong)dwmac_setup_gx }, + { .compatible = "amlogic,meson-axg-dwmac", .data = (ulong)dwmac_setup_axg }, + { } +}; + +U_BOOT_DRIVER(dwmac_meson8b) = { + .name = "dwmac_meson8b", + .id = UCLASS_ETH, + .of_match = dwmac_meson8b_ids, + .of_to_plat = dwmac_meson8b_of_to_plat, + .probe = dwmac_meson8b_probe, + .ops = &designware_eth_ops, + .priv_auto = sizeof(struct dw_eth_dev), + .plat_auto = sizeof(struct dwmac_meson8b_plat), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; -- 2.25.1

1 1

[PATCH 0/5] riscv: enable SBI system reset
by Heinrich Schuchardt 08 Mar '21

08 Mar '21

The purpose of this series is to provide the UEFI ResetSystem() service at runtime on RISC-V systems. With SBI v0.3 a system reset extension is available. This allows to implement reboot and poweroff in U-Boot in a system independent way. OpenSBI already provides an implementation of the extension for the Kendryte K210 and other platforms. * Provide a system reset driver using the system reset extension. * Enable the driver on the MAIX board. * Change the sbi command to use contants instead of raw numbers where applicable. Heinrich Schuchardt (5): risv: add missing SBI extension definitions cmd/sbi: use constants instead of numerical values sysreset: provide SBI based sysreset driver pinctrl: K210_PINCTRL depends on REGMAP and on SYSCON maix: enable SBI system reset for MAIX MAINTAINERS | 1 + arch/riscv/include/asm/sbi.h | 37 +++++++++- arch/riscv/lib/sbi.c | 21 ++++-- board/sipeed/maix/maix.c | 4 ++ cmd/riscv/sbi.c | 30 ++++---- configs/sipeed_maix_smode_defconfig | 2 + drivers/pinctrl/Kconfig | 2 + drivers/sysreset/Kconfig | 7 ++ drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_sbi.c | 102 ++++++++++++++++++++++++++++ lib/efi_loader/Kconfig | 2 +- 11 files changed, 187 insertions(+), 22 deletions(-) create mode 100644 drivers/sysreset/sysreset_sbi.c -- 2.30.1

4 18

[RFC] tests in test/dm/video.c are not independent
by Heinrich Schuchardt 08 Mar '21

08 Mar '21

Hello Simon, looking at the tests in test/dm/video.c it seems that none of them clears the screen before adding text and testing the hash of the frame buffer. So it is hard to tell which output led to changes in subsequent tests. I think the tests should first clear the screen to start from a defined state. This will make the tests independent of each other. What is your view? Best regards Heinrich

2 1

[PATCH v4 00/42] test: Refactor tests to have a single test runner
by Simon Glass 08 Mar '21

08 Mar '21

At present U-Boot has two broad sets of tests in the C code: driver model tests which do a lot of pre-/post-init and command tests which do not. This separation makes it slightly harder to write a test, since there are two different test-state structures and different rules for running the two different test types. At present these rules are determined by where the test is (actually its prefix). All unit tests can be run from the command line with the 'ut' command. Since SPL does not have commands, it currently calls the test runner directly and offers no control of which tests are run. This seems like a good time to refactor the tests into a unified test runner, allowing U-Boot proper and SPL to use the same path, perhaps with some different conditions along the way. This series sets up a unified runner called ut_run_list(), which runs a set of tests from a linker_list. Driver model tests are distinguished by a new UT_TESTF_DM flag so that the necessary init and cleanup can still be done. The runner is modified to support running SPL tests that are not solely for driver model. An example test for FIT loading is added as a demonstration. In addition, some documentation is added to explain how to write tests. This series is available at u-boot-dm/test-working Changes in v4: - Fix 'of-pldata' typo - Rebase on master - Add correct SPDX header Changes in v3: - Add new patch to re-enable test_ofplatdata - Reword the SPL tests section for clarity - Use test_set_state() throughout test-main.c instead of direct assignment - Update the pytest collector as well Changes in v2: - Use correct rst format for 'Ad-hoc tests' section - Expand docs on how each type of test is marked - Put the docs in tests_sandbox since it is more related to sandbox - Put in a mention of tests_sandbox in the main testing docs - Add a note that SPL tests can in fact be run individualy - Document how to run all C tests with 'ut all' - Fix 'get list' typo - Fix conditions so non-DM SPL tests are actually run - Allow for prefix to be NULL, to match function comment - Add new patches to cover running an SPL test Simon Glass (42): dm: core: Fix allocation of empty of-platdata doc: Tidy up testing section doc: Document make tcheck sandbox: Drop the 'starting...' message unless testing test: Re-enable test_ofplatdata doc: Explain how to run tests without pytest doc: Document how sandbox_spl_tests are run test: Correct setexpr test prefix test: Mark all driver model tests with a flag test: Rename test-main.c to test-dm.c test: Add an overall test runner test: Create pre/post-run functions test: Call test_pre/post_run() from driver model tests test: Move dm_extended_scan() to test_pre_run() test: Move do_autoprobe() to test_pre_run() test: Move dm_scan_plat() to test_pre_run() test: Drop mallinfo() work-around test: Move console silencing to test_pre_run() test: Move delay skipping to test_pre_run() test: Handle driver model reinit in test_pre_run() test: Drop struct dm_test_state test: Move dm_test_init() into test-main.c test: Move dm_test_destroy() into test-main.c test: Move test running into a separate function test: Use ut_run_test() to run driver model tests test: Drop dm_do_test() test: Add ut_run_test_live_flat() to run tests twice test: Use a local variable for test state test: Run driver-model tests using ut_run_list() test: Use return values in dm_test_run() test: Move the devicetree check into ut_run_list() test: Move restoring of driver model state to ut_run_list() test: log: Rename log main test file to log_ut.c test: Add a macros for finding tests in linker_lists test: Rename all linker lists to have a ut_ prefix test: Allow SPL to run any available test sandbox: Update os_find_u_boot() to find the .img file spl: Convert spl_fit to work with sandbox doc: Move coccinelle into its own section spl: test: Add a test for spl_load_simple_fit() test: sandbox: Move sandbox test docs into doc/develop doc: Explain briefly how to write new tests arch/sandbox/cpu/os.c | 8 +- arch/sandbox/cpu/spl.c | 9 +- arch/sandbox/cpu/start.c | 15 +- arch/sandbox/include/asm/state.h | 1 + common/spl/spl.c | 3 +- common/spl/spl_fit.c | 27 +- configs/sandbox_spl_defconfig | 2 +- doc/arch/sandbox.rst | 48 +--- doc/develop/index.rst | 11 +- doc/develop/py_testing.rst | 3 +- doc/develop/testing.rst | 46 +++- doc/develop/tests_sandbox.rst | 208 ++++++++++++++ doc/develop/tests_writing.rst | 339 +++++++++++++++++++++++ drivers/core/device.c | 17 +- include/dm/test.h | 20 +- include/os.h | 3 +- include/spl.h | 9 + include/test/test.h | 38 ++- include/test/ut.h | 45 +++ test/Makefile | 3 + test/bloblist.c | 5 +- test/bootm.c | 4 +- test/cmd/mem.c | 4 +- test/cmd/setexpr.c | 28 +- test/cmd_ut.c | 38 +-- test/compression.c | 5 +- test/dm/Makefile | 2 +- test/dm/core.c | 58 ++-- test/dm/test-dm.c | 51 ++++ test/dm/test-driver.c | 12 +- test/dm/test-main.c | 230 ---------------- test/dm/test-uclass.c | 10 +- test/env/cmd_ut_env.c | 4 +- test/image/Makefile | 5 + test/image/spl_load.c | 91 ++++++ test/lib/cmd_ut_lib.c | 4 +- test/log/Makefile | 2 +- test/log/{test-main.c => log_ut.c} | 4 +- test/optee/cmd_ut_optee.c | 5 +- test/overlay/cmd_ut_overlay.c | 5 +- test/py/conftest.py | 2 +- test/py/tests/test_log.py | 2 +- test/py/tests/test_ofplatdata.py | 2 +- test/str_ut.c | 5 +- test/test-main.c | 426 +++++++++++++++++++++++++++++ test/unicode_ut.c | 4 +- test/ut.c | 7 + 47 files changed, 1422 insertions(+), 448 deletions(-) create mode 100644 doc/develop/tests_sandbox.rst create mode 100644 doc/develop/tests_writing.rst create mode 100644 test/dm/test-dm.c delete mode 100644 test/dm/test-main.c create mode 100644 test/image/Makefile create mode 100644 test/image/spl_load.c rename test/log/{test-main.c => log_ut.c} (75%) create mode 100644 test/test-main.c -- 2.30.1.766.gb4fecdf3b7-goog

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[PATCH 00/20] binman: Support devicetree update in all entries
by Simon Glass 07 Mar '21

07 Mar '21

U-Boot's various phase binaries actually comprise two or three pieces. For example, u-boot.bin has the executable followed by a devicetree. With binman we want to be able to update that devicetree with full image information so that it is accessible to the executable. This is tricky if it is not clear where the devicetree starts. At present this is handled manually, by creating two separate nodes in the binman definition, u-boot-nodtb and u-boot-dtb, so that binman sees them separately and can easily update the devicetree. But this is not very convenient. Of course we could try to detect the devicetree in the binary, which is easy enough for binman to do. But this approach rapidly gets out of hand. When listing an existing image, should we show the devicetree separately? If we don't then binman cannot extract it by itself, only the whole binary. With SPL and TPL we may have BSS padding and this is harder to detect reliably. Also, a design goal of binman is to provide full information about what is in the image. The detection approach goes against that. So instead it seems best to convert these multi-part binaries into a section with the component parts inside. We can do this automatically without affecting the operation of binman very much. One implementation option for this feature would be to update the entries to behave in two different ways, i.e. either to act as a section containing sub-entries, or as a simple blob. However this is tricky because each entry has to use a particular base class. It is not reasonably possible for an entry to choose between using one base class (e.g. blob) or another (e.g. section), depending on a flag. Instead, the approach taken in this series is to replace an entry type with an expanded version, so 'u-boot' becomes 'u-boot-expanded', for example. The new entry is a section containing two or three sub-entries. A similar approach could be take to reduce the complexity of the x86 binman definition. The microcode is either in TPL, SPL or U-Boot proper, so an entryarg could control which of those is expanded to include microcode. That possibility is left for future consideration. Simon Glass (20): binman: Allow extracting to current directory binman: Document ExpandEntries() in the base class binman: Update entry help for files-align binman: Tidy up underscores in entry documentation binman: Correct the documentation for u-boot-spl-bss-pad binman: Add support for u-boot-tpl-nodtb binman: Add support for u-boot-tpl-bss-bad binman: Allow using an an 'expanded' entry type binman: Allow a way to select expanded entries binman: Plumb expanded entries through fully binman: Automatically expand phase binaries into sections Makefile: Pass new entry args to binman x86: Make use of binman expanded entries x86: dts: Drop unused CONFIG_SPL doc: Move UEFI down a bit binman: doc: Add documentation to htmldocs binman: Rearrange documentation into headings binman: Incorporate entry documentation binman: Drop repetitive heading for each entry binman: Update various pieces of the documentation Makefile | 8 + arch/x86/dts/u-boot.dtsi | 17 +- doc/index.rst | 25 +- doc/package/binman | 1 + doc/package/fit.rst | 8 + doc/package/index.rst | 20 + tools/binman/{README => README.rst} | 955 ++++++++++--------- tools/binman/cmdline.py | 5 +- tools/binman/control.py | 28 +- tools/binman/{README.entries => entries.rst} | 318 ++++-- tools/binman/entry.py | 71 +- tools/binman/entry_test.py | 12 + tools/binman/etype/atf_bl31.py | 2 +- tools/binman/etype/blob.py | 4 +- tools/binman/etype/blob_ext.py | 2 +- tools/binman/etype/blob_phase.py | 51 + tools/binman/etype/cbfs.py | 12 +- tools/binman/etype/fdtmap.py | 30 +- tools/binman/etype/files.py | 2 +- tools/binman/etype/fit.py | 21 +- tools/binman/etype/intel_cmc.py | 2 +- tools/binman/etype/intel_fsp.py | 2 +- tools/binman/etype/intel_fsp_m.py | 2 +- tools/binman/etype/intel_fsp_s.py | 2 +- tools/binman/etype/intel_fsp_t.py | 2 +- tools/binman/etype/intel_ifwi.py | 10 +- tools/binman/etype/intel_me.py | 2 +- tools/binman/etype/intel_mrc.py | 2 +- tools/binman/etype/intel_refcode.py | 2 +- tools/binman/etype/intel_vbt.py | 2 +- tools/binman/etype/intel_vga.py | 2 +- tools/binman/etype/mkimage.py | 4 +- tools/binman/etype/scp.py | 2 +- tools/binman/etype/section.py | 15 +- tools/binman/etype/text.py | 6 +- tools/binman/etype/u_boot.py | 8 +- tools/binman/etype/u_boot_dtb_with_ucode.py | 4 +- tools/binman/etype/u_boot_expanded.py | 24 + tools/binman/etype/u_boot_nodtb.py | 8 +- tools/binman/etype/u_boot_spl.py | 3 + tools/binman/etype/u_boot_spl_bss_pad.py | 17 +- tools/binman/etype/u_boot_spl_expanded.py | 45 + tools/binman/etype/u_boot_spl_nodtb.py | 10 +- tools/binman/etype/u_boot_tpl.py | 3 + tools/binman/etype/u_boot_tpl_bss_pad.py | 44 + tools/binman/etype/u_boot_tpl_expanded.py | 45 + tools/binman/etype/u_boot_tpl_nodtb.py | 28 + tools/binman/etype/u_boot_with_ucode_ptr.py | 2 +- tools/binman/ftest.py | 219 ++++- tools/binman/image.py | 17 +- tools/binman/index.rst | 9 + tools/binman/setup.py | 2 +- tools/binman/state.py | 19 +- tools/binman/test/192_u_boot_tpl_nodtb.dts | 13 + tools/binman/test/193_tpl_bss_pad.dts | 19 + tools/binman/test/194_fdt_incl.dts | 17 + tools/binman/test/195_fdt_incl_tpl.dts | 13 + 57 files changed, 1547 insertions(+), 671 deletions(-) create mode 120000 doc/package/binman create mode 100644 doc/package/fit.rst create mode 100644 doc/package/index.rst rename tools/binman/{README => README.rst} (64%) rename tools/binman/{README.entries => entries.rst} (83%) create mode 100644 tools/binman/etype/blob_phase.py create mode 100644 tools/binman/etype/u_boot_expanded.py create mode 100644 tools/binman/etype/u_boot_spl_expanded.py create mode 100644 tools/binman/etype/u_boot_tpl_bss_pad.py create mode 100644 tools/binman/etype/u_boot_tpl_expanded.py create mode 100644 tools/binman/etype/u_boot_tpl_nodtb.py create mode 100644 tools/binman/index.rst create mode 100644 tools/binman/test/192_u_boot_tpl_nodtb.dts create mode 100644 tools/binman/test/193_tpl_bss_pad.dts create mode 100644 tools/binman/test/194_fdt_incl.dts create mode 100644 tools/binman/test/195_fdt_incl_tpl.dts -- 2.30.1.766.gb4fecdf3b7-goog

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[PATCH 0/2] drivers: usb: phy: add driver for usb-nop-xceiv
by Ying-Chun Liu 07 Mar '21

07 Mar '21

From: "Ying-Chun Liu (PaulLiu)" <paul.liu(a)linaro.org> implement the generic NOP USB transceiver for all USB transceiver which are either built-in into USB IP or which are mostly autonomous. Ying-Chun Liu (PaulLiu) (2): drivers: usb: phy: add driver for usb-nop-xceiv doc: device-tree-bindings: phy: usb-nop-xceiv .../phy/usb-nop-xceiv.txt | 43 ++++++ drivers/usb/phy/Kconfig | 8 + drivers/usb/phy/Makefile | 1 + drivers/usb/phy/usb_nop_phy.c | 137 ++++++++++++++++++ 4 files changed, 189 insertions(+) create mode 100644 doc/device-tree-bindings/phy/usb-nop-xceiv.txt create mode 100644 drivers/usb/phy/usb_nop_phy.c -- 2.30.1

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rpi: "stdout=serial,vidconsole\0"
by Heinrich Schuchardt 07 Mar '21

07 Mar '21

Hello Matthias, currently the UEFI sub-systems determines the width of the terminal according to the following rules: If stdout="vidconsole", use the size of the video console, otherwise use the terminal size from the serial console. So if stdout="serial,vidconsole" the size of the video is ignored. With a patch I am about to merge the size of vidconsole will be used if the first 10 characters of stdout are "vidconsole": * stdout="vidconsole": use video console size * stdout="vidconsole,serial": use video console size * stdout="serial,vidconsole": use serial terminal size * stdout="serial": use serial terminal size The difference can for instance be seen when using GRUB_TERMINAL=console. This setting allows GRUB to be displayed both on the serial console as well as on the video console. At least for the Raspberry Pi 400 stdout="vidconsole,serial" seems to be the best choice as it will typically be used with a monitor. Best regards Heinrich

1 0

Broken build on OpenBSD
by Mark Kettenis 07 Mar '21

07 Mar '21

Hi Simon, Commit c5819701a3de61e2ba2ef7ad0b616565b32305e5 broke the build on OpenBSD and probably other non-Linux systems. ENODATA, which is now used in fit_check_format(), isn't defined. It isn't part of POSIX[1] and generally not available on BSD-derived systems. Could you pick another error code for this case? Thanks, Mark [1] It is mentioned in the Open Group Base Specification, however it is part of the obsolete XSI STREAMS extension which was never part of POSIX proper.

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