March 2021 - U-Boot

[PATCH 0/4] Add WATCHDOG_RESET() in MTD framework and STM32 QSPI driver
by Patrice Chotard 12 Mar '21

12 Mar '21

In case of large area read/write/erase on spi nor and spi nand, watchdog may occurs depending on watchdog timeout and MTD device size. Some of these use-cases has been reproduced with stm32mp157-ev1 board. To prevent this situation, WATHDOG_RESET() are added at several location: - Add WATCHDOG_RESET() in spi_nor_erase() and spi_nor_write() - Add WATCHDOG_RESET() in _stm32_qspi_read_fifo() - Add WATCHDOG_RESET() in nanddev_mtd_erase() - Add WATCHDOG_RESET() in spinand_mtd_read() and spinand_mtd_erase() Patrice Chotard (4): mtd: spi-nor: Add WATCHDOG_RESET() in spi_nor_core callbacks spi: stm32_qspi: Add WATCHDOG_RESET in _stm32_qspi_read_fifo() mtd: nand: Add WATCHDOG_RESET() in nanddev_mtd_erase() mtd: spinand: Add WATCHDOG_RESET() in spinand_mtd_read/write() drivers/mtd/nand/core.c | 2 ++ drivers/mtd/nand/spi/core.c | 3 +++ drivers/mtd/spi/spi-nor-core.c | 3 +++ drivers/spi/stm32_qspi.c | 2 ++ 4 files changed, 10 insertions(+) -- 2.17.1

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[PATCH 1/2] configs: stm32: Remove BOARD_EARLY_INIT_F and BOARD_LATE_INIT for stm32 boards
by Patrice Chotard 12 Mar '21

12 Mar '21

These flags was defined and callbacks linked to these flags are empty and only returning 0. Remove BOARD_EARLY_INIT_F and BOARD_LATE_INIT flags for these stm32 boards. Signed-off-by: Patrice Chotard <patrice.chotard(a)foss.st.com> --- configs/stm32f429-discovery_defconfig | 1 - configs/stm32f429-evaluation_defconfig | 1 - configs/stm32f469-discovery_defconfig | 1 - configs/stm32f746-disco_defconfig | 1 - configs/stm32f769-disco_defconfig | 2 -- configs/stm32h743-disco_defconfig | 2 -- configs/stm32h743-eval_defconfig | 2 -- 7 files changed, 10 deletions(-) diff --git a/configs/stm32f429-discovery_defconfig b/configs/stm32f429-discovery_defconfig index 99bf64ace5..a1721fddfd 100644 --- a/configs/stm32f429-discovery_defconfig +++ b/configs/stm32f429-discovery_defconfig @@ -14,7 +14,6 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot > " diff --git a/configs/stm32f429-evaluation_defconfig b/configs/stm32f429-evaluation_defconfig index 4511ac85ce..55505ea378 100644 --- a/configs/stm32f429-evaluation_defconfig +++ b/configs/stm32f429-evaluation_defconfig @@ -11,7 +11,6 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 # CONFIG_USE_BOOTCOMMAND is not set # CONFIG_DISPLAY_CPUINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CMD_IMLS=y diff --git a/configs/stm32f469-discovery_defconfig b/configs/stm32f469-discovery_defconfig index d13794e420..37603970c2 100644 --- a/configs/stm32f469-discovery_defconfig +++ b/configs/stm32f469-discovery_defconfig @@ -11,7 +11,6 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 # CONFIG_USE_BOOTCOMMAND is not set # CONFIG_DISPLAY_CPUINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CMD_IMLS=y diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig index 106ef28b83..e6585e5e9c 100644 --- a/configs/stm32f746-disco_defconfig +++ b/configs/stm32f746-disco_defconfig @@ -18,7 +18,6 @@ CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel # CONFIG_USE_BOOTCOMMAND is not set # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CMD_GPT=y diff --git a/configs/stm32f769-disco_defconfig b/configs/stm32f769-disco_defconfig index cc3fad603b..6dc9668326 100644 --- a/configs/stm32f769-disco_defconfig +++ b/configs/stm32f769-disco_defconfig @@ -18,8 +18,6 @@ CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel # CONFIG_USE_BOOTCOMMAND is not set # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_LATE_INIT=y CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CMD_GPT=y # CONFIG_RANDOM_UUID is not set diff --git a/configs/stm32h743-disco_defconfig b/configs/stm32h743-disco_defconfig index 788da28f55..4f4144c917 100644 --- a/configs/stm32h743-disco_defconfig +++ b/configs/stm32h743-disco_defconfig @@ -15,8 +15,6 @@ CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_USE_BOOTCOMMAND is not set CONFIG_DEFAULT_FDT_FILE="stm32h743i-disco" # CONFIG_DISPLAY_CPUINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_LATE_INIT=y CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y diff --git a/configs/stm32h743-eval_defconfig b/configs/stm32h743-eval_defconfig index d752f5e792..18124859e6 100644 --- a/configs/stm32h743-eval_defconfig +++ b/configs/stm32h743-eval_defconfig @@ -15,8 +15,6 @@ CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_USE_BOOTCOMMAND is not set CONFIG_DEFAULT_FDT_FILE="stm32h743i-eval" # CONFIG_DISPLAY_CPUINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_LATE_INIT=y CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y -- 2.17.1

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[PATCH] arm: stm32mp: Fix compilation issue when SYS_DCACHE_OFF and/or SYS_DCACHE_SYS are enabled
by Patrice Chotard 12 Mar '21

12 Mar '21

From: Patrice Chotard <patrice.chotard(a)st.com> Fix following compilation issue when SYS_DCACHE_OFF and/or SYS_DCACHE_SYS are enabled : arch/arm/mach-stm32mp/cpu.c: In function ‘early_enable_caches’: arch/arm/mach-stm32mp/cpu.c:223:10: error: ‘volatile struct arch_global_data’ has no member named ‘tlb_size’ 223 | gd->arch.tlb_size = PGTABLE_SIZE; | ^ arch/arm/mach-stm32mp/cpu.c:224:10: error: ‘volatile struct arch_global_data’ has no member named ‘tlb_addr’ 224 | gd->arch.tlb_addr = (unsigned long)&early_tlb; | ^ Signed-off-by: Patrice Chotard <patrice.chotard(a)st.com> Signed-off-by: Patrice Chotard <patrice.chotard(a)foss.st.com> --- arch/arm/mach-stm32mp/cpu.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c index 3faa4ec18a..cd503b7294 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/cpu.c @@ -223,8 +223,10 @@ static void early_enable_caches(void) if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) return; - gd->arch.tlb_size = PGTABLE_SIZE; - gd->arch.tlb_addr = (unsigned long)&early_tlb; + if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) { + gd->arch.tlb_size = PGTABLE_SIZE; + gd->arch.tlb_addr = (unsigned long)&early_tlb; + } dcache_enable(); -- 2.17.1

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Regression on RPi with commit 4cbb293 (efi_loader: consider no-map property of reserved memory)
by Peter Robinson 12 Mar '21

12 Mar '21

Hey Heinrich, Not sure why this hasn't come up before as the issue with testing goes back to 2021.01-rc1/merge window, or if it's something like a newer firmware (I currently have one from 2021-02-25) but I'm seeing issues with the Raspberry Pi bringing up the secondary CPUs in Linux [1]. Ine of our users worked out it was a u-boot issue and with bisecting I got it down to down to the "efi_loader: consider no-map property of reserved memory" commit 4cbb293. I don't know too much about SMP bringing online CPUs on the RPi raspberry pi but I wonder if that commit is clobbering some piece of memory needed for that (I vaguely remember some mention of spin tables). I see it on both the original RPi3 and the 3B+, what are your thoughts? Peter [ 0.008498] Remapping and enabling EFI services. [ 0.009304] smp: Bringing up secondary CPUs ... [ 5.042966] CPU1: failed to come online [ 5.042994] CPU1: failed in unknown state : 0x0 [ 10.085989] CPU2: failed to come online [ 10.086017] CPU2: failed in unknown state : 0x0 [ 15.128975] CPU3: failed to come online [ 15.129003] CPU3: failed in unknown state : 0x0 [ 15.129114] smp: Brought up 1 node, 1 CPU [ 15.129138] SMP: Total of 1 processors activated. [1] https://bugzilla.redhat.com/show_bug.cgi?id=1921924

1 0

Dead code CONFIG_ARMADA_39X?
by Pali Rohár 12 Mar '21

12 Mar '21

Hello! I see in more U-Boot files check for ifdef CONFIG_ARMADA_39X but I do not see that CONFIG_ARMADA_39X could be defined in some header or board code. So does it mean that all code under ifdef CONFIG_ARMADA_39X is dead? Has U-Boot support for Marvell A39X SoC? If it is really dead code, should not be ifdef CONFIG_ARMADA_39X completely removed?

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[PATCH] arm: a37xx: pci: Implement workaround for the readback value of VEND_ID
by Pali Rohár 12 Mar '21

12 Mar '21

Marvell Armada 3720 Functional Errata, Guidelines, and Restrictions document describes in erratum 4.1 PCIe value of vendor ID (Ref #: 243): The readback value of VEND_ID (RD0070000h [15:0]) is 1B4Bh, while it should read 11ABh. The firmware can write the correct value, 11ABh, through VEND_ID (RD0076044h [15:0]). Implement this workaround in U-Boot PCIe controller driver aardvark for both PCI vendor id and PCI subsystem vendor id. This change affects PCI vendor id of PCIe root bridge emulated by Linux kernel. With this change Linux kernel reports correct vendor id 11AB. Signed-off-by: Pali Rohár <pali(a)kernel.org> --- drivers/pci/pci-aardvark.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index b4e1b602405f..3b9309f52c57 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -105,6 +105,7 @@ #define LTSSM_SHIFT 24 #define LTSSM_MASK 0x3f #define LTSSM_L0 0x10 +#define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44) /* PCIe core controller registers */ #define CTRL_CORE_BASE_ADDR 0x18000 @@ -529,6 +530,15 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie) reg |= (IS_RC_MSK << IS_RC_SHIFT); advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); + /* + * Replace incorrect PCI vendor id value 0x1b4b by correct value 0x11ab. + * VENDOR_ID_REG contains vendor id in low 16 bits and subsystem vendor + * id in high 16 bits. Updating this register changes readback value of + * read-only vendor id bits in PCIE_CORE_DEV_ID_REG register. Workaround + * for erratum 4.1: "The value of device and vendor ID is incorrect". + */ + advk_writel(pcie, 0x11ab11ab, VENDOR_ID_REG); + /* Set Advanced Error Capabilities and Control PF0 register */ reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX | PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN | -- 2.20.1

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[PATCH] arm: mvebu: Espressobin: Enable additional options
by Pali Rohár 12 Mar '21

12 Mar '21

Enable support for NVMe disks which can be connected to mPCIe slot via M.2 reduction. Enable btrfs and squashfs filesystems which are used by more Linux distributions. And enable fsuuid and setexpr commands which can be useful in scripting. Signed-off-by: Pali Rohár <pali(a)kernel.org> --- configs/mvebu_espressobin-88f3720_defconfig | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig index 4956199ccdac..c791f98dfea5 100644 --- a/configs/mvebu_espressobin-88f3720_defconfig +++ b/configs/mvebu_espressobin-88f3720_defconfig @@ -32,12 +32,14 @@ CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TFTPPUT=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_MVEBU_BUBT=y +CONFIG_CMD_BTRFS=y CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_SQUASHFS=y +CONFIG_CMD_FS_UUID=y CONFIG_MAC_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y @@ -65,6 +67,7 @@ CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MVNETA=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_PCI_AARDVARK=y -- 2.20.1

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[PATCH u-boot-marvell] ddr: marvell: axp: fix array types have different bounds warning
by Marek Behún 12 Mar '21

12 Mar '21

The arrays `pbs_dq_mapping`, `div_ratio1to1` and `div_ratio2to1` have different bounds declared in header files where these variables are also defined from the ones declared in source files. This causes the compiler to complain (when building with LTO): ddr3_sdram.c:24:12: warning: type of ‘pbs_dq_mapping’ does not match original declaration [-Wlto-type-mismatch] ddr3_patterns_64bit.h:911:5: note: array types have different bounds ddr3_patterns_64bit.h:911:5: note: ‘pbs_dq_mapping’ was previously declared here ddr3_dfs.c:45:11: warning: type of ‘div_ratio1to1’ does not match original declaration [-Wlto-type-mismatch] ddr3_axp_vars.h:167:4: note: array types have different bounds ddr3_axp_vars.h:167:4: note: ‘div_ratio1to1’ was previously declared here ddr3_dfs.c:46:11: warning: type of ‘div_ratio2to1’ does not match original declaration [-Wlto-type-mismatch] ddr3_axp_vars.h:196:4: note: array types have different bounds ddr3_axp_vars.h:196:4: note: ‘div_ratio2to1’ was previously declared here CI managed to trigger this as an error when compiling with LTO for AXP. Fix this by using values from the header files, which seem to be the correct ones. Signed-off-by: Marek Behún <marek.behun(a)nic.cz> --- drivers/ddr/marvell/axp/ddr3_dfs.c | 4 ++-- drivers/ddr/marvell/axp/ddr3_sdram.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/ddr/marvell/axp/ddr3_dfs.c b/drivers/ddr/marvell/axp/ddr3_dfs.c index b58c0fe01e..2a4596680b 100644 --- a/drivers/ddr/marvell/axp/ddr3_dfs.c +++ b/drivers/ddr/marvell/axp/ddr3_dfs.c @@ -42,8 +42,8 @@ extern u8 div_ratio[CLK_VCO][CLK_DDR]; extern void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps); #else extern u16 odt_dynamic[ODT_OPT][MAX_CS]; -extern u8 div_ratio1to1[CLK_CPU][CLK_DDR]; -extern u8 div_ratio2to1[CLK_CPU][CLK_DDR]; +extern u8 div_ratio1to1[CLK_VCO][CLK_DDR]; +extern u8 div_ratio2to1[CLK_VCO][CLK_DDR]; #endif extern u16 odt_static[ODT_OPT][MAX_CS]; diff --git a/drivers/ddr/marvell/axp/ddr3_sdram.c b/drivers/ddr/marvell/axp/ddr3_sdram.c index 3a266c6de4..0b150b20f3 100644 --- a/drivers/ddr/marvell/axp/ddr3_sdram.c +++ b/drivers/ddr/marvell/axp/ddr3_sdram.c @@ -21,7 +21,7 @@ extern u32 pbs_pattern_32b[2][LEN_PBS_PATTERN]; #if defined(MV88F78X60) extern u32 pbs_pattern_64b[2][LEN_PBS_PATTERN]; #endif -extern u32 pbs_dq_mapping[PUP_NUM_64BIT][DQ_NUM]; +extern u32 pbs_dq_mapping[PUP_NUM_64BIT + 1][DQ_NUM]; #if defined(MV88F78X60) || defined(MV88F672X) /* PBS locked dq (per pup) */ -- 2.26.2

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[PATCH BUGFIX u-boot-marvell] ddr: marvell: axp: align signature of mv_xor_mem_init() with a38x
by Marek Behún 12 Mar '21

12 Mar '21

In arch/arm/mach-mvebu/dram.c we always include axp's xor.h for common XOR definitions, regardless whether we compile for axp or a38x. But the declaration of this function has a different signature in axp's xor.h from the one used in a38x' implementation - one parameter is u64 instead of u32. This can result in wrong argument's being passed to that function on a38x with no one the wiser. I discovered this when building U-Boot for Turris Omnia with LTO. The compiler complains about the different signatures being thrown into the same linking process: axp/xor.h:67:5: warning: type of ‘mv_xor_mem_init’ does not match original declaration [-Wlto-type-mismatch] 67 | int mv_xor_mem_init(u32 chan, u32 start_ptr, u32 block_size, | ^ a38x/xor.c:165:5: note: type mismatch in parameter 3 165 | int mv_xor_mem_init(u32 chan, u32 start_ptr, unsigned long long | ^ a38x/xor.c:165:5: note: type ‘long long unsigned int’ should match type ‘u32’ Fix this by changing the type of the block_size argument in the axp's implementation and header file to the one used in a38x (and upstream mv-ddr-marvell). Signed-off-by: Marek Behún <marek.behun(a)nic.cz> --- drivers/ddr/marvell/axp/xor.c | 4 ++-- drivers/ddr/marvell/axp/xor.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/ddr/marvell/axp/xor.c b/drivers/ddr/marvell/axp/xor.c index 17bfe6a7bf..76aea96682 100644 --- a/drivers/ddr/marvell/axp/xor.c +++ b/drivers/ddr/marvell/axp/xor.c @@ -152,8 +152,8 @@ static int mv_xor_ctrl_set(u32 chan, u32 xor_ctrl) return MV_OK; } -int mv_xor_mem_init(u32 chan, u32 start_ptr, u32 block_size, u32 init_val_high, - u32 init_val_low) +int mv_xor_mem_init(u32 chan, u32 start_ptr, unsigned long long block_size, + u32 init_val_high, u32 init_val_low) { u32 tmp; diff --git a/drivers/ddr/marvell/axp/xor.h b/drivers/ddr/marvell/axp/xor.h index 97d1056432..a7c6ae840c 100644 --- a/drivers/ddr/marvell/axp/xor.h +++ b/drivers/ddr/marvell/axp/xor.h @@ -64,7 +64,7 @@ int mv_xor_state_get(u32 chan); void mv_sys_xor_init(MV_DRAM_INFO *dram_info); void mv_sys_xor_finish(void); int mv_xor_transfer(u32 chan, int xor_type, u32 xor_chain_ptr); -int mv_xor_mem_init(u32 chan, u32 start_ptr, u32 block_size, u32 init_val_high, - u32 init_val_low); +int mv_xor_mem_init(u32 chan, u32 start_ptr, unsigned long long block_size, + u32 init_val_high, u32 init_val_low); #endif /* __XOR_H */ -- 2.26.2

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[PATCH u-boot-marvell] ddr: marvell: a38x: Sync code with Marvell mv-ddr-marvell repository
by Pali Rohár 12 Mar '21

12 Mar '21

This syncs drivers/ddr/marvell/a38x/ with the master branch of repository https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git up to the commit 7c351731d196 ("Merge pull request #29 from pali/sync-a38x-uboot"). This patch was created by following steps: 1. Replace all a38x files in U-Boot tree by files from upstream github Marvell mv-ddr-marvell repository. 2. Run following command to omit portions not relevant for a38x and ddr3: files=drivers/ddr/marvell/a38x/* sed 's/#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)/#ifdef TRUE/' -i $files unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 -UCONFIG_APN806 \ -UCONFIG_MC_STATIC -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \ -UCONFIG_PHY_STATIC_PRINT -UCONFIG_CUSTOMER_BOARD_SUPPORT \ -UCONFIG_A3700 -UA3900 -UA80X0 -UA70X0 -DTRUE $files 3. Manually omit SPDX-License-Identifier changes from this patch as upstream license in upstream github repository contains long license texts and U-Boot is using just SPDX-License-Identifier. After applying this patch, a38x ddr3 code in upstream Marvell github repository and in U-Boot would be fully identical. So in future applying above steps could be used to sync code again. The only change in this patch is removal of dead code and some fixes with include files. Signed-off-by: Pali Rohár <pali(a)kernel.org> --- This patch depends on Marek's patch "ddr: marvell: a38x Add more space for additional info from SPD" [1]. Please apply my patch on top Marek's patch. [1] - https://patchwork.ozlabs.org/project/uboot/patch/20210226105659.3054-1-mare… --- drivers/ddr/marvell/a38x/ddr3_debug.c | 1 - drivers/ddr/marvell/a38x/ddr3_init.c | 3 --- drivers/ddr/marvell/a38x/ddr3_training.c | 11 +---------- .../ddr/marvell/a38x/ddr3_training_ip_engine.c | 8 +++----- drivers/ddr/marvell/a38x/ddr3_training_leveling.c | 1 - drivers/ddr/marvell/a38x/ddr_ml_wrapper.h | 2 -- drivers/ddr/marvell/a38x/mv_ddr_plat.c | 1 - drivers/ddr/marvell/a38x/mv_ddr_plat.h | 2 ++ drivers/ddr/marvell/a38x/mv_ddr_sys_env_lib.h | 15 --------------- drivers/ddr/marvell/a38x/xor.c | 2 -- 10 files changed, 6 insertions(+), 40 deletions(-) diff --git a/drivers/ddr/marvell/a38x/ddr3_debug.c b/drivers/ddr/marvell/a38x/ddr3_debug.c index 22e0cc4d9176..f5fc964d6f87 100644 --- a/drivers/ddr/marvell/a38x/ddr3_debug.c +++ b/drivers/ddr/marvell/a38x/ddr3_debug.c @@ -6,7 +6,6 @@ #include "ddr3_init.h" #include "mv_ddr_training_db.h" #include "mv_ddr_regs.h" -#include <log.h> u8 is_reg_dump = 0; u8 debug_pbs = DEBUG_LEVEL_ERROR; diff --git a/drivers/ddr/marvell/a38x/ddr3_init.c b/drivers/ddr/marvell/a38x/ddr3_init.c index 7488770268cf..f878b4512bfc 100644 --- a/drivers/ddr/marvell/a38x/ddr3_init.c +++ b/drivers/ddr/marvell/a38x/ddr3_init.c @@ -77,9 +77,6 @@ int ddr3_init(void) return status; } -#if defined(CONFIG_PHY_STATIC_PRINT) - mv_ddr_phy_static_print(); -#endif /* Post MC/PHY initializations */ mv_ddr_post_training_soc_config(ddr_type); diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c index 2b3af23202b6..2512b58cb7b2 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training.c +++ b/drivers/ddr/marvell/a38x/ddr3_training.c @@ -7,8 +7,6 @@ #include "mv_ddr_common.h" #include "mv_ddr_training_db.h" #include "mv_ddr_regs.h" -#include <log.h> -#include <linux/delay.h> #define GET_CS_FROM_MASK(mask) (cs_mask2_num[mask]) #define CS_CBE_VALUE(cs_num) (cs_cbe_reg[cs_num]) @@ -207,7 +205,6 @@ static int ddr3_tip_pad_inv(void) if (tm->interface_params[0].as_bus_params[sphy]. is_ck_swap == 1 && sphy == 0) { /* TODO: move this code to per platform one */ -#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X) /* clock swap for both cs0 and cs1 */ data = (INVERT_PAD << INV_PAD2_OFFS | INVERT_PAD << INV_PAD6_OFFS | @@ -219,9 +216,6 @@ static int ddr3_tip_pad_inv(void) DDR_PHY_CONTROL, PHY_CTRL_PHY_REG, data, data); -#else /* !CONFIG_ARMADA_38X && !CONFIG_ARMADA_39X */ -#pragma message "unknown platform to configure ddr clock swap" -#endif } } @@ -2014,9 +2008,7 @@ int ddr3_tip_adll_regs_bypass(u32 dev_num, u32 reg_val1, u32 reg_val2) static int ddr3_tip_ddr3_training_main_flow(u32 dev_num) { /* TODO: enable this functionality for other platforms */ -#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X) struct init_cntr_param init_cntr_prm; -#endif int ret = MV_OK; int adll_bypass_flag = 0; u32 if_id; @@ -2050,7 +2042,6 @@ static int ddr3_tip_ddr3_training_main_flow(u32 dev_num) } /* TODO: enable this functionality for other platforms */ -#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X) if (is_adll_calib_before_init != 0) { DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("with adll calib before init\n")); @@ -2081,7 +2072,6 @@ static int ddr3_tip_ddr3_training_main_flow(u32 dev_num) return MV_FAIL; } } -#endif ret = adll_calibration(dev_num, ACCESS_TYPE_MULTICAST, 0, freq); if (ret != MV_OK) { @@ -2905,3 +2895,4 @@ unsigned int mv_ddr_misl_phy_odt_n_get(void) return odt_n; } + diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c index 5fd9a052fa0d..102f9bd633f5 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c @@ -6,8 +6,6 @@ #include "ddr3_init.h" #include "mv_ddr_regs.h" #include "ddr_training_ip_db.h" -#include <image.h> -#include <linux/delay.h> #define PATTERN_1 0x55555555 #define PATTERN_2 0xaaaaaaaa @@ -614,9 +612,9 @@ int ddr3_tip_load_pattern_to_odpg(u32 dev_num, enum hws_access_type access_type, MASK_ALL_BITS)); } - CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, - ODPG_DATA_BUFFER_OFFS_REG, - load_addr, MASK_ALL_BITS)); + CHECK_STATUS(ddr3_tip_if_write + (dev_num, access_type, if_id, + ODPG_DATA_BUFFER_OFFS_REG, load_addr, MASK_ALL_BITS)); return MV_OK; } diff --git a/drivers/ddr/marvell/a38x/ddr3_training_leveling.c b/drivers/ddr/marvell/a38x/ddr3_training_leveling.c index dadb06b31814..7f7df6794a95 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_leveling.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_leveling.c @@ -7,7 +7,6 @@ #include "mv_ddr_training_db.h" #include "ddr_training_ip_db.h" #include "mv_ddr_regs.h" -#include <linux/delay.h> #define WL_ITERATION_NUM 10 diff --git a/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h b/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h index ac9250f74ed8..735731196589 100644 --- a/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h +++ b/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h @@ -13,9 +13,7 @@ #include <asm/arch/cpu.h> #include <asm/arch/soc.h> -#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X) #define INTER_REGS_BASE SOC_REGS_PHY_BASE -#endif /* * MV_DEBUG_INIT need to be defines, otherwise the output of the diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.c b/drivers/ddr/marvell/a38x/mv_ddr_plat.c index 0d1df189e820..da0d63d4f7a4 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_plat.c +++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.c @@ -8,7 +8,6 @@ #include "mv_ddr_training_db.h" #include "mv_ddr_regs.h" #include "mv_ddr_sys_env_lib.h" -#include <linux/delay.h> #define DDR_INTERFACES_NUM 1 #define DDR_INTERFACE_OCTETS_NUM 5 diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.h b/drivers/ddr/marvell/a38x/mv_ddr_plat.h index 281d4c23013e..44998847c254 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_plat.h +++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.h @@ -6,6 +6,8 @@ #ifndef _MV_DDR_PLAT_H #define _MV_DDR_PLAT_H +#include <linux/delay.h> + #define MAX_DEVICE_NUM 1 #define MAX_INTERFACE_NUM 1 #define MAX_BUS_NUM 5 diff --git a/drivers/ddr/marvell/a38x/mv_ddr_sys_env_lib.h b/drivers/ddr/marvell/a38x/mv_ddr_sys_env_lib.h index dc6977c33455..cf5142094d31 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_sys_env_lib.h +++ b/drivers/ddr/marvell/a38x/mv_ddr_sys_env_lib.h @@ -78,20 +78,6 @@ enum suspend_wakeup_status { * set '-2' * If suspend to RAM is not supported set '-1' */ -#ifdef CONFIG_CUSTOMER_BOARD_SUPPORT -#ifdef CONFIG_ARMADA_38X -#define MV_BOARD_WAKEUP_GPIO_INFO { \ - {A38X_CUSTOMER_BOARD_ID0, -1 }, \ - {A38X_CUSTOMER_BOARD_ID0, -1 }, \ -}; -#else -#define MV_BOARD_WAKEUP_GPIO_INFO { \ - {A39X_CUSTOMER_BOARD_ID0, -1 }, \ - {A39X_CUSTOMER_BOARD_ID0, -1 }, \ -}; -#endif /* CONFIG_ARMADA_38X */ - -#else #ifdef CONFIG_ARMADA_38X #define MV_BOARD_WAKEUP_GPIO_INFO { \ @@ -109,7 +95,6 @@ enum suspend_wakeup_status { {A39X_DB_69XX_ID, -1 }, \ }; #endif /* CONFIG_ARMADA_38X */ -#endif /* CONFIG_CUSTOMER_BOARD_SUPPORT */ enum suspend_wakeup_status mv_ddr_sys_env_suspend_wakeup_check(void); u32 mv_ddr_sys_env_get_cs_ena_from_reg(void); diff --git a/drivers/ddr/marvell/a38x/xor.c b/drivers/ddr/marvell/a38x/xor.c index 98fb39eaf0fa..7bc6268293e5 100644 --- a/drivers/ddr/marvell/a38x/xor.c +++ b/drivers/ddr/marvell/a38x/xor.c @@ -347,10 +347,8 @@ void ddr3_new_tip_ecc_scrub(void) for (cs_c = 0; cs_c < max_cs; cs_c++) cs_ena |= 1 << cs_c; -#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X) /* all chip-selects are of same size */ ddr3_calc_mem_cs_size(0, &cs_mem_size_mb); -#endif cs_mem_size = cs_mem_size_mb * _1M; mv_sys_xor_init(max_cs, cs_ena, cs_mem_size, 0); total_mem_size = max_cs * cs_mem_size; -- 2.20.1

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