December 2021 - U-Boot

[PATCH] doc: rockchip: puma: update build and flash instructions
by Quentin Schulz 23 Dec '21

23 Dec '21

Long gone is the time a custom TF-A was needed for Puma, upstream TF-A works just fine now. The flashing instructions are updated to match how newer rkdeveloptool and rkbin work. Finally, rkbin provides a way to flash SPI via USB OTG interface so let's document that. Cc: Quentin Schulz <foss+u-boot(a)0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz(a)theobroma-systems.com> --- board/theobroma-systems/puma_rk3399/README | 66 ++++++++++------------ doc/README.rockchip | 27 +++------ 2 files changed, 38 insertions(+), 55 deletions(-) diff --git a/board/theobroma-systems/puma_rk3399/README b/board/theobroma-systems/puma_rk3399/README index 9b31b0b379..254c3bbe96 100644 --- a/board/theobroma-systems/puma_rk3399/README +++ b/board/theobroma-systems/puma_rk3399/README @@ -26,25 +26,17 @@ RK3399-Q7 features: Here is the step-by-step to boot to U-Boot on rk3399. -Get the Source and build ATF/Cortex-M0 binaries -=============================================== +Get the Source and build ATF binary +=================================== - > git clone git://git.theobroma-systems.com/arm-trusted-firmware.git - > git clone git://git.theobroma-systems.com/rk3399-cortex-m0.git + > git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git Compile the ATF =============== - > cd arm-trusted-firmware + > cd trusted-firmware-a > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31 - > cp build/rk3399/release/bl31.bin ../u-boot/bl31-rk3399.bin - -Compile the M0 firmware -======================= - - > cd ../rk3399-cortex-m0 - > make CROSS_COMPILE=arm-cortex_m0-eabi- - > cp rk3399m0.bin ../u-boot + > cp build/rk3399/release/bl31/bl31.elf ../u-boot/bl31.elf Compile the U-Boot ================== @@ -55,23 +47,22 @@ Compile the U-Boot Package the image ================= -Creating a SPL image for SD-Card/eMMC - > tools/mkimage -n rk3399 -T rksd -d spl/u-boot-spl.bin spl_mmc.img -Creating a SPL image for SPI-NOR - > tools/mkimage -n rk3399 -T rkspi -d spl/u-boot-spl.bin spl_nor.img -Create the FIT image containing U-Boot proper, ATF, M0 Firmware, devicetree - > make CROSS_COMPILE=aarch64-linux-gnu- +The SPL image for SD-Card/eMMC is readily available in idbloader.img at the +root of U-Boot after compilation. + +Creating an SPL image for SPI-NOR: + > tools/mkimage -n rk3399 -T rkspi -d spl/u-boot-spl.bin idbloader-spi.img Flash the image =============== Copy the SPL to offset 32k for SD/eMMC, offset 0 for NOR-Flash and the FIT -image to offset 256k card. +image to offset 256k. SD-Card ------- - > dd if=spl_mmc.img of=/dev/sdb seek=64 + > dd if=idbloader.img of=/dev/sdb seek=64 > dd if=u-boot.itb of=/dev/sdb seek=512 eMMC @@ -84,24 +75,27 @@ help of the Rockchip loader binary. > cd rkdeveloptool > autoreconf -i && ./configure && make > git clone https://github.com/rockchip-linux/rkbin.git - > ./rkdeveloptool db rkbin/rk33/rk3399_loader_v1.08.106.bin - > ./rkdeveloptool wl 64 ../spl_mmc.img + > cd rkbin + > ./tools/boot_merger RKBOOT/RK3399MINIALL.ini + > cd .. + > ./rkdeveloptool db rkbin/rk3399_loader_v1.25.126.bin + > ./rkdeveloptool wl 64 ../idbloader.img > ./rkdeveloptool wl 512 ../u-boot.itb NOR-Flash --------- -Writing the SPI NOR Flash requires a running U-Boot. For the sake of simplicity -we assume you have a SD-Card with a partition containing the required files -ready. - - > load mmc 1:1 ${kernel_addr_r} spl_nor.img - > sf probe - > sf erase 0 +$filesize - > sf write $kernel_addr_r 0 ${filesize} - > load mmc 1:1 ${kernel_addr_r} u-boot.itb - > sf erase 0x40000 +$filesize - > sf write $kernel_addr_r 0x40000 ${filesize} - +rkdeveloptool allows to flash the on-board SPI via the USB OTG interface with +help of the Rockchip loader binary. -Reboot the system and you should see a U-Boot console on UART0 (115200n8). + > git clone https://github.com/rockchip-linux/rkdeveloptool + > cd rkdeveloptool + > autoreconf -i && ./configure && make + > git clone https://github.com/rockchip-linux/rkbin.git + > cd rkbin + > ./tools/boot_merger RKBOOT/RK3399MINIALL_SPINOR.ini + > cd .. + > ./rkdeveloptool db rkbin/rk3399_loader_spinor_v1.25.114.bin + > ./rkdeveloptool ef + > ./rkdeveloptool wl 0 ../idbloader-spi.img + > ./rkdeveloptool wl 512 ../u-boot.itb diff --git a/doc/README.rockchip b/doc/README.rockchip index 154166ec78..52b5140eca 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -81,30 +81,19 @@ Building - Compile ATF - For Puma board. + => git clone https://github.com/ARM-software/arm-trusted-firmware.git + => cd arm-trusted-firmware - => git clone git://git.theobroma-systems.com/arm-trusted-firmware.git - => cd arm-trusted-firmware - => make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31 + (export cross compiler path for Cortex-M0 MCU likely arm-none-eabi-) + => make realclean + => make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 - (export bl31.bin) - => export BL31=/path/to/arm-trusted-firmware/build/rk3399/release/bl31/bl31.bin - - For rest of rk3399 boards. - - => git clone https://github.com/ARM-software/arm-trusted-firmware.git - => cd arm-trusted-firmware - - (export cross compiler path for Cortex-M0 MCU likely arm-none-eabi-) - => make realclean - => make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 - - (export bl31.elf) - => export BL31=/path/to/arm-trusted-firmware/build/rk3399/release/bl31/bl31.elf + (export bl31.elf) + => export BL31=/path/to/arm-trusted-firmware/build/rk3399/release/bl31/bl31.elf - Compile PMU M0 firmware - This is optional for most of the rk3399 boards and required only for Puma board. + This is optional for most of the rk3399 boards. => git clone git://git.theobroma-systems.com/rk3399-cortex-m0.git => cd rk3399-cortex-m0 -- 2.33.1

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[PATCH v1 1/3] arm: xea: Modify board code to generate single binary u-boot
by Lukasz Majewski 23 Dec '21

23 Dec '21

This change provides the possibility to build XEA (imx287 based) board U-Boot as a single binary (without support for CONFIG_SPL_FRAMEWORK). The generated u-boot.sb can be used in the factory environment to for example perform initial setup or HW testing. It can be used with 'uuu' utility (SDPS: boot -f /srv/tftp/xea/u-boot.sb) The board_init_ll() is used in arch/arm/cpu/arm926ejs/mxs/start.S, which is utilized when CONFIG_SPL_FRAMEWORK is disabled. However, when it is enabled the arch/arm/cpu/arm926ejs/start.S is used, which requires the lowlevel_init() function. Signed-off-by: Lukasz Majewski <lukma(a)denx.de> --- board/liebherr/xea/spl_xea.c | 8 ++++++++ board/liebherr/xea/xea.c | 3 ++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/board/liebherr/xea/spl_xea.c b/board/liebherr/xea/spl_xea.c index 192f68fca5f..5ee561b8b78 100644 --- a/board/liebherr/xea/spl_xea.c +++ b/board/liebherr/xea/spl_xea.c @@ -290,6 +290,13 @@ u32 mxs_dram_vals[] = { 0x00000000, 0xffffffff }; +/* #ifndef CONFIG_SPL_FRAMEWORK */ +#if !CONFIG_IS_ENABLED(FRAMEWORK) +void board_init_ll(const u32 arg, const uint32_t *resptr) +{ + mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); +} +#else void lowlevel_init(void) { struct mxs_pinctrl_regs *pinctrl_regs = @@ -301,3 +308,4 @@ void lowlevel_init(void) mxs_common_spl_init(0, NULL, iomux_setup, ARRAY_SIZE(iomux_setup)); } +#endif diff --git a/board/liebherr/xea/xea.c b/board/liebherr/xea/xea.c index cd11b0ada77..685e2e26a18 100644 --- a/board/liebherr/xea/xea.c +++ b/board/liebherr/xea/xea.c @@ -58,7 +58,8 @@ static void init_clocks(void) mxs_set_sspclk(MXC_SSPCLK3, 96000, 0); } -#ifdef CONFIG_SPL_BUILD +/* #if CONFIG_SPL_BUILD && CONFIG_SPL_FRAMEWORK */ +#if CONFIG_IS_ENABLED(BUILD) && CONFIG_IS_ENABLED(FRAMEWORK) void board_init_f(ulong arg) { init_clocks(); -- 2.20.1

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[PATCH v2 00/16] Sync NXP LS1028A-RDB device trees between U-Boot and Linux
by Vladimir Oltean 23 Dec '21

23 Dec '21

The changes were intended to be minimal, but unfortunately I discovered some other stuff as well: - we need to make some changes to the compatible strings of RTC devices and I2C muxes. This has ramifications to other NXP boards which were also updated. - I broke Ethernet on LS1028A boards through a patch that is currently in Ramon's tree. Therefore this patch set is a bit larger than would be otherwise expected. The Linux device tree changes have just been posted by me here and are currently in flight, but they are rather small so I don't expect too much pushback on them: https://lore.kernel.org/linux-arm-kernel/20211202141528.2450169-5-vladimir.… I've also triggered an Azure CI build with these changes: https://github.com/u-boot/u-boot/pull/102 and it appears that 2 tests fail due to external causes: 1. https://dev.azure.com/u-boot/u-boot/_build/results?buildId=3283&view=logs&j… 2. https://dev.azure.com/u-boot/u-boot/_build/results?buildId=3283&view=logs&j… Unable to find image 'trini/u-boot-gitlab-ci-runner:focal-20211006-14Nov2021' locally docker: Error response from daemon: Head "https://registry-1.docker.io/v2/trini/u-boot-gitlab-ci-runner/manifests/foc…": received unexpected HTTP status: 502 Bad Gateway. The other tests seem to pass. Cc: Heiko Schocher <hs(a)denx.de> Cc: Simon Glass <sjg(a)chromium.org> Cc: Ramon Fried <rfried.dev(a)gmail.com> Vladimir Oltean (16): i2c: muxes: pca954x: add PCA9847 variant rtc: pcf2127: sync with Linux compatible strings arm: dts: ls1088a-qds: use Linux compatible string for RTC arm: dts: ls1088a-rdb: use Linux compatible string for RTC arm: dts: lx2160a-qds: use Linux compatible string for RTC arm: dts: ls1028a-qds: use Linux compatible string for RTC arm: dts: ls1028a-rdb: use Linux compatible string for RTC arm: dts: lx2160a-rdb: use Linux compatible string for RTC rtc: pcf2127: remove U-Boot specific compatible string arm: dts: ls1028a-rdb: sort nodes alphabetically arm: dts: ls1028a-rdb: sync Ethernet device tree nodes with Linux arm: dts: ls1028a-rdb: disable DSPI nodes arm: dts: ls1028a-rdb: disable I2C buses 1 through 7 arm: dts: ls1028a-rdb: enable PCIe controllers from U-Boot dtsi arm: dts: ls1028a-rdb: sync device tree with Linux arm: dts: ls1028a-qds: declare in-band autoneg for Ethernet ports .../dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi | 1 + .../dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi | 1 + .../fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi | 4 + .../dts/fsl-ls1028a-qds-9999-sch-24801.dtsi | 4 + .../fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi | 4 + .../fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi | 4 + arch/arm/dts/fsl-ls1028a-qds.dtsi | 2 +- arch/arm/dts/fsl-ls1028a-rdb-u-boot.dtsi | 15 + arch/arm/dts/fsl-ls1028a-rdb.dts | 295 ++++++++++++------ arch/arm/dts/fsl-ls1088a-qds.dtsi | 2 +- arch/arm/dts/fsl-ls1088a-rdb.dts | 2 +- arch/arm/dts/fsl-lx2160a-qds.dtsi | 2 +- arch/arm/dts/fsl-lx2160a-rdb.dts | 2 +- drivers/i2c/muxes/pca954x.c | 9 +- drivers/rtc/pcf2127.c | 4 +- 15 files changed, 242 insertions(+), 109 deletions(-) create mode 100644 arch/arm/dts/fsl-ls1028a-rdb-u-boot.dtsi -- 2.25.1

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[PATCH] board: ls1088a: update ifc node name to be memory-controller
by Jianpeng Bu 23 Dec '21

23 Dec '21

LF-4834: kernel boot failed IFC-NOR and QSPI are muxed on SoC. So disable IFC node in dts if QSPI is enabled or disable QSPI node in dts in case QSPI is not enabled. The nor-flash offset in uboot is invalid because of the following changes: project: linux-nxp * commit 'b6bd3c1f6ce17353601187c51424c18257735cc3': arm64: dts: freescale: update ifc node name to be memory-controller Need to modify "ifc/nor" to "memory-controller/nor" in fdt_path_offset(). Signed-off-by: Jianpeng Bu <jianpeng.bu(a)nxp.com> --- board/freescale/ls1088a/ls1088a.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index f5dc449d89..7b5f8d2486 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2017-2018 NXP + * Copyright 2017-2018, 2021 NXP */ #include <common.h> #include <env.h> @@ -923,10 +923,10 @@ void fsl_fdt_fixup_flash(void *fdt) } if (disable_ifc) { - offset = fdt_path_offset(fdt, "/soc/ifc/nor"); + offset = fdt_path_offset(fdt, "/soc/memory-controller/nor"); if (offset < 0) - offset = fdt_path_offset(fdt, "/ifc/nor"); + offset = fdt_path_offset(fdt, "/memory-controller/nor"); } else { offset = fdt_path_offset(fdt, "/soc/quadspi"); @@ -936,10 +936,10 @@ void fsl_fdt_fixup_flash(void *fdt) #else #ifdef CONFIG_FSL_QSPI - offset = fdt_path_offset(fdt, "/soc/ifc/nor"); + offset = fdt_path_offset(fdt, "/soc/memory-controller/nor"); if (offset < 0) - offset = fdt_path_offset(fdt, "/ifc/nor"); + offset = fdt_path_offset(fdt, "/memory-controller/nor"); #else offset = fdt_path_offset(fdt, "/soc/quadspi"); -- 2.25.1

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[PATCH 1/2] fsl-layerscape: add dtb overlay feature
by Sahil Malhotra 23 Dec '21

23 Dec '21

From: Sahil Malhotra <sahil.malhotra(a)nxp.com> This patch enables the DTB overlay feature for LS platforms. Signed-off-by: Sahil Malhotra <sahil.malhotra(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 + arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c | 39 +++++++++++++++++++ arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h | 10 +++++ arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 12 ++++++ .../cpu/armv8/fsl-layerscape/lowlevel_init.S | 25 ++++++++++++ 5 files changed, 87 insertions(+) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index 598c36ee66..97f1f291dd 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -7,6 +7,7 @@ obj-y += lowlevel.o obj-y += soc.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_MP) += mp.o spintable.o +obj-$(CONFIG_OF_LIBFDT_OVERLAY) += lowlevel_init.o dt_optee.o obj-$(CONFIG_OF_LIBFDT) += fdt.o endif obj-$(CONFIG_SPL) += spl.o diff --git a/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c new file mode 100644 index 0000000000..2418ad09c7 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ +#include <common.h> +#include <errno.h> +#include <fdt_support.h> +#include <linux/sizes.h> +#include "dt_optee.h" + +int ft_add_optee_overlay(void *fdt, struct bd_info *bd) +{ + int ret = 0; + + /* + * No BL32_BASE passed means no TEE running, so no + * need to add optee node in dts + */ + if (!rom_pointer[0]) { + debug("No BL32_BASE passed means no TEE running\n"); + return ret; + } + + if (rom_pointer[2]) { + debug("OP-TEE: applying overlay on 0x%lx\n", rom_pointer[2]); + ret = fdt_check_header((void *)rom_pointer[2]); + if (ret == 0) { + /* Copy the fdt overlay to next 1M and use copied overlay */ + memcpy((void *)(rom_pointer[2] + SZ_1M), (void *)rom_pointer[2], + fdt_totalsize((void *)rom_pointer[2])); + ret = fdt_overlay_apply_verbose(fdt, (void *)(rom_pointer[2] + SZ_1M)); + if (ret == 0) { + debug("Overlay applied with success"); + fdt_pack(fdt); + } + } + } + return ret; +} diff --git a/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h new file mode 100644 index 0000000000..d1ff25d531 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ +#ifndef __DT_OPTEE_H__ +#define __DT_OPTEE_H__ + +extern unsigned long rom_pointer[]; +int ft_add_optee_overlay(void *fdt, struct bd_info *bd); +#endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index f1624ff30a..0824c62264 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -31,6 +31,7 @@ #endif #include <asm/arch/speed.h> #include <fsl_qbman.h> +#include "dt_optee.h" int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc) { @@ -698,3 +699,14 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) fdt_fixup_ecam(blob); #endif } + +#ifdef CONFIG_OF_SYSTEM_SETUP +int ft_system_setup(void *blob, struct bd_info *bd) +{ +#ifdef CONFIG_OF_LIBFDT_OVERLAY + return ft_add_optee_overlay(blob, bd); +#else + return 0; +#endif +} +#endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S new file mode 100644 index 0000000000..1d6a2d85fa --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +#include <config.h> + +.align 8 +.global rom_pointer +rom_pointer: + .space 32 + +/* + * Routine: save_boot_params (called after reset from start.S) + */ + +.global save_boot_params +save_boot_params: + /* The firmware provided FDT address can be found in r2/x0 */ + adr x0, rom_pointer + stp x1, x2, [x0], #16 + stp x3, x4, [x0], #16 + + ldr x1, =save_boot_params_ret + br x1 -- 2.17.1

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[PATCH] arm: socfpga: vining: Unmount UBIFS and detach UBI in ubi_load script
by Marek Vasut 23 Dec '21

23 Dec '21

Clean up in ubiload script. Unmount UBIFS from which kernel image was loaded and detach UBI on which the UBIFS is located, otherwise message similar to the following is printed just before booting kernel: Removing MTD device #7 (rootfs) with use count 1 Error when deleting partition "rootfs" (-16) Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Siew Chin Lim <elly.siew.chin.lim(a)intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> Cc: Tien Fong Chee <tien.fong.chee(a)intel.com> --- include/configs/socfpga_vining_fpga.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h index d9d0a4af5ac..5c0ed07c427 100644 --- a/include/configs/socfpga_vining_fpga.h +++ b/include/configs/socfpga_vining_fpga.h @@ -118,7 +118,8 @@ "addargs=run addcons addmtd addmisc\0" \ "ubiload=" \ "ubi part ${ubimtd} ; ubifsmount ${ubipart} ; " \ - "ubifsload ${kernel_addr_r} /boot/${bootfile}\0" \ + "ubifsload ${kernel_addr_r} /boot/${bootfile} ; " \ + "ubifsumount ; ubi detach\0" \ "netload=" \ "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \ "miscargs=nohlt panic=1\0" \ -- 2.34.1

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Please pull u-boot-marvell/next
by Stefan Roese 23 Dec '21

23 Dec '21

Hi Tom, please pull the following Marvell MVEBU related patches into next: ---------------------------------------------------------------- - pci_mvebu: Misc improvements and cleanup (Pali) - turris_mox: Remove extra newline after module topology (Marek) ---------------------------------------------------------------- Here the Azure build, without any issues: https://dev.azure.com/sr0718/u-boot/_build/results?buildId=142&view=results Thanks, Stefan The following changes since commit 4afab30caea3211032710c4298a8839d3254e7f7: Merge tag 'v2022.01-rc4' into next (2021-12-20 17:12:04 -0500) are available in the Git repository at: git@source.denx.de:u-boot/custodians/u-boot-marvell.git next for you to fetch changes up to 6488939b4a78e03999c15314bed358b4e26940d0: arm: mvebu: turris_mox: Remove extra newline after module topology (2021-12-21 07:42:01 +0100) ---------------------------------------------------------------- Marek Behún (1): arm: mvebu: turris_mox: Remove extra newline after module topology Pali Rohár (3): pci: pci_mvebu: Move setup for BAR[0] where other BARs are setup pci: pci_mvebu: Replace MBUS_PCI_*_SIZE by resource_size() pci: pci_mvebu: Remove unused DECLARE_GLOBAL_DATA_PTR board/CZ.NIC/turris_mox/turris_mox.c | 3 --- drivers/pci/pci_mvebu.c | 27 +++++++++++++-------------- 2 files changed, 13 insertions(+), 17 deletions(-)

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[PATCH] usb: ehci-mx6: Enable OTG detection on imx8mm and imx8mn
by Adam Ford 22 Dec '21

22 Dec '21

The imx8mm and imx8mn appear compatible with imx7d-usb flags in the OTG driver. If the dr_mode is defined as host or peripheral, the device appears to operate correctly, however the auto host/peripheral detection results in an error. Simply adding checks in ehci_usb_phy_mode for 8mm and 8mn in ehci_usb_phy_mode is not enough, because ehci_usb_of_to_plat is run before the clock is enabled which results in a hang. Enable the USB clock in ehci_usb_of_to_plat and add checks in ehci_usb_phy_mode for 8mm and 8mn to enable auto detection of the OTG mode on i.MX8M Mini and Nano. Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index 1bd6147c76..fa0798171b 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -543,7 +543,7 @@ static int ehci_usb_phy_mode(struct udevice *dev) plat->init_type = USB_INIT_DEVICE; else plat->init_type = USB_INIT_HOST; - } else if (is_mx7()) { + } else if (is_mx7() || is_imx8mm() || is_imx8mn()) { phy_status = (void __iomem *)(addr + USBNC_PHY_STATUS_OFFSET); val = readl(phy_status); @@ -561,11 +561,30 @@ static int ehci_usb_phy_mode(struct udevice *dev) static int ehci_usb_of_to_plat(struct udevice *dev) { +#if CONFIG_IS_ENABLED(CLK) + int ret = 0; + struct ehci_mx6_priv_data *priv = dev_get_priv(dev); + + ret = clk_get_by_index(dev, 0, &priv->clk); + if (ret < 0) + return ret; + + ret = clk_enable(&priv->clk); + if (ret) + return ret; +#endif + struct usb_plat *plat = dev_get_plat(dev); enum usb_dr_mode dr_mode; dr_mode = usb_get_dr_mode(dev_ofnode(dev)); +#if CONFIG_IS_ENABLED(CLK) + ret = clk_disable(&priv->clk); + if (ret) + return ret; +#endif + switch (dr_mode) { case USB_DR_MODE_HOST: plat->init_type = USB_INIT_HOST; -- 2.32.0

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[PATCH] console: usb: kbd: Limit poll frequency to improve performance
by Thomas Watson 22 Dec '21

22 Dec '21

Using the XHCI driver, the function `usb_kbd_poll_for_event` takes 30-40ms to run. The exact time is dependent on the polling interval the keyboard requests in its descriptor, and likely cannot be significantly reduced without major rework to the XHCI driver. The U-Boot EFI console service sets a timer to poll the keyboard every 5 microseconds, and this timer is checked every time a block is read off disk. The net effect is that, on my system, loading a ~40MiB kernel and initrd takes about 62 seconds with a slower keyboard and 53 seconds with a faster one, with the vast majority of the time spent polling the keyboard. To solve this problem, this patch adds a 20ms delay between consecutive calls to `usb_kbd_poll_for_event`. This is sufficient to reduce the total loading time to under half a second for both keyboards, and does not impact the perceived keystroke latency. Signed-off-by: Thomas Watson <twatson52(a)icloud.com> --- common/usb_kbd.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/common/usb_kbd.c b/common/usb_kbd.c index afad260d3d..0131b7dfab 100644 --- a/common/usb_kbd.c +++ b/common/usb_kbd.c @@ -118,7 +118,7 @@ struct usb_kbd_pdata { extern int __maybe_unused net_busy_flag; /* The period of time between two calls of usb_kbd_testc(). */ -static unsigned long __maybe_unused kbd_testc_tms; +static unsigned long kbd_testc_tms; /* Puts character in the queue and sets up the in and out pointer. */ static void usb_kbd_put_queue(struct usb_kbd_pdata *data, u8 c) @@ -394,21 +394,31 @@ static int usb_kbd_testc(struct stdio_dev *sdev) struct usb_device *usb_kbd_dev; struct usb_kbd_pdata *data; + /* + * Polling the keyboard for an event can take dozens of milliseconds. Add a + * delay between polls to avoid blocking activity which polls rapidly, like + * the UEFI console timer. + */ + unsigned long poll_delay = CONFIG_SYS_HZ / 50; + #ifdef CONFIG_CMD_NET /* * If net_busy_flag is 1, NET transfer is running, * then we check key-pressed every second (first check may be * less than 1 second) to improve TFTP booting performance. */ - if (net_busy_flag && (get_timer(kbd_testc_tms) < CONFIG_SYS_HZ)) - return 0; - kbd_testc_tms = get_timer(0); + if (net_busy_flag) + poll_delay = CONFIG_SYS_HZ; #endif + dev = stdio_get_by_name(sdev->name); usb_kbd_dev = (struct usb_device *)dev->priv; data = usb_kbd_dev->privptr; - usb_kbd_poll_for_event(usb_kbd_dev); + if (get_timer(kbd_testc_tms) >= poll_delay) { + usb_kbd_poll_for_event(usb_kbd_dev); + kbd_testc_tms = get_timer(0); + } return !(data->usb_in_pointer == data->usb_out_pointer); } -- 2.17.1

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[PATCH v1 0/4] usb: ehci: Conversion of ehci-mxs driver to support DM (i.MX28)
by Lukasz Majewski 22 Dec '21

22 Dec '21

This patch series focuses on converting ehci-mxs driver to support DM and work with i.MX28 (SoC). The XEA board has been used to test the proposed code with USB pen drive. Lukasz Majewski (4): usb: Modify Kconfig of the USB_EHCI_MXS to use this driver with imx28 usb: ehci: Refactor the ehci_mxs_toggle_clock function to be reused with DM usb: ehci: Move common mxs code to separate functions (ehci_hcd_{stop|start}) usb: ehci: dm: Convert i.MX28 ehci code to driver model drivers/usb/host/Kconfig | 7 +- drivers/usb/host/ehci-mxs.c | 328 ++++++++++++++++++++++++++++-------- 2 files changed, 266 insertions(+), 69 deletions(-) -- 2.20.1

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