December 2021 - U-Boot

[PATCH 1/4] rockchip: mkimage: rename RK_SIGNATURE to RK_MAGIC
by Kever Yang 24 Dec '21

24 Dec '21

The first 4byte of idbimage is a magic number instead of signature, correct it. Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- tools/rkcommon.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/tools/rkcommon.c b/tools/rkcommon.c index d55cd2c2d5..1274293acf 100644 --- a/tools/rkcommon.c +++ b/tools/rkcommon.c @@ -15,7 +15,7 @@ #include "rkcommon.h" enum { - RK_SIGNATURE = 0x0ff0aa55, + RK_MAGIC = 0x0ff0aa55, }; /** @@ -24,14 +24,14 @@ enum { * This is stored at SD card block 64 (where each block is 512 bytes, or at * the start of SPI flash. It is encoded with RC4. * - * @signature: Signature (must be RKSD_SIGNATURE) + * @magic: Magic (must be RK_MAGIC) * @disable_rc4: 0 to use rc4 for boot image, 1 to use plain binary * @init_offset: Offset in blocks of the SPL code from this header * block. E.g. 4 means 2KB after the start of this header. * Other fields are not used by U-Boot */ struct header0_info { - uint32_t signature; + uint32_t magic; uint8_t reserved[4]; uint32_t disable_rc4; uint16_t init_offset; @@ -224,7 +224,7 @@ static void rkcommon_set_header0(void *buf, struct image_tool_params *params) uint32_t init_boot_size; memset(buf, '\0', RK_INIT_OFFSET * RK_BLK_SIZE); - hdr->signature = cpu_to_le32(RK_SIGNATURE); + hdr->magic = cpu_to_le32(RK_MAGIC); hdr->disable_rc4 = cpu_to_le32(!rkcommon_need_rc4_spl(params)); hdr->init_offset = cpu_to_le16(RK_INIT_OFFSET); hdr->init_size = cpu_to_le16(spl_params.init_size / RK_BLK_SIZE); @@ -294,7 +294,7 @@ static int rkcommon_parse_header(const void *buf, struct header0_info *header0, memcpy((void *)header0, buf, sizeof(struct header0_info)); rc4_encode((void *)header0, sizeof(struct header0_info), rc4_key); - if (le32_to_cpu(header0->signature) != RK_SIGNATURE) + if (le32_to_cpu(header0->magic) != RK_MAGIC) return -EPROTO; /* We don't support RC4 encoded image payloads here, yet... */ -- 2.25.1

1 3

[PATCH] configs: rock-pi-4: Enable rockchip efuse support
by Sjoerd Simons 24 Dec '21

24 Dec '21

Enable efuse support for reading the cpuid#, serial# and generate a board unique mac address Signed-off-by: Sjoerd Simons <sjoerd(a)collabora.com> --- configs/rock-pi-4-rk3399_defconfig | 1 + configs/rock-pi-4c-rk3399_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index 9366eba8f15..032b9086699 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -31,6 +31,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y +CONFIG_ROCKCHIP_EFUSE=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_MMC_DW=y diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig index ac045d1492f..6f5e8666b0d 100644 --- a/configs/rock-pi-4c-rk3399_defconfig +++ b/configs/rock-pi-4c-rk3399_defconfig @@ -31,6 +31,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y +CONFIG_ROCKCHIP_EFUSE=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y CONFIG_MMC_DW=y -- 2.34.0

2 1

[PATCH] rockchip: boot_mode: fix fastboot command
by John Keeping 24 Dec '21

24 Dec '21

The USB controller index must be separated from the type argument, otherwise the preboot command fails with the error: Error: Wrong USB controller index format Add the missing space to fix fastboot mode here. Signed-off-by: John Keeping <john(a)metanate.com> --- arch/arm/mach-rockchip/boot_mode.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/boot_mode.c b/arch/arm/mach-rockchip/boot_mode.c index 2158934159..1a1a887fc2 100644 --- a/arch/arm/mach-rockchip/boot_mode.c +++ b/arch/arm/mach-rockchip/boot_mode.c @@ -95,7 +95,7 @@ int setup_boot_mode(void) switch (boot_mode) { case BOOT_FASTBOOT: debug("%s: enter fastboot!\n", __func__); - env_set("preboot", "setenv preboot; fastboot usb0"); + env_set("preboot", "setenv preboot; fastboot usb 0"); break; case BOOT_UMS: debug("%s: enter UMS!\n", __func__); -- 2.34.1

2 1

[PATCH v2 0/4] rockchip: Improve support for Bob chromebook and add support for Kevin
by Alper Nebi Yasak 24 Dec '21

24 Dec '21

I have recently started testing booting U-Boot from SPI on my gru-kevin (as opposed to chainloading it from vendor coreboot + depthcharge) and brought it to a better working state based on an initial support patch from Marty [1][2] and some follow-up work by Simon [3]. I tried to keep them as the git author when I took things from their work, but squashing other changes into those and rewriting commit messages makes things a bit weird in my opinion, especially for keeping their signoff. Do tell me if there is a better way to that. As the Kevin and Bob boards are very similar, I assumed the config and devicetree changes will be appropriate for Bob as well, and applied them to it first. I do not have a Bob, so could not test on one myself, but Simon did test an earlier version of this and it appears to work [4]. Other useful things for these boards: - Patch to fix a hang when usb controllers exit [5] (or [6]) - Series to support HS400ES mode as HS400 training fails [7] - Hack to skip eMMC reinitialization so it keeps working [8] [1] https://patchwork.ozlabs.org/patch/1053386/ [2] https://patchwork.ozlabs.org/comment/2488899/ [3] https://github.com/sjg20/u-boot/commits/kevin [4] https://patchwork.ozlabs.org/comment/2799106/ [5] https://patchwork.ozlabs.org/project/uboot/patch/20210406151059.1187379-1-i… [6] https://patchwork.ozlabs.org/project/uboot/patch/20211210200124.19226-1-alp… [7] https://patchwork.ozlabs.org/project/uboot/list/?series=269768 [8] https://patchwork.ozlabs.org/comment/2779784/ Changes in v2: - Drop unnecessary ifdef. - Clarify commit message regarding 'values set in coreboot'. - Rebase on u-boot/next, fixing conflict in board_debug_uart_init() v1: https://patchwork.ozlabs.org/project/uboot/list/?series=273848 Alper Nebi Yasak (2): rockchip: gru: Set up SoC IO domain registers rockchip: bob: Enable more configs Marty E. Plummer (1): rockchip: rk3399: Add support for chromebook_kevin Simon Glass (1): rockchip: gru: Add more devicetree settings arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-gru-kevin-u-boot.dtsi | 11 ++ arch/arm/dts/rk3399-gru-u-boot.dtsi | 55 +++++++++ arch/arm/mach-rockchip/rk3399/Kconfig | 11 ++ arch/arm/mach-rockchip/rk3399/rk3399.c | 3 +- arch/arm/mach-rockchip/spl.c | 3 +- board/google/gru/Kconfig | 16 +++ board/google/gru/MAINTAINERS | 8 ++ board/google/gru/gru.c | 54 +++++++- configs/chromebook_bob_defconfig | 27 +++- configs/chromebook_kevin_defconfig | 116 ++++++++++++++++++ doc/board/rockchip/rockchip.rst | 1 + include/configs/gru.h | 3 + include/dt-bindings/input/linux-event-codes.h | 3 +- 14 files changed, 307 insertions(+), 5 deletions(-) create mode 100644 arch/arm/dts/rk3399-gru-kevin-u-boot.dtsi create mode 100644 configs/chromebook_kevin_defconfig -- 2.34.1

3 10

[PATCH v2 1/3] arm64: dts: rockchip: px30: Move dmc into -u-boot.dtsi
by Jagan Teki 24 Dec '21

24 Dec '21

dmc node is specific to U-Boot, it is always better practice to maintain U-Boot specific nodes into -u-boot.dtsi files in order to maintain Linux dts file sync compatibility. Move the dmc into px30-u-boot.dtsi, also add dmc node explicitly in rk3326-odroid-go2-u-boot.dtsi since it is using px30.dts. Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- Changes for v2: - none arch/arm/dts/px30-u-boot.dtsi | 10 ++++++---- arch/arm/dts/px30.dtsi | 5 ----- arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 10 ++++++---- 3 files changed, 12 insertions(+), 13 deletions(-) diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi index 029c8fbd8d..bbed7dcde5 100644 --- a/arch/arm/dts/px30-u-boot.dtsi +++ b/arch/arm/dts/px30-u-boot.dtsi @@ -13,6 +13,12 @@ u-boot,spl-boot-order = &emmc, &sdmmc; }; + dmc { + u-boot,dm-pre-reloc; + compatible = "rockchip,px30-dmc", "syscon"; + reg = <0x0 0xff2a0000 0x0 0x1000>; + }; + rng: rng@ff0b0000 { compatible = "rockchip,cryptov2-rng"; reg = <0x0 0xff0b0000 0x0 0x4000>; @@ -20,10 +26,6 @@ }; }; -&dmc { - u-boot,dm-pre-reloc; -}; - &uart2 { clock-frequency = <24000000>; u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/px30.dtsi b/arch/arm/dts/px30.dtsi index ef706486dc..ef77b7b997 100644 --- a/arch/arm/dts/px30.dtsi +++ b/arch/arm/dts/px30.dtsi @@ -151,11 +151,6 @@ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; - dmc: dmc { - compatible = "rockchip,px30-dmc", "syscon"; - reg = <0x0 0xff2a0000 0x0 0x1000>; - }; - display_subsystem: display-subsystem { compatible = "rockchip,display-subsystem"; ports = <&vopb_out>, <&vopl_out>; diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi index bffaa3edf3..63d87e16e1 100644 --- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi +++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi @@ -16,6 +16,12 @@ serial2 = &uart2; spi0 = &sfc; }; + + dmc { + u-boot,dm-pre-reloc; + compatible = "rockchip,px30-dmc", "syscon"; + reg = <0x0 0xff2a0000 0x0 0x1000>; + }; }; /* U-Boot clk driver for px30 cannot set GPU_CLK */ @@ -32,10 +38,6 @@ <100000000>, <17000000>; }; -&dmc { - u-boot,dm-pre-reloc; -}; - &gpio0 { u-boot,dm-pre-reloc; }; -- 2.25.1

2 7

[PATCH] power: pmic/fan53555: allow dm be omitted by SPL
by Quentin Schulz 24 Dec '21

24 Dec '21

Allow the dm driver be omitted by SPL. Cc: Quentin Schulz <foss+u-boot(a)0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz(a)theobroma-systems.com> --- drivers/power/pmic/Kconfig | 14 ++++++++++++++ drivers/power/pmic/Makefile | 2 +- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index b9fda428df..ce0adb18a4 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -128,6 +128,20 @@ config DM_PMIC_FAN53555 The driver implements read/write operations for use with the FAN53555 regulator driver and binds the regulator driver to its node. +config SPL_DM_PMIC_FAN53555 + bool "Enable support for OnSemi FAN53555 in SPL" + depends on SPL_DM_REGULATOR && SPL_DM_I2C + select SPL_DM_REGULATOR_FAN53555 + help + This config enables implementation of driver-model PMIC + uclass features for the FAN53555 regulator. The FAN53555 is + a (family of) single-output regulators that supports + transitioning between two different output voltages based on + an voltage selection pin. + + The driver implements read/write operations for use with the FAN53555 + regulator driver and binds the regulator driver to its node. + config DM_PMIC_MP5416 bool "Enable Driver Model for PMIC MP5416" help diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index e1922df00f..401cde32cf 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -4,7 +4,7 @@ # Lukasz Majewski <l.majewski(a)samsung.com> obj-$(CONFIG_$(SPL_TPL_)DM_PMIC) += pmic-uclass.o -obj-$(CONFIG_DM_PMIC_FAN53555) += fan53555.o +obj-$(CONFIG_$(SPL_)DM_PMIC_FAN53555) += fan53555.o obj-$(CONFIG_$(SPL_)DM_PMIC_DA9063) += da9063.o obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o obj-$(CONFIG_DM_PMIC_MAX8998) += max8998.o -- 2.33.1

4 3

[PATCH] rockchip: Add initial support for the PinePhone Pro
by Martijn Braam 24 Dec '21

24 Dec '21

This is a new device by PINE64 that's very similar to the Pinebook Pro that's already supported. Specification: - Rockchip RK3399 - 4GB Dual-Channel LPDDR4 - 128GB eMMC - mSD card slot - AP6255 for 802.11ac WiFi and Bluetooth - 6 inch 720*1440 DSI display - Quectel EG25g usb modem - Type-C port with alt-mode display (DP 1.2) and PD charging. Signed-off-by: Martijn Braam <martijn(a)brixit.nl> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 44 ++ arch/arm/dts/rk3399-pinephone-pro.dts | 520 ++++++++++++++++++ arch/arm/mach-rockchip/rk3399/Kconfig | 8 + board/pine64/pinephone-pro-rk3399/Kconfig | 15 + board/pine64/pinephone-pro-rk3399/MAINTAINERS | 8 + board/pine64/pinephone-pro-rk3399/Makefile | 1 + .../pinephone-pro-rk3399.c | 57 ++ configs/pinephone-pro-rk3399_defconfig | 92 ++++ include/configs/pinephone-pro-rk3399.h | 23 + 10 files changed, 769 insertions(+) create mode 100644 arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-pinephone-pro.dts create mode 100644 board/pine64/pinephone-pro-rk3399/Kconfig create mode 100644 board/pine64/pinephone-pro-rk3399/MAINTAINERS create mode 100644 board/pine64/pinephone-pro-rk3399/Makefile create mode 100644 board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c create mode 100644 configs/pinephone-pro-rk3399_defconfig create mode 100644 include/configs/pinephone-pro-rk3399.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ed3d360bb1..3206370226 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -137,6 +137,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-nanopi-r4s.dtb \ rk3399-orangepi.dtb \ rk3399-pinebook-pro.dtb \ + rk3399-pinephone-pro.dtb \ rk3399-puma-haikou.dtb \ rk3399-roc-pc.dtb \ rk3399-roc-pc-mezzanine.dtb \ diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi new file mode 100644 index 0000000000..9d44db5978 --- /dev/null +++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Peter Robinson <pbrobinson at gmail.com> + * Copyright (C) 2021 Martijn Braam <martijn at brixit.nl> + */ + +#include "rk3399-u-boot.dtsi" +#include "rk3399-sdram-lpddr4-100.dtsi" + +/ { + aliases { + spi0 = &spi1; + }; + + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; + }; + + config { + u-boot,spl-payload-offset = <0x60000>; /* @ 384KB */ + }; +}; + +&i2c0 { + u-boot,dm-pre-reloc; +}; + +&rk818 { + u-boot,dm-pre-reloc; +}; + +&rng { + status = "okay"; +}; + +&sdhci { + max-frequency = <25000000>; + u-boot,dm-pre-reloc; +}; + +&sdmmc { + max-frequency = <20000000>; + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3399-pinephone-pro.dts b/arch/arm/dts/rk3399-pinephone-pro.dts new file mode 100644 index 0000000000..3fe1845ced --- /dev/null +++ b/arch/arm/dts/rk3399-pinephone-pro.dts @@ -0,0 +1,520 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Martijn Braam <martijn(a)brixit.nl> + */ + +/dts-v1/; +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + model = "Pine64 PinePhone Pro"; + compatible = "pine64,pinephone-pro", "rockchip,rk3399"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + }; + + /* Power tree */ + /* Root power source */ + vcc_sysin: vcc-sysin { + compatible = "regulator-fixed"; + regulator-name = "vcc_sysin"; + regulator-always-on; + regulator-boot-on; + }; + + /* Main 3.3v supply */ + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sysin>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + rk818: pmic@1c { + compatible = "rockchip,rk818"; + reg = <0x1c>; + interrupt-parent = <&gpio1>; + interrupts = <RK_PC5 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sysin>; + vcc2-supply = <&vcc_sysin>; + vcc3-supply = <&vcc_sysin>; + vcc4-supply = <&vcc_sysin>; + vcc6-supply = <&vcc_sysin>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc_sysin>; + vcc9-supply = <&vcc3v3_sys>; + + regulators { + vdd_cpu_l: DCDC_REG1 { + regulator-name = "vdd_cpu_1"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_center: DCDC_REG2 { + regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca3v0_codec: LDO_REG1 { + regulator-name = "vcca3v0_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v0_touch: LDO_REG2 { + regulator-name = "vcc3v0_touch"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_codec: LDO_REG3 { + regulator-name = "vcca1v8_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_power_on: LDO_REG4 { + regulator-name = "vcc_power_on"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_3v0: LDO_REG5 { + regulator-name = "vcc_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcc1v8_dvp: LDO_REG7 { + regulator-name = "vcc1v8_dvp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s3: LDO_REG8 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_sd: LDO_REG9 { + regulator-name = "vcc_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc3v3_s0: SWITCH_REG { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + boost_otg: DCDC_BOOST { + regulator-name = "boost_otg"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <5000000>; + }; + }; + + otg_switch: OTG_SWITCH { + regulator-name = "otg_switch"; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_pin>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel2_pin>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c3 { + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c4 { + i2c-scl-rising-time-ns = <600>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + + fusb0: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + status = "okay"; + }; +}; + +&io_domains { + status = "okay"; + + bt656-supply = <&vcc1v8_dvp>; + audio-supply = <&vcca1v8_codec>; + sdmmc-supply = <&vcc_sd>; + gpio1830-supply = <&vcc_3v0>; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc_3v0>; + status = "okay"; +}; + +&pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + fusb302x { + fusb0_int: fusb0-int { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + work_led_pin: work-led-pin { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + diy_led_pin: diy-led-pin { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_perst: pcie-perst { + rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_pwr_en: pcie-pwr-en { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vsel1_pin: vsel1-pin { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_pin: vsel2-pin { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdcard { + sdmmc0_pwr_h: sdmmc0-pwr-h { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + vcc5v0_typec_en: vcc5v0_typec_en { + rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; + vmmc-supply = <&vcc3v3_s3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 17628f9171..3ba603ca80 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -28,6 +28,13 @@ config TARGET_PINEBOOK_PRO_RK3399 with 4Gb RAM, onboard eMMC, USB-C, a USB3 and USB2 port, 1920*1080 screen and all the usual laptop features. +config TARGET_PINEPHONE_PRO_RK3399 + bool "PinePhone Pro" + help + PinePhone Pro is a phone based on the Rockchip rk3399 SoC + with 4Gb RAM, onboard eMMC, USB-C, a headphone jack, + 720x1440 screen and an external Quectel USB modem. + config TARGET_PUMA_RK3399 bool "Theobroma Systems RK3399-Q7 (Puma)" help @@ -154,6 +161,7 @@ endif # BOOTCOUNT_LIMIT source "board/firefly/roc-pc-rk3399/Kconfig" source "board/google/gru/Kconfig" source "board/pine64/pinebook-pro-rk3399/Kconfig" +source "board/pine64/pinephone-pro-rk3399/Kconfig" source "board/pine64/rockpro64_rk3399/Kconfig" source "board/rockchip/evb_rk3399/Kconfig" source "board/theobroma-systems/puma_rk3399/Kconfig" diff --git a/board/pine64/pinephone-pro-rk3399/Kconfig b/board/pine64/pinephone-pro-rk3399/Kconfig new file mode 100644 index 0000000000..13d6465ae6 --- /dev/null +++ b/board/pine64/pinephone-pro-rk3399/Kconfig @@ -0,0 +1,15 @@ +if TARGET_PINEPHONE_PRO_RK3399 + +config SYS_BOARD + default "pinephone-pro-rk3399" + +config SYS_VENDOR + default "pine64" + +config SYS_CONFIG_NAME + default "pinephone-pro-rk3399" + +config BOARD_SPECIFIC_OPTIONS + def_bool y + +endif diff --git a/board/pine64/pinephone-pro-rk3399/MAINTAINERS b/board/pine64/pinephone-pro-rk3399/MAINTAINERS new file mode 100644 index 0000000000..9ca4fc4cbe --- /dev/null +++ b/board/pine64/pinephone-pro-rk3399/MAINTAINERS @@ -0,0 +1,8 @@ +PINEPHONE_PRO +M: Martijn Braam <martijn(a)brixit.nl> +S: Maintained +F: board/pine64/rk3399-pinephone-pro/ +F: include/configs/rk3399-pinephone-pro.h +F: arch/arm/dts/rk3399-pinephone-pro.dts +F: arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi +F: configs/pinephone-pro-rk3399_defconfig diff --git a/board/pine64/pinephone-pro-rk3399/Makefile b/board/pine64/pinephone-pro-rk3399/Makefile new file mode 100644 index 0000000000..8d9203053e --- /dev/null +++ b/board/pine64/pinephone-pro-rk3399/Makefile @@ -0,0 +1 @@ +obj-y += pinephone-pro-rk3399.o diff --git a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c new file mode 100644 index 0000000000..8efeb6ea3d --- /dev/null +++ b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Vasily Khoruzhick <anarsoul(a)gmail.com> + * (C) Copyright 2021 Martijn Braam <martijn(a)brixit.nl> + */ + +#include <common.h> +#include <dm.h> +#include <init.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/grf_rk3399.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/misc.h> + +#define GRF_IO_VSEL_BT565_SHIFT 0 +#define PMUGRF_CON0_VSEL_SHIFT 8 + +#ifdef CONFIG_MISC_INIT_R +static void setup_iodomain(void) +{ + struct rk3399_grf_regs *grf = + syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + struct rk3399_pmugrf_regs *pmugrf = + syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); + + /* BT565 is in 1.8v domain */ + rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT); + + /* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */ + rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT); +} + +int misc_init_r(void) +{ + const u32 cpuid_offset = 0x7; + const u32 cpuid_length = 0x10; + u8 cpuid[cpuid_length]; + int ret; + + setup_iodomain(); + + ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); + if (ret) + return ret; + + ret = rockchip_cpuid_set(cpuid, cpuid_length); + if (ret) + return ret; + + ret = rockchip_setup_macaddr(); + + return ret; +} + +#endif diff --git a/configs/pinephone-pro-rk3399_defconfig b/configs/pinephone-pro-rk3399_defconfig new file mode 100644 index 0000000000..2cf80f7d35 --- /dev/null +++ b/configs/pinephone-pro-rk3399_defconfig @@ -0,0 +1,92 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x8000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_PINEPHONE_PRO_RK3399=y +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinephone-pro" +CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-pinephone-pro.dtb" +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_MISC_INIT_R=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_TPL=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_DM_KEYBOARD=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_ETH=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y +CONFIG_DM_PMIC_FAN53555=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM_RK3399_LPDDR4=y +CONFIG_DM_RESET=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_KEYBOARD=y +CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_EDP=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y diff --git a/include/configs/pinephone-pro-rk3399.h b/include/configs/pinephone-pro-rk3399.h new file mode 100644 index 0000000000..fefa793fdd --- /dev/null +++ b/include/configs/pinephone-pro-rk3399.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Rockchip Electronics Co., Ltd + * Copyright (C) 2020 Peter Robinson <pbrobinson at gmail.com> + * Copyright (C) 2021 Martijn Braam <martijn(a)brixit.nl> + */ + +#ifndef __PINEPHONE_PRO_RK3399_H +#define __PINEPHONE_PRO_RK3399_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdin=serial,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include <configs/rk3399_common.h> + +#define SDRAM_BANK_SIZE (2UL << 30) + +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 + +#endif -- 2.33.1

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[PATCH] engicam: Rename board dir, px30_core to px30
by Jagan Teki 24 Dec '21

24 Dec '21

Engicam hardware design solutions are based on System On Modules(SoM) with various SoCs like i.MX6, i.MX8 and PX30 etc. The current directory structure uses the simplest way to understand these designs by listing each of these SoC in board/engicam/SoC and inside SoC directory has SoM file name as a board file name. Right now all of the SoC's follow a similar approach except px30. So rename px30_core to px30. Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- Note: This patch is on top of https://patchwork.ozlabs.org/project/uboot/cover/20210804090551.90819-1-jag… arch/arm/mach-rockchip/px30/Kconfig | 2 +- board/engicam/{px30_core => px30}/Kconfig | 2 +- board/engicam/{px30_core => px30}/MAINTAINERS | 0 board/engicam/{px30_core => px30}/Makefile | 0 board/engicam/{px30_core => px30}/px30_core.c | 0 5 files changed, 2 insertions(+), 2 deletions(-) rename board/engicam/{px30_core => px30}/Kconfig (90%) rename board/engicam/{px30_core => px30}/MAINTAINERS (100%) rename board/engicam/{px30_core => px30}/Makefile (100%) rename board/engicam/{px30_core => px30}/px30_core.c (100%) diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index 98e09019a2..7b9b380dfa 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -68,7 +68,7 @@ config DEBUG_UART_CHANNEL For using the UART for early debugging the route to use needs to be declared (0 or 1). -source "board/engicam/px30_core/Kconfig" +source "board/engicam/px30/Kconfig" source "board/hardkernel/odroid_go2/Kconfig" source "board/rockchip/evb_px30/Kconfig" diff --git a/board/engicam/px30_core/Kconfig b/board/engicam/px30/Kconfig similarity index 90% rename from board/engicam/px30_core/Kconfig rename to board/engicam/px30/Kconfig index a03be78369..10a7ec203f 100644 --- a/board/engicam/px30_core/Kconfig +++ b/board/engicam/px30/Kconfig @@ -1,7 +1,7 @@ if TARGET_PX30_CORE config SYS_BOARD - default "px30_core" + default "px30" config SYS_VENDOR default "engicam" diff --git a/board/engicam/px30_core/MAINTAINERS b/board/engicam/px30/MAINTAINERS similarity index 100% rename from board/engicam/px30_core/MAINTAINERS rename to board/engicam/px30/MAINTAINERS diff --git a/board/engicam/px30_core/Makefile b/board/engicam/px30/Makefile similarity index 100% rename from board/engicam/px30_core/Makefile rename to board/engicam/px30/Makefile diff --git a/board/engicam/px30_core/px30_core.c b/board/engicam/px30/px30_core.c similarity index 100% rename from board/engicam/px30_core/px30_core.c rename to board/engicam/px30/px30_core.c -- 2.25.1

2 1

[PATCH v2 0/3] Conformance Profiles Table support in U-boot
by Jose Marinho 23 Dec '21

23 Dec '21

patch v2: - address v1 comments - define EFI_EBBR_2_0_CONFORMANCE unconditionally. - introduce ECPT EFI selftet - drop the efidebug ECPT print The Conformance Profiles Table (ECPT) table will be included in the UEFI specification 2.9+. The ECPT table was introduced in UEFI following the code-first path. The acceptance ticket can be viewed at: https://bugzilla.tianocore.org/show_bug.cgi?id=3591 This patch set implements the ECPT table in U-boot. Jose Marinho (3): efi: Create ECPT table efi: ECPT add EBBRv2.0 conformance profile efi: ECPT EFI selftest cmd/efidebug.c | 4 + include/efi_api.h | 14 ++++ include/efi_loader.h | 7 ++ lib/efi_loader/Kconfig | 11 +++ lib/efi_loader/Makefile | 1 + lib/efi_loader/efi_conformance.c | 75 +++++++++++++++++++ lib/efi_loader/efi_setup.c | 6 ++ lib/efi_selftest/Makefile | 2 + lib/efi_selftest/efi_selftest_ecpt.c | 105 +++++++++++++++++++++++++++ 9 files changed, 225 insertions(+) create mode 100644 lib/efi_loader/efi_conformance.c create mode 100644 lib/efi_selftest/efi_selftest_ecpt.c -- 2.25.1

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[PATCH] rockchip: puma/lion: update MAINTAINERS file
by Quentin Schulz 23 Dec '21

23 Dec '21

Cc: Quentin Schulz <foss+u-boot(a)0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz(a)theobroma-systems.com> --- board/theobroma-systems/lion_rk3368/MAINTAINERS | 2 +- board/theobroma-systems/puma_rk3399/MAINTAINERS | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/board/theobroma-systems/lion_rk3368/MAINTAINERS b/board/theobroma-systems/lion_rk3368/MAINTAINERS index 857f784d21..a5b4cb31b4 100644 --- a/board/theobroma-systems/lion_rk3368/MAINTAINERS +++ b/board/theobroma-systems/lion_rk3368/MAINTAINERS @@ -1,5 +1,5 @@ LION-RK3368 (RK3368-uQ7 system-on-module) -M: Philipp Tomsich <philipp.tomsich(a)theobroma-systems.com> +M: Quentin Schulz <quentin.schulz(a)theobroma-systems.com> M: Klaus Goger <klaus.goger(a)theobroma-systems.com> S: Maintained F: board/theobroma-systems/lion_rk3368 diff --git a/board/theobroma-systems/puma_rk3399/MAINTAINERS b/board/theobroma-systems/puma_rk3399/MAINTAINERS index ccec09c386..1ec2dd72d6 100644 --- a/board/theobroma-systems/puma_rk3399/MAINTAINERS +++ b/board/theobroma-systems/puma_rk3399/MAINTAINERS @@ -1,5 +1,5 @@ PUMA-RK3399 -M: Philipp Tomsich <philipp.tomsich(a)theobroma-systems.com> +M: Quentin Schulz <quentin.schulz(a)theobroma-systems.com> M: Klaus Goger <klaus.goger(a)theobroma-systems.com> S: Maintained F: board/theobroma-systems/puma_rk3399 -- 2.33.1

2 1