November 2021 - U-Boot

[PATCH 03/18] km/ls102xa: use qrio selftest_pin for reading selftest
by Aleksandar Gerasimovski 16 Nov '21

16 Nov '21

QRIO library now supports direct read of the test pin status. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski(a)hitachienergy.com> --- board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c index db49e8f..2be2b64 100644 --- a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c +++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c @@ -150,9 +150,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) #if defined(CONFIG_POST) int post_hotkeys_pressed(void) { - /* DIC26_SELFTEST: GPRTA0, GPA0 */ - qrio_gpio_direction_input(QRIO_GPIO_A, 0); - return qrio_get_gpio(QRIO_GPIO_A, 0); + /* DIC26_SELFTEST: QRIO, SLFTEST */ + return qrio_get_selftest_pin(); } ulong post_word_load(void) -- 1.8.3.1

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[PATCH 02/18] km: qrio: add function to read SLFTEST pin status
by Aleksandar Gerasimovski 16 Nov '21

16 Nov '21

There is a request from HW designers to use this QRIO pin for detecting DIC26_SELFTEST status instead of a GPIO pin. This pin is typically used during production for executing POST tests and starting test ESW bank. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski(a)hitachienergy.com> --- board/keymile/common/qrio.c | 13 +++++++++++++ board/keymile/common/qrio.h | 1 + 2 files changed, 14 insertions(+) diff --git a/board/keymile/common/qrio.c b/board/keymile/common/qrio.c index da51691..ed5e472 100644 --- a/board/keymile/common/qrio.c +++ b/board/keymile/common/qrio.c @@ -27,6 +27,19 @@ void show_qrio(void) (id_rev >> 8) & 0xff, id_rev & 0xff); } +#define SLFTEST_OFF 0x06 + +bool qrio_get_selftest_pin(void) +{ + u8 slftest; + + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + slftest = in_8(qrio_base + SLFTEST_OFF); + + return (slftest & 1) > 0; +} + int qrio_get_gpio(u8 port_off, u8 gpio_nr) { u32 gprt; diff --git a/board/keymile/common/qrio.h b/board/keymile/common/qrio.h index 757bcbf..c341cd9 100644 --- a/board/keymile/common/qrio.h +++ b/board/keymile/common/qrio.h @@ -12,6 +12,7 @@ #define QRIO_GPIO_B 0x60 void show_qrio(void); +bool qrio_get_selftest_pin(void); int qrio_get_gpio(u8 port_off, u8 gpio_nr); void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val); void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value); -- 1.8.3.1

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[PATCH 01/18] arm: ls1021a: limit debug eth phy speed to 100Mbps
by Aleksandar Gerasimovski 16 Nov '21

16 Nov '21

Beside that mounted rgmii debug phy is 1000Mbps capable, the debug link between the piggy board and the phy is 100Mbps only. This leads to longer link establishment time when working in debug mode, as phy tries to autoneg 1000Mbps. This patch fixes the speed to 100Mbps and allows smother link establishment time for the debug interface. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski(a)hitachienergy.com> --- arch/arm/dts/ls1021a-pg-wcom-seli8.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/ls1021a-pg-wcom-seli8.dts b/arch/arm/dts/ls1021a-pg-wcom-seli8.dts index e335188..f2cadd7 100644 --- a/arch/arm/dts/ls1021a-pg-wcom-seli8.dts +++ b/arch/arm/dts/ls1021a-pg-wcom-seli8.dts @@ -38,6 +38,7 @@ &enet2 { phy-handle = <&debug_phy>; phy-connection-type = "rgmii-id"; + max-speed = <100>; status = "okay"; }; -- 1.8.3.1

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RE: [EXT] Your message to U-Boot awaits moderator approval
by Sahil Malhotra 16 Nov '21

16 Nov '21

Hi, I am trying to send some patches on u-boot(a)lists.denx.de but every time I am getting reply "Your message to U-Boot awaits moderator approval". Created account on http://patchwork.ozlabs.org/user/, Also subscribed to the list u-boot(a)lists.denx.de. Tried multiple times, but always getting this reply. Any help regarding this is really appreciated. Regards, Sahil Malhotra -----Original Message----- From: U-Boot <u-boot-bounces(a)lists.denx.de> On Behalf Of u-boot-owner(a)lists.denx.de Sent: Tuesday, November 16, 2021 2:05 PM To: Sahil Malhotra <sahil.malhotra(a)nxp.com> Subject: [EXT] Your message to U-Boot awaits moderator approval Caution: EXT Email Your mail to 'U-Boot' with the subject [PATCH 2/2] configs: enabled DTB overlay feature for LS SoCs Is being held until the list moderator can review it for approval. The reason it is being held: Post to moderated list Either the message will get posted to the list, or you will receive notification of the moderator's decision. If you would like to cancel this posting, please visit the following URL: https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.den…

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[PATCH 1/2] fsl-layerscape: add dtb overlay feature
by Sahil Malhotra 16 Nov '21

16 Nov '21

From: Sahil Malhotra <sahil.malhotra(a)nxp.com> This patch enables the DTB overlay feature for LS platforms. Signed-off-by: Sahil Malhotra <sahil.malhotra(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 + arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c | 39 +++++++++++++++++++ arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h | 10 +++++ arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 12 ++++++ .../cpu/armv8/fsl-layerscape/lowlevel_init.S | 25 ++++++++++++ 5 files changed, 87 insertions(+) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index 598c36ee66..97f1f291dd 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -7,6 +7,7 @@ obj-y += lowlevel.o obj-y += soc.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_MP) += mp.o spintable.o +obj-$(CONFIG_OF_LIBFDT_OVERLAY) += lowlevel_init.o dt_optee.o obj-$(CONFIG_OF_LIBFDT) += fdt.o endif obj-$(CONFIG_SPL) += spl.o diff --git a/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c new file mode 100644 index 0000000000..2418ad09c7 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ +#include <common.h> +#include <errno.h> +#include <fdt_support.h> +#include <linux/sizes.h> +#include "dt_optee.h" + +int ft_add_optee_overlay(void *fdt, struct bd_info *bd) +{ + int ret = 0; + + /* + * No BL32_BASE passed means no TEE running, so no + * need to add optee node in dts + */ + if (!rom_pointer[0]) { + debug("No BL32_BASE passed means no TEE running\n"); + return ret; + } + + if (rom_pointer[2]) { + debug("OP-TEE: applying overlay on 0x%lx\n", rom_pointer[2]); + ret = fdt_check_header((void *)rom_pointer[2]); + if (ret == 0) { + /* Copy the fdt overlay to next 1M and use copied overlay */ + memcpy((void *)(rom_pointer[2] + SZ_1M), (void *)rom_pointer[2], + fdt_totalsize((void *)rom_pointer[2])); + ret = fdt_overlay_apply_verbose(fdt, (void *)(rom_pointer[2] + SZ_1M)); + if (ret == 0) { + debug("Overlay applied with success"); + fdt_pack(fdt); + } + } + } + return ret; +} diff --git a/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h new file mode 100644 index 0000000000..d1ff25d531 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ +#ifndef __DT_OPTEE_H__ +#define __DT_OPTEE_H__ + +extern unsigned long rom_pointer[]; +int ft_add_optee_overlay(void *fdt, struct bd_info *bd); +#endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index f1624ff30a..0824c62264 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -31,6 +31,7 @@ #endif #include <asm/arch/speed.h> #include <fsl_qbman.h> +#include "dt_optee.h" int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc) { @@ -698,3 +699,14 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) fdt_fixup_ecam(blob); #endif } + +#ifdef CONFIG_OF_SYSTEM_SETUP +int ft_system_setup(void *blob, struct bd_info *bd) +{ +#ifdef CONFIG_OF_LIBFDT_OVERLAY + return ft_add_optee_overlay(blob, bd); +#else + return 0; +#endif +} +#endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S new file mode 100644 index 0000000000..1d6a2d85fa --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +#include <config.h> + +.align 8 +.global rom_pointer +rom_pointer: + .space 32 + +/* + * Routine: save_boot_params (called after reset from start.S) + */ + +.global save_boot_params +save_boot_params: + /* The firmware provided FDT address can be found in r2/x0 */ + adr x0, rom_pointer + stp x1, x2, [x0], #16 + stp x3, x4, [x0], #16 + + ldr x1, =save_boot_params_ret + br x1 -- 2.17.1

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board_init.c file not compiled
by Chan Kim 16 Nov '21

16 Nov '21

Hello all, I'm new to u-boot and having difficulty while trying to build u-boot for our test board.(arm64, armv8) I wanted to try the "SPL falcon" mode". The DDR is not ready yet in the board. A small scp chip(cortex-M7) will initialize clk and will load kernel(including initramfs), dtb, u-boot-spl, images to a small internal RAM. And the AP chip will start from the u-boot-spl. (I know some low-level init can be skipped) I added SPL related config settings and ran this command. make CROSS_COMPILE=aarch64-none-elf- ab21m_defconfig make CROSS_COMPILE=aarch64-none-elf- I see "u-boot/arch/arm/lib/crt0_64.S:88: undefined reference to `board_init_f_alloc_reserve'" error during the u-boot build. (not related to SPL). By comparing the build process with that of rk3036 board (arm board with SUPPORT_SPL, no SUPPORT_TPL), I found in my case even common/board_init.c is not compiled. Where should I look? I'm reading the documents or build scripts here and there but can't figure it out. Thank you. Chan Kim

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[PATCH 1/2] fsl-layerscape: add dtb overlay feature
by Sahil Malhotra 16 Nov '21

16 Nov '21

This patch enables the DTB overlay feature for LS platforms. Signed-off-by: Sahil Malhotra <sahil.malhotra(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 + arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c | 39 +++++++++++++++++++ arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h | 10 +++++ arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 12 ++++++ .../cpu/armv8/fsl-layerscape/lowlevel_init.S | 25 ++++++++++++ 5 files changed, 87 insertions(+) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index 598c36ee66..97f1f291dd 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -7,6 +7,7 @@ obj-y += lowlevel.o obj-y += soc.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_MP) += mp.o spintable.o +obj-$(CONFIG_OF_LIBFDT_OVERLAY) += lowlevel_init.o dt_optee.o obj-$(CONFIG_OF_LIBFDT) += fdt.o endif obj-$(CONFIG_SPL) += spl.o diff --git a/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c new file mode 100644 index 0000000000..2418ad09c7 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ +#include <common.h> +#include <errno.h> +#include <fdt_support.h> +#include <linux/sizes.h> +#include "dt_optee.h" + +int ft_add_optee_overlay(void *fdt, struct bd_info *bd) +{ + int ret = 0; + + /* + * No BL32_BASE passed means no TEE running, so no + * need to add optee node in dts + */ + if (!rom_pointer[0]) { + debug("No BL32_BASE passed means no TEE running\n"); + return ret; + } + + if (rom_pointer[2]) { + debug("OP-TEE: applying overlay on 0x%lx\n", rom_pointer[2]); + ret = fdt_check_header((void *)rom_pointer[2]); + if (ret == 0) { + /* Copy the fdt overlay to next 1M and use copied overlay */ + memcpy((void *)(rom_pointer[2] + SZ_1M), (void *)rom_pointer[2], + fdt_totalsize((void *)rom_pointer[2])); + ret = fdt_overlay_apply_verbose(fdt, (void *)(rom_pointer[2] + SZ_1M)); + if (ret == 0) { + debug("Overlay applied with success"); + fdt_pack(fdt); + } + } + } + return ret; +} diff --git a/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h new file mode 100644 index 0000000000..d1ff25d531 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ +#ifndef __DT_OPTEE_H__ +#define __DT_OPTEE_H__ + +extern unsigned long rom_pointer[]; +int ft_add_optee_overlay(void *fdt, struct bd_info *bd); +#endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index f1624ff30a..0824c62264 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -31,6 +31,7 @@ #endif #include <asm/arch/speed.h> #include <fsl_qbman.h> +#include "dt_optee.h" int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc) { @@ -698,3 +699,14 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) fdt_fixup_ecam(blob); #endif } + +#ifdef CONFIG_OF_SYSTEM_SETUP +int ft_system_setup(void *blob, struct bd_info *bd) +{ +#ifdef CONFIG_OF_LIBFDT_OVERLAY + return ft_add_optee_overlay(blob, bd); +#else + return 0; +#endif +} +#endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S new file mode 100644 index 0000000000..1d6a2d85fa --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +#include <config.h> + +.align 8 +.global rom_pointer +rom_pointer: + .space 32 + +/* + * Routine: save_boot_params (called after reset from start.S) + */ + +.global save_boot_params +save_boot_params: + /* The firmware provided FDT address can be found in r2/x0 */ + adr x0, rom_pointer + stp x1, x2, [x0], #16 + stp x3, x4, [x0], #16 + + ldr x1, =save_boot_params_ret + br x1 -- 2.17.1

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[PATCH 1/2] fsl-layerscape: add dtb overlay feature
by Sahil Malhotra 16 Nov '21

16 Nov '21

From: Sahil Malhotra <sahil.malhotra(a)nxp.com> This patch enables the DTB overlay feature for LS platforms. Signed-off-by: Sahil Malhotra <sahil.malhotra(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 + arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c | 39 +++++++++++++++++++ arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h | 10 +++++ arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 12 ++++++ .../cpu/armv8/fsl-layerscape/lowlevel_init.S | 25 ++++++++++++ 5 files changed, 87 insertions(+) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index 598c36ee66..97f1f291dd 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -7,6 +7,7 @@ obj-y += lowlevel.o obj-y += soc.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_MP) += mp.o spintable.o +obj-$(CONFIG_OF_LIBFDT_OVERLAY) += lowlevel_init.o dt_optee.o obj-$(CONFIG_OF_LIBFDT) += fdt.o endif obj-$(CONFIG_SPL) += spl.o diff --git a/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c new file mode 100644 index 0000000000..2418ad09c7 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ +#include <common.h> +#include <errno.h> +#include <fdt_support.h> +#include <linux/sizes.h> +#include "dt_optee.h" + +int ft_add_optee_overlay(void *fdt, struct bd_info *bd) +{ + int ret = 0; + + /* + * No BL32_BASE passed means no TEE running, so no + * need to add optee node in dts + */ + if (!rom_pointer[0]) { + debug("No BL32_BASE passed means no TEE running\n"); + return ret; + } + + if (rom_pointer[2]) { + debug("OP-TEE: applying overlay on 0x%lx\n", rom_pointer[2]); + ret = fdt_check_header((void *)rom_pointer[2]); + if (ret == 0) { + /* Copy the fdt overlay to next 1M and use copied overlay */ + memcpy((void *)(rom_pointer[2] + SZ_1M), (void *)rom_pointer[2], + fdt_totalsize((void *)rom_pointer[2])); + ret = fdt_overlay_apply_verbose(fdt, (void *)(rom_pointer[2] + SZ_1M)); + if (ret == 0) { + debug("Overlay applied with success"); + fdt_pack(fdt); + } + } + } + return ret; +} diff --git a/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h new file mode 100644 index 0000000000..d1ff25d531 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ +#ifndef __DT_OPTEE_H__ +#define __DT_OPTEE_H__ + +extern unsigned long rom_pointer[]; +int ft_add_optee_overlay(void *fdt, struct bd_info *bd); +#endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index f1624ff30a..0824c62264 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -31,6 +31,7 @@ #endif #include <asm/arch/speed.h> #include <fsl_qbman.h> +#include "dt_optee.h" int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc) { @@ -698,3 +699,14 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) fdt_fixup_ecam(blob); #endif } + +#ifdef CONFIG_OF_SYSTEM_SETUP +int ft_system_setup(void *blob, struct bd_info *bd) +{ +#ifdef CONFIG_OF_LIBFDT_OVERLAY + return ft_add_optee_overlay(blob, bd); +#else + return 0; +#endif +} +#endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S new file mode 100644 index 0000000000..1d6a2d85fa --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +#include <config.h> + +.align 8 +.global rom_pointer +rom_pointer: + .space 32 + +/* + * Routine: save_boot_params (called after reset from start.S) + */ + +.global save_boot_params +save_boot_params: + /* The firmware provided FDT address can be found in r2/x0 */ + adr x0, rom_pointer + stp x1, x2, [x0], #16 + stp x3, x4, [x0], #16 + + ldr x1, =save_boot_params_ret + br x1 -- 2.17.1

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[PATCH 1/2] fsl-layerscape: add dtb overlay feature
by Sahil Malhotra 16 Nov '21

16 Nov '21

This patch enables the DTB overlay feature for LS platforms. Signed-off-by: Sahil Malhotra <sahil.malhotra(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 + arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c | 39 +++++++++++++++++++ arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h | 10 +++++ arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 12 ++++++ .../cpu/armv8/fsl-layerscape/lowlevel_init.S | 25 ++++++++++++ 5 files changed, 87 insertions(+) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index 598c36ee66..97f1f291dd 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -7,6 +7,7 @@ obj-y += lowlevel.o obj-y += soc.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_MP) += mp.o spintable.o +obj-$(CONFIG_OF_LIBFDT_OVERLAY) += lowlevel_init.o dt_optee.o obj-$(CONFIG_OF_LIBFDT) += fdt.o endif obj-$(CONFIG_SPL) += spl.o diff --git a/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c new file mode 100644 index 0000000000..2418ad09c7 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ +#include <common.h> +#include <errno.h> +#include <fdt_support.h> +#include <linux/sizes.h> +#include "dt_optee.h" + +int ft_add_optee_overlay(void *fdt, struct bd_info *bd) +{ + int ret = 0; + + /* + * No BL32_BASE passed means no TEE running, so no + * need to add optee node in dts + */ + if (!rom_pointer[0]) { + debug("No BL32_BASE passed means no TEE running\n"); + return ret; + } + + if (rom_pointer[2]) { + debug("OP-TEE: applying overlay on 0x%lx\n", rom_pointer[2]); + ret = fdt_check_header((void *)rom_pointer[2]); + if (ret == 0) { + /* Copy the fdt overlay to next 1M and use copied overlay */ + memcpy((void *)(rom_pointer[2] + SZ_1M), (void *)rom_pointer[2], + fdt_totalsize((void *)rom_pointer[2])); + ret = fdt_overlay_apply_verbose(fdt, (void *)(rom_pointer[2] + SZ_1M)); + if (ret == 0) { + debug("Overlay applied with success"); + fdt_pack(fdt); + } + } + } + return ret; +} diff --git a/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h new file mode 100644 index 0000000000..d1ff25d531 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ +#ifndef __DT_OPTEE_H__ +#define __DT_OPTEE_H__ + +extern unsigned long rom_pointer[]; +int ft_add_optee_overlay(void *fdt, struct bd_info *bd); +#endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index f1624ff30a..0824c62264 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -31,6 +31,7 @@ #endif #include <asm/arch/speed.h> #include <fsl_qbman.h> +#include "dt_optee.h" int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc) { @@ -698,3 +699,14 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) fdt_fixup_ecam(blob); #endif } + +#ifdef CONFIG_OF_SYSTEM_SETUP +int ft_system_setup(void *blob, struct bd_info *bd) +{ +#ifdef CONFIG_OF_LIBFDT_OVERLAY + return ft_add_optee_overlay(blob, bd); +#else + return 0; +#endif +} +#endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S new file mode 100644 index 0000000000..1d6a2d85fa --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +#include <config.h> + +.align 8 +.global rom_pointer +rom_pointer: + .space 32 + +/* + * Routine: save_boot_params (called after reset from start.S) + */ + +.global save_boot_params +save_boot_params: + /* The firmware provided FDT address can be found in r2/x0 */ + adr x0, rom_pointer + stp x1, x2, [x0], #16 + stp x3, x4, [x0], #16 + + ldr x1, =save_boot_params_ret + br x1 -- 2.17.1

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[PATCH 1/2] fsl-layerscape: add dtb overlay feature
by Sahil Malhotra 16 Nov '21

16 Nov '21

From: Sahil Malhotra <sahil.malhotra(a)nxp.com> This patch enables the DTB overlay feature for LS platforms. Signed-off-by: Sahil Malhotra <sahil.malhotra(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 + arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c | 39 +++++++++++++++++++ arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h | 10 +++++ arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 12 ++++++ .../cpu/armv8/fsl-layerscape/lowlevel_init.S | 25 ++++++++++++ 5 files changed, 87 insertions(+) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index 598c36ee66..97f1f291dd 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -7,6 +7,7 @@ obj-y += lowlevel.o obj-y += soc.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_MP) += mp.o spintable.o +obj-$(CONFIG_OF_LIBFDT_OVERLAY) += lowlevel_init.o dt_optee.o obj-$(CONFIG_OF_LIBFDT) += fdt.o endif obj-$(CONFIG_SPL) += spl.o diff --git a/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c new file mode 100644 index 0000000000..2418ad09c7 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ +#include <common.h> +#include <errno.h> +#include <fdt_support.h> +#include <linux/sizes.h> +#include "dt_optee.h" + +int ft_add_optee_overlay(void *fdt, struct bd_info *bd) +{ + int ret = 0; + + /* + * No BL32_BASE passed means no TEE running, so no + * need to add optee node in dts + */ + if (!rom_pointer[0]) { + debug("No BL32_BASE passed means no TEE running\n"); + return ret; + } + + if (rom_pointer[2]) { + debug("OP-TEE: applying overlay on 0x%lx\n", rom_pointer[2]); + ret = fdt_check_header((void *)rom_pointer[2]); + if (ret == 0) { + /* Copy the fdt overlay to next 1M and use copied overlay */ + memcpy((void *)(rom_pointer[2] + SZ_1M), (void *)rom_pointer[2], + fdt_totalsize((void *)rom_pointer[2])); + ret = fdt_overlay_apply_verbose(fdt, (void *)(rom_pointer[2] + SZ_1M)); + if (ret == 0) { + debug("Overlay applied with success"); + fdt_pack(fdt); + } + } + } + return ret; +} diff --git a/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h new file mode 100644 index 0000000000..d1ff25d531 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ +#ifndef __DT_OPTEE_H__ +#define __DT_OPTEE_H__ + +extern unsigned long rom_pointer[]; +int ft_add_optee_overlay(void *fdt, struct bd_info *bd); +#endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index f1624ff30a..0824c62264 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -31,6 +31,7 @@ #endif #include <asm/arch/speed.h> #include <fsl_qbman.h> +#include "dt_optee.h" int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc) { @@ -698,3 +699,14 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) fdt_fixup_ecam(blob); #endif } + +#ifdef CONFIG_OF_SYSTEM_SETUP +int ft_system_setup(void *blob, struct bd_info *bd) +{ +#ifdef CONFIG_OF_LIBFDT_OVERLAY + return ft_add_optee_overlay(blob, bd); +#else + return 0; +#endif +} +#endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S new file mode 100644 index 0000000000..1d6a2d85fa --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +#include <config.h> + +.align 8 +.global rom_pointer +rom_pointer: + .space 32 + +/* + * Routine: save_boot_params (called after reset from start.S) + */ + +.global save_boot_params +save_boot_params: + /* The firmware provided FDT address can be found in r2/x0 */ + adr x0, rom_pointer + stp x1, x2, [x0], #16 + stp x3, x4, [x0], #16 + + ldr x1, =save_boot_params_ret + br x1 -- 2.17.1

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