November 2021 - U-Boot

[RFC] libretech-cc: Disable CONFIG_NET_RANDOM_ETHADDR
by Tom Rini 15 Nov '21

15 Nov '21

This board has a persistent ethernet MAC address and does not enable USB gadget ethernet support, so does not require this functionality. Remove it. Cc: Neil Armstrong <narmstrong(a)baylibre.com> Signed-off-by: Tom Rini <trini(a)konsulko.com> --- As mentioned in https://lore.kernel.org/u-boot/f6aead46-f220-ff51-f70d-de95daac9840@xilinx.… it seems many boards are enabling CONFIG_NET_RANDOM_ETHADDR and don't need it. I have a libretec-cc (v1, not v2). Given a "nowhere" environment and persistent ethaddr before/after this change on my board, I believe this isn't needed here. I suspect it's not needed on a whole host of amlogic boards I don't have as well. --- configs/libretech-cc_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/libretech-cc_defconfig b/configs/libretech-cc_defconfig index b729308c8eeb..b4413ed9b7ff 100644 --- a/configs/libretech-cc_defconfig +++ b/configs/libretech-cc_defconfig @@ -26,7 +26,6 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SARADC_MESON=y CONFIG_MMC_MESON_GX=y CONFIG_PHY_MESON_GXL=y -- 2.25.1

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[PATCH] lib: sparse: Make CHUNK_TYPE_RAW buffer aligned
by qianfanguijin＠qq.com 15 Nov '21

15 Nov '21

From: qianfan Zhao <qianfanguijin(a)163.com> CHUNK_TYPE_RAW buffer is not aligned, and flash sparse images by fastboot will report "Misaligned operation" if DCACHE is enabled. Flashing Sparse Image CACHE: Misaligned operation at range [84000028, 84001028] CACHE: Misaligned operation at range [84001034, 84002034] CACHE: Misaligned operation at range [8401104c, 8401304c] Fix it Signed-off-by: qianfan Zhao <qianfanguijin(a)163.com> --- lib/image-sparse.c | 54 +++++++++++++++++++++++++++++++++++++++------- 1 file changed, 46 insertions(+), 8 deletions(-) diff --git a/lib/image-sparse.c b/lib/image-sparse.c index d80fdbbf58..1143c88a79 100644 --- a/lib/image-sparse.c +++ b/lib/image-sparse.c @@ -49,6 +49,48 @@ static void default_log(const char *ignored, char *response) {} +static lbaint_t write_sparse_chunk_raw(struct sparse_storage *info, + lbaint_t blk, lbaint_t blkcnt, + void *data, + char *response) +{ + lbaint_t n, write_blks, blks = 0, aligned_buf_blks = 100; + uint32_t *aligned_buf = NULL; + + if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + return info->write(info, blk, blkcnt, data); + + aligned_buf = memalign(ARCH_DMA_MINALIGN, info->blksz * aligned_buf_blks); + if (!aligned_buf) { + info->mssg("Malloc failed for: CHUNK_TYPE_RAW", response); + return -ENOMEM; + } + + while (blkcnt > 0) { + n = min(aligned_buf_blks, blkcnt); + memcpy(aligned_buf, data, n * info->blksz); + + /* write_blks might be > n due to NAND bad-blocks */ + write_blks = info->write(info, blk + blks, n, aligned_buf); + if (write_blks < 0 || write_blks < n) { + printf("%s: %s" LBAFU " [" LBAFU "]\n", + __func__, "Write failed, block #", + blk + blks, n); + info->mssg("flash write failure", response); + free(aligned_buf); + + return min(write_blks, (lbaint_t)-1); + } + + blks += write_blks; + data += n * info->blksz; + blkcnt -= n; + } + + free(aligned_buf); + return blks; +} + int write_sparse_image(struct sparse_storage *info, const char *part_name, void *data, char *response) { @@ -152,15 +194,11 @@ int write_sparse_image(struct sparse_storage *info, return -1; } - blks = info->write(info, blk, blkcnt, data); - /* blks might be > blkcnt (eg. NAND bad-blocks) */ - if (blks < blkcnt) { - printf("%s: %s" LBAFU " [" LBAFU "]\n", - __func__, "Write failed, block #", - blk, blks); - info->mssg("flash write failure", response); + blks = write_sparse_chunk_raw(info, blk, blkcnt, + data, response); + if (blks < 0) return -1; - } + blk += blks; bytes_written += ((u64)blkcnt) * info->blksz; total_blocks += chunk_header->chunk_sz; -- 2.17.1

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[PATCH] xilinx: zynqmp: fix ZYNQMP_RESTORE_JTAG check
by Ricardo Salveti 15 Nov '21

15 Nov '21

Config check should be done without the SPL_ prefix. Signed-off-by: Ricardo Salveti <ricardo(a)foundries.io> --- board/xilinx/zynqmp/zynqmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index dfb5dab7afa..2b5239ccb47 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -394,7 +394,7 @@ int board_init(void) printf("Silicon version:\t%d\n", zynqmp_get_silicon_version()); /* the CSU disables the JTAG interface when secure boot is enabled */ - if (CONFIG_IS_ENABLED(SPL_ZYNQMP_RESTORE_JTAG)) + if (CONFIG_IS_ENABLED(ZYNQMP_RESTORE_JTAG)) restore_jtag(); #else if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM)) -- 2.33.0

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[PATCH 1/1] tpm: clear state post probing
by Heinrich Schuchardt 15 Nov '21

15 Nov '21

Before we can start measuring the TPM must be cleared. Do this in the post_probe() method of the uclass. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- drivers/tpm/tpm-uclass.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/tpm/tpm-uclass.c b/drivers/tpm/tpm-uclass.c index f67fe1019b..9180551d6f 100644 --- a/drivers/tpm/tpm-uclass.c +++ b/drivers/tpm/tpm-uclass.c @@ -11,6 +11,7 @@ #include <log.h> #include <linux/delay.h> #include <linux/unaligned/be_byteshift.h> +#include <tpm_api.h> #include <tpm-v1.h> #include <tpm-v2.h> #include "tpm_internal.h" @@ -136,6 +137,26 @@ int tpm_xfer(struct udevice *dev, const uint8_t *sendbuf, size_t send_size, return 0; } +static int dm_tpm_post_probe(struct udevice *dev) +{ + struct tpm_chip_priv *priv = dev_get_uclass_priv(dev); + + /* + * Clearing the TPM state is only possible once after a hard reset. + * As we do not know if the TPM has been cleared by a prior boot stage + * ignore the return value here. + */ + switch (priv->version) { + case TPM_V1: + tpm_startup(dev, TPM_ST_CLEAR); + break; + case TPM_V2: + tpm2_startup(dev, TPM2_SU_CLEAR); + break; + } + return 0; +} + UCLASS_DRIVER(tpm) = { .id = UCLASS_TPM, .name = "tpm", @@ -143,5 +164,6 @@ UCLASS_DRIVER(tpm) = { #if CONFIG_IS_ENABLED(OF_REAL) .post_bind = dm_scan_fdt_dev, #endif + .post_probe = dm_tpm_post_probe, .per_device_auto = sizeof(struct tpm_chip_priv), }; -- 2.32.0

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U-Boot Ultrazed-EG QSPI NOR access issues (data corruption)
by Igor Opaniuk 15 Nov '21

15 Nov '21

Hi Michal, I'm currently observing QSPI NOR access issues, for instance both read/write operations return invalid data (even using sf read for the images flashed from Linux using mtd-utils/flashcp). I was able to reproduce this issue on both Xilinx downstream U-Boot xilinx-v2022.01-bsp, xilinx-v2021.07-bsp and U-Boot mainline. This issue doesn't reproduce in Linux using mtd-utils (using flashcp and mtd_debug, both writing/reading work perfectly): # flashcp u-boot0001.itb /dev/mtd3 # mtd_debug read /dev/mtd3 0x0 0x6D95B9 /mnt/u-boot0001.itb.dump Copied 7181753 bytes from address 0x00000000 in flash to /mnt/u-boot0001.itb.dump # md5sum u-boot0001.itb 730a86e2677dd082f72d5c3f6d20458a u-boot0001.itb # md5sum u-boot0001.itb.dump 730a86e2677dd082f72d5c3f6d20458a u-boot0001.itb.dump However when I dump the same image from U-Boot after reboot: sf probe; mmc dev ${bootseq}; sf read ${loadaddr} 0x100000 0x6d9be1; fatwritemmc ${bootseq}:1 ${loadaddr} u-boot0001.itb.dump 0x6D95B9; and then md5summ: # md5sum u-boot0001.itb.dump 841f088fdfd9fd12d080711030faecdd Check the attached screenshot of binary diff (usually around 3-4% of dumped file is randomly filled with zeros instead of correct data). I've also tried to lower QSPI clock frequency and check if it has any impact - same corruption issues are reproduced. btw, I noticed different capabilities (erase block size, 128 vs 64kb, I guess in U-Boot dual spi mode is not selected for some reason) reported in Linux and U-Boot: # mtdinfo /dev/mtd0 mtd0 Name: spi0.0 Type: nor Eraseblock size: 131072 bytes, 128.0 KiB Amount of eraseblocks: 512 (67108864 bytes, 64.0 MiB) Minimum input/output unit size: 1 byte Sub-page size: 1 byte Character device major/minor: 90:0 Bad blocks are allowed: false Device is writable: true U-Boot: ZynqMP> sf probe; SF: Detected n25q256ax1 with page size 256 Bytes, erase size 64 KiB, total 32 MiB board: Avnet Ultrazed-EG SoM + Ultrazed-EG IO Carrier defconfig: xilinx_zynqmp_virt_defconfig device tree: zynqmp-zcu102-rev1.0.dts is used Have you ever noticed similar issues on this/other boards with this SoC? Any ideas what could be a root cause? Looking forward for you reply Regards, Igor -- Best regards - Freundliche Grüsse - Meilleures salutations Igor Opaniuk Embedded Software Engineer T: +380 938364067 E: igor.opaniuk(a)foundries.io W: www.foundries.io

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[PATCH] drivers: musb_gadget: Save endpoint desc to usb_ep->desc
by qianfanguijin＠qq.com 15 Nov '21

15 Nov '21

From: qianfan Zhao <qianfanguijin(a)163.com> Fix fastboot flash bug. If the downloading file size is equal to the partition size, "fastboot flash" can't work, at least in sunxi platform, because used an uninitalized point: ep->desc. Reproduce: fastboot flash loader1 spl/sunxi-spl.bin. Signed-off-by: qianfan Zhao <qianfanguijin(a)163.com> --- drivers/usb/musb-new/musb_gadget.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/musb-new/musb_gadget.c b/drivers/usb/musb-new/musb_gadget.c index 5b149dac6d..12d9911ecd 100644 --- a/drivers/usb/musb-new/musb_gadget.c +++ b/drivers/usb/musb-new/musb_gadget.c @@ -1188,6 +1188,7 @@ static int musb_gadget_enable(struct usb_ep *ep, } else musb_ep->dma = NULL; + musb_ep->end_point.desc = desc; musb_ep->desc = desc; musb_ep->busy = 0; musb_ep->wedged = 0; -- 2.17.1

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[PATCH] drivers: net: add Aspeed MDIO driver
by Dylan Hung 15 Nov '21

15 Nov '21

Add a driver for the MDIO interface for Aspeed AST2600 SOC. The driver only supports clause 22 for now. Signed-off-by: Dylan Hung <dylan_hung(a)aspeedtech.com> --- drivers/net/Kconfig | 7 +++ drivers/net/Makefile | 1 + drivers/net/aspeed_mdio.c | 128 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 136 insertions(+) create mode 100644 drivers/net/aspeed_mdio.c diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 6c12959f37..4638180b74 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -826,6 +826,13 @@ config FSL_LS_MDIO This driver supports the MDIO bus found on the Fman 10G Ethernet MACs and on the mEMAC (which supports both Clauses 22 and 45). +config ASPEED_MDIO + bool "Aspeed MDIO interface support" + depends on DM_MDIO + help + This driver supports the MDIO bus of Aspeed AST2600 SOC. The driver + currently supports Clause 22. + config MDIO_MUX_MMIOREG bool "MDIO MUX accessed as a MMIO register access" depends on DM_MDIO_MUX diff --git a/drivers/net/Makefile b/drivers/net/Makefile index e4078d15a9..fe6c00fa48 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -101,3 +101,4 @@ obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o obj-$(CONFIG_MDIO_SANDBOX) += mdio_sandbox.o obj-$(CONFIG_FSL_ENETC) += fsl_enetc.o fsl_enetc_mdio.o obj-$(CONFIG_FSL_LS_MDIO) += fsl_ls_mdio.o +obj-$(CONFIG_ASPEED_MDIO) += aspeed_mdio.o diff --git a/drivers/net/aspeed_mdio.c b/drivers/net/aspeed_mdio.c new file mode 100644 index 0000000000..a99715a728 --- /dev/null +++ b/drivers/net/aspeed_mdio.c @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Aspeed MDIO driver + * + * (C) Copyright 2021 Aspeed Technology Inc. + * + * This file is inspired from the Linux kernel driver drivers/net/phy/mdio-aspeed.c + */ + +#include <common.h> +#include <dm.h> +#include <log.h> +#include <miiphy.h> +#include <net.h> +#include <reset.h> +#include <linux/bitops.h> +#include <linux/bitfield.h> +#include <linux/io.h> +#include <linux/iopoll.h> + +#define ASPEED_MDIO_CTRL 0x0 +#define ASPEED_MDIO_CTRL_FIRE BIT(31) +#define ASPEED_MDIO_CTRL_ST BIT(28) +#define ASPEED_MDIO_CTRL_ST_C45 0 +#define ASPEED_MDIO_CTRL_ST_C22 1 +#define ASPEED_MDIO_CTRL_OP GENMASK(27, 26) +#define MDIO_C22_OP_WRITE 0b01 +#define MDIO_C22_OP_READ 0b10 +#define ASPEED_MDIO_CTRL_PHYAD GENMASK(25, 21) +#define ASPEED_MDIO_CTRL_REGAD GENMASK(20, 16) +#define ASPEED_MDIO_CTRL_MIIWDATA GENMASK(15, 0) + +#define ASPEED_MDIO_DATA 0x4 +#define ASPEED_MDIO_DATA_MDC_THRES GENMASK(31, 24) +#define ASPEED_MDIO_DATA_MDIO_EDGE BIT(23) +#define ASPEED_MDIO_DATA_MDIO_LATCH GENMASK(22, 20) +#define ASPEED_MDIO_DATA_IDLE BIT(16) +#define ASPEED_MDIO_DATA_MIIRDATA GENMASK(15, 0) + +#define ASPEED_MDIO_TIMEOUT_US 1000 + +struct aspeed_mdio_priv { + void *base; +}; + +static int aspeed_mdio_read(struct udevice *mdio_dev, int addr, int devad, int reg) +{ + struct aspeed_mdio_priv *priv = dev_get_priv(mdio_dev); + u32 ctrl; + u32 data; + int rc; + + if (devad != MDIO_DEVAD_NONE) + return -EOPNOTSUPP; + + ctrl = ASPEED_MDIO_CTRL_FIRE + | FIELD_PREP(ASPEED_MDIO_CTRL_ST, ASPEED_MDIO_CTRL_ST_C22) + | FIELD_PREP(ASPEED_MDIO_CTRL_OP, MDIO_C22_OP_READ) + | FIELD_PREP(ASPEED_MDIO_CTRL_PHYAD, addr) + | FIELD_PREP(ASPEED_MDIO_CTRL_REGAD, reg); + + writel(ctrl, priv->base + ASPEED_MDIO_CTRL); + + rc = readl_poll_timeout(priv->base + ASPEED_MDIO_DATA, data, + data & ASPEED_MDIO_DATA_IDLE, + ASPEED_MDIO_TIMEOUT_US); + + if (rc < 0) + return rc; + + return FIELD_GET(ASPEED_MDIO_DATA_MIIRDATA, data); +} + +static int aspeed_mdio_write(struct udevice *mdio_dev, int addr, int devad, int reg, u16 val) +{ + struct aspeed_mdio_priv *priv = dev_get_priv(mdio_dev); + u32 ctrl; + + if (devad != MDIO_DEVAD_NONE) + return -EOPNOTSUPP; + + ctrl = ASPEED_MDIO_CTRL_FIRE + | FIELD_PREP(ASPEED_MDIO_CTRL_ST, ASPEED_MDIO_CTRL_ST_C22) + | FIELD_PREP(ASPEED_MDIO_CTRL_OP, MDIO_C22_OP_WRITE) + | FIELD_PREP(ASPEED_MDIO_CTRL_PHYAD, addr) + | FIELD_PREP(ASPEED_MDIO_CTRL_REGAD, reg) + | FIELD_PREP(ASPEED_MDIO_CTRL_MIIWDATA, val); + + writel(ctrl, priv->base + ASPEED_MDIO_CTRL); + + return readl_poll_timeout(priv->base + ASPEED_MDIO_CTRL, ctrl, + !(ctrl & ASPEED_MDIO_CTRL_FIRE), + ASPEED_MDIO_TIMEOUT_US); +} + +static const struct mdio_ops aspeed_mdio_ops = { + .read = aspeed_mdio_read, + .write = aspeed_mdio_write, +}; + +static int aspeed_mdio_probe(struct udevice *dev) +{ + struct aspeed_mdio_priv *priv = dev_get_priv(dev); + struct reset_ctl reset_ctl; + int ret = 0; + + priv->base = dev_read_addr_ptr(dev); + + ret = reset_get_by_index(dev, 0, &reset_ctl); + reset_deassert(&reset_ctl); + + return 0; +} + +static const struct udevice_id aspeed_mdio_ids[] = { + { .compatible = "aspeed,ast2600-mdio" }, + { } +}; + +U_BOOT_DRIVER(aspeed_mdio) = { + .name = "aspeed_mdio", + .id = UCLASS_MDIO, + .of_match = aspeed_mdio_ids, + .probe = aspeed_mdio_probe, + .ops = &aspeed_mdio_ops, + .plat_auto = sizeof(struct mdio_perdev_priv), + .priv_auto = sizeof(struct aspeed_mdio_priv), +}; -- 2.25.1

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[PATCH v2] pinctrl: meson: Correct the driver GPIO declaration
by Simon Glass 15 Nov '21

15 Nov '21

This should use the provided U_BOOT_DRIVER() macro so that the driver gets added to the appropriate linker list. Fix it. Signed-off-by: Simon Glass <sjg(a)chromium.org> Fixes: 7c9dcfed50f ("pinctrl: meson: rework gx pmx function") --- Changes in v2: - Fix the gxl driver also drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c | 2 +- drivers/pinctrl/meson/pinctrl-meson-gx.h | 2 +- drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 4 ++-- drivers/pinctrl/meson/pinctrl-meson-gxl.c | 4 ++-- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c b/drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c index 159f3406a20..99502d89c6c 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c @@ -145,7 +145,7 @@ static const struct dm_gpio_ops meson_gx_gpio_ops = { .direction_output = meson_gpio_direction_output, }; -const struct driver meson_gx_gpio_driver = { +U_BOOT_DRIVER(meson_gx_gpio_driver) = { .name = "meson-gx-gpio", .id = UCLASS_GPIO, .probe = meson_gpio_probe, diff --git a/drivers/pinctrl/meson/pinctrl-meson-gx.h b/drivers/pinctrl/meson/pinctrl-meson-gx.h index 4c1aa1a3002..c70c1f51c6d 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gx.h +++ b/drivers/pinctrl/meson/pinctrl-meson-gx.h @@ -43,6 +43,6 @@ struct meson_gx_pmx_data { } extern const struct pinctrl_ops meson_gx_pinctrl_ops; -extern const struct driver meson_gx_gpio_driver; +extern U_BOOT_DRIVER(meson_gx_gpio_driver); #endif /* __PINCTRL_MESON_GX_H__ */ diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c index 8c01c739068..93a895c9fa7 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c @@ -439,7 +439,7 @@ struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data = { .num_groups = ARRAY_SIZE(meson_gxbb_periphs_groups), .num_funcs = ARRAY_SIZE(meson_gxbb_periphs_functions), .num_banks = ARRAY_SIZE(meson_gxbb_periphs_banks), - .gpio_driver = &meson_gx_gpio_driver, + .gpio_driver = DM_DRIVER_REF(meson_gx_gpio_driver), }; struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = { @@ -452,7 +452,7 @@ struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = { .num_groups = ARRAY_SIZE(meson_gxbb_aobus_groups), .num_funcs = ARRAY_SIZE(meson_gxbb_aobus_functions), .num_banks = ARRAY_SIZE(meson_gxbb_aobus_banks), - .gpio_driver = &meson_gx_gpio_driver, + .gpio_driver = DM_DRIVER_REF(meson_gx_gpio_driver), }; static const struct udevice_id meson_gxbb_pinctrl_match[] = { diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c index 51a0b4c5cad..a44145e2d4e 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c @@ -701,7 +701,7 @@ struct meson_pinctrl_data meson_gxl_periphs_pinctrl_data = { .num_groups = ARRAY_SIZE(meson_gxl_periphs_groups), .num_funcs = ARRAY_SIZE(meson_gxl_periphs_functions), .num_banks = ARRAY_SIZE(meson_gxl_periphs_banks), - .gpio_driver = &meson_gx_gpio_driver, + .gpio_driver = DM_DRIVER_REF(meson_gx_gpio_driver), }; struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data = { @@ -714,7 +714,7 @@ struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data = { .num_groups = ARRAY_SIZE(meson_gxl_aobus_groups), .num_funcs = ARRAY_SIZE(meson_gxl_aobus_functions), .num_banks = ARRAY_SIZE(meson_gxl_aobus_banks), - .gpio_driver = &meson_gx_gpio_driver, + .gpio_driver = DM_DRIVER_REF(meson_gx_gpio_driver), }; static const struct udevice_id meson_gxl_pinctrl_match[] = { -- 2.34.0.rc1.387.gb447b232ab-goog

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[PATCH u-boot-marvell 0/5] More verifications for kwbimage in SPL
by Marek Behún 15 Nov '21

15 Nov '21

From: Marek Behún <marek.behun(a)nic.cz> Hello Stefan, this series adds more checks for kwbimage validity and consistency to SPL, mainly checking image data checksum. Marek Pali Rohár (5): arm: mvebu: Check that kwbimage offset and blocksize are valid SPL: Add struct spl_boot_device parameter into spl_parse_board_header() arm: mvebu: Check that kwbimage blockid matches boot mode SPL: Add support for checking board / BootROM specific image types arm: mvebu: Check for kwbimage data checksum arch/arm/mach-mvebu/spl.c | 71 +++++++++++++++++++++++++---- arch/arm/mach-sunxi/spl_spi_sunxi.c | 2 +- common/spl/spl.c | 13 +++++- common/spl/spl_ext.c | 9 ++-- common/spl/spl_fat.c | 11 +++-- common/spl/spl_legacy.c | 3 +- common/spl/spl_mmc.c | 43 ++++++++++------- common/spl/spl_nand.c | 5 +- common/spl/spl_net.c | 2 +- common/spl/spl_nor.c | 4 +- common/spl/spl_onenand.c | 2 +- common/spl/spl_ram.c | 2 +- common/spl/spl_sata.c | 9 ++-- common/spl/spl_sdp.c | 2 +- common/spl/spl_spi.c | 9 ++-- common/spl/spl_ubi.c | 4 +- common/spl/spl_usb.c | 4 +- common/spl/spl_xip.c | 4 +- common/spl/spl_ymodem.c | 4 +- drivers/usb/gadget/f_sdp.c | 12 +++-- include/sdp.h | 3 +- include/spl.h | 7 +++ 22 files changed, 160 insertions(+), 65 deletions(-) -- 2.32.0

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[PATCH v3 0/3] fpga: zynqmp: Adding support of loading authenticated images
by Oleksandr Suvorov 15 Nov '21

15 Nov '21

This patchset introduces support for the authenticated FPGA images on ZynqMP boards, besides that introducing common way to pass the compatible property to any fpga driver. It bases on the initial work by Jorge Ramirez-Ortiz <jorge(a)foundries.io> https://patchwork.ozlabs.org/project/uboot/patch/20211015091506.2602-1-jorg… https://patchwork.ozlabs.org/project/uboot/patch/20211005111324.19749-3-jor… Changes in v3: - remove the patch which introduced CMD_SPL_FPGA_LOAD_SECURE. - fix mixing definitions/declarations. - replace strcmp() calls with more secure strncmp(). - document the "u-boot,zynqmp-fpga-ddrauth" compatible string. - fix code style by check-patch recommendations. Changes in v2: - add function fit_fpga_load() to simplify calls of fpga_load() from contexts without a compatible attribute. - move all ZynqMP-specific logic to drivers/fpga/zynqmppl.c - prepare for passing a "compatible" FDT property to any fpga driver. Oleksandr Suvorov (3): fpga: add option for loading FPGA secure bitstreams fpga: add fit_fpga_load function fpga: zynqmp: support loading authenticated images cmd/Kconfig | 3 ++- common/Kconfig.boot | 4 +-- common/spl/spl_fit.c | 6 ++--- doc/uImage.FIT/source_file_format.txt | 5 +++- drivers/fpga/Kconfig | 14 ++++++++++ drivers/fpga/fpga.c | 37 +++++++++++++++++++++------ drivers/fpga/xilinx.c | 2 +- drivers/fpga/zynqmppl.c | 25 ++++++++++++++++-- include/fpga.h | 4 +++ 9 files changed, 81 insertions(+), 19 deletions(-) -- 2.31.1

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