January 2021 - U-Boot

[PATCH v1 0/2] Fix kmeter1 support
by Heiko Schocher 22 Feb '21

22 Feb '21

Fix kmeter1 support after testing next branch on board. I try to add this board to my daily u-boot mainline tests with tbot: http://xeidos.ddns.net/ubtestresults/home Changes only in kmeter1_defconfig needed. Patches are based against next branch, commit * 0ac83d080a - Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 into next If needed, I can do a rebase to master... Heiko Schocher (2): mpc83xx: kmeter1_defconfig add missing BAT4 config mpc83xx: kmeter1: increase malloc_f space configs/kmeter1_defconfig | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.24.1

2 4

[PATCH] mpc8379erdb: Convert to DM_MMC
by sinan＠writeme.com 22 Feb '21

22 Feb '21

From: Sinan Akman <sinan(a)writeme.com> Signed-off-by: Sinan Akman <sinan(a)writeme.com> Cc: mario.six(a)gdsys.cc --- arch/powerpc/dts/Makefile | 1 + arch/powerpc/dts/mpc8379erdb.dts | 239 ++++++++++++++++++++++++++++++ board/freescale/mpc837xerdb/mpc837xerdb.c | 9 +- configs/MPC837XERDB_defconfig | 5 +- 4 files changed, 252 insertions(+), 2 deletions(-) create mode 100644 arch/powerpc/dts/mpc8379erdb.dts diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index 3195351c9c..e3ec033096 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ +dtb-$(CONFIG_TARGET_MPC837XERDB) += mpc8379erdb.dtb dtb-$(CONFIG_TARGET_MPC8548CDS) += mpc8548cds.dtb mpc8548cds_36b.dtb dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb diff --git a/arch/powerpc/dts/mpc8379erdb.dts b/arch/powerpc/dts/mpc8379erdb.dts new file mode 100644 index 0000000000..33afaf9a94 --- /dev/null +++ b/arch/powerpc/dts/mpc8379erdb.dts @@ -0,0 +1,239 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * MPC8379E RDB Device Tree Source + * + * Copyright 2020 NXP + */ + +/dts-v1/; + +/ { + compatible = "fsl,mpc8379erdb"; + + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8379@0 { + device_type = "cpu"; + reg = <0x0>; + d-cache-line-size = <32>; + i-cache-line-size = <32>; + d-cache-size = <32768>; + i-cache-size = <32768>; + timebase-frequency = <0>; + bus-frequency = <0>; + clock-frequency = <0>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; // 256MB at 0 + }; + + localbus@e0005000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,elbc", "simple-bus"; + reg = <0xe0005000 0x1000>; + interrupts = <77 0x8>; + interrupt-parent = <&ipic>; + }; + + immr@e0000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + ranges = <0 0xe0000000 0x00100000>; + reg = <0xe0000000 0x00000200>; + bus-frequency = <0>; + + wdt@200 { + device_type = "watchdog"; + compatible = "mpc83xx_wdt"; + reg = <0x200 0x100>; + }; + + gpio0: gpio@c00 { + #gpio-cells = <2>; + device_type = "gpio"; + compatible = "fsl,mpc8379-gpio", "fsl,mpc8349-gpio"; + reg = <0xc00 0x18>; + interrupts = <74 0x8>; + interrupt-parent = <&ipic>; + gpio-controller; + }; + + gpio2: gpio-controller@d00 { + #gpio-cells = <2>; + device_type = "gpio"; + compatible = "fsl,mpc8379-gpio", "fsl,mpc8349-gpio"; + reg = <0xd00 0x100>; + interrupts = <75 0x8>; + interrupt-parent = <&ipic>; + gpio-controller; + }; + + i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <14 0x8>; + interrupt-parent = <&ipic>; + dfsrr; + }; + + i2c@3100 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + compatible = "fsl-i2c"; + reg = <0x3100 0x100>; + interrupts = <15 0x8>; + interrupt-parent = <&ipic>; + dfsrr; + }; + + spi@7000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl,spi"; + reg = <0x7000 0x1000>; + interrupts = <16 0x8>; + interrupt-parent = <&ipic>; + mode = "cpu"; + }; + + sdhc@2e000 { + compatible = "fsl,esdhc"; + reg = <0x2e000 0x1000>; + bus-width = <0x4>; + clock-frequency = <0>; + }; + + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <133333333>; + interrupts = <9 0x8>; + interrupt-parent = <&ipic>; + }; + + serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x4600 0x100>; + clock-frequency = <133333333>; + interrupts = <10 0x8>; + interrupt-parent = <&ipic>; + }; + + ipic: interrupt-controller@700 { + compatible = "fsl,ipic"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x700 0x100>; + device_type = "ipic"; + }; + + pmc: power@b00 { + compatible = "fsl,mpc8379-pmc", "fsl,mpc8349-pmc"; + reg = <0xb00 0x100 0xa00 0x100>; + interrupts = <80 0x8>; + interrupt-parent = <&ipic>; + }; + + usb@23000 { + compatible = "fsl-usb2-dr"; + reg = <0x23000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&ipic>; + interrupts = <38 0x8>; + phy_type = "ulpi"; + sleep = <&pmc 0x00c00000>; + }; + + enet0: ethernet@24000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x24000 0x1000>; + + cell-index = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar", "fsl,tsec"; + reg = <0x24000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <32 0x8 33 0x8 34 0x8>; + interrupt-parent = <&ipic>; + tbi-handle = < &tbi0 >; + phy-handle = < &phy2 >; + fsl,magic-packet; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-mdio"; + reg = <0x520 0x20>; + + phy2: ethernet-phy@2 { + interrupt-parent = <&ipic>; + interrupts = <17 0x8>; + reg = <0x2>; + device_type = "ethernet-phy"; + }; + tbi0: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + + enet1: ethernet@25000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <1>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar", "fsl,tsec"; + reg = <0x25000 0x1000>; + ranges = <0x0 0x25000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <35 0x8 36 0x8 37 0x8>; + interrupt-parent = <&ipic>; + tbi-handle = <&tbi1>; + fsl,magic-packet; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x520 0x20>; + + tbi1: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + }; + +}; diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index 45038acf32..9321952674 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -136,8 +136,8 @@ int checkboard(void) int board_early_init_f(void) { -#ifdef CONFIG_FSL_SERDES immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; +#ifdef CONFIG_FSL_SERDES u32 spridr = in_be32(&immr->sysconf.spridr); /* we check only part num, and don't look for CPU revisions */ @@ -164,10 +164,16 @@ int board_early_init_f(void) break; } #endif /* CONFIG_FSL_SERDES */ + +#ifdef CONFIG_FSL_ESDHC + clrsetbits_be32(&immr->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD); + clrsetbits_be32(&immr->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD); +#endif return 0; } #ifdef CONFIG_FSL_ESDHC +#if !(CONFIG_IS_ENABLED(DM_MMC)) int board_mmc_init(bd_t *bd) { struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; @@ -186,6 +192,7 @@ int board_mmc_init(bd_t *bd) return fsl_esdhc_mmc_init(bd); } #endif +#endif /* * Miscellaneous late-boot configurations diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index fd8335ee4e..8ef193a6e5 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -160,7 +160,11 @@ CONFIG_CMD_PING=y CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="mpc8379erdb" CONFIG_ENV_ADDR=0xFE080000 +CONFIG_DM=y +CONFIG_DM_MMC=y CONFIG_FSL_SATA=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y @@ -174,4 +178,3 @@ CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y -- 2.14.5

4 6

[PATCH] sunxi: board: Splitting CHIP defconfig for nand.
by Alexandre GRIVEAUX 22 Feb '21

22 Feb '21

This patch split CHIP defconfig to add nand 4G and 8G support. Some CONFIG was put at the end of defconfig to ease comparison between: - CHIP Pro - CHIP with Toshiba 4G - CHIP with Hynix 8G Witch are essentialy the same board with differents nand and memory. Values was taken from now defunct compagny script "chip-update-firmware.sh" Signed-off-by: Alexandre GRIVEAUX <agriveaux(a)deutnet.info> --- ...CHIP_defconfig => CHIP_Hynix_8G_defconfig} | 21 +++++++++--- configs/CHIP_Toshiba_4G_defconfig | 32 +++++++++++++++++++ 2 files changed, 49 insertions(+), 4 deletions(-) rename configs/{CHIP_defconfig => CHIP_Hynix_8G_defconfig} (50%) create mode 100644 configs/CHIP_Toshiba_4G_defconfig diff --git a/configs/CHIP_defconfig b/configs/CHIP_Hynix_8G_defconfig similarity index 50% rename from configs/CHIP_defconfig rename to configs/CHIP_Hynix_8G_defconfig index a70ee31d40..4d04a2798e 100644 --- a/configs/CHIP_defconfig +++ b/configs/CHIP_Hynix_8G_defconfig @@ -4,16 +4,29 @@ CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y CONFIG_USB0_VBUS_PIN="PB10" -CONFIG_VIDEO_COMPOSITE=y CONFIG_DEFAULT_DEVICE_TREE="sun5i-r8-chip" CONFIG_SPL_I2C_SUPPORT=y -CONFIG_CMD_DFU=y -CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_DFU_RAM=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=sunxi-nand.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=sunxi-nand.0:256k(spl),256k(spl-backup),2m(uboot),2m(uboot-backup),-(UBI)" +CONFIG_ENV_IS_IN_UBI=y +CONFIG_ENV_UBI_PART="UBI" +CONFIG_ENV_UBI_VOLUME="uboot-env" # CONFIG_MMC is not set +CONFIG_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_SYS_NAND_BLOCK_SIZE=0x400000 +CONFIG_SYS_NAND_PAGE_SIZE=0x4000 +CONFIG_SYS_NAND_OOBSIZE=0x680 CONFIG_AXP_ALDO3_VOLT=3300 CONFIG_AXP_ALDO4_VOLT=3300 CONFIG_CONS_INDEX=2 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_GADGET=y +CONFIG_USB_FUNCTION_MASS_STORAGE=y +CONFIG_VIDEO_COMPOSITE=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_DFU_RAM=y diff --git a/configs/CHIP_Toshiba_4G_defconfig b/configs/CHIP_Toshiba_4G_defconfig new file mode 100644 index 0000000000..bbc6cd9744 --- /dev/null +++ b/configs/CHIP_Toshiba_4G_defconfig @@ -0,0 +1,32 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SPL=y +CONFIG_MACH_SUN5I=y +CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y +CONFIG_USB0_VBUS_PIN="PB10" +CONFIG_DEFAULT_DEVICE_TREE="sun5i-r8-chip" +CONFIG_SPL_I2C_SUPPORT=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=sunxi-nand.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=sunxi-nand.0:256k(spl),256k(spl-backup),2m(uboot),2m(uboot-backup),-(UBI)" +CONFIG_ENV_IS_IN_UBI=y +CONFIG_ENV_UBI_PART="UBI" +CONFIG_ENV_UBI_VOLUME="uboot-env" +# CONFIG_MMC is not set +CONFIG_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_SYS_NAND_BLOCK_SIZE=0x400000 +CONFIG_SYS_NAND_PAGE_SIZE=0x4000 +CONFIG_SYS_NAND_OOBSIZE=0x500 +CONFIG_AXP_ALDO3_VOLT=3300 +CONFIG_AXP_ALDO4_VOLT=3300 +CONFIG_CONS_INDEX=2 +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_MUSB_GADGET=y +CONFIG_USB_FUNCTION_MASS_STORAGE=y +CONFIG_VIDEO_COMPOSITE=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_DFU_RAM=y -- 2.20.1

3 2

i2c: i2c-gpio: Fix GPIO output
by Harm Berntsen 21 Feb '21

21 Feb '21

The dm_gpio_set_dir_flags function cannot be used to update the configuration of a GPIO pin because it does a bitwise OR with the existing flags. Looks like commit 788ea834124b ("gpio: add function _dm_gpio_set_dir_flags") has introduced this behaviour and the i2c-gpio driver has been broken since. Signed-off-by: Harm Berntsen <harm.berntsen(a)nedap.com> CC: Heiko Schocher <hs(a)denx.de> CC: Patrick Delaunay <patrick.delaunay(a)st.com> --- drivers/i2c/i2c-gpio.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/i2c/i2c-gpio.c b/drivers/i2c/i2c-gpio.c index 381938c956..9c5e0d4d68 100644 --- a/drivers/i2c/i2c-gpio.c +++ b/drivers/i2c/i2c-gpio.c @@ -50,9 +50,10 @@ static void i2c_gpio_sda_set(struct i2c_gpio_bus *bus, int bit) struct gpio_desc *sda = &bus->gpios[PIN_SDA]; if (bit) - dm_gpio_set_dir_flags(sda, GPIOD_IS_IN); + sda->flags = (sda->flags & ~GPIOD_IS_OUT) | GPIOD_IS_IN; else - dm_gpio_set_dir_flags(sda, GPIOD_IS_OUT); + sda->flags = (sda->flags & (~GPIOD_IS_IN & ~GPIOD_IS_OUT_ACTIVE)) | GPIOD_IS_OUT; + dm_gpio_set_dir(sda); } static void i2c_gpio_scl_set(struct i2c_gpio_bus *bus, int bit) @@ -61,14 +62,16 @@ static void i2c_gpio_scl_set(struct i2c_gpio_bus *bus, int bit) int count = 0; if (bit) { - dm_gpio_set_dir_flags(scl, GPIOD_IS_IN); + scl->flags = (scl->flags & ~GPIOD_IS_OUT) | GPIOD_IS_IN; + dm_gpio_set_dir(scl); while (!dm_gpio_get_value(scl) && count++ < 100000) udelay(1); if (!dm_gpio_get_value(scl)) pr_err("timeout waiting on slave to release scl\n"); } else { - dm_gpio_set_dir_flags(scl, GPIOD_IS_OUT); + scl->flags = (scl->flags & (~GPIOD_IS_IN & ~GPIOD_IS_OUT_ACTIVE)) | GPIOD_IS_OUT; + dm_gpio_set_dir(scl); } } @@ -76,11 +79,11 @@ static void i2c_gpio_scl_set(struct i2c_gpio_bus *bus, int bit) static void i2c_gpio_scl_set_output_only(struct i2c_gpio_bus *bus, int bit) { struct gpio_desc *scl = &bus->gpios[PIN_SCL]; - ulong flags = GPIOD_IS_OUT; + scl->flags = (scl->flags & (~GPIOD_IS_IN & ~GPIOD_IS_OUT_ACTIVE)) | GPIOD_IS_OUT; if (bit) - flags |= GPIOD_IS_OUT_ACTIVE; - dm_gpio_set_dir_flags(scl, flags); + scl->flags |= GPIOD_IS_OUT_ACTIVE; + dm_gpio_set_dir(scl); } static void i2c_gpio_write_bit(struct i2c_gpio_bus *bus, int delay, uchar bit) -- 2.29.2

2 1

[PATCH] i2c: at91: fix crash when using 'i2c probe'
by Eugen Hristev 21 Feb '21

21 Feb '21

When issuing 'i2c probe', the driver was crashing, because at probe there is a request with zero length buffer to write to i2c bus. The xfer_msg function assumes the buffer is always there, and never checks for the buffer length. => i2c dev 0 Setting bus to 0 => i2c probe Valid chip addresses: data abort pc : [<7ffa97dc>] lr : [<7ffa96f8>] reloc pc : [<66f277dc>] lr : [<66f276f8>] sp : 7fb7c110 ip : 7ff87a28 fp : 7ff99938 r10: 00000002 r9 : 7fb7dec0 r8 : 00000000 r7 : e181c600 r6 : 7fb88c20 r5 : 00000000 r4 : 7fb7c128 r3 : 00000000 r2 : 00000001 r1 : 00000000 r0 : 00000009 Flags: nZCv IRQs off FIQs off Mode SVC_32 Code: eb0092f4 e1a00005 e8bd81f0 e594300c (e5d33000) Resetting CPU ... Fixes: 8800e0fa20 ("i2c: atmel: add i2c driver") Signed-off-by: Eugen Hristev <eugen.hristev(a)microchip.com> --- drivers/i2c/at91_i2c.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/i2c/at91_i2c.c b/drivers/i2c/at91_i2c.c index 9d6c6d80e2..dfd649cd57 100644 --- a/drivers/i2c/at91_i2c.c +++ b/drivers/i2c/at91_i2c.c @@ -50,6 +50,10 @@ static int at91_i2c_xfer_msg(struct at91_i2c_bus *bus, struct i2c_msg *msg) u32 i; int ret = 0; + /* if there is no message to send/receive, just exit quietly */ + if (msg->len == 0) + return ret; + readl(&reg->sr); if (is_read) { writel(TWI_CR_START, &reg->cr); -- 2.25.1

2 1

[PATCH v4 0/8] spl: fit: Play nicely with OP-TEE and Linux
by Alexandru Gagniuc 19 Feb '21

19 Feb '21

The purpose of this series is to allow SPL to boot an image with both OP-TEE and Linux. The "simple" fit code was mostly ready for this, albeit quite unreadable. To be able to make these changes reviewable, some major refactoring had to be done. In fact, of the eight changes, (6) are refactoring patches, and (2) are functional changes. I wish I could have written this with a negative line count. I have unfortunately failed at that, and this series will be adding 5 lines to u-boot. The takeaway is that the following type FIT can be loaded from SPL directly: images { optee@1 { type = "tee"; os = "tee"; ... }; kernel@1 { type = "kernel"; os = "linux"; ... }; fdt(a)devicetree.dtb { ... } fdt(a)overlay.dto { ... }; }; configurations { conf@quickboot { kernel = "optee@1"; fdt = "fdt(a)stm32mp157c-ev1.dtb", "fdt(a)overlay.dto"; loadables = "kernel@1"; }; }; Changes since v2: * Fix copmiler error for IMX spl.c Changes since v2: * Fixed embarrasing rebase mishap on one of the patches. Changes since v1: * Added struct comments (Simon Glass) * Added comment do describe args of board_spl_fit_post_load() (Simon Glass) * Fixed predicate of if clause on spl_load_simple_fit() (me) Alexandru Gagniuc (8): spl: fit: Drop 'length' argument to board_spl_fit_post_load() spl: fit: Factor out FIT parsing and use a context struct spl: fit: Pass FIT context via a structure pointer spl: fit: Remove useless loop in spl_fit_get_image_name() spl: fit: Only look up FIT configuration node once image: Do not #if guard board_fit_image_post_process() prototype spl: fit: Replace #ifdef blocks with more readable constructs spl: fit: Load devicetree when a Linux payload is found arch/arm/mach-imx/spl.c | 7 +- common/spl/spl_fit.c | 261 +++++++++++++++++++++------------------- include/image.h | 7 -- include/spl.h | 4 +- 4 files changed, 142 insertions(+), 137 deletions(-) -- 2.26.2

2 16

[PATCH v2 1/1] timer: dw-apb: fix compiler warnings
by Heinrich Schuchardt 18 Feb '21

18 Feb '21

readl() and writel() expect void *. Do not pass an integer value. Remove unused include asm/arch/timer.h. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> Reviewed-by: Bin Meng <bin.meng(a)windriver.com> --- v2: correct typo in commit message --- drivers/timer/dw-apb-timer.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/timer/dw-apb-timer.c b/drivers/timer/dw-apb-timer.c index 35271b20c8..c8be4417fd 100644 --- a/drivers/timer/dw-apb-timer.c +++ b/drivers/timer/dw-apb-timer.c @@ -14,7 +14,6 @@ #include <dm/device_compat.h> #include <asm/io.h> -#include <asm/arch/timer.h> #define DW_APB_LOAD_VAL 0x0 #define DW_APB_CURR_VAL 0x4 @@ -34,7 +33,7 @@ static int dw_apb_timer_get_count(struct udevice *dev, u64 *count) * requires the count to be incrementing. Invert the * result. */ - *count = timer_conv_64(~readl(priv->regs + DW_APB_CURR_VAL)); + *count = timer_conv_64(~readl((void *)(priv->regs + DW_APB_CURR_VAL))); return 0; } @@ -61,8 +60,8 @@ static int dw_apb_timer_probe(struct udevice *dev) clk_free(&clk); /* init timer */ - writel(0xffffffff, priv->regs + DW_APB_LOAD_VAL); - writel(0xffffffff, priv->regs + DW_APB_CURR_VAL); + writel(0xffffffff, (void *)(priv->regs + DW_APB_LOAD_VAL)); + writel(0xffffffff, (void *)(priv->regs + DW_APB_CURR_VAL)); setbits_le32(priv->regs + DW_APB_CTRL, 0x3); return 0; -- 2.27.0

2 3

[PATCH v5 0/6] Add support for ECDSA image signing (with test)
by Alexandru Gagniuc 18 Feb '21

18 Feb '21

## Purpose and intent The purpose of this series is to enable ECDSA as an alternative to RSA for FIT signing. As new chips have built-in support for ECDSA verified boot, it makes sense to stick to one signing algorithm, instead of resorting to RSA for u-boot images. The focus of this series is signing an existing FIT image: mkimage -F some-existing.fit --signing-key some/key.pem Signing while assembling a FIT is not a tested use case. # Implementation ## Code organization Unlike the RSA path, which mixes host and firmware code in the same, source files, this series keeps a very clear distinction. ecdsa-libcrypto.c is intended to be used for host code and only for host code. There is more opportunity for code reuse this way. ## Signing There is one major difference from the RSA path. The 'key-name-hint' property is ignored in the ECDSA path. There are two reasons: (1) The intent of 'key-name-hint' is not clear (2) Initial implementation is much easier to review There is an intentional side-effect. The RSA path takes 'key-name-hint' to decide which key file to read from disk. In the context of "which fdt node describes my signing key", this makes sense. On the other hand, 'key-name-hint' is also used as the basename of where the key is on the filesystem. This leads to some funny search paths, such as "some/dir/(null).key" So I am using the -K option to mkimage as the _full_ path to the key file. It doesn't have to be named .key, it doesn't have to be named .crt, and it doesn't have to exist in a particular directory (as is the case for the RSA path). I understand and recognize that this discrepancy must be resolved, but resolving it right now would make the initial implementation much harder and longer. # Testing test/py/tests/test_fit_ecdsa.py is implemented withe the goal to check that the signing is done correctly, and that the signature is encoded in the proper raw format. Verification is done with pyCryptodomex, so this test will catch both coding errors and openssl bugs. This is the only scope of testing proposed here. # Things not yet resolved: - is mkimage '-k' supposed to be a directory or file path I'm hoping I can postpone answering this question pending further discussion. Changes since v4: - Fixed tools/ build issue with # FIT_SIGNATURE is not selected This caught me by surprise that the build of the host tools could somehow depend on the target configuration. In my view, the tools should behave identically across all targets. However, I've decided to go along with it, and fix the build. Changes since v3: - Don't use 'log_msg_ret()', as it's not available host-side Changes since v1 and v2: - Added lots of function comments - Replaced hardcoded error numbers with more meaningful errno numbers - Changed some error paths to use 'return log_msg_ret' Alexandru Gagniuc (6): lib: Rename rsa-checksum.c to hash-checksum.c lib/rsa: Make fdt_add_bignum() available outside of RSA code lib: Add support for ECDSA image signing doc: signature.txt: Document devicetree format for ECDSA keys test/py: Add pycryptodomex to list of required pakages test/py: ecdsa: Add test for mkimage ECDSA signing common/image-fit-sig.c | 2 +- common/image-sig.c | 13 +- doc/uImage.FIT/signature.txt | 7 +- include/image.h | 5 +- include/u-boot/ecdsa.h | 94 ++++++ include/u-boot/fdt-libcrypto.h | 27 ++ .../{rsa-checksum.h => hash-checksum.h} | 0 lib/Makefile | 1 + lib/crypto/pkcs7_verify.c | 2 +- lib/crypto/x509_public_key.c | 2 +- lib/ecdsa/ecdsa-libcrypto.c | 306 ++++++++++++++++++ lib/fdt-libcrypto.c | 72 +++++ lib/{rsa/rsa-checksum.c => hash-checksum.c} | 3 +- lib/rsa/Makefile | 2 +- lib/rsa/rsa-sign.c | 65 +--- test/py/requirements.txt | 1 + test/py/tests/test_fit_ecdsa.py | 111 +++++++ tools/Makefile | 11 +- 18 files changed, 649 insertions(+), 75 deletions(-) create mode 100644 include/u-boot/ecdsa.h create mode 100644 include/u-boot/fdt-libcrypto.h rename include/u-boot/{rsa-checksum.h => hash-checksum.h} (100%) create mode 100644 lib/ecdsa/ecdsa-libcrypto.c create mode 100644 lib/fdt-libcrypto.c rename lib/{rsa/rsa-checksum.c => hash-checksum.c} (96%) create mode 100644 test/py/tests/test_fit_ecdsa.py -- 2.26.2

4 11

[PATCH V2] cmd: mmc: update the mmc command's usage about argument
by Jaehoon Chung 18 Feb '21

18 Feb '21

It's confusing whether arguments are optional or mandatory. Update the command's usage to clarify how to use. Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- Changed on V2 - Update commit-msg - Add Simon's Reviewed-by tag --- cmd/mmc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/cmd/mmc.c b/cmd/mmc.c index 1529a3e05ddd..cb6b59f36a43 100644 --- a/cmd/mmc.c +++ b/cmd/mmc.c @@ -1017,13 +1017,13 @@ U_BOOT_CMD( " Power cycling is required to initialize partitions after set to complete.\n" #endif #ifdef CONFIG_SUPPORT_EMMC_BOOT - "mmc bootbus dev boot_bus_width reset_boot_bus_width boot_mode\n" + "mmc bootbus <dev> <boot_bus_width> <reset_boot_bus_width> <boot_mode>\n" " - Set the BOOT_BUS_WIDTH field of the specified device\n" "mmc bootpart-resize <dev> <boot part size MB> <RPMB part size MB>\n" " - Change sizes of boot and RPMB partitions of specified device\n" - "mmc partconf dev [boot_ack boot_partition partition_access]\n" + "mmc partconf <dev> [boot_ack boot_partition partition_access]\n" " - Show or change the bits of the PARTITION_CONFIG field of the specified device\n" - "mmc rst-function dev value\n" + "mmc rst-function <dev> <value>\n" " - Change the RST_n_FUNCTION field of the specified device\n" " WARNING: This is a write-once field and 0 / 1 / 2 are the only valid values.\n" #endif -- 2.29.0

1 1

[PATCH] mmc: initialize an err variable
by Jaehoon Chung 18 Feb '21

18 Feb '21

Initialize an err variable to 0. Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> --- drivers/mmc/mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index a6394bcf308f..5151339d3aa3 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -2062,7 +2062,7 @@ static int mmc_select_hs400es(struct mmc *mmc) static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps) { - int err; + int err = 0; const struct mode_width_tuning *mwt; const struct ext_csd_bus_width *ecbw; -- 2.29.0

2 2