January 2021 - U-Boot

[PATCH v2] time: Fix get_ticks being non-monotonic
by Sean Anderson 02 Mar '21

02 Mar '21

get_ticks does not always succeed. Sometimes it can be called before the timer has been initialized. If it does, it returns a negative errno. This causes the timer to appear non-monotonic, because the value will become much smaller after the timer is initialized. No users of get_ticks which I checked handle errors of this kind. Further, functions like tick_to_time mangle the result of get_ticks, making it very unlikely that one could check for an error without suggesting a patch such as this one. This patch panics if we ever get an error. There are two cases in which this can occur. The first is if we couldn't find/probe the timer for some reason. One reason for this is if the timer is not available so early. This likely indicates misconfiguration. Another reason is that the timer has an invalid/missing device tree binding. In this case, panicing is also correct. The second case covers errors calling get_count. This can only occur if the timer is missing a get_count function (or on RISC-V, but that should be fixed soon). Fixes: c8a7ba9e6a5 Signed-off-by: Sean Anderson <seanga2(a)gmail.com> --- Changes in v2: - Panic on error lib/time.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/time.c b/lib/time.c index 47f8c84327..88bc50405f 100644 --- a/lib/time.c +++ b/lib/time.c @@ -91,13 +91,13 @@ uint64_t notrace get_ticks(void) ret = dm_timer_init(); if (ret) - return ret; + panic("Could not initialize timer (err %d)\n", ret); #endif } ret = timer_get_count(gd->timer, &count); if (ret) - return ret; + panic("Could not read count from timer (err %d)\n", ret); return count; } -- 2.28.0

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[PATCH 0/2] pinctrl: at91-pio4: add support for slew-rate
by Claudiu Beznea 26 Feb '21

26 Feb '21

Hi, This series adds support for slew rate on AT91 PIO4 driver. The support is enabled on SAMA7G5. Thank you, Claudiu Beznea Claudiu Beznea (2): dt-bindings: pinctrl: at91-pio4: add slew-rate pinctrl: at91-pio4: add support for slew-rate arch/arm/mach-at91/include/mach/atmel_pio4.h | 1 + .../pinctrl/atmel,at91-pio4-pinctrl.txt | 7 +++--- drivers/pinctrl/pinctrl-at91-pio4.c | 26 +++++++++++++++++++--- 3 files changed, 28 insertions(+), 6 deletions(-) -- 2.7.4

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[PATCH v1 4/7] write WPEN bit for SST26* devices when locking
by Bernhard Kirchen 26 Feb '21

26 Feb '21

"sf protect lock" did only protect against accidental writes by software. it did not lock down the config or block-protection registers if the WP# pin was deasserted. hardware write protection was never enabled for these devices. this change implements setting the WPEN bit and clearing the IOC bit in SST26* devices' config register if any block is protected by "sf protect lock" command, thus enabling hardware write protection. this behavior is similar to the "sf protect lock" implementation for Micron (and compatible) chips. Signed-off-by: Bernhard Kirchen <bernhard.kirchen(a)mbconnectline.com> --- drivers/mtd/spi/spi-nor-core.c | 64 ++++++++++++++++++++++++++++++++-- include/linux/mtd/spi-nor.h | 1 + 2 files changed, 63 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 050aeac3fa..10c01cf20e 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -185,7 +185,9 @@ static int read_fsr(struct spi_nor *nor) * location. Return the configuration register value. * Returns negative if error occurred. */ -#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) +#if defined(CONFIG_SPI_FLASH_SPANSION) || \ + defined(CONFIG_SPI_FLASH_WINBOND) || \ + defined(CONFIG_SPI_FLASH_SST) static int read_cr(struct spi_nor *nor) { int ret; @@ -972,6 +974,8 @@ read_err: #define SST26_MAX_BPR_REG_LEN (18 + 1) #define SST26_BOUND_REG_SIZE ((32 + SST26_BPR_8K_NUM * 8) * SZ_1K) +static int write_cr(struct spi_nor *nor, u8 value); + enum lock_ctl { SST26_CTL_LOCK, SST26_CTL_UNLOCK, @@ -994,6 +998,35 @@ static bool sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl ctl) return false; } +static int sst26_hardware_write_protection(struct spi_nor *nor, bool lock) +{ + int ret; + u8 cr_val; + + cr_val = read_cr(nor); + if (cr_val < 0) { + dev_err(nor->dev, "fail to read config register value\n"); + return cr_val; + } + + cr_val &= ~CR_WPEN; + + if (lock) { + // disallow further writes if WP# pin is not asserted. + cr_val |= CR_WPEN; + // force quad SPI disabled as otherwise WP# pin works as data line. + cr_val &= ~CR_QUAD_EN_SPAN; + } + + ret = write_cr(nor, cr_val); + if (ret < 0) { + dev_err(nor->dev, "fail to configure WP# pin (hardware write protection)\n"); + return ret; + } + + return 0; +} + /* * Lock, unlock or check lock status of the flash region of the flash (depending * on the lock_ctl value) @@ -1101,6 +1134,14 @@ static int sst26_lock_ctl(struct spi_nor *nor, loff_t ofs, uint64_t len, enum lo return ret; } + // enable hardware write protection iff any protection bit is set + for (i = 0; i < bpr_size; ++i) + if (bpr_buff[i] != 0) + break; + ret = sst26_hardware_write_protection(nor, i < bpr_size); + if (ret < 0) + return ret; + // ignore return value. even if write disable failed, the actual task // (write block protecton register) was completed successfully. write_disable(nor); @@ -1339,7 +1380,9 @@ static int macronix_quad_enable(struct spi_nor *nor) } #endif -#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) +#if defined(CONFIG_SPI_FLASH_SPANSION) || \ + defined(CONFIG_SPI_FLASH_WINBOND) || \ + defined(CONFIG_SPI_FLASH_SST) /* * Write status Register and configuration register with 2 bytes * The first byte will be written to the status register, while the @@ -1369,6 +1412,23 @@ static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr) return 0; } +static int write_cr(struct spi_nor *nor, u8 value) +{ + int ret; + u8 sr_cr[2]; + + ret = read_sr(nor); + if (ret < 0) + return ret; + + sr_cr[0] = ret; + sr_cr[1] = value; + + return write_sr_cr(nor, sr_cr); +} +#endif + +#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) /** * spansion_read_cr_quad_enable() - set QE bit in Configuration Register. * @nor: pointer to a 'struct spi_nor' diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 4a8e19ee4f..ee5a59cf0a 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -151,6 +151,7 @@ /* Configuration Register bits. */ #define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */ +#define CR_WPEN BIT(7) /* SST26* Write-Protection Pin (WP#) Enable */ /* Status Register 2 bits. */ #define SR2_QUAD_EN_BIT7 BIT(7) -- 2.29.2

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[PATCH 1/2] spi: nxp_fspi: Fix error reporting
by Adam Ford 26 Feb '21

26 Feb '21

On the i.MX8M Mini, ret = clk_set_rate() sets ret to the value of the rate the clock was able to set. When checking for errors, it only checks that it is not NULL. Since positive numbers are not errors, only check for negative numbers when handling errors. Fixes: 383fded70c4f ("spi: nxp_fspi: new driver for the FlexSPI controller") Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/drivers/spi/nxp_fspi.c b/drivers/spi/nxp_fspi.c index 006dd04b9e..d74561578a 100644 --- a/drivers/spi/nxp_fspi.c +++ b/drivers/spi/nxp_fspi.c @@ -815,7 +815,7 @@ static int nxp_fspi_default_setup(struct nxp_fspi *f) /* the default frequency, we will change it later if necessary. */ ret = clk_set_rate(&f->clk, 20000000); - if (ret) + if (ret < 0) return ret; ret = nxp_fspi_clk_prep_enable(f); @@ -906,7 +906,7 @@ static int nxp_fspi_set_speed(struct udevice *bus, uint speed) nxp_fspi_clk_disable_unprep(f); ret = clk_set_rate(&f->clk, speed); - if (ret) + if (ret < 0) return ret; ret = nxp_fspi_clk_prep_enable(f); -- 2.25.1

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[PATCH v1 3/7] SST26* locking: need to enable write
by Bernhard Kirchen 26 Feb '21

26 Feb '21

prior to using the WBPR (write block protection register) command to write new block protection register values, the WREN command must be sent. otherwise the new values are not applied. Signed-off-by: Bernhard Kirchen <bernhard.kirchen(a)mbconnectline.com> --- drivers/mtd/spi/spi-nor-core.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index e16b0e1462..050aeac3fa 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -1091,12 +1091,20 @@ static int sst26_lock_ctl(struct spi_nor *nor, loff_t ofs, uint64_t len, enum lo if (ctl == SST26_CTL_CHECK) return 0; + ret = write_enable(nor); + if (ret < 0) + return ret; + ret = nor->write_reg(nor, SPINOR_OP_WRITE_BPR, bpr_buff, bpr_size); if (ret < 0) { dev_err(nor->dev, "fail to write block-protection register\n"); return ret; } + // ignore return value. even if write disable failed, the actual task + // (write block protecton register) was completed successfully. + write_disable(nor); + return 0; } -- 2.29.2

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[PATCH v1 0/7] fix and improve Micron/SST26* SPI NOR protection handling
by Bernhard Kirchen 26 Feb '21

26 Feb '21

these patches improve the existing SPI NOR flash protection features by enabling hardware write protection where applicable, by fixing bugs, and by providing more information on the status of protection. this shall make using the protection feature more user-friendly and help meeting user expectations. Bernhard Kirchen (7): command sf: help text format sf protect: warn about failed (un)lock operation SST26* locking: need to enable write write WPEN bit for SST26* devices when locking sf protect (un)lock for SST26*: test BPR values fix sst26_process_bpr check provide "sf protect check" command cmd/sf.c | 74 ++++++++----- drivers/mtd/spi/spi-nor-core.c | 186 ++++++++++++++++++++++++++++----- include/linux/mtd/spi-nor.h | 18 +++- include/spi_flash.h | 8 ++ 4 files changed, 232 insertions(+), 54 deletions(-) -- 2.29.2

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[PATCH 0/1] Add flash protection support for Winbond's w25q128
by Su Baocheng 26 Feb '21

26 Feb '21

From: Su Baocheng <baocheng_su(a)siemens.com> According to datasheets, all 3 types of w25q128 support ST Micro-like flash protection that using BP{0-2}/TB bits in status register. Su Baocheng (1): mtd: spi-nor-ids: Add support of flash protection to w25q128 drivers/mtd/spi/spi-nor-ids.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) -- 2.25.1

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[PATCH] mtd: spi-nor.h: Change spaces to tabs
by Bin Meng 26 Feb '21

26 Feb '21

U-Boot coding convention prefers tabs over spaces. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- include/linux/mtd/spi-nor.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 233fdc341a..988c1bd0c1 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -48,13 +48,13 @@ #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */ #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */ #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */ -#define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */ -#define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */ +#define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */ +#define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */ #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */ #define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */ #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */ -#define SPINOR_OP_PP_1_1_8 0x82 /* Octal page program */ -#define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */ +#define SPINOR_OP_PP_1_1_8 0x82 /* Octal page program */ +#define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */ #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */ #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */ #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */ @@ -75,13 +75,13 @@ #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */ #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */ #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */ -#define SPINOR_OP_READ_1_1_8_4B 0x7c /* Read data bytes (Octal Output SPI) */ -#define SPINOR_OP_READ_1_8_8_4B 0xcc /* Read data bytes (Octal I/O SPI) */ +#define SPINOR_OP_READ_1_1_8_4B 0x7c /* Read data bytes (Octal Output SPI) */ +#define SPINOR_OP_READ_1_8_8_4B 0xcc /* Read data bytes (Octal I/O SPI) */ #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */ #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */ #define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */ -#define SPINOR_OP_PP_1_1_8_4B 0x84 /* Octal page program */ -#define SPINOR_OP_PP_1_8_8_4B 0x8e /* Octal page program */ +#define SPINOR_OP_PP_1_1_8_4B 0x84 /* Octal page program */ +#define SPINOR_OP_PP_1_8_8_4B 0x8e /* Octal page program */ #define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */ #define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */ #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */ @@ -122,8 +122,8 @@ #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ /* Used for Micron flashes only. */ -#define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */ -#define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */ +#define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */ +#define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */ /* Status Register bits. */ #define SR_WIP BIT(0) /* Write in progress */ -- 2.25.1

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[PATCH 1/2] mtd: spi-nor: Correct spi-nor-ids.c license to GPL-2.0
by Alper Nebi Yasak 26 Feb '21

26 Feb '21

The contents of this file were introduced in commit 7aeedac01534 ("mtd: spi: Port SPI NOR framework from Linux") to spi-nor-core.c under GPL-2.0; then moved with some modifications into a new spi-nor-ids.c file in commit 778572d7cb1e ("mtd: spi: Add lightweight SPI flash stack for SPL") which marked the then-new file incorrectly as GPL-2.0+. This corrects the file's license header to GPL-2.0, which is also necessary to sync further changes from Linux. Signed-off-by: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> --- drivers/mtd/spi/spi-nor-ids.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index bc9d4f7e9f86..4de60b0165fd 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: GPL-2.0 /* * * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. -- 2.29.1

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[PATCH] ARM: imx: Add missing FEC ethernet quirk for MX8M
by Marek Vasut 25 Feb '21

25 Feb '21

The MX8M also contains a gigabit MAC, so define FEC_QUIRK_ENET_MAC. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> --- arch/arm/include/asm/arch-imx8m/imx-regs.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index f1c410ec78a..3f20f8ef506 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -62,6 +62,8 @@ #define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000)) #define DDR_CSD1_BASE_ADDR 0x40000000 +#define FEC_QUIRK_ENET_MAC + #if !defined(__ASSEMBLY__) #include <asm/types.h> #include <linux/bitops.h> -- 2.29.2

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