January 2021 - U-Boot

[PATCH 1/2] timer: mtk_timer: initialize the timer before use
by Weijie Gao 19 Jan '21

19 Jan '21

The timer being used by this driver may have already been used by first stage bootloader (e.g. ATF/preloader), and it's settings may differ from what this driver is going to use. This may cause issues, such as inaccurate timer frequency due to incorrect clock divider. This patch adds the initialization code to avoid them. Signed-off-by: Weijie Gao <weijie.gao(a)mediatek.com> --- drivers/timer/mtk_timer.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/timer/mtk_timer.c b/drivers/timer/mtk_timer.c index 448a76a7e1..f6b97f868c 100644 --- a/drivers/timer/mtk_timer.c +++ b/drivers/timer/mtk_timer.c @@ -61,6 +61,16 @@ static int mtk_timer_probe(struct udevice *dev) if (!uc_priv->clock_rate) return -EINVAL; + /* + * Initialize the timer: + * 1. set clock source to system clock with clock divider setting to 1 + * 2. set timer mode to free running + * 3. reset timer counter to 0 then enable the timer + */ + writel(GPT4_CLK_SYS | GPT4_CLK_DIV1, priv->base + MTK_GPT4_CLK); + writel(GPT4_FREERUN | GPT4_CLEAR | GPT4_ENABLE, + priv->base + MTK_GPT4_CTRL); + return 0; } -- 2.17.1

3 6

[PATCH v2 1/1] pinctrl: mediatek: correct error handling
by Heinrich Schuchardt 19 Jan '21

19 Jan '21

If no GPIO controller is found, the return value should not depend on a random value on the stack. Initialize variable ret. The problem was indicated by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- v2: move the assigment to the certain code-path (Andy) --- drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index 6553dde45c..4dd3f73ead 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -615,6 +615,7 @@ static int mtk_gpiochip_register(struct udevice *parent) if (!drv) return -ENOENT; + ret = -ENOENT; dev_for_each_subnode(node, parent) if (ofnode_read_bool(node, "gpio-controller")) { ret = 0; -- 2.29.2

3 2

[PATCH] mtd: remove drivers/mtd/mw_eeprom.c
by Heinrich Schuchardt 19 Jan '21

19 Jan '21

drivers/mtd/mw_eeprom.c contains code that never worked. mw_eeprom_write() and mw_eeprom_read() have incorrect loop conditions: while (len <= 2) { CONFIG_MW_EEPROM is not set anywhere. So let's simply drop the module. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- drivers/mtd/Makefile | 1 - drivers/mtd/mw_eeprom.c | 238 ---------------------------------------- 2 files changed, 239 deletions(-) delete mode 100644 drivers/mtd/mw_eeprom.c diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile index 318788c5e2..6d77ebfaa5 100644 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -11,7 +11,6 @@ mtd-$(CONFIG_ALTERA_QSPI) += altera_qspi.o mtd-$(CONFIG_FLASH_CFI_DRIVER) += cfi_flash.o mtd-$(CONFIG_FLASH_CFI_MTD) += cfi_mtd.o mtd-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o -mtd-$(CONFIG_MW_EEPROM) += mw_eeprom.o mtd-$(CONFIG_FLASH_PIC32) += pic32_flash.o mtd-$(CONFIG_ST_SMI) += st_smi.o mtd-$(CONFIG_STM32_FLASH) += stm32_flash.o diff --git a/drivers/mtd/mw_eeprom.c b/drivers/mtd/mw_eeprom.c deleted file mode 100644 index 9837733bee..0000000000 --- a/drivers/mtd/mw_eeprom.c +++ /dev/null @@ -1,238 +0,0 @@ -/* Three-wire (MicroWire) serial eeprom driver (for 93C46 and compatibles) */ - -#include <common.h> -#include <eeprom.h> -#include <asm/ic/ssi.h> -#include <linux/delay.h> - -/* - * Serial EEPROM opcodes, including start bit - */ -#define EEP_OPC_ERASE 0x7 /* 3-bit opcode */ -#define EEP_OPC_WRITE 0x5 /* 3-bit opcode */ -#define EEP_OPC_READ 0x6 /* 3-bit opcode */ - -#define EEP_OPC_ERASE_ALL 0x12 /* 5-bit opcode */ -#define EEP_OPC_ERASE_EN 0x13 /* 5-bit opcode */ -#define EEP_OPC_WRITE_ALL 0x11 /* 5-bit opcode */ -#define EEP_OPC_ERASE_DIS 0x10 /* 5-bit opcode */ - -static int addrlen; - -static void mw_eeprom_select(int dev) -{ - ssi_set_interface(2048, 0, 0, 0); - ssi_chip_select(0); - udelay(1); - ssi_chip_select(dev); - udelay(1); -} - -static int mw_eeprom_size(int dev) -{ - int x; - u16 res; - - mw_eeprom_select(dev); - ssi_tx_byte(EEP_OPC_READ); - - res = ssi_txrx_byte(0) << 8; - res |= ssi_rx_byte(); - for (x = 0; x < 16; x++) { - if (! (res & 0x8000)) { - break; - } - res <<= 1; - } - ssi_chip_select(0); - - return x; -} - -int mw_eeprom_erase_enable(int dev) -{ - mw_eeprom_select(dev); - ssi_tx_byte(EEP_OPC_ERASE_EN); - ssi_tx_byte(0); - udelay(1); - ssi_chip_select(0); - - return 0; -} - -int mw_eeprom_erase_disable(int dev) -{ - mw_eeprom_select(dev); - ssi_tx_byte(EEP_OPC_ERASE_DIS); - ssi_tx_byte(0); - udelay(1); - ssi_chip_select(0); - - return 0; -} - - -u32 mw_eeprom_read_word(int dev, int addr) -{ - u16 rcv; - u16 res; - int bits; - - mw_eeprom_select(dev); - ssi_tx_byte((EEP_OPC_READ << 5) | ((addr >> (addrlen - 5)) & 0x1f)); - rcv = ssi_txrx_byte(addr << (13 - addrlen)); - res = rcv << (16 - addrlen); - bits = 4 + addrlen; - - while (bits>0) { - rcv = ssi_rx_byte(); - if (bits > 7) { - res |= rcv << (bits - 8); - } else { - res |= rcv >> (8 - bits); - } - bits -= 8; - } - - ssi_chip_select(0); - - return res; -} - -int mw_eeprom_write_word(int dev, int addr, u16 data) -{ - u8 byte1=0; - u8 byte2=0; - - mw_eeprom_erase_enable(dev); - mw_eeprom_select(dev); - - switch (addrlen) { - case 6: - byte1 = EEP_OPC_WRITE >> 2; - byte2 = (EEP_OPC_WRITE << 6)&0xc0; - byte2 |= addr; - break; - case 7: - byte1 = EEP_OPC_WRITE >> 1; - byte2 = (EEP_OPC_WRITE << 7)&0x80; - byte2 |= addr; - break; - case 8: - byte1 = EEP_OPC_WRITE; - byte2 = addr; - break; - case 9: - byte1 = EEP_OPC_WRITE << 1; - byte1 |= addr >> 8; - byte2 = addr & 0xff; - break; - case 10: - byte1 = EEP_OPC_WRITE << 2; - byte1 |= addr >> 8; - byte2 = addr & 0xff; - break; - default: - printf("Unsupported number of address bits: %d\n", addrlen); - return -1; - - } - - ssi_tx_byte(byte1); - ssi_tx_byte(byte2); - ssi_tx_byte(data >> 8); - ssi_tx_byte(data & 0xff); - ssi_chip_select(0); - udelay(10000); /* Worst case */ - mw_eeprom_erase_disable(dev); - - return 0; -} - - -int mw_eeprom_write(int dev, int addr, u8 *buffer, int len) -{ - int done; - - done = 0; - if (addr & 1) { - u16 temp = mw_eeprom_read_word(dev, addr >> 1); - temp &= 0xff00; - temp |= buffer[0]; - - mw_eeprom_write_word(dev, addr >> 1, temp); - len--; - addr++; - buffer++; - done++; - } - - while (len <= 2) { - mw_eeprom_write_word(dev, addr >> 1, *(u16*)buffer); - len-=2; - addr+=2; - buffer+=2; - done+=2; - } - - if (len) { - u16 temp = mw_eeprom_read_word(dev, addr >> 1); - temp &= 0x00ff; - temp |= buffer[0] << 8; - - mw_eeprom_write_word(dev, addr >> 1, temp); - len--; - addr++; - buffer++; - done++; - } - - return done; -} - - -int mw_eeprom_read(int dev, int addr, u8 *buffer, int len) -{ - int done; - - done = 0; - if (addr & 1) { - u16 temp = mw_eeprom_read_word(dev, addr >> 1); - buffer[0]= temp & 0xff; - - len--; - addr++; - buffer++; - done++; - } - - while (len <= 2) { - *(u16*)buffer = mw_eeprom_read_word(dev, addr >> 1); - len-=2; - addr+=2; - buffer+=2; - done+=2; - } - - if (len) { - u16 temp = mw_eeprom_read_word(dev, addr >> 1); - buffer[0] = temp >> 8; - - len--; - addr++; - buffer++; - done++; - } - - return done; -} - -int mw_eeprom_probe(int dev) -{ - addrlen = mw_eeprom_size(dev); - - if (addrlen < 6 || addrlen > 10) { - return -1; - } - return 0; -} -- 2.29.2

2 1

[PATCH 1/1] drivers: qe: avoid double free()
by Heinrich Schuchardt 19 Jan '21

19 Jan '21

Avoid calling free(addr) twice if the device for ucode is not found. The problem was indicated by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- drivers/qe/qe.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 1a829b5a4c..259e4e3e67 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -288,7 +288,6 @@ void u_qe_init(void) struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); if (!mmc) { - free(addr); printf("\nMMC cannot find device for ucode\n"); } else { printf("\nMMC read: dev # %u, block # %u, count %u ...\n", -- 2.29.2

2 1

[PATCH 1/1] mmc: fsl_esdhc_spl: remove superfluous free()
by Heinrich Schuchardt 19 Jan '21

19 Jan '21

Freeing a buffer before calling hang() is superfluous. Removing the call reduces the SPL size. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- drivers/mmc/fsl_esdhc_spl.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c index afe55fad9d..bee76572ac 100644 --- a/drivers/mmc/fsl_esdhc_spl.c +++ b/drivers/mmc/fsl_esdhc_spl.c @@ -91,20 +91,17 @@ void __noreturn mmc_boot(void) CONFIG_CFG_DATA_SECTOR, 1, tmp_buf); if (err != 1) { puts("spl: mmc read failed!!\n"); - free(tmp_buf); hang(); } val = *(tmp_buf + MBRDBR_BOOT_SIG_55); if (0x55 != val) { puts("spl: mmc signature is not valid!!\n"); - free(tmp_buf); hang(); } val = *(tmp_buf + MBRDBR_BOOT_SIG_AA); if (0xAA != val) { puts("spl: mmc signature is not valid!!\n"); - free(tmp_buf); hang(); } -- 2.29.2

3 2

[PATCH 1/1] dma: bcm6348: incorrect buffer allocation
by Heinrich Schuchardt 19 Jan '21

19 Jan '21

Calling calloc() for 0 members does not make any sense. Setting ch_priv->busy_desc = NULL for ch_priv->desc_cnt > 0 is equally unreasonable. The current code will lead to a NULL dereference in bcm6348_iudma_enable(). The assignments for ch_priv->busy_desc are obviously swapped. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- I have no device to actually test the driver. --- drivers/dma/bcm6348-iudma.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/dma/bcm6348-iudma.c b/drivers/dma/bcm6348-iudma.c index 91172d483c..81597c56a7 100644 --- a/drivers/dma/bcm6348-iudma.c +++ b/drivers/dma/bcm6348-iudma.c @@ -313,10 +313,10 @@ static int bcm6348_iudma_request(struct dma *dma) ch_priv->desc_id = 0; if (bcm6348_iudma_chan_is_rx(dma->id)) { ch_priv->desc_cnt = 0; - ch_priv->busy_desc = calloc(ch_priv->desc_cnt, sizeof(bool)); + ch_priv->busy_desc = NULL; } else { ch_priv->desc_cnt = ch_priv->dma_ring_size; - ch_priv->busy_desc = NULL; + ch_priv->busy_desc = calloc(ch_priv->desc_cnt, sizeof(bool)); } return 0; -- 2.29.2

3 3

[PATCH v4] cmd: Add a pwm command
by Pragnesh Patel 19 Jan '21

19 Jan '21

Add the command "pwm" for controlling the pwm channels. This command provides pwm invert/config/enable/disable functionalities via PWM uclass drivers Signed-off-by: Pragnesh Patel <pragnesh.patel(a)sifive.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- Changes in v4: - Add ut_assertok() for every run_command() Changes in v3: - Replace goto with return - Print return value for error - Change the assert condition for success Changes in v2: - Add test for pwm command README | 1 + cmd/Kconfig | 6 ++ cmd/Makefile | 1 + cmd/pwm.c | 117 ++++++++++++++++++++++++++++++++++++++ configs/sandbox_defconfig | 1 + test/cmd/Makefile | 1 + test/cmd/pwm.c | 47 +++++++++++++++ 7 files changed, 174 insertions(+) create mode 100644 cmd/pwm.c create mode 100644 test/cmd/pwm.c diff --git a/README b/README index cb49aa15da..dab291e0d0 100644 --- a/README +++ b/README @@ -3160,6 +3160,7 @@ i2c - I2C sub-system sspi - SPI utility commands base - print or set address offset printenv- print environment variables +pwm - control pwm channels setenv - set environment variables saveenv - save environment variables to persistent storage protect - enable or disable FLASH write protection diff --git a/cmd/Kconfig b/cmd/Kconfig index 1595de999b..0d085108f4 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -918,6 +918,12 @@ config CMD_GPIO help GPIO support. +config CMD_PWM + bool "pwm" + depends on DM_PWM + help + Control PWM channels, this allows invert/config/enable/disable PWM channels. + config CMD_GPT bool "GPT (GUID Partition Table) command" select EFI_PARTITION diff --git a/cmd/Makefile b/cmd/Makefile index dd86675bf2..75df3c136c 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -120,6 +120,7 @@ endif obj-$(CONFIG_CMD_PINMUX) += pinmux.o obj-$(CONFIG_CMD_PMC) += pmc.o obj-$(CONFIG_CMD_PSTORE) += pstore.o +obj-$(CONFIG_CMD_PWM) += pwm.o obj-$(CONFIG_CMD_PXE) += pxe.o pxe_utils.o obj-$(CONFIG_CMD_WOL) += wol.o obj-$(CONFIG_CMD_QFW) += qfw.o diff --git a/cmd/pwm.c b/cmd/pwm.c new file mode 100644 index 0000000000..5849fc57b6 --- /dev/null +++ b/cmd/pwm.c @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Control PWM channels + * + * Copyright (c) 2020 SiFive, Inc + * author: Pragnesh Patel <pragnesh.patel(a)sifive.com> + */ + +#include <command.h> +#include <dm.h> +#include <pwm.h> + +enum pwm_cmd { + PWM_SET_INVERT, + PWM_SET_CONFIG, + PWM_SET_ENABLE, + PWM_SET_DISABLE, +}; + +static int do_pwm(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + const char *str_cmd, *str_channel = NULL, *str_enable = NULL; + const char *str_pwm = NULL, *str_period = NULL, *str_duty = NULL; + enum pwm_cmd sub_cmd; + struct udevice *dev; + u32 channel, pwm_enable, pwm_dev, period_ns = 0, duty_ns = 0; + int ret; + + if (argc < 4) + return CMD_RET_USAGE; + + str_cmd = argv[1]; + argc -= 2; + argv += 2; + + if (argc > 0) { + str_pwm = *argv; + argc--; + argv++; + } + + if (!str_pwm) + return CMD_RET_USAGE; + + switch (*str_cmd) { + case 'i': + sub_cmd = PWM_SET_INVERT; + break; + case 'c': + sub_cmd = PWM_SET_CONFIG; + break; + case 'e': + sub_cmd = PWM_SET_ENABLE; + break; + case 'd': + sub_cmd = PWM_SET_DISABLE; + break; + default: + return CMD_RET_USAGE; + } + + pwm_dev = simple_strtoul(str_pwm, NULL, 10); + ret = uclass_get_device(UCLASS_PWM, pwm_dev, &dev); + if (ret) { + printf("pwm: '%s' not found\n", str_pwm); + return cmd_process_error(cmdtp, ret); + } + + if (argc > 0) { + str_channel = *argv; + channel = simple_strtoul(str_channel, NULL, 10); + argc--; + argv++; + } else { + return CMD_RET_USAGE; + } + + if (sub_cmd == PWM_SET_INVERT && argc > 0) { + str_enable = *argv; + pwm_enable = simple_strtoul(str_enable, NULL, 10); + ret = pwm_set_invert(dev, channel, pwm_enable); + } else if (sub_cmd == PWM_SET_CONFIG && argc == 2) { + str_period = *argv; + argc--; + argv++; + period_ns = simple_strtoul(str_period, NULL, 10); + + if (argc > 0) { + str_duty = *argv; + duty_ns = simple_strtoul(str_duty, NULL, 10); + } + + ret = pwm_set_config(dev, channel, period_ns, duty_ns); + } else if (sub_cmd == PWM_SET_ENABLE) { + ret = pwm_set_enable(dev, channel, 1); + } else if (sub_cmd == PWM_SET_DISABLE) { + ret = pwm_set_enable(dev, channel, 0); + } else { + printf("PWM arguments missing\n"); + return CMD_RET_FAILURE; + } + + if (ret) { + printf("error(%d)\n", ret); + return CMD_RET_FAILURE; + } + + return CMD_RET_SUCCESS; +} + +U_BOOT_CMD(pwm, 6, 0, do_pwm, + "control pwm channels", + "pwm <invert> <pwm_dev_num> <channel> <polarity>\n" + "pwm <config> <pwm_dev_num> <channel> <period_ns> <duty_ns>\n" + "pwm <enable/disable> <pwm_dev_num> <channel>\n" + "Note: All input values are in decimal"); diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index f2a767a4cd..7a16603461 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -58,6 +58,7 @@ CONFIG_CMD_LSBLK=y CONFIG_CMD_MUX=y CONFIG_CMD_OSD=y CONFIG_CMD_PCI=y +CONFIG_CMD_PWM=y CONFIG_CMD_READ=y CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_SPI=y diff --git a/test/cmd/Makefile b/test/cmd/Makefile index 859dcda239..dde98dd371 100644 --- a/test/cmd/Makefile +++ b/test/cmd/Makefile @@ -4,3 +4,4 @@ obj-y += mem.o obj-$(CONFIG_CMD_MEM_SEARCH) += mem_search.o +obj-$(CONFIG_CMD_PWM) += pwm.o diff --git a/test/cmd/pwm.c b/test/cmd/pwm.c new file mode 100644 index 0000000000..5343af83fa --- /dev/null +++ b/test/cmd/pwm.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Test for pwm command + * + * Copyright 2020 SiFive, Inc + * + * Authors: + * Pragnesh Patel <pragnesh.patel(a)sifive.com> + */ + +#include <dm.h> +#include <dm/test.h> +#include <test/test.h> +#include <test/ut.h> + +/* Basic test of 'pwm' command */ +static int dm_test_pwm_cmd(struct unit_test_state *uts) +{ + struct udevice *dev; + + ut_assertok(uclass_get_device(UCLASS_PWM, 0, &dev)); + ut_assertnonnull(dev); + + ut_assertok(console_record_reset_enable()); + + /* pwm <invert> <pwm_dev_num> <channel> <polarity> */ + ut_assertok(run_command("pwm invert 0 0 1", 0)); + ut_assert_console_end(); + + ut_assertok(run_command("pwm invert 0 0 0", 0)); + ut_assert_console_end(); + + /* pwm <config> <pwm_dev_num> <channel> <period_ns> <duty_ns> */ + ut_assertok(run_command("pwm config 0 0 10 50", 0)); + ut_assert_console_end(); + + /* pwm <enable/disable> <pwm_dev_num> <channel> */ + ut_assertok(run_command("pwm enable 0 0", 0)); + ut_assert_console_end(); + + ut_assertok(run_command("pwm disable 0 0", 0)); + ut_assert_console_end(); + + return 0; +} + +DM_TEST(dm_test_pwm_cmd, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC); -- 2.17.1

3 4

[PATCH] power: pmic: add driver for Monolithic Power mp5416
by Tim Harvey 19 Jan '21

19 Jan '21

This adds basic register access and child regulator binding for the Monolithic MP5416 Power Management IC which integrates four DC/DC switching converters and five LDO regulators. Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> --- drivers/power/pmic/Kconfig | 15 +++++++ drivers/power/pmic/Makefile | 1 + drivers/power/pmic/mp5416.c | 98 +++++++++++++++++++++++++++++++++++++++++++++ include/power/mp5416.h | 41 +++++++++++++++++++ 4 files changed, 155 insertions(+) create mode 100644 drivers/power/pmic/mp5416.c create mode 100644 include/power/mp5416.h diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index a62aa38..13a9cb0 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -91,6 +91,21 @@ config DM_PMIC_FAN53555 The driver implements read/write operations for use with the FAN53555 regulator driver and binds the regulator driver to its node. +config DM_PMIC_MP5416 + bool "Enable Driver Model for PMIC MP5416" + depends on DM_PMIC + help + This config enables implementation of driver-model pmic uclass features + for PMIC MP5416. The driver implements read/write operations. + +config SPL_DM_PMIC_MP5416 + bool "Enable Driver Model for PMIC MP5416 in SPL stage" + depends on DM_PMIC + help + This config enables implementation of driver-model pmic uclass + features for PMIC MP5416. The driver implements read/write + operations. + config DM_PMIC_PCA9450 bool "Enable Driver Model for PMIC PCA9450" depends on DM_PMIC diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 9cd6c37..2b2a6dd 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o obj-$(CONFIG_DM_PMIC_MAX8998) += max8998.o obj-$(CONFIG_DM_PMIC_MC34708) += mc34708.o obj-$(CONFIG_$(SPL_)DM_PMIC_BD71837) += bd71837.o +obj-$(CONFIG_$(SPL_)DM_PMIC_MP5416) += mp5416.o obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o obj-$(CONFIG_$(SPL_)DM_PMIC_PCA9450) += pca9450.o obj-$(CONFIG_PMIC_S2MPS11) += s2mps11.o diff --git a/drivers/power/pmic/mp5416.c b/drivers/power/pmic/mp5416.c new file mode 100644 index 0000000..458c4df --- /dev/null +++ b/drivers/power/pmic/mp5416.c @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 Gateworks Corporation + */ +#include <common.h> +#include <errno.h> +#include <dm.h> +#include <i2c.h> +#include <log.h> +#include <power/pmic.h> +#include <power/regulator.h> +#include <power/mp5416.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct pmic_child_info pmic_children_info[] = { + /* buck */ + { .prefix = "b", .driver = MP6416_REGULATOR_DRIVER }, + /* ldo */ + { .prefix = "l", .driver = MP6416_REGULATOR_DRIVER }, + { }, +}; + +static int mp5416_reg_count(struct udevice *dev) +{ + return MP5416_NUM_OF_REGS - 1; +} + +static int mp5416_write(struct udevice *dev, uint reg, const uint8_t *buff, + int len) +{ + if (dm_i2c_write(dev, reg, buff, len)) { + pr_err("write error to device: %p register: %#x!", dev, reg); + return -EIO; + } + + return 0; +} + +static int mp5416_read(struct udevice *dev, uint reg, uint8_t *buff, int len) +{ + if (dm_i2c_read(dev, reg, buff, len)) { + pr_err("read error from device: %p register: %#x!", dev, reg); + return -EIO; + } + + return 0; +} + +static int mp5416_bind(struct udevice *dev) +{ + int children; + ofnode regulators_node; + + debug("%s %s\n", __func__, dev->name); + regulators_node = dev_read_subnode(dev, "regulators"); + if (!ofnode_valid(regulators_node)) { + debug("%s: %s regulators subnode not found!\n", __func__, + dev->name); + return -ENXIO; + } + + debug("%s: '%s' - found regulators subnode\n", __func__, dev->name); + + children = pmic_bind_children(dev, regulators_node, pmic_children_info); + if (!children) + debug("%s: %s - no child found\n", __func__, dev->name); + + /* Always return success for this device */ + return 0; +} + +static int mp5416_probe(struct udevice *dev) +{ + debug("%s %s\n", __func__, dev->name); + + return 0; +} + +static struct dm_pmic_ops mp5416_ops = { + .reg_count = mp5416_reg_count, + .read = mp5416_read, + .write = mp5416_write, +}; + +static const struct udevice_id mp5416_ids[] = { + { .compatible = "mps,mp5416", }, + { } +}; + +U_BOOT_DRIVER(pmic_mp5416) = { + .name = "mp5416 pmic", + .id = UCLASS_PMIC, + .of_match = mp5416_ids, + .bind = mp5416_bind, + .probe = mp5416_probe, + .ops = &mp5416_ops, +}; diff --git a/include/power/mp5416.h b/include/power/mp5416.h new file mode 100644 index 0000000..dc096fe --- /dev/null +++ b/include/power/mp5416.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright (C) 2020 Gateworks Corporation */ + +#ifndef MP5416_H_ +#define MP5416_H_ + +#define MP6416_REGULATOR_DRIVER "mp5416_regulator" + +enum { + MP5416_CTL0 = 0x00, + MP5416_CTL1 = 0x01, + MP5416_CTL2 = 0x02, + MP5416_ILIMIT = 0x03, + MP5416_VSET_SW1 = 0x04, + MP5416_VSET_SW2 = 0x05, + MP5416_VSET_SW3 = 0x06, + MP5416_VSET_SW4 = 0x07, + MP5416_VSET_LDO2 = 0x08, + MP5416_VSET_LDO3 = 0x09, + MP5416_VSET_LDO4 = 0x0a, + MP5416_VSET_LDO5 = 0x0b, + MP5416_STATUS1 = 0x0d, + MP5416_STATUS2 = 0x0e, + MP5416_STATUS3 = 0x0f, + MP5416_ID2 = 0x11, + MP5416_NUM_OF_REGS = 0x12, +}; + +#define MP5416_VSET_EN BIT(7) +#define MP5416_VSET_SW1_GVAL(x) ((((x) & 0x7f) * 12500) + 600000) +#define MP5416_VSET_SW2_GVAL(x) ((((x) & 0x7f) * 25000) + 800000) +#define MP5416_VSET_SW3_GVAL(x) ((((x) & 0x7f) * 12500) + 600000) +#define MP5416_VSET_SW4_GVAL(x) ((((x) & 0x7f) * 25000) + 800000) +#define MP5416_VSET_LDO_GVAL(x) ((((x) & 0x7f) * 25000) + 800000) +#define MP5416_VSET_LDO_SVAL(x) ((((x) & 0x7f) * 25000) + 800000) +#define MP5416_VSET_SW1_SVAL(x) (((x) - 600000) / 12500) +#define MP5416_VSET_SW2_SVAL(x) (((x) - 800000) / 25000) +#define MP5416_VSET_SW3_SVAL(x) (((x) - 600000) / 12500) +#define MP5416_VSET_SW4_SVAL(x) (((x) - 800000) / 25000) + +#endif -- 2.7.4

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[PATCH 0/7] Add Aspeed AST2600 support
by Chia-Wei, Wang 19 Jan '21

19 Jan '21

The patch series add the U-boot support for AST2600, which is the 7th generation BMC chip introduced by ASPEED technogology. The change includes the newly added low level platform code, Kconfig, and device tree of AST2600. In addition, certain fundamental drivers such as DRAM, reset, and watchodg are implemented for the AST2600 new design. Note that these patches currently supports only memory mapped SPI flash booting. Chia-Wei, Wang (5): wdt: aspeed: Add AST2600 watchdog support reset: aspeed: Add AST2600 reset support ARM: dts: aspeed: Add AST2600 SoC support aspeed: Add AST2600 platform support configs: aspeed: Add defconfig for AST2600 EVB Dylan Hung (1): ram: aspeed: Add AST2600 DRAM control support Ryan Chen (1): clk: aspeed: Add AST2600 clock support arch/arm/dts/Makefile | 1 + arch/arm/dts/ast2600-evb.dts | 179 ++ arch/arm/dts/ast2600-u-boot.dtsi | 44 + arch/arm/dts/ast2600.dtsi | 1946 +++++++++++++++++ arch/arm/include/asm/arch-aspeed/boot0.h | 23 + arch/arm/include/asm/arch-aspeed/platform.h | 5 + .../arm/include/asm/arch-aspeed/scu_ast2600.h | 338 +++ .../include/asm/arch-aspeed/sdram_ast2600.h | 163 ++ .../arm/include/asm/arch-aspeed/wdt_ast2600.h | 129 ++ arch/arm/mach-aspeed/Kconfig | 20 + arch/arm/mach-aspeed/Makefile | 1 + arch/arm/mach-aspeed/ast2600/Kconfig | 17 + arch/arm/mach-aspeed/ast2600/Makefile | 2 + arch/arm/mach-aspeed/ast2600/board_common.c | 105 + arch/arm/mach-aspeed/ast2600/lowlevel_init.S | 233 ++ arch/arm/mach-aspeed/ast2600/spl.c | 55 + board/aspeed/evb_ast2600/Kconfig | 12 + board/aspeed/evb_ast2600/Makefile | 1 + board/aspeed/evb_ast2600/evb_ast2600.c | 5 + configs/evb-ast2600_defconfig | 69 + drivers/clk/aspeed/Makefile | 1 + drivers/clk/aspeed/clk_ast2600.c | 1173 ++++++++++ drivers/ram/aspeed/Kconfig | 61 +- drivers/ram/aspeed/Makefile | 3 +- drivers/ram/aspeed/sdram_ast2600.c | 1061 +++++++++ drivers/reset/Kconfig | 9 + drivers/reset/Makefile | 1 + drivers/reset/reset-ast2600.c | 108 + drivers/sysreset/sysreset_ast.c | 5 + drivers/watchdog/Kconfig | 9 + drivers/watchdog/Makefile | 1 + drivers/watchdog/ast2600_wdt.c | 110 + include/configs/evb_ast2600.h | 16 + include/dt-bindings/clock/ast2600-clock.h | 62 + include/dt-bindings/reset/ast2600-reset.h | 70 + 35 files changed, 6036 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/ast2600-evb.dts create mode 100644 arch/arm/dts/ast2600-u-boot.dtsi create mode 100644 arch/arm/dts/ast2600.dtsi create mode 100644 arch/arm/include/asm/arch-aspeed/boot0.h create mode 100644 arch/arm/include/asm/arch-aspeed/scu_ast2600.h create mode 100644 arch/arm/include/asm/arch-aspeed/sdram_ast2600.h create mode 100644 arch/arm/include/asm/arch-aspeed/wdt_ast2600.h create mode 100644 arch/arm/mach-aspeed/ast2600/Kconfig create mode 100644 arch/arm/mach-aspeed/ast2600/Makefile create mode 100644 arch/arm/mach-aspeed/ast2600/board_common.c create mode 100644 arch/arm/mach-aspeed/ast2600/lowlevel_init.S create mode 100644 arch/arm/mach-aspeed/ast2600/spl.c create mode 100644 board/aspeed/evb_ast2600/Kconfig create mode 100644 board/aspeed/evb_ast2600/Makefile create mode 100644 board/aspeed/evb_ast2600/evb_ast2600.c create mode 100644 configs/evb-ast2600_defconfig create mode 100644 drivers/clk/aspeed/clk_ast2600.c create mode 100644 drivers/ram/aspeed/sdram_ast2600.c create mode 100644 drivers/reset/reset-ast2600.c create mode 100644 drivers/watchdog/ast2600_wdt.c create mode 100644 include/configs/evb_ast2600.h create mode 100644 include/dt-bindings/clock/ast2600-clock.h create mode 100644 include/dt-bindings/reset/ast2600-reset.h -- 2.17.1

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[PATCH] doc: board: freescale: advise to use newer atf and firmware
by Andrey Zhizhikin 19 Jan '21

19 Jan '21

Update branch and version information of ATF and DDR firmware files to point to latest releases provided by NXP. This is especially critical for imx8mp evk, as the ATF support for that SoC is only available in latest releases. Align all SoCs from imx8m family to use identical revisions of ATF and DDR firmware. Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin(a)leica-geosystems.com> --- doc/board/freescale/imx8mm_evk.rst | 10 +++++----- doc/board/freescale/imx8mn_evk.rst | 10 +++++----- doc/board/freescale/imx8mp_evk.rst | 16 ++++++++-------- doc/board/freescale/imx8mq_evk.rst | 12 ++++++------ 4 files changed, 24 insertions(+), 24 deletions(-) diff --git a/doc/board/freescale/imx8mm_evk.rst b/doc/board/freescale/imx8mm_evk.rst index f75190227c..a9ccdb7850 100644 --- a/doc/board/freescale/imx8mm_evk.rst +++ b/doc/board/freescale/imx8mm_evk.rst @@ -18,7 +18,7 @@ Get and Build the ARM Trusted firmware Note: builddir is U-Boot build directory (source directory for in-tree builds) Get ATF from: https://source.codeaurora.org/external/imx/imx-atf -branch: imx_4.19.35_1.0.0 +branch: imx_5.4.47_2.2.0 .. code-block:: bash @@ -30,10 +30,10 @@ Get the ddr firmware .. code-block:: bash - $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin - $ chmod +x firmware-imx-8.0.bin - $ ./firmware-imx-8.0 - $ cp firmware-imx-8.0/firmware/ddr/synopsys/lpddr4*.bin $(builddir) + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin + $ chmod +x firmware-imx-8.9.bin + $ ./firmware-imx-8.9 + $ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin $(builddir) Build U-Boot ------------ diff --git a/doc/board/freescale/imx8mn_evk.rst b/doc/board/freescale/imx8mn_evk.rst index c3e92cecee..375e0bb761 100644 --- a/doc/board/freescale/imx8mn_evk.rst +++ b/doc/board/freescale/imx8mn_evk.rst @@ -18,7 +18,7 @@ Get and Build the ARM Trusted firmware Note: srctree is U-Boot source directory Get ATF from: https://source.codeaurora.org/external/imx/imx-atf -branch: imx_4.19.35_1.1.0 +branch: imx_5.4.47_2.2.0 .. code-block:: bash @@ -30,10 +30,10 @@ Get the ddr firmware .. code-block:: bash - $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.5.bin - $ chmod +x firmware-imx-8.5.bin - $ ./firmware-imx-8.5 - $ cp firmware-imx-8.5/firmware/ddr/synopsys/ddr4*.bin $(srctree) + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin + $ chmod +x firmware-imx-8.9.bin + $ ./firmware-imx-8.9 + $ cp firmware-imx-8.9/firmware/ddr/synopsys/ddr4*.bin $(srctree) Build U-Boot ------------ diff --git a/doc/board/freescale/imx8mp_evk.rst b/doc/board/freescale/imx8mp_evk.rst index 96df6d470f..ccffcf7257 100644 --- a/doc/board/freescale/imx8mp_evk.rst +++ b/doc/board/freescale/imx8mp_evk.rst @@ -18,7 +18,7 @@ Get and Build the ARM Trusted firmware Note: $(srctree) is the U-Boot source directory Get ATF from: https://source.codeaurora.org/external/imx/imx-atf -branch: imx_5.4.3_2.0.0 +branch: imx_5.4.47_2.2.0 .. code-block:: bash @@ -30,13 +30,13 @@ Get the ddr firmware .. code-block:: bash - $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.7.bin - $ chmod +x firmware-imx-8.7.bin - $ ./firmware-imx-8.7.bin - $ cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_1d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_1d_dmem.bin - $ cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_1d_imem_201904.bin $(srctree)/lpddr4_pmu_train_1d_imem.bin - $ cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_2d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_2d_dmem.bin - $ cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_2d_imem_201904.bin $(srctree)/lpddr4_pmu_train_2d_imem.bin + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin + $ chmod +x firmware-imx-8.9.bin + $ ./firmware-imx-8.9.bin + $ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4_pmu_train_1d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_1d_dmem.bin + $ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4_pmu_train_1d_imem_201904.bin $(srctree)/lpddr4_pmu_train_1d_imem.bin + $ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4_pmu_train_2d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_2d_dmem.bin + $ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4_pmu_train_2d_imem_201904.bin $(srctree)/lpddr4_pmu_train_2d_imem.bin Build U-Boot ------------ diff --git a/doc/board/freescale/imx8mq_evk.rst b/doc/board/freescale/imx8mq_evk.rst index 0a64ecc5ba..c269fdebe3 100644 --- a/doc/board/freescale/imx8mq_evk.rst +++ b/doc/board/freescale/imx8mq_evk.rst @@ -18,7 +18,7 @@ Get and Build the ARM Trusted firmware Note: srctree is U-Boot source directory Get ATF from: https://source.codeaurora.org/external/imx/imx-atf -branch: imx_4.19.35_1.0.0 +branch: imx_5.4.47_2.2.0 .. code-block:: bash @@ -30,11 +30,11 @@ Get the ddr and hdmi firmware .. code-block:: bash - $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.9.bin - $ chmod +x firmware-imx-7.9.bin - $ ./firmware-imx-7.9.bin - $ cp firmware-imx-7.9/firmware/hdmi/cadence/signed_hdmi_imx8m.bin $(builddir) - $ cp firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(builddir) + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin + $ chmod +x firmware-imx-8.9.bin + $ ./firmware-imx-8.9.bin + $ cp firmware-imx-8.9/firmware/hdmi/cadence/signed_hdmi_imx8m.bin $(builddir) + $ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin $(builddir) Build U-Boot ------------ -- 2.17.1

5 6