January 2021 - U-Boot

[PATCH 1/1] efi_loader: provide initrddump test tool
by Heinrich Schuchardt 19 Jan '21

19 Jan '21

Provide an UEFI application to save the initial RAM disk provided by U-Boot via the Load File2 protocol. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- lib/efi_selftest/Makefile | 6 + lib/efi_selftest/initrddump.c | 378 ++++++++++++++++++++++++++++++++++ 2 files changed, 384 insertions(+) create mode 100644 lib/efi_selftest/initrddump.c diff --git a/lib/efi_selftest/Makefile b/lib/efi_selftest/Makefile index fa3dc66baa..7d6ea30102 100644 --- a/lib/efi_selftest/Makefile +++ b/lib/efi_selftest/Makefile @@ -14,6 +14,8 @@ CFLAGS_efi_selftest_miniapp_exit.o := $(CFLAGS_EFI) -Os -ffreestanding CFLAGS_REMOVE_efi_selftest_miniapp_exit.o := $(CFLAGS_NON_EFI) CFLAGS_efi_selftest_miniapp_return.o := $(CFLAGS_EFI) -Os -ffreestanding CFLAGS_REMOVE_efi_selftest_miniapp_return.o := $(CFLAGS_NON_EFI) +CFLAGS_initrddump_exit.o := $(CFLAGS_EFI) -Os -ffreestanding +CFLAGS_REMOVE_initrddump.o := $(CFLAGS_NON_EFI) obj-y += \ efi_selftest.o \ @@ -82,6 +84,10 @@ ifeq ($(CONFIG_GENERATE_ACPI_TABLE),) always += dtbdump.efi endif +ifdef CONFIG_EFI_LOAD_FILE2_INITRD +always += initrddump.efi +endif + $(obj)/efi_miniapp_file_image_exception.h: $(obj)/efi_selftest_miniapp_exception.efi $(obj)/../../tools/file2include $(obj)/efi_selftest_miniapp_exception.efi > \ $(obj)/efi_miniapp_file_image_exception.h diff --git a/lib/efi_selftest/initrddump.c b/lib/efi_selftest/initrddump.c new file mode 100644 index 0000000000..e0d578d440 --- /dev/null +++ b/lib/efi_selftest/initrddump.c @@ -0,0 +1,378 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020, Heinrich Schuchardt <xypron.glpk(a)gmx.de> + * + * initrddump.efi saves the initial RAM disk provided via the + * EFI_LOAD_FILE2_PROTOCOL. + */ + +#include <common.h> +#include <efi_api.h> +#include <efi_load_initrd.h> + +#define BUFFER_SIZE 64 +#define ESC 0x17 + +#define efi_size_in_pages(size) (((size) + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT) + +static struct efi_system_table *systable; +static struct efi_boot_services *bs; +static struct efi_simple_text_output_protocol *cerr; +static struct efi_simple_text_output_protocol *cout; +static struct efi_simple_text_input_protocol *cin; +static const efi_guid_t loaded_image_guid = EFI_LOADED_IMAGE_PROTOCOL_GUID; +static const efi_guid_t guid_simple_file_system_protocol = + EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID; +static const efi_guid_t load_file2_guid = EFI_LOAD_FILE2_PROTOCOL_GUID; +static efi_handle_t handle; + +/* + * Device path defined by Linux to identify the handle providing the + * EFI_LOAD_FILE2_PROTOCOL used for loading the initial ramdisk. + */ +static const struct efi_initrd_dp initrd_dp = { + .vendor = { + { + DEVICE_PATH_TYPE_MEDIA_DEVICE, + DEVICE_PATH_SUB_TYPE_VENDOR_PATH, + sizeof(initrd_dp.vendor), + }, + EFI_INITRD_MEDIA_GUID, + }, + .end = { + DEVICE_PATH_TYPE_END, + DEVICE_PATH_SUB_TYPE_END, + sizeof(initrd_dp.end), + } +}; + +/** + * error() - print error string + * + * @string: error text + */ +static void error(u16 *string) +{ + cout->set_attribute(cout, EFI_LIGHTRED | EFI_BACKGROUND_BLACK); + cout->output_string(cout, string); + cout->set_attribute(cout, EFI_LIGHTBLUE | EFI_BACKGROUND_BLACK); +} + +/** + * efi_input_yn() - get answer to yes/no question + * + * Return: + * y or Y + * EFI_SUCCESS + * n or N + * EFI_ACCESS_DENIED + * ESC + * EFI_ABORTED + */ +static efi_status_t efi_input_yn(void) +{ + struct efi_input_key key = {0}; + efi_uintn_t index; + efi_status_t ret; + + /* Drain the console input */ + ret = cin->reset(cin, true); + for (;;) { + ret = bs->wait_for_event(1, &cin->wait_for_key, &index); + if (ret != EFI_SUCCESS) + continue; + ret = cin->read_key_stroke(cin, &key); + if (ret != EFI_SUCCESS) + continue; + switch (key.scan_code) { + case 0x17: /* Escape */ + return EFI_ABORTED; + default: + break; + } + /* Convert to lower case */ + switch (key.unicode_char | 0x20) { + case 'y': + return EFI_SUCCESS; + case 'n': + return EFI_ACCESS_DENIED; + default: + break; + } + } +} + +/** + * efi_input() - read string from console + * + * @buffer: input buffer + * @buffer_size: buffer size + * Return: status code + */ +static efi_status_t efi_input(u16 *buffer, efi_uintn_t buffer_size) +{ + struct efi_input_key key = {0}; + efi_uintn_t index; + efi_uintn_t pos = 0; + u16 outbuf[2] = L" "; + efi_status_t ret; + + /* Drain the console input */ + ret = cin->reset(cin, true); + *buffer = 0; + for (;;) { + ret = bs->wait_for_event(1, &cin->wait_for_key, &index); + if (ret != EFI_SUCCESS) + continue; + ret = cin->read_key_stroke(cin, &key); + if (ret != EFI_SUCCESS) + continue; + switch (key.scan_code) { + case 0x17: /* Escape */ + cout->output_string(cout, L"\nAborted\n"); + return EFI_ABORTED; + default: + break; + } + switch (key.unicode_char) { + case 0x08: /* Backspace */ + if (pos) { + buffer[pos--] = 0; + cout->output_string(cout, L"\b \b"); + } + break; + case 0x0a: /* Linefeed */ + case 0x0d: /* Carriage return */ + cout->output_string(cout, L"\n"); + return EFI_SUCCESS; + default: + break; + } + /* Ignore surrogate codes */ + if (key.unicode_char >= 0xD800 && key.unicode_char <= 0xDBFF) + continue; + if (key.unicode_char >= 0x20 && + pos < buffer_size - 1) { + *outbuf = key.unicode_char; + buffer[pos++] = key.unicode_char; + buffer[pos] = 0; + cout->output_string(cout, outbuf); + } + } +} + +/** + * skip_whitespace() - skip over leading whitespace + * + * @pos: UTF-16 string + * Return: pointer to first non-whitespace + */ +static u16 *skip_whitespace(u16 *pos) +{ + for (; *pos && *pos <= 0x20; ++pos) + ; + return pos; +} + +/** + * starts_with() - check if @string starts with @keyword + * + * @string: string to search for keyword + * @keyword: keyword to be searched + * Return: true fi @string starts with the keyword + */ +static bool starts_with(u16 *string, u16 *keyword) +{ + for (; *keyword; ++string, ++keyword) { + if (*string != *keyword) + return false; + } + return true; +} + +/** + * do_help() - print help + */ +static void do_help(void) +{ + error(L"save <initrd> - save initial RAM disk to file\n"); + error(L"exit - exit the shell\n"); +} + +/** + * get_initrd() - read initial RAM disk via EFI_LOAD_FILE2_PROTOCOL + * + * @initrd: on return buffer with initial RAM disk + * @initrd_size: size of initial RAM disk + * Return: status code + */ +static efi_status_t get_initrd(void **initrd, efi_uintn_t *initrd_size) +{ + struct efi_device_path *dp = (struct efi_device_path *)&initrd_dp; + struct efi_load_file_protocol *load_file2_prot; + u64 buffer; + efi_handle_t handle; + efi_status_t ret; + + *initrd = NULL; + *initrd_size = 0; + ret = bs->locate_device_path(&load_file2_guid, &dp, &handle); + if (ret != EFI_SUCCESS) { + error(L"Load File2 protocol not found\n"); + return ret; + } + ret = bs->handle_protocol(handle, &load_file2_guid, + (void **)&load_file2_prot); + ret = load_file2_prot->load_file(load_file2_prot, dp, false, + initrd_size, NULL); + if (ret != EFI_BUFFER_TOO_SMALL) { + error(L"Load File2 protocol does not provide file length\n"); + return EFI_LOAD_ERROR; + } + ret = bs->allocate_pages(EFI_ALLOCATE_ANY_PAGES, EFI_LOADER_DATA, + efi_size_in_pages(*initrd_size), &buffer); + if (ret != EFI_SUCCESS) { + error(L"Out of memory\n"); + return ret; + } + *initrd = (void *)buffer; + ret = load_file2_prot->load_file(load_file2_prot, dp, false, + initrd_size, *initrd); + if (ret != EFI_SUCCESS) { + error(L"Load File2 protocol failed to provide file\n"); + bs->free_pages(buffer, efi_size_in_pages(*initrd_size)); + return EFI_LOAD_ERROR; + } + return ret; +} + +/** + * do_save() - save initial RAM disk + * + * @filename: file name + * Return: status code + */ +static efi_status_t do_save(u16 *filename) +{ + struct efi_loaded_image *loaded_image; + struct efi_simple_file_system_protocol *file_system; + struct efi_file_handle *root, *file; + void *initrd; + efi_uintn_t initrd_size; + efi_uintn_t ret; + + ret = get_initrd(&initrd, &initrd_size); + if (ret != EFI_SUCCESS) + return ret; + + filename = skip_whitespace(filename); + + ret = bs->open_protocol(handle, &loaded_image_guid, + (void **)&loaded_image, NULL, NULL, + EFI_OPEN_PROTOCOL_GET_PROTOCOL); + if (ret != EFI_SUCCESS) { + error(L"Loaded image protocol not found\n"); + goto out; + } + + /* Open the simple file system protocol */ + ret = bs->open_protocol(loaded_image->device_handle, + &guid_simple_file_system_protocol, + (void **)&file_system, NULL, NULL, + EFI_OPEN_PROTOCOL_GET_PROTOCOL); + if (ret != EFI_SUCCESS) { + error(L"Failed to open simple file system protocol\n"); + goto out; + } + + /* Open volume */ + ret = file_system->open_volume(file_system, &root); + if (ret != EFI_SUCCESS) { + error(L"Failed to open volume\n"); + goto out; + } + /* Check if file already exists */ + ret = root->open(root, &file, filename, EFI_FILE_MODE_READ, 0); + if (ret == EFI_SUCCESS) { + file->close(file); + cout->output_string(cout, L"Overwrite existing file (y/n)? "); + ret = efi_input_yn(); + cout->output_string(cout, L"\n"); + if (ret != EFI_SUCCESS) { + root->close(root); + error(L"Aborted by user\n"); + goto out; + } + } + + /* Create file */ + ret = root->open(root, &file, filename, + EFI_FILE_MODE_READ | EFI_FILE_MODE_WRITE | + EFI_FILE_MODE_CREATE, EFI_FILE_ARCHIVE); + if (ret == EFI_SUCCESS) { + /* Write file */ + ret = file->write(file, &initrd_size, initrd); + if (ret != EFI_SUCCESS) { + error(L"Failed to write file\n"); + } else { + cout->output_string(cout, filename); + cout->output_string(cout, L" written\n"); + } + file->close(file); + } else { + error(L"Failed to open file\n"); + } + root->close(root); + +out: + if (initrd) + bs->free_pages((uintptr_t)initrd, + efi_size_in_pages(initrd_size)); + return ret; +} + +/** + * efi_main() - entry point of the EFI application. + * + * @handle: handle of the loaded image + * @systab: system table + * @return: status code + */ +efi_status_t EFIAPI efi_main(efi_handle_t image_handle, + struct efi_system_table *systab) +{ + handle = image_handle; + systable = systab; + cerr = systable->std_err; + cout = systable->con_out; + cin = systable->con_in; + bs = systable->boottime; + + cout->set_attribute(cout, EFI_LIGHTBLUE | EFI_BACKGROUND_BLACK); + cout->clear_screen(cout); + cout->set_attribute(cout, EFI_WHITE | EFI_BACKGROUND_BLACK); + cout->output_string(cout, L"INITRD Dump\n========\n\n"); + cout->set_attribute(cout, EFI_LIGHTBLUE | EFI_BACKGROUND_BLACK); + + for (;;) { + u16 command[BUFFER_SIZE]; + u16 *pos; + efi_uintn_t ret; + + cout->output_string(cout, L"=> "); + ret = efi_input(command, sizeof(command)); + if (ret == EFI_ABORTED) + break; + pos = skip_whitespace(command); + if (starts_with(pos, L"exit")) + break; + else if (starts_with(pos, L"save ")) + do_save(pos + 5); + else + do_help(); + } + + cout->set_attribute(cout, EFI_LIGHTGRAY | EFI_BACKGROUND_BLACK); + cout->clear_screen(cout); + return EFI_SUCCESS; +} -- 2.29.2

3 4

[PATCH v2 0/6] add support for sama7g5 ethernet interfaces
by Claudiu Beznea 19 Jan '21

19 Jan '21

Hi, This series add support for SAMA7G5 ethernet interfaces: one gigabit interface and one 10/100Mbps interface. Thank you, Claudiu Beznea Changes in v2: - fix compilation error on patch 6/6 for wb50n_defconfig Claudiu Beznea (6): net: macb: use dummy descriptor for RBQP net: macb: add user io config data structure net: macb: check clk_set_rate return value to be negative net: macb: add support for sama7g5 gmac net: macb: add support for sama7g5 emac net: macb: take into account all RGMII interface types drivers/net/macb.c | 101 +++++++++++++++++++++++++++++++++++++++++++++-------- drivers/net/macb.h | 2 ++ 2 files changed, 89 insertions(+), 14 deletions(-) -- 2.7.4

2 7

[PATCH 4/4] board: keymile: add support for seli8 design based on nxp ls102x soc
by Aleksandar Gerasimovski 19 Jan '21

19 Jan '21

The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung(a)hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni(a)hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski(a)hitachi-powergrids.com> --- arch/arm/Kconfig | 19 ++ arch/arm/dts/Makefile | 2 + arch/arm/dts/ls1021a-pg-wcom-seli8.dts | 111 +++++++++ board/keymile/Kconfig | 23 +- board/keymile/common/ivm.c | 19 +- board/keymile/pg-wcom-ls102xa/Kconfig | 19 ++ board/keymile/pg-wcom-ls102xa/MAINTAINERS | 10 + board/keymile/pg-wcom-ls102xa/Makefile | 11 + board/keymile/pg-wcom-ls102xa/ddr.c | 90 +++++++ board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c | 160 ++++++++++++ configs/pg_wcom_seli8_defconfig | 63 +++++ include/configs/km/pg-wcom-ls102xa.h | 309 ++++++++++++++++++++++++ include/configs/pg-wcom-seli8.h | 45 ++++ 13 files changed, 870 insertions(+), 11 deletions(-) create mode 100644 arch/arm/dts/ls1021a-pg-wcom-seli8.dts create mode 100644 board/keymile/pg-wcom-ls102xa/Kconfig create mode 100644 board/keymile/pg-wcom-ls102xa/MAINTAINERS create mode 100644 board/keymile/pg-wcom-ls102xa/Makefile create mode 100644 board/keymile/pg-wcom-ls102xa/ddr.c create mode 100644 board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c create mode 100644 configs/pg_wcom_seli8_defconfig create mode 100644 include/configs/km/pg-wcom-ls102xa.h create mode 100644 include/configs/pg-wcom-seli8.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fbe9087..13fdf3c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1515,6 +1515,24 @@ config TARGET_LS1021ATWR select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI imply SCSI +config TARGET_PG_WCOM_SELI8 + bool "Support Hitachi-Powergrids SELI8 service unit card" + select ARCH_LS1021A + select ARCH_SUPPORT_PSCI + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + select CPU_V7A + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT + select SYS_FSL_DDR + select FSL_DDR_INTERACTIVE + select VENDOR_KM + imply SCSI + help + Support for Hitachi-Powergrids SELI8 service unit card. + SELI8 is a QorIQ LS1021a based service unit card used + in XMC20 and FOX615 product families. + config TARGET_LS1021ATSN bool "Support ls1021atsn" select ARCH_LS1021A @@ -2034,6 +2052,7 @@ source "board/variscite/dart_6ul/Kconfig" source "board/vscom/baltos/Kconfig" source "board/phytium/durian/Kconfig" source "board/xen/xenguest_arm64/Kconfig" +source "board/keymile/Kconfig" source "arch/arm/Kconfig.debug" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index fd47e40..ec93f93 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -393,6 +393,8 @@ dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \ ls1021a-qds-lpuart.dtb \ ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \ ls1021a-iot-duart.dtb ls1021a-tsn.dtb +dtb-$(CONFIG_TARGET_PG_WCOM_SELI8) += ls1021a-pg-wcom-seli8.dtb + dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ fsl-ls2080a-qds-42-x.dtb \ fsl-ls2080a-rdb.dtb \ diff --git a/arch/arm/dts/ls1021a-pg-wcom-seli8.dts b/arch/arm/dts/ls1021a-pg-wcom-seli8.dts new file mode 100644 index 0000000..e335188 --- /dev/null +++ b/arch/arm/dts/ls1021a-pg-wcom-seli8.dts @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2013-2015 Freescale Semiconductor, Inc. + * Copyright 2020 Hitachi Power Grids. All rights reserved. + */ + +/dts-v1/; +#include "ls1021a.dtsi" + +/ { + model = "Hitachi-Powergrids SELI8 Service Unit for XMC and FOX"; + + chosen { + stdout-path = &uart0; + }; +}; + +&enet0 { + status = "okay"; + tbi-handle = <&tbi0>; + phy-connection-type = "sgmii"; + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&enet1 { + status = "okay"; + tbi-handle = <&tbi1>; + phy-connection-type = "sgmii"; + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&enet2 { + phy-handle = <&debug_phy>; + phy-connection-type = "rgmii-id"; + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&ifc { + #address-cells = <2>; + #size-cells = <1>; + /* NOR Flash on board */ + ranges = <0x0 0x0 0x60000000 0x04000000>; + status = "okay"; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x4000000>; + bank-width = <2>; + device-width = <1>; + + partition@0 { + label = "rcw"; + reg = <0x0 0x20000>; + read-only; + }; + partition@20000 { + label = "qe"; + reg = <0x20000 0x20000>; + }; + partition@40000 { + label = "envred"; + reg = <0x40000 0x20000>; + }; + partition@60000 { + label = "env"; + reg = <0x60000 0x20000>; + }; + partition@100000 { + label = "u-boot"; + reg = <0x100000 0x100000>; + }; + partition@200000 { + label = "ubi0"; + reg = <0x200000 0x3E00000>; + }; + }; +}; + +&mdio0 { + debug_phy: ethernet-phy@11 { + reg = <0x11>; + }; + + tbi0: tbi-phy@0xb { + reg = <0xb>; + device_type = "tbi-phy"; + }; +}; + +&mdio1 { + tbi1: tbi-phy@0xd { + reg = <0xd>; + device_type = "tbi-phy"; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig index e590690..965a537 100644 --- a/board/keymile/Kconfig +++ b/board/keymile/Kconfig @@ -20,8 +20,8 @@ config KM_PNVRAM config KM_PHRAM hex "Physical RAM" - default 0x17F000 if ARM - default 0x100000 if PPC + default 0x17F000 if ARM && !ARCH_LS1021A + default 0x100000 if PPC || ARCH_LS1021A depends on !ARCH_SOCFPGA help Start address of the physical RAM, which is the mounted /var folder. @@ -30,13 +30,14 @@ config KM_RESERVED_PRAM hex "Reserved RAM" default 0x801000 if ARCH_KIRKWOOD default 0x0 if MPC83xx - default 0x1000 if MPC85xx + default 0x1000 if MPC85xx || ARCH_LS1021A depends on !ARCH_SOCFPGA help Reserved physical RAM area at the end of memory for special purposes. config KM_CRAMFS_ADDR hex "CRAMFS Address" + default 0x83000000 if ARCH_LS1021A default 0x3000000 depends on !ARCH_SOCFPGA help @@ -44,16 +45,25 @@ config KM_CRAMFS_ADDR config KM_KERNEL_ADDR hex "Kernel Load Address" + default 0x82000000 if ARCH_LS1021A default 0x2000000 help Address where to load Linux kernel in RAM. config KM_FDT_ADDR hex "FDT Load Address" + default 0x82FC0000 if ARCH_LS1021A default 0x2FC0000 help Address where to load flattened device tree in RAM. +config SYS_PAX_BASE + hex "PAX IFC Base Address" + default 0x78000000 + depends on ARCH_LS1021A + help + IFC Base Address for PAXx FPGA. + config KM_CONSOLE_TTY string "KM Console" default "ttyS0" @@ -69,9 +79,9 @@ config KM_DEF_NETDEV config KM_COMMON_ETH_INIT bool "Common Ethernet Initialization" default y if ARCH_KIRKWOOD || MPC83xx - default n if MPC85xx || ARCH_SOCFPGA + default n if MPC85xx || ARCH_SOCFPGA || ARCH_LS1021A help - Use the Ethernet initialization implemented in common code, which + Use the Ethernet initialization implemented in common code that detects if a Piggy board is present. config PIGGY_MAC_ADDRESS_OFFSET @@ -90,7 +100,7 @@ config KM_MVEXTSW_ADDR config KM_IVM_BUS int "IVM I2C Bus" default 0 if ARCH_SOCFPGA - default 1 if ARCH_KIRKWOOD || MPC85xx + default 1 if ARCH_KIRKWOOD || MPC85xx || ARCH_LS1021A default 2 if MPC83xx help Identifier number of I2C bus, where the inventory EEPROM is connected to. @@ -116,6 +126,7 @@ config SYS_IVM_EEPROM_PAGE_LEN source "board/keymile/km83xx/Kconfig" source "board/keymile/kmp204x/Kconfig" source "board/keymile/km_arm/Kconfig" +source "board/keymile/pg-wcom-ls102xa/Kconfig" endmenu diff --git a/board/keymile/common/ivm.c b/board/keymile/common/ivm.c index e989bf6..48817cb 100644 --- a/board/keymile/common/ivm.c +++ b/board/keymile/common/ivm.c @@ -306,11 +306,7 @@ static int ivm_populate_env(unsigned char *buf, int len, int mac_address_offset) return 0; page2 = &buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2]; - if (!IS_ENABLED(CONFIG_KMTEGR1)) { - /* if an offset is defined, add it */ - process_mac(valbuf, page2, mac_address_offset, true); - env_set((char *)"ethaddr", (char *)valbuf); - } else { + if (IS_ENABLED(CONFIG_KMTEGR1)) { /* KMTEGR1 has a special setup. eth0 has no connection to the * outside and gets an locally administred MAC address, eth1 is * the debug interface and gets the official MAC address from @@ -320,6 +316,19 @@ static int ivm_populate_env(unsigned char *buf, int len, int mac_address_offset) env_set((char *)"ethaddr", (char *)valbuf); process_mac(valbuf, page2, mac_address_offset, true); env_set((char *)"eth1addr", (char *)valbuf); + } else if (IS_ENABLED(CONFIG_ARCH_LS1021A)) { + /* LS102xA has 1xRGMII for debug connection and + * 2xSGMII for back-plane mgmt connection + */ + process_mac(valbuf, page2, 1, true); + env_set((char *)"ethaddr", (char *)valbuf); + process_mac(valbuf, page2, 2, true); + env_set((char *)"eth1addr", (char *)valbuf); + process_mac(valbuf, page2, mac_address_offset, true); + env_set((char *)"eth2addr", (char *)valbuf); + } else { + process_mac(valbuf, page2, mac_address_offset, true); + env_set((char *)"ethaddr", (char *)valbuf); } return 0; diff --git a/board/keymile/pg-wcom-ls102xa/Kconfig b/board/keymile/pg-wcom-ls102xa/Kconfig new file mode 100644 index 0000000..15c009d --- /dev/null +++ b/board/keymile/pg-wcom-ls102xa/Kconfig @@ -0,0 +1,19 @@ +if TARGET_PG_WCOM_SELI8 + +config SYS_BOARD + default "pg-wcom-ls102xa" + +config SYS_VENDOR + default "keymile" + +config SYS_SOC + default "ls102xa" + +config SYS_CONFIG_NAME + default "pg-wcom-seli8" + +config BOARD_SPECIFIC_OPTIONS + def_bool y + imply FS_CRAMFS + +endif diff --git a/board/keymile/pg-wcom-ls102xa/MAINTAINERS b/board/keymile/pg-wcom-ls102xa/MAINTAINERS new file mode 100644 index 0000000..e1bc90a --- /dev/null +++ b/board/keymile/pg-wcom-ls102xa/MAINTAINERS @@ -0,0 +1,10 @@ +Hitachi Power Grids LS102XA BOARD +M: Aleksandar Gerasimovski <aleksandar.gerasimovski(a)hitachi-powergrids.com> +M: Rainer Boschung <rainer.boschung(a)hitachi-powergrids.com> +M: Matteo Ghidoni <matteo.ghidoni(a)hitachi-powergrids.com> +S: Maintained +F: board/keymile/pg-wcom-ls102xa/ +F: include/configs/km/pg-wcom-ls102xa.h +F: include/configs/pg-wcom-seli8.h +F: configs/pg_wcom_seli8_defconfig +F: arch/arm/dts/ls1021a-pg-wcom-seli8.dts diff --git a/board/keymile/pg-wcom-ls102xa/Makefile b/board/keymile/pg-wcom-ls102xa/Makefile new file mode 100644 index 0000000..229b0c2 --- /dev/null +++ b/board/keymile/pg-wcom-ls102xa/Makefile @@ -0,0 +1,11 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2021 Hitachi Power Grids. All rights reserved. +# + +obj-y += pg-wcom-ls102xa.o ddr.o +obj-y += ../common/common.o ../common/ivm.o ../common/qrio.o +obj-$(CONFIG_LAYERSCAPE_NS_ACCESS) += ../../freescale/common/ns_access.o +obj-$(CONFIG_LS102XA_STREAM_ID) += ../../freescale/common/ls102xa_stream_id.o +obj-$(CONFIG_ID_EEPROM) += ../../freescale/common/sys_eeprom.o diff --git a/board/keymile/pg-wcom-ls102xa/ddr.c b/board/keymile/pg-wcom-ls102xa/ddr.c new file mode 100644 index 0000000..6023573 --- /dev/null +++ b/board/keymile/pg-wcom-ls102xa/ddr.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 Hitachi Power Grids. All rights reserved. + */ + +#include <common.h> +#include <fsl_ddr_sdram.h> +#include <fsl_ddr_dimm_params.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/ls102xa_soc.h> + +DECLARE_GLOBAL_DATA_PTR; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + if (ctrl_num > 1) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + + // 1/2 DRAM cycle (should be increased in case of ADDR/CMD heavily loaded than the clock) + popts->clk_adjust = 0x4; + popts->write_data_delay = 0x4; + // wr leveling start value for lane 0 + popts->wrlvl_start = 0x5; + // wr leveling start values for lanes 1-3 (lane 4 not there) + popts->wrlvl_ctl_2 = 0x05050500; + // 32-bit DRAM, no need to set start values for lanes we do not have (5-8) + popts->wrlvl_ctl_3 = 0x0; + popts->cpo_override = 0x1f; + + /* force DDR bus width to 32 bits */ + popts->data_bus_width = 1; + popts->otf_burst_chop_en = 0; + popts->burst_length = DDR_BL8; + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 1; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + popts->cswl_override = DDR_CSWL_CS0; + + /* optimize cpo for erratum A-009942 */ + popts->cpo_sample = 0x58; + + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +} + +int fsl_initdram(void) +{ + phys_size_t dram_size; + + puts("Initializing DDR....using SPD\n"); + dram_size = fsl_ddr_sdram(); + + erratum_a008850_post(); + + gd->ram_size = dram_size; + + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = gd->ram_size; + + return 0; +} diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c new file mode 100644 index 0000000..6b0e963 --- /dev/null +++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 Hitachi Power Grids. All rights reserved. + */ + +#include <common.h> +#include <i2c.h> +#include <asm/io.h> +#include <asm/arch/immap_ls102xa.h> +#include <asm/arch/clock.h> +#include <asm/arch/fsl_serdes.h> +#include <asm/arch/ls102xa_devdis.h> +#include <asm/arch/ls102xa_soc.h> +#include <hwconfig.h> +#include <mmc.h> +#include <fsl_csu.h> +#include <fsl_esdhc.h> +#include <fsl_ifc.h> +#include <fsl_immap.h> +#include <netdev.h> +#include <fsl_mdio.h> +#include <tsec.h> +#include <fsl_sec.h> +#include <fsl_devdis.h> +#include <fsl_ddr.h> +#include <spl.h> +#include <fdt_support.h> +#include <fsl_qe.h> +#include <fsl_validate.h> + +#include "../common/common.h" +#include "../common/qrio.h" + +DECLARE_GLOBAL_DATA_PTR; + +static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; + +int checkboard(void) +{ + show_qrio(); + + return 0; +} + +int dram_init(void) +{ + return fsl_initdram(); +} + +int board_early_init_f(void) +{ + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; + + /* Disable unused MCK1 */ + setbits_be32(&gur->ddrclkdr, 2); + + /* IFC Global Configuration */ + setbits_be32(&ifc.gregs->ifc_gcr, 12 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); + setbits_be32(&ifc.gregs->ifc_ccr, IFC_CCR_CLK_DIV(3) | + IFC_CCR_INV_CLK_EN); + + /* clear BD & FR bits for BE BD's and frame data */ + clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); + out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); + + init_early_memctl_regs(); + + /* QRIO Configuration */ + qrio_uprstreq(UPREQ_CORE_RST); + + if (IS_ENABLED(CONFIG_TARGET_PG_WCOM_SELI8)) { + qrio_prstcfg(KM_LIU_RST, PRSTCFG_POWUP_UNIT_RST); + qrio_wdmask(KM_LIU_RST, true); + + qrio_prstcfg(KM_PAXK_RST, PRSTCFG_POWUP_UNIT_RST); + qrio_wdmask(KM_PAXK_RST, true); + + qrio_prstcfg(KM_DBG_ETH_RST, PRSTCFG_POWUP_UNIT_CORE_RST); + qrio_prst(KM_DBG_ETH_RST, false, false); + } + + i2c_deblock_gpio_cfg(); + + arch_soc_init(); + + return 0; +} + +int board_init(void) +{ + if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A010315)) + erratum_a010315(); + + fsl_serdes_init(); + + ls102xa_smmu_stream_id_init(); + + u_qe_init(); + + return 0; +} + +int board_late_init(void) +{ + return 0; +} + +int misc_init_r(void) +{ + if (IS_ENABLED(CONFIG_FSL_DEVICE_DISABLE)) + device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); + + ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN, + CONFIG_PIGGY_MAC_ADDRESS_OFFSET); + + return 0; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + ft_cpu_setup(blob, bd); + + if (IS_ENABLED(CONFIG_PCI)) + ft_pci_setup(blob, bd); + + return 0; +} + +u8 flash_read8(void *addr) +{ + return __raw_readb(addr + 1); +} + +void flash_write16(u16 val, void *addr) +{ + u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); + + __raw_writew(shftval, addr); +} + +u16 flash_read16(void *addr) +{ + u16 val = __raw_readw(addr); + + return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); +} + +int hush_init_var(void) +{ + ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); + return 0; +} + +int last_stage_init(void) +{ + set_km_env(); + return 0; +} diff --git a/configs/pg_wcom_seli8_defconfig b/configs/pg_wcom_seli8_defconfig new file mode 100644 index 0000000..2d58fa0 --- /dev/null +++ b/configs/pg_wcom_seli8_defconfig @@ -0,0 +1,63 @@ +CONFIG_ARM=y +CONFIG_TARGET_PG_WCOM_SELI8=y +CONFIG_SYS_TEXT_BASE=0x60100000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_KM_DEF_NETDEV="eth2" +CONFIG_KM_COMMON_ETH_INIT=y +CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x9fffffff +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_BOOTCOUNT_BOOTLIMIT=3 +CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020 +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-pg-wcom-seli8" +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0" +CONFIG_SILENT_CONSOLE=y +CONFIG_MISC_INIT_R=y +CONFIG_LAST_STAGE_INIT=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_CRAMFS=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nor0=60000000.nor,nand0=68000000.flash" +CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:128k(rcw),128k(qe),128k(envred),128k(env),512k(res),1m(u-boot),-(ubi0);68000000.flash:-(ubi1)" +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_ENV_ADDR=0x60060000 +CONFIG_DM=y +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_FSL_DDR3=y +# CONFIG_MMC is not set +CONFIG_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_MTD_RAW_NAND=y +CONFIG_PHY_MARVELL=y +CONFIG_PHY_FIXED=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_PHY_GIGE=y +CONFIG_MII=y +CONFIG_TSEC_ENET=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h new file mode 100644 index 0000000..55fb909 --- /dev/null +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -0,0 +1,309 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Hitachi Power Grids. All rights reserved. + */ + +#ifndef __CONFIG_PG_WCOM_LS102XA_H +#define __CONFIG_PG_WCOM_LS102XA_H + +#define CONFIG_SYS_FSL_CLK + +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* include common defines/options for all Keymile boards */ +#include "keymile-common.h" + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) + +#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE + +#define CONFIG_SYS_CLK_FREQ 66666666 +/* + * Take into account default implementation where DDR_FDBK_MULTI is consider as + * configured for DDR_PLL = 2*MEM_PLL_RAT. + * In our case DDR_FDBK_MULTI is 2, means DDR_PLL = MEM_PLL_RAT. + */ +#define CONFIG_DDR_CLK_FREQ (100000000 >> 1) + +#define PHYS_SDRAM 0x80000000 +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 + +#define CONFIG_DDR_SPD + +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS 0x54 + +/* + * IFC Definitions + */ +/* NOR Flash Definitions */ +#define CONFIG_FSL_IFC +#define CONFIG_SYS_FLASH_BASE 0x60000000 +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE + +#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_TE | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024) + +#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | \ + CSOR_NOR_ADM_SHIFT(0x4) | \ + CSOR_NOR_NOR_MODE_AYSNC_NOR | \ + CSOR_NOR_TRHZ_20 | \ + CSOR_NOR_BCTLD) +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ + FTIM0_NOR_TEADC(0x7) | \ + FTIM0_NOR_TAVDS(0x0) | \ + FTIM0_NOR_TEAHC(0x1)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ + FTIM1_NOR_TRAD_NOR(0x21) | \ + FTIM1_NOR_TSEQRAD_NOR(0x21)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \ + FTIM2_NOR_TCH(0x1) | \ + FTIM2_NOR_TWPH(0x6) | \ + FTIM2_NOR_TWP(0xb)) +#define CONFIG_SYS_NOR_FTIM3 0 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } + +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_SYS_WRITE_SWAPPED_DATA + +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 + +/* NAND Flash Definitions */ +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_BASE 0x68000000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE + +#define CONFIG_SYS_NAND_CSPR_EXT (0x0) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \ + CSPR_PORT_SIZE_8 | \ + CSPR_TE | \ + CSPR_MSEL_NAND | \ + CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \ + | CSOR_NAND_ECC_DEC_EN \ + | CSOR_NAND_ECC_MODE_4 \ + | CSOR_NAND_RAL_3 \ + | CSOR_NAND_PGS_2K \ + | CSOR_NAND_SPRZ_64 \ + | CSOR_NAND_PB(64) \ + | CSOR_NAND_TRHZ_40 \ + | CSOR_NAND_BCTLD) + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \ + FTIM0_NAND_TWP(0x8) | \ + FTIM0_NAND_TWCHT(0x3) | \ + FTIM0_NAND_TWH(0x5)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \ + FTIM1_NAND_TWBE(0x1e) | \ + FTIM1_NAND_TRR(0x6) | \ + FTIM1_NAND_TRP(0x8)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \ + FTIM2_NAND_TREH(0x5) | \ + FTIM2_NAND_TWHRE(0x3c)) +#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e)) + +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +/* QRIO FPGA Definitions */ +#define CONFIG_SYS_QRIO_BASE 0x70000000 +#define CONFIG_SYS_QRIO_BASE_PHYS CONFIG_SYS_QRIO_BASE + +#define CONFIG_SYS_CSPR2_EXT (0x00) +#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \ + CSPR_PORT_SIZE_8 | \ + CSPR_TE | \ + CSPR_MSEL_GPCM | \ + CSPR_V) +#define CONFIG_SYS_AMASK2 IFC_AMASK(64 * 1024) +#define CONFIG_SYS_CSOR2 (CSOR_GPCM_ADM_SHIFT(0x4) | \ + CSOR_GPCM_TRHZ_20 | \ + CSOR_GPCM_BCTLD) +#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \ + FTIM0_GPCM_TEADC(0x8) | \ + FTIM0_GPCM_TEAHC(0x2)) +#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ + FTIM1_GPCM_TRAD(0x6)) +#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x1) | \ + FTIM2_GPCM_TCH(0x1) | \ + FTIM2_GPCM_TWP(0x7)) +#define CONFIG_SYS_CS2_FTIM3 0x04000000 + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + +/* + * I2C + */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ + +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_NUM_I2C_BUSES 3 +#define I2C_MUX_PCA_ADDR 0x70 +#define I2C_MUX_CH_DEFAULT 0x0 +#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \ + {1, {I2C_NULL_HOP} }, \ + } + +#ifndef __ASSEMBLY__ +void set_sda(int state); +void set_scl(int state); +int get_sda(void); +int get_scl(void); +#endif + +/* + * eTSEC + */ +#ifdef CONFIG_TSEC_ENET +#define CONFIG_ETHPRIME "ethernet@2d90000" +#endif + +#define CONFIG_CMDLINE_TAG + +#define CONFIG_LAYERSCAPE_NS_ACCESS +#define CONFIG_SMP_PEN_ADDR 0x01ee0200 +#define COUNTER_FREQUENCY 12500000 + +#define CONFIG_HWCONFIG +#define HWCONFIG_BUFFER_SIZE 256 +#define CONFIG_FSL_DEVICE_DISABLE + +/* + * Miscellaneous configurable options + */ + +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +#define CONFIG_LS102XA_STREAM_ID + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_MONITOR_LEN 0x100000 /* 1Mbyte */ +#define CONFIG_SYS_QE_FW_ADDR 0x60020000 + +#define CONFIG_SYS_BOOTCOUNT_BE + +/* + * Environment + */ + +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) + +#define CONFIG_ENV_TOTAL_SIZE 0x40000 +#define ENV_DEL_ADDR 0x60040000 /* direct for newenv */ + +#define CONFIG_ENV_OVERWRITE +#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ +#define CONFIG_KM_DEF_ENV +#endif + +#ifndef CONFIG_KM_DEF_BOOT_ARGS_CPU +#define CONFIG_KM_DEF_BOOT_ARGS_CPU "" +#endif + +#define CONFIG_KM_DEF_ENV_CPU \ + "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ + "cramfsloadfdt=" \ + "cramfsload ${fdt_addr_r} " \ + "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ + "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \ + "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize} && " \ + "erase " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize} && " \ + "cp.b ${load_addr_r} " \ + __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \ + "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize}\0" \ + "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \ + " +${filesize} && " \ + "erase " __stringify(CONFIG_SYS_FLASH_BASE) \ + " +${filesize} && " \ + "cp.b ${load_addr_r} " \ + __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && " \ + "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +" __stringify(CONFIG_SYS_MONITOR_LEN)"\0" \ + "set_fdthigh=true\0" \ + "checkfdt=true\0" \ + "" + +#define CONFIG_KM_NEW_ENV \ + "newenv=protect off " __stringify(ENV_DEL_ADDR) \ + " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \ + "erase " __stringify(ENV_DEL_ADDR) \ + " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \ + "protect on " __stringify(ENV_DEL_ADDR) \ + " +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_NEW_ENV \ + CONFIG_KM_DEF_ENV \ + "EEprom_ivm=pca9547:70:9\0" \ + "" + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Increase map for Linux */ + +#endif diff --git a/include/configs/pg-wcom-seli8.h b/include/configs/pg-wcom-seli8.h new file mode 100644 index 0000000..9a7669c --- /dev/null +++ b/include/configs/pg-wcom-seli8.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Hitachi Power Grids. All rights reserved. + */ + +#ifndef __CONFIG_PG_WCOM_SELI8_H +#define __CONFIG_PG_WCOM_SELI8_H + +#define CONFIG_HOSTNAME "SELI8" + +#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" +#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" + +/* PAXK FPGA Definitions */ +#define CONFIG_SYS_CSPR3_EXT (0x00) +#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_PAX_BASE) | \ + CSPR_PORT_SIZE_8 | \ + CSPR_MSEL_GPCM | \ + CSPR_V) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) +#define CONFIG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \ + CSOR_GPCM_TRHZ_40) +#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \ + FTIM0_GPCM_TEADC(0x7) | \ + FTIM0_GPCM_TEAHC(0x2)) +#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ + FTIM1_GPCM_TRAD(0x12)) +#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \ + FTIM2_GPCM_TCH(0x1) | \ + FTIM2_GPCM_TWP(0x12)) +#define CONFIG_SYS_CS3_FTIM3 0x04000000 + +/* PRST */ +#define KM_LIU_RST 0 +#define KM_PAXK_RST 1 +#define KM_DBG_ETH_RST 15 + +/* QRIO GPIOs used for deblocking */ +#define KM_I2C_DEBLOCK_PORT QRIO_GPIO_A +#define KM_I2C_DEBLOCK_SCL 20 +#define KM_I2C_DEBLOCK_SDA 21 + +#include "km/pg-wcom-ls102xa.h" + +#endif /* __CONFIG_PG_WCOM_SELI8_H */ -- 1.8.3.1

2 1

[PATCH 3/4] board: keymile: common: fix pnvramaddr and varaddr address calculation
by Aleksandar Gerasimovski 19 Jan '21

19 Jan '21

Take into account SDRAM_BASE address when calculating pnvramaddr and varaddr offsets. Up to now Keymile designs had SDRAM_BASE equal to zero and the offsets where calculated correctly, this fix is for the upcoming designs that have SDRAM_BASE different then zero. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski(a)hitachi-powergrids.com> --- board/keymile/common/common.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index df507e2..e3e9c4a 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -49,8 +49,8 @@ int set_km_env(void) char *p; unsigned long rootfssize = 0; - pnvramaddr = gd->ram_size - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM - - CONFIG_KM_PNVRAM; + pnvramaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size - + CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM - CONFIG_KM_PNVRAM; sprintf((char *)buf, "0x%x", pnvramaddr); env_set("pnvramaddr", (char *)buf); @@ -63,7 +63,8 @@ int set_km_env(void) sprintf((char *)buf, "0x%x", pram); env_set("pram", (char *)buf); - varaddr = gd->ram_size - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM; + varaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size - + CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM; sprintf((char *)buf, "0x%x", varaddr); env_set("varaddr", (char *)buf); -- 1.8.3.1

2 1

[v2 00/33] gpio: layerscape: fix gpio bug and enable gpio
by Biwen Li 19 Jan '21

19 Jan '21

From: Biwen Li <biwen.li(a)nxp.com> Change in v2: - fix warnings when check patches - enable gpio command for boards ls1021atwr, ls1021aqds Biwen Li (33): gpio: mpc8xxx_gpio: fix a bug on ls1046ardb arm: dts: ls1021a: add gpio node arm64: dts: ls1012a: add gpio node arm64: dts: ls1028a: add gpio node arm64: dts: ls1043a: add gpio node arm64: dts: ls1046a: add gpio node arm64: dts: ls1088a: add gpio node arm64: dts: ls208xa: add gpio node configs: ls1012a: enable CONFIG_MPC8XXX_GPIO configs: ls1043a: enable CONFIG_MPC8XXX_GPIO configs: ls1028a: enable CONFIG_MPC8XXX_GPIO configs: ls1088a: enable CONFIG_MPC8XXX_GPIO configs: ls208xa: enable CONFIG_MPC8XXX_GPIO configs: lx2160a: enable CONFIG_MPC8XXX_GPIO configs: ls1046a: enable MPC8XXX_GPIO configs: ls1021atwr: enable CONFIG_MPC8XXX_GPIO configs: ls1021aqds: enable CONFIG_MPC8XXX_GPIO configs: ls1012afrwy: enable CMD_GPIO configs: ls1012ardb: enable CMD_GPIO configs: ls1021aqds: enable CMD_GPIO configs: ls1021atwr: enable CMD_GPIO configs: ls1028aqds: enable CMD_GPIO configs: ls1028ardb: enable CMD_GPIO configs: ls1043aqds: enable CMD_GPIO configs: ls1043ardb: enable CMD_GPIO configs: ls1046ardb: enable CMD_GPIO configs: ls1046aqds: enable CMD_GPIO configs: ls2088ardb: enable DM_GPIO and CMD_GPIO configs: ls2088aqds: enable CMD_GPIO configs: ls1088aqds: enable DM_GPIO and CMD_GPIO configs: ls1088ardb: enable DM_GPIO and CMD_GPIO configs: lx2160ardb: enable CMD_GPIO configs: lx2160aqds: enable CMD_GPIO arch/arm/dts/fsl-ls1012a.dtsi | 20 ++++++++ arch/arm/dts/fsl-ls1028a.dtsi | 33 +++++++++++++ arch/arm/dts/fsl-ls1043a.dtsi | 40 ++++++++++++++++ arch/arm/dts/fsl-ls1046a.dtsi | 40 ++++++++++++++++ arch/arm/dts/fsl-ls1088a.dtsi | 46 +++++++++++++++++++ arch/arm/dts/fsl-ls2080a.dtsi | 45 ++++++++++++++++++ arch/arm/dts/ls1021a.dtsi | 40 ++++++++++++++++ .../asm/arch-fsl-layerscape/immap_lsch3.h | 10 ++++ .../ls1012afrwy_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1012afrwy_qspi_defconfig | 1 + configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1012afrwy_tfa_defconfig | 1 + configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1012ardb_qspi_defconfig | 1 + configs/ls1012ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1012ardb_tfa_defconfig | 1 + configs/ls1021aqds_ddr4_nor_defconfig | 1 + configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 1 + configs/ls1021aqds_nand_defconfig | 1 + configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 1 + configs/ls1021aqds_nor_defconfig | 1 + configs/ls1021aqds_nor_lpuart_defconfig | 1 + configs/ls1021aqds_qspi_defconfig | 1 + configs/ls1021aqds_sdcard_ifc_defconfig | 1 + configs/ls1021aqds_sdcard_qspi_defconfig | 1 + configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_nor_defconfig | 1 + configs/ls1021atwr_nor_lpuart_defconfig | 1 + configs/ls1021atwr_qspi_defconfig | 1 + ...s1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_sdcard_ifc_defconfig | 1 + configs/ls1021atwr_sdcard_qspi_defconfig | 1 + configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1028aqds_tfa_defconfig | 1 + configs/ls1028aqds_tfa_lpuart_defconfig | 1 + configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1028ardb_tfa_defconfig | 1 + configs/ls1043aqds_defconfig | 1 + configs/ls1043aqds_lpuart_defconfig | 1 + configs/ls1043aqds_nand_defconfig | 1 + configs/ls1043aqds_nor_ddr3_defconfig | 1 + configs/ls1043aqds_qspi_defconfig | 1 + configs/ls1043aqds_sdcard_ifc_defconfig | 1 + configs/ls1043aqds_sdcard_qspi_defconfig | 1 + configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1043aqds_tfa_defconfig | 1 + configs/ls1043ardb_SECURE_BOOT_defconfig | 1 + configs/ls1043ardb_defconfig | 1 + configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 1 + configs/ls1043ardb_nand_defconfig | 1 + .../ls1043ardb_sdcard_SECURE_BOOT_defconfig | 1 + configs/ls1043ardb_sdcard_defconfig | 1 + configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1043ardb_tfa_defconfig | 1 + configs/ls1046aqds_SECURE_BOOT_defconfig | 1 + configs/ls1046aqds_defconfig | 1 + configs/ls1046aqds_lpuart_defconfig | 1 + configs/ls1046aqds_nand_defconfig | 1 + configs/ls1046aqds_qspi_defconfig | 1 + configs/ls1046aqds_sdcard_ifc_defconfig | 1 + configs/ls1046aqds_sdcard_qspi_defconfig | 1 + configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1046aqds_tfa_defconfig | 1 + configs/ls1046ardb_emmc_defconfig | 1 + configs/ls1046ardb_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1046ardb_qspi_defconfig | 1 + configs/ls1046ardb_qspi_spl_defconfig | 1 + .../ls1046ardb_sdcard_SECURE_BOOT_defconfig | 1 + configs/ls1046ardb_sdcard_defconfig | 1 + configs/ls1046ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1046ardb_tfa_defconfig | 1 + configs/ls1088aqds_defconfig | 2 + configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 2 + configs/ls1088aqds_qspi_defconfig | 2 + configs/ls1088aqds_sdcard_ifc_defconfig | 2 + configs/ls1088aqds_sdcard_qspi_defconfig | 2 + configs/ls1088aqds_tfa_defconfig | 1 + configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 2 + configs/ls1088ardb_qspi_defconfig | 2 + ...1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 2 + configs/ls1088ardb_sdcard_qspi_defconfig | 2 + configs/ls1088ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1088ardb_tfa_defconfig | 1 + configs/ls2088aqds_tfa_defconfig | 1 + configs/ls2088ardb_qspi_SECURE_BOOT_defconfig | 2 + configs/ls2088ardb_qspi_defconfig | 2 + configs/ls2088ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls2088ardb_tfa_defconfig | 1 + configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160aqds_tfa_defconfig | 1 + configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160ardb_tfa_defconfig | 1 + configs/lx2160ardb_tfa_stmm_defconfig | 1 + drivers/gpio/mpc8xxx_gpio.c | 45 +++--------------- include/configs/ls1012a_common.h | 7 +++ include/configs/ls1021aqds.h | 7 +++ include/configs/ls1021atwr.h | 7 +++ include/configs/ls1028a_common.h | 7 +++ include/configs/ls1043a_common.h | 7 +++ include/configs/ls1046a_common.h | 7 +++ include/configs/ls1088a_common.h | 7 +++ include/configs/ls2080a_common.h | 7 +++ include/configs/lx2160a_common.h | 7 +++ 103 files changed, 440 insertions(+), 38 deletions(-) -- 2.17.1

2 34

arm: rk3399: add support nanopi r4s
by alex tian 19 Jan '21

19 Jan '21

>From e4f4c74b1f0e2bb7205a7b083fab6faf0b65c1ba Mon Sep 17 00:00:00 2001 From: Xiaobo Tian <peterwillcn(a)gmail.com> Date: Sat, 26 Dec 2020 00:13:37 +0800 Subject: [PATCH] arm: rk3399: add support nanopi r4s Signed-off-by: Xiaobo Tian <peterwillcn(a)gmail.com> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi | 7 ++ arch/arm/dts/rk3399-nanopi-r4s.dts | 120 +++++++++++++++++++++ configs/nanopi-r4s-rk3399_defconfig | 62 +++++++++++ 4 files changed, 190 insertions(+) create mode 100644 arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-nanopi-r4s.dts create mode 100644 configs/nanopi-r4s-rk3399_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index fd47e408f8..8d42c37fcb 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -92,6 +92,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \ rk3288-evb.dtb \ rk3288-firefly.dtb \ rk3288-miqi.dtb \ + rk3399-nanopi-r4s.dtb \ rk3288-phycore-rdk.dtb \ rk3288-popmetal.dtb \ rk3288-rock2-square.dtb \ diff --git a/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi new file mode 100644 index 0000000000..05f785e662 --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Xiaobo <tianxiaobo(a)gelaxy.io> + */ + +#include "rk3399-nanopi4-u-boot.dtsi" +#include "rk3399-sdram-lpddr4-100.dtsi" diff --git a/arch/arm/dts/rk3399-nanopi-r4s.dts b/arch/arm/dts/rk3399-nanopi-r4s.dts new file mode 100644 index 0000000000..5c65447f0e --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi-r4s.dts @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (C) 2020 Xiaobo <tianxiaobo(a)gelaxy.io> + */ + +/dts-v1/; +#include "rk3399-nanopi4.dtsi" + +/ { + model = "FriendlyElec NanoPi R4S"; + compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399"; + + vdd_5v: vdd-5v { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v"; + regulator-always-on; + regulator-boot-on; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + /* FIXME: adjust leveles for the connected fan */ + cooling-levels = <0 12 18 255>; + #cooling-cells = <2>; + fan-supply = <&vdd_5v>; + pwms = <&pwm1 0 50000 0>; + }; +}; + +&cpu_thermal { + trips { + cpu_warm: cpu_warm { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_hot: cpu_hot { + temperature = <65000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map2 { + trip = <&cpu_warm>; + cooling-device = <&fan THERMAL_NO_LIMIT 1>; + }; + + map3 { + trip = <&cpu_hot>; + cooling-device = <&fan 2 THERMAL_NO_LIMIT>; + }; + }; +}; + +&emmc_phy { + status = "disabled"; +}; + +&fusb0 { + status = "disabled"; +}; + +&leds { + lan_led: led-1 { + gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; + label = "nanopi-r4s:green:lan"; + }; + + wan_led: led-2 { + gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; + label = "nanopi-r4s:green:wan"; + }; +}; + +&leds_gpio { + rockchip,pins = + <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; +}; + +&pcie0 { + max-link-speed = <1>; + num-lanes = <1>; + vpcie3v3-supply = <&vcc3v3_sys>; +}; + +&sdhci { + status = "disabled"; +}; + +&sdio0 { + status = "disabled"; +}; + +&sdmmc { + host-index-min = <1>; +}; + +&u2phy0_host { + phy-supply = <&vdd_5v>; +}; + +&u2phy1_host { + status = "disabled"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "host"; +}; + +&vcc3v3_sys { + vin-supply = <&vcc5v0_sys>; +}; diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig new file mode 100644 index 0000000000..0a3c28b012 --- /dev/null +++ b/configs/nanopi-r4s-rk3399_defconfig @@ -0,0 +1,62 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_EVB_RK3399=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4s.dtb" +CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_TPL=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4s" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM_RK3399_LPDDR4=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y -- 2.30.0 -- -- Tian Xiaobo )\._.,--....,'``. /, _.. \ _\ ;`._ ,. `._.-(,_..'--(,_..'`-.;.' WeChat: Yesloveme QQ: 56775982 Best Regards !

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Invitation: Regular U-Boot video call (Tuesday 19th)
by Simon Glass 19 Jan '21

19 Jan '21

Hi, (This has been discussed for a while now so I thought I would just try it) As an experiment I'd like to set up a regular 30-minute U-Boot call for people to discuss features, bugs, patches, etc. The meeting notes and details are here[1]. Please feel free to send this to others. I cc'd a small number of people on the list. Regards, Simon [1] https://bit.ly/3bFvwA1

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[PATCH] spi: zynqmp_gqspi: support dual and quad mode
by Brandon Maier 18 Jan '21

18 Jan '21

The dm_spi_ops.xfer() API does not support dual and quad SPI modes. It also doesn't allow the zynqmp_gqspi driver to calculate the correct number of dummy cycles for some NOR ops (as doing so also requires the buswidth). Port the zynqmp_gqspi driver to spi_controller_mem_ops, which gives us the buswidth values to correctly support all SNOR_PROTO_X_X_X commands and to properly calculate dummy cycles. Signed-off-by: Brandon Maier <brandon.maier(a)rockwellcollins.com> CC: jagan(a)amarulasolutions.com CC: michal.simek(a)xilinx.com --- drivers/spi/zynqmp_gqspi.c | 164 ++++++++++++++++--------------------- 1 file changed, 70 insertions(+), 94 deletions(-) diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index efcbd0557f..e1fd551f68 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -16,6 +16,7 @@ #include <malloc.h> #include <memalign.h> #include <spi.h> +#include <spi-mem.h> #include <ubi_uboot.h> #include <wait_bit.h> #include <dm/device_compat.h> @@ -171,8 +172,7 @@ struct zynqmp_qspi_priv { unsigned int len; int bytes_to_transfer; int bytes_to_receive; - unsigned int is_inst; - unsigned int cs_change:1; + const struct spi_mem_op *op; }; static int zynqmp_qspi_of_to_plat(struct udevice *bus) @@ -221,6 +221,21 @@ static u32 zynqmp_qspi_bus_select(struct zynqmp_qspi_priv *priv) return gqspi_fifo_reg; } +static u32 zynqmp_qspi_genfifo_mode(u8 buswidth) +{ + switch (buswidth) { + case 1: + return GQSPI_SPI_MODE_SPI; + case 2: + return GQSPI_SPI_MODE_DUAL_SPI; + case 4: + return GQSPI_SPI_MODE_QSPI; + default: + debug("Unsupported bus width %u\n", buswidth); + return GQSPI_SPI_MODE_SPI; + } +} + static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv, u32 gqspi_fifo_reg) { @@ -445,21 +460,42 @@ static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size) static void zynqmp_qspi_genfifo_cmd(struct zynqmp_qspi_priv *priv) { + const struct spi_mem_op *op = priv->op; u32 gen_fifo_cmd; - u32 bytecount = 0; + u8 i, dummy_cycles, addr; + + /* Send opcode */ + gen_fifo_cmd = zynqmp_qspi_bus_select(priv); + gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op->cmd.buswidth); + gen_fifo_cmd |= GQSPI_GFIFO_TX; + gen_fifo_cmd |= op->cmd.opcode; + zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd); + + /* Send address */ + for (i = 0; i < op->addr.nbytes; i++) { + addr = op->addr.val >> (8 * (op->addr.nbytes - i - 1)); - while (priv->len) { gen_fifo_cmd = zynqmp_qspi_bus_select(priv); - gen_fifo_cmd |= GQSPI_GFIFO_TX | GQSPI_SPI_MODE_SPI; - gen_fifo_cmd |= *(u8 *)priv->tx_buf; - bytecount++; - priv->len--; - priv->tx_buf = (u8 *)priv->tx_buf + 1; + gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op->addr.buswidth); + gen_fifo_cmd |= GQSPI_GFIFO_TX; + gen_fifo_cmd |= addr; debug("GFIFO_CMD_Cmd = 0x%x\n", gen_fifo_cmd); zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd); } + + /* Send dummy */ + if (op->dummy.nbytes) { + dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth; + + gen_fifo_cmd = zynqmp_qspi_bus_select(priv); + gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op->dummy.buswidth); + gen_fifo_cmd &= ~(GQSPI_GFIFO_TX | GQSPI_GFIFO_RX); + gen_fifo_cmd |= GQSPI_GFIFO_DATA_XFR_MASK; + gen_fifo_cmd |= dummy_cycles; + zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd); + } } static u32 zynqmp_qspi_calc_exp(struct zynqmp_qspi_priv *priv, @@ -496,11 +532,10 @@ static int zynqmp_qspi_genfifo_fill_tx(struct zynqmp_qspi_priv *priv) int ret = 0; gen_fifo_cmd = zynqmp_qspi_bus_select(priv); + gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth); gen_fifo_cmd |= GQSPI_GFIFO_TX | GQSPI_GFIFO_DATA_XFR_MASK; - gen_fifo_cmd |= GQSPI_SPI_MODE_SPI; - while (priv->len) { len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd); zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd); @@ -574,11 +609,10 @@ static int zynqmp_qspi_genfifo_fill_rx(struct zynqmp_qspi_priv *priv) u32 actuallen = priv->len; gen_fifo_cmd = zynqmp_qspi_bus_select(priv); + gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth); gen_fifo_cmd |= GQSPI_GFIFO_RX | GQSPI_GFIFO_DATA_XFR_MASK; - gen_fifo_cmd |= GQSPI_SPI_MODE_SPI; - /* * Check if receive buffer is aligned to 4 byte and length * is multiples of four byte as we are using dma to receive. @@ -595,62 +629,6 @@ static int zynqmp_qspi_genfifo_fill_rx(struct zynqmp_qspi_priv *priv) return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf); } -static int zynqmp_qspi_start_transfer(struct zynqmp_qspi_priv *priv) -{ - int ret = 0; - - if (priv->is_inst) { - if (priv->tx_buf) - zynqmp_qspi_genfifo_cmd(priv); - else - return -EINVAL; - } else { - if (priv->tx_buf) - ret = zynqmp_qspi_genfifo_fill_tx(priv); - else if (priv->rx_buf) - ret = zynqmp_qspi_genfifo_fill_rx(priv); - else - return -EINVAL; - } - return ret; -} - -static int zynqmp_qspi_transfer(struct zynqmp_qspi_priv *priv) -{ - static unsigned int cs_change = 1; - int status = 0; - - debug("%s\n", __func__); - - while (1) { - /* Select the chip if required */ - if (cs_change) - zynqmp_qspi_chipselect(priv, 1); - - cs_change = priv->cs_change; - - if (!priv->tx_buf && !priv->rx_buf && priv->len) { - status = -EINVAL; - break; - } - - /* Request the transfer */ - if (priv->len) { - status = zynqmp_qspi_start_transfer(priv); - priv->is_inst = 0; - if (status < 0) - break; - } - - if (cs_change) - /* Deselect the chip */ - zynqmp_qspi_chipselect(priv, 0); - break; - } - - return status; -} - static int zynqmp_qspi_claim_bus(struct udevice *dev) { struct udevice *bus = dev->parent; @@ -673,45 +651,43 @@ static int zynqmp_qspi_release_bus(struct udevice *dev) return 0; } -int zynqmp_qspi_xfer(struct udevice *dev, unsigned int bitlen, const void *dout, - void *din, unsigned long flags) +static int zynqmp_qspi_exec_op(struct spi_slave *slave, + const struct spi_mem_op *op) { - struct udevice *bus = dev->parent; - struct zynqmp_qspi_priv *priv = dev_get_priv(bus); + struct zynqmp_qspi_priv *priv = dev_get_priv(slave->dev->parent); + int ret; - debug("%s: priv: 0x%08lx bitlen: %d dout: 0x%08lx ", __func__, - (unsigned long)priv, bitlen, (unsigned long)dout); - debug("din: 0x%08lx flags: 0x%lx\n", (unsigned long)din, flags); + priv->op = op; + priv->tx_buf = op->data.buf.out; + priv->rx_buf = op->data.buf.in; + priv->len = op->data.nbytes; - priv->tx_buf = dout; - priv->rx_buf = din; - priv->len = bitlen / 8; + zynqmp_qspi_chipselect(priv, 1); - /* - * Assume that the beginning of a transfer with bits to - * transmit must contain a device command. - */ - if (dout && flags & SPI_XFER_BEGIN) - priv->is_inst = 1; - else - priv->is_inst = 0; + /* Send opcode, addr, dummy */ + zynqmp_qspi_genfifo_cmd(priv); - if (flags & SPI_XFER_END) - priv->cs_change = 1; - else - priv->cs_change = 0; + /* Request the transfer */ + if (op->data.dir == SPI_MEM_DATA_IN) + ret = zynqmp_qspi_genfifo_fill_rx(priv); + else if (op->data.dir == SPI_MEM_DATA_OUT) + ret = zynqmp_qspi_genfifo_fill_tx(priv); - zynqmp_qspi_transfer(priv); + zynqmp_qspi_chipselect(priv, 0); - return 0; + return ret; } +static const struct spi_controller_mem_ops zynqmp_qspi_mem_ops = { + .exec_op = zynqmp_qspi_exec_op, +}; + static const struct dm_spi_ops zynqmp_qspi_ops = { .claim_bus = zynqmp_qspi_claim_bus, .release_bus = zynqmp_qspi_release_bus, - .xfer = zynqmp_qspi_xfer, .set_speed = zynqmp_qspi_set_speed, .set_mode = zynqmp_qspi_set_mode, + .mem_ops = &zynqmp_qspi_mem_ops, }; static const struct udevice_id zynqmp_qspi_ids[] = { -- 2.29.1

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[PULL] u-boot-sh/master
by Marek Vasut 18 Jan '21

18 Jan '21

The following changes since commit 14ea1b3635b4af8d9e283e3671f7ee872d50b859: Merge branch '2021-01-15-assorted-improvements' (2021-01-16 11:14:21 -0500) are available in the Git repository at: git://git.denx.de/u-boot-sh.git master for you to fetch changes up to 67704d6dfba5dcb3c33b0eb91e10f908c3dbbdcd: ARM: dts: renesas: Remove leading 0x from rpc node (2021-01-18 13:29:12 +0100) ---------------------------------------------------------------- Lad Prabhakar (3): pinctrl: renesas: Make sure the pin type is updated after setting the MUX pinctrl: renesas: Implement get_pin_muxing() callback ARM: dts: renesas: Remove leading 0x from rpc node arch/arm/dts/r7s72100-gr-peach-u-boot.dts | 2 +- arch/arm/dts/r8a77950-u-boot.dtsi | 2 +- arch/arm/dts/r8a77960-u-boot.dtsi | 2 +- arch/arm/dts/r8a77965-u-boot.dtsi | 2 +- arch/arm/dts/r8a77970-u-boot.dtsi | 2 +- arch/arm/dts/r8a77980-u-boot.dtsi | 2 +- arch/arm/dts/r8a77990-u-boot.dtsi | 2 +- arch/arm/dts/r8a77995-u-boot.dtsi | 2 +- drivers/pinctrl/renesas/pfc.c | 77 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++----- 9 files changed, 80 insertions(+), 13 deletions(-)

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Pull request: u-boot-riscv/master
by uboot＠andestech.com 18 Jan '21

18 Jan '21

Hi Tom, Please pull some riscv updates: - Update qemu-riscv.rst build instructions. - Add support for SPI on Kendryte K210. - Add Microchip PolarFire SoC Icicle Kit support. - Add support for an early timer. - select TIMER_EARLY to avoid infinite recursion for Trace. Thanks Rick CI: passed https://gitlab.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/5918 The following changes since commit 14ea1b3635b4af8d9e283e3671f7ee872d50b859: Merge branch '2021-01-15-assorted-improvements' (2021-01-16 11:14:21 -0500) are available in the Git repository at: git@gitlab.denx.de:u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 9e550e18305fb31af83bfb72d16e86d8c054fb65: doc: board: Add Microchip MPFS Icicle Kit doc (2021-01-18 11:06:39 +0800) ---------------------------------------------------------------- Atish Patra (1): doc: qemu-riscv: Fix opensbi build instructions Padmarao Begari (7): riscv: Add DMA 64-bit address support net: macb: Add DMA 64-bit address support for macb net: macb: Add phy address to read it from device tree clk: Add Microchip PolarFire SoC clock driver riscv: dts: Add device tree for Microchip Icicle Kit riscv: Add Microchip MPFS Icicle Kit support doc: board: Add Microchip MPFS Icicle Kit doc Pragnesh Patel (2): trace: select TIMER_EARLY to avoid infinite recursion riscv: timer: Add support for an early timer Sean Anderson (1): riscv: Add support for SPI on Kendryte K210 arch/riscv/Kconfig | 4 + arch/riscv/dts/Makefile | 1 + arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi | 14 +++ arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 421 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/riscv/include/asm/types.h | 4 + board/microchip/mpfs_icicle/Kconfig | 23 +++++ board/microchip/mpfs_icicle/mpfs_icicle.c | 99 +++++++++++++++++- board/sipeed/maix/Kconfig | 16 +++ configs/microchip_mpfs_icicle_defconfig | 9 +- configs/sipeed_maix_bitm_defconfig | 11 ++ doc/board/emulation/qemu-riscv.rst | 2 +- doc/board/index.rst | 1 + doc/board/microchip/index.rst | 9 ++ doc/board/microchip/mpfs_icicle.rst | 810 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ doc/board/sipeed/maix.rst | 315 ++++++++++++++++++++++++++++++++++++++++++++++++--------- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/microchip/Kconfig | 5 + drivers/clk/microchip/Makefile | 1 + drivers/clk/microchip/mpfs_clk.c | 123 +++++++++++++++++++++++ drivers/clk/microchip/mpfs_clk.h | 44 ++++++++ drivers/clk/microchip/mpfs_clk_cfg.c | 152 ++++++++++++++++++++++++++++ drivers/clk/microchip/mpfs_clk_periph.c | 187 ++++++++++++++++++++++++++++++++++ drivers/net/macb.c | 144 ++++++++++++++++++++++---- drivers/net/macb.h | 6 ++ drivers/timer/andes_plmt_timer.c | 21 +++- drivers/timer/riscv_timer.c | 21 +++- drivers/timer/sifive_clint_timer.c | 21 +++- include/configs/ax25-ae350.h | 5 + include/configs/microchip_mpfs_icicle.h | 59 ++++------- include/configs/qemu-riscv.h | 5 + include/configs/sifive-fu540.h | 5 + include/configs/sipeed-maix.h | 7 +- include/dt-bindings/clock/microchip-mpfs-clock.h | 45 +++++++++ lib/Kconfig | 1 + 35 files changed, 2477 insertions(+), 116 deletions(-) create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit.dts create mode 100644 doc/board/microchip/index.rst create mode 100644 doc/board/microchip/mpfs_icicle.rst create mode 100644 drivers/clk/microchip/Kconfig create mode 100644 drivers/clk/microchip/Makefile create mode 100644 drivers/clk/microchip/mpfs_clk.c create mode 100644 drivers/clk/microchip/mpfs_clk.h create mode 100644 drivers/clk/microchip/mpfs_clk_cfg.c create mode 100644 drivers/clk/microchip/mpfs_clk_periph.c create mode 100644 include/dt-bindings/clock/microchip-mpfs-clock.h

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