September 2020 - U-Boot

[PATCH v3] mmc: fsl_esdhc_imx: check the clock stable status after config the clock rate.
by haibo.chen＠nxp.com 18 Sep '20

18 Sep '20

From: Haibo Chen <haibo.chen(a)nxp.com> Currently, after config the clock rate, delay 10ms, this is quite a rough method. Check the clock stable status in the present status register is enough. Tested-by: Ji Luo <ji.luo(a)nxp.com> Signed-off-by: Haibo Chen <haibo.chen(a)nxp.com> --- drivers/mmc/fsl_esdhc_imx.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 788677984b..0c866b168f 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -36,6 +36,7 @@ #include <dt-structs.h> #include <mapmem.h> #include <dm/ofnode.h> +#include <linux/iopoll.h> #if !CONFIG_IS_ENABLED(BLK) #include "mmc_private.h" @@ -631,6 +632,8 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) { struct fsl_esdhc *regs = priv->esdhc_regs; int div = 1; + u32 tmp; + int ret; #ifdef ARCH_MXC #ifdef CONFIG_MX53 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */ @@ -664,7 +667,9 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk); - udelay(10000); + ret = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp, tmp & PRSSTAT_SDSTB, 100); + if (ret) + pr_warn("fsl_esdhc_imx: Internal clock never stabilised.\n"); #ifdef CONFIG_FSL_USDHC esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN); -- 2.17.1

2 1

[PATCH 1/5] imx7: ccm: correct target interface num
by peng.fan＠nxp.com 18 Sep '20

18 Sep '20

From: Peng Fan <peng.fan(a)nxp.com> According to i.MX 7Dual Applications Processor Reference Manual, Rev. 1 The target interface CCM root index ranges [0,124], so the number should be 125. Reported-by: Coverity 18045 Signed-off-by: Peng Fan <peng.fan(a)nxp.com> Reviewed-by: Ye Li <ye.li(a)nxp.com> --- arch/arm/include/asm/arch-mx7/crm_regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-mx7/crm_regs.h b/arch/arm/include/asm/arch-mx7/crm_regs.h index f3515fab03..bfa68a9d2a 100644 --- a/arch/arm/include/asm/arch-mx7/crm_regs.h +++ b/arch/arm/include/asm/arch-mx7/crm_regs.h @@ -57,7 +57,7 @@ struct mxc_ccm_reg { uint32_t reserved_0[4092]; struct mxc_ccm_ccgr ccgr_array[191]; /* offset 0x4000 */ uint32_t reserved_1[3332]; - struct mxc_ccm_root_slice root[121]; /* offset 0x8000 */ + struct mxc_ccm_root_slice root[125]; /* offset 0x8000 */ }; -- 2.28.0

2 9

[PATCH v1 1/2] colibri-imx8qxp: rename all occurences to colibri-imx8x
by Igor Opaniuk 18 Sep '20

18 Sep '20

From: Philippe Schenker <philippe.schenker(a)toradex.com> The Toradex product is called colibri-imx8x consisting of SoM with i.MX8QXP and i.MX8DX SoCs. Signed-off-by: Philippe Schenker <philippe.schenker(a)toradex.com> Reviewed-by: Igor Opaniuk <igor.opaniuk(a)toradex.com> --- arch/arm/dts/fsl-imx8qxp-colibri.dts | 6 +++--- board/toradex/colibri-imx8x/MAINTAINERS | 2 +- ...ibri-imx8qxp-imximage.cfg => colibri-imx8x-imximage.cfg} | 0 .../{colibri-imx8qxp_defconfig => colibri-imx8x_defconfig} | 2 +- doc/board/toradex/colibri-imx8x.rst | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-) rename board/toradex/colibri-imx8x/{colibri-imx8qxp-imximage.cfg => colibri-imx8x-imximage.cfg} (100%) rename configs/{colibri-imx8qxp_defconfig => colibri-imx8x_defconfig} (98%) diff --git a/arch/arm/dts/fsl-imx8qxp-colibri.dts b/arch/arm/dts/fsl-imx8qxp-colibri.dts index 0c20edf2cf..11ece34c02 100644 --- a/arch/arm/dts/fsl-imx8qxp-colibri.dts +++ b/arch/arm/dts/fsl-imx8qxp-colibri.dts @@ -9,8 +9,8 @@ #include "fsl-imx8qxp-colibri-u-boot.dtsi" / { - model = "Toradex Colibri iMX8QXP"; - compatible = "toradex,colibri-imx8qxp", "fsl,imx8qxp"; + model = "Toradex Colibri iMX8X"; + compatible = "toradex,colibri-imx8x", "fsl,imx8qxp"; chosen { bootargs = "console=ttyLP3,115200 earlycon=lpuart32,0x5a090000,115200"; @@ -32,7 +32,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_hog2>; - colibri-imx8qxp { + colibri-imx8x { pinctrl_lpuart0: lpuart0grp { fsl,pins = < SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 diff --git a/board/toradex/colibri-imx8x/MAINTAINERS b/board/toradex/colibri-imx8x/MAINTAINERS index f6853586c8..de62f87a56 100644 --- a/board/toradex/colibri-imx8x/MAINTAINERS +++ b/board/toradex/colibri-imx8x/MAINTAINERS @@ -5,6 +5,6 @@ S: Maintained F: arch/arm/dts/fsl-imx8x-colibri.dts F: arch/arm/dts/fsl-imx8x-colibri-u-boot.dtsi F: board/toradex/colibri-imx8x/ -F: configs/colibri-imx8qxp_defconfig +F: configs/colibri-imx8x_defconfig F: doc/board/toradex/colibri-imx8x.rst F: include/configs/colibri-imx8x.h diff --git a/board/toradex/colibri-imx8x/colibri-imx8qxp-imximage.cfg b/board/toradex/colibri-imx8x/colibri-imx8x-imximage.cfg similarity index 100% rename from board/toradex/colibri-imx8x/colibri-imx8qxp-imximage.cfg rename to board/toradex/colibri-imx8x/colibri-imx8x-imximage.cfg diff --git a/configs/colibri-imx8qxp_defconfig b/configs/colibri-imx8x_defconfig similarity index 98% rename from configs/colibri-imx8qxp_defconfig rename to configs/colibri-imx8x_defconfig index 719e7473e1..92dc103ce3 100644 --- a/configs/colibri-imx8qxp_defconfig +++ b/configs/colibri-imx8x_defconfig @@ -10,7 +10,7 @@ CONFIG_TARGET_COLIBRI_IMX8X=y CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-colibri" CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri-imx8x/colibri-imx8qxp-imximage.cfg" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri-imx8x/colibri-imx8x-imximage.cfg" CONFIG_LOG=y CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/doc/board/toradex/colibri-imx8x.rst b/doc/board/toradex/colibri-imx8x.rst index 244e5a4c04..616f40ae0f 100644 --- a/doc/board/toradex/colibri-imx8x.rst +++ b/doc/board/toradex/colibri-imx8x.rst @@ -52,7 +52,7 @@ Build U-Boot .. code-block:: bash - $ make colibri-imx8qxp_defconfig + $ make colibri-imx8x_defconfig $ make u-boot-dtb.imx Load the U-Boot Binary Using UUU -- 2.17.1

2 3

arm: dts: lx2162aqds: support eMMC HS400 mode
by Yangbo Lu 18 Sep '20

18 Sep '20

From: Guanhua Gao <guanhua.gao(a)nxp.com> From: Yangbo Lu <yangbo.lu(a)nxp.com> Add properties related to eMMC HS400 mode. Signed-off-by: Yangbo Lu <yangbo.lu(a)nxp.com> diff --git a/arch/arm/dts/fsl-lx2162a-qds.dts b/arch/arm/dts/fsl-lx2162a-qds.dts index 8c29fd2..a2be9ac 100644 --- a/arch/arm/dts/fsl-lx2162a-qds.dts +++ b/arch/arm/dts/fsl-lx2162a-qds.dts @@ -55,6 +55,9 @@ &esdhc1 { status = "okay"; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + bus-width = <8>; }; &i2c0 {

2 1

[PATCH] pci: layerscape: Fixup PCIe EP mode DT nodes for LX2160A rev2
by Zhiqiang Hou 18 Sep '20

18 Sep '20

From: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> LX2160A rev2 uses different PCIe controller, so EP mode DT nodes also need to be fixed up. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> --- drivers/pci/pcie_layerscape_fixup_common.c | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/pci/pcie_layerscape_fixup_common.c b/drivers/pci/pcie_layerscape_fixup_common.c index fef0a75f11..0a42997696 100644 --- a/drivers/pci/pcie_layerscape_fixup_common.c +++ b/drivers/pci/pcie_layerscape_fixup_common.c @@ -41,6 +41,8 @@ int lx2_board_fix_fdt(void *fdt) { "config_axi_slave", "config" } }; int off = -1, i; + const fdt32_t *prop; + u32 ob_wins, ib_wins; off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie"); while (off != -FDT_ERR_NOTFOUND) { @@ -86,6 +88,30 @@ int lx2_board_fix_fdt(void *fdt) off = fdt_node_offset_by_compatible(fdt, off, "fsl,lx2160a-pcie"); } + + /* Fixup PCIe EP nodes */ + off = -1; + off = fdt_node_offset_by_compatible(fdt, off, "fsl,lx2160a-pcie-ep"); + while (off != -FDT_ERR_NOTFOUND) { + fdt_setprop_string(fdt, off, "compatible", + "fsl,lx2160ar2-pcie-ep"); + prop = fdt_getprop(fdt, off, "apio-wins", NULL); + if (!prop) { + printf("%s: Failed to fixup PCIe EP node @0x%x\n", + __func__, off); + continue; + } + + ob_wins = fdt32_to_cpu(*prop); + ib_wins = (ob_wins == 256) ? 24 : 8; + fdt_setprop_u32(fdt, off, "num-ib-windows", ib_wins); + fdt_setprop_u32(fdt, off, "num-ob-windows", ob_wins); + fdt_delprop(fdt, off, "apio-wins"); + + off = fdt_node_offset_by_compatible(fdt, off, + "fsl,lx2160a-pcie-ep"); + } + return 0; } -- 2.17.1

2 1

[PATCH 1/2] net: pfe_eth: Fix resoure leak in pfe_spi_flash_init
by Kuldeep Singh 18 Sep '20

18 Sep '20

Fix Coverity issue: RESOURCE_LEAK. leaked_storage: Variable addr going out of scope leaks the storage it points to. Fixes: e0152dbed683 ("net: pfe_eth: Use spi_flash_read API to access flash memory") Signed-off-by: Kuldeep Singh <kuldeep.singh(a)nxp.com> --- drivers/net/pfe_eth/pfe_firmware.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/pfe_eth/pfe_firmware.c b/drivers/net/pfe_eth/pfe_firmware.c index 55e661c..4ad09dd 100644 --- a/drivers/net/pfe_eth/pfe_firmware.c +++ b/drivers/net/pfe_eth/pfe_firmware.c @@ -170,6 +170,9 @@ int pfe_spi_flash_init(void) int ret = 0; void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); + if (!addr) + return -ENOMEM; + #ifdef CONFIG_DM_SPI_FLASH struct udevice *new; @@ -186,6 +189,7 @@ int pfe_spi_flash_init(void) #endif if (!pfe_flash) { printf("SF: probe for pfe failed\n"); + free(addr); return -ENODEV; } -- 2.7.4

2 2

[PATCH v2 00/30] Add DM support for omap PWM backlight
by Dario Binacchi 18 Sep '20

18 Sep '20

The series was born from the need to manage the PWM backlight of the display connected to my beaglebone board. To hit the target, I had to develop drivers for PWM management which in turn relied on drivers for managing timers and clocks, all developed according to the driver model. My intention was to use the SoC-specific API only at strictly necessary points in the code. My previous patches for migrating the AM335x display driver to the driver model had required the implementation of additional functions outside the concerns of the driver, (settings for dividing the pixel clock rate, configuring the display DPLL rate, ....) not being able to use the API of the related clock drivers. This series shouldn't have repeated the same kind of mistake. Furthermore, I also wanted to fix that kind of forced choice. Almost everything should have been accessible via the driver model API. In the series there are also some patches that could be submitted separately, but which I have however inserted to avoid applying future patches to incorporate them. With this last consideration, I hope I have convincingly justified the large number of patches in the series. The patch enabling address translation into a CPU physical address from device-tree even in case of crossing levels with #size-cells = <0>, is crucial for the series. The previous implementation was unable to perform the address translation required by the am33xx device tree. I tried to apply in a conservative way as few changes as possible and to verify the execution of all the tests already developed, as well as the new ones I added for the new feature. Changes in v2: - Add the clk_ prefix to the divider functions. - Add kernel-doc comments to the exported functions. - Merged to patch [09/31] clk: ti: refactor mux and divider clock drivers. - Remove the 'ti_am3_prcm_clocks' driver. Handle 'prcm_clocks' node in the 'ti_am3_prcm' driver. - Update the commit message. - Fix a missing line in the commit message. - Add dm_flags to global_data structure and GD_DM_FLG_SIZE_CELLS_0 macro to test without recompiling. - Update the OF_CHECK_COUNTS macro in order to have just one #define by bringing the GD_DM_FLG_SIZE_CELLS_0 into the expression. - Lower-case the 0xC019 hex number. - Remove the 'ti_am3_scm_clocks' driver. Handle 'scm_clocks' node in the 'ti_am3_scm' driver. - Update the commit message. Dario Binacchi (30): clk: remove a redundant header clk: export generic routines arch: sandbox: fix typo in clk.h clk: add clk_round_rate() clk: ti: add mux clock driver arm: ti: am33xx: add DPLL_EN_FAST_RELOCK_BYPASS macro clk: ti: am33xx: add DPLL clock drivers clk: ti: add divider clock driver clk: ti: add gate clock driver ti: am33xx: fix do_enable_clocks() to accept NULL parameters clk: ti: add support for clkctrl clocks clk: ti: move drivers to 'ti' directory clk: ti: omap4: add clock manager driver clk: ti: am335x: add clock manager driver fdt: translate address if #size-cells = <0> omap: timer: fix the rate setting misc: am33xx: add control module driver pwm: ti: am33xx: add enhanced pwm driver pwm: ti: am33xx: add subsystem driver video: backlight: fix pwm's duty cycle calculation video: backlight: fix pwm data structure description dm: core: improve uclass_get_device_by_phandle_id() description gpio: fix gpio_request_by_name() description dm: core: add a function to decode display timings video: omap: add panel driver video: omap: enable LCD clock domain through DM API video: omap: set LCD clock rate through DM API video: omap: split the legacy code from the DM code video: omap: move drivers to 'ti' directory board: ti: am335x-ice: get CDCE913 clock device arch/arm/dts/am335x-brppt1-mmc.dts | 3 +- arch/arm/dts/am335x-brppt1-nand.dts | 3 +- arch/arm/dts/am335x-brppt1-spi.dts | 3 +- arch/arm/dts/am335x-brsmarc1.dts | 2 +- arch/arm/dts/am335x-brxre1.dts | 3 +- arch/arm/dts/am335x-evm-u-boot.dtsi | 7 +- arch/arm/dts/am335x-evmsk-u-boot.dtsi | 6 +- arch/arm/dts/am335x-guardian-u-boot.dtsi | 8 +- arch/arm/dts/am335x-pdu001-u-boot.dtsi | 8 +- arch/arm/dts/am335x-pxm50-u-boot.dtsi | 6 +- arch/arm/dts/am335x-rut-u-boot.dtsi | 6 +- arch/arm/dts/am33xx.dtsi | 12 + arch/arm/dts/da850-evm-u-boot.dtsi | 8 +- arch/arm/include/asm/arch-am33xx/clock.h | 1 + arch/arm/mach-omap2/am33xx/clock.c | 10 +- arch/arm/mach-omap2/am33xx/clock_am33xx.c | 2 +- arch/sandbox/dts/test.dts | 67 +++ arch/sandbox/include/asm/clk.h | 35 +- board/ti/am335x/board.c | 2 +- board/ti/am43xx/board.c | 2 +- common/fdt_support.c | 6 +- doc/device-tree-bindings/arm/omap,ctrl.txt | 82 +++ doc/device-tree-bindings/arm/omap,prcm.txt | 63 +++ .../clock/clock-bindings.txt | 186 +++++++ .../clock/gpio-gate-clock.txt | 21 + .../clock/ti,autoidle.txt | 39 ++ doc/device-tree-bindings/clock/ti,clkctrl.txt | 61 +++ .../clock/ti,clockdomain.txt | 24 + doc/device-tree-bindings/clock/ti,divider.txt | 117 +++++ doc/device-tree-bindings/clock/ti,dpll.txt | 85 ++++ doc/device-tree-bindings/clock/ti,gate.txt | 106 ++++ doc/device-tree-bindings/clock/ti,mux.txt | 79 +++ .../pinctrl/pinctrl-single.txt | 255 ++++++++++ doc/device-tree-bindings/pwm/ti,ehrpwm.txt | 49 ++ doc/device-tree-bindings/pwm/ti,pwmss.txt | 58 +++ drivers/clk/Kconfig | 9 +- drivers/clk/Makefile | 2 +- drivers/clk/clk-divider.c | 24 +- drivers/clk/clk-uclass.c | 15 + drivers/clk/clk_sandbox.c | 17 + drivers/clk/clk_sandbox_test.c | 10 + drivers/clk/ti/Kconfig | 42 ++ drivers/clk/ti/Makefile | 18 + drivers/clk/ti/am3-prcm.c | 65 +++ drivers/clk/ti/clk-am3-dpll-x2.c | 78 +++ drivers/clk/ti/clk-am3-dpll.c | 267 ++++++++++ drivers/clk/ti/clk-ctrl.c | 102 ++++ drivers/clk/ti/clk-divider.c | 380 ++++++++++++++ drivers/clk/ti/clk-gate.c | 92 ++++ drivers/clk/ti/clk-mux.c | 252 ++++++++++ drivers/clk/{clk-ti-sci.c => ti/clk-sci.c} | 0 drivers/clk/ti/clk.c | 34 ++ drivers/clk/ti/clk.h | 13 + drivers/clk/ti/omap4-cm.c | 22 + drivers/core/Kconfig | 12 + drivers/core/fdtaddr.c | 2 +- drivers/core/of_addr.c | 14 +- drivers/core/ofnode.c | 7 +- drivers/core/read.c | 6 + drivers/core/root.c | 3 + drivers/misc/Kconfig | 7 + drivers/misc/Makefile | 1 + drivers/misc/ti-am3-scm.c | 81 +++ drivers/pwm/Kconfig | 13 + drivers/pwm/Makefile | 2 + drivers/pwm/pwm-ti-ehrpwm.c | 465 ++++++++++++++++++ drivers/pwm/pwm-ti-pwmss.c | 95 ++++ drivers/timer/omap-timer.c | 6 +- drivers/video/Kconfig | 5 +- drivers/video/Makefile | 2 +- drivers/video/pwm_backlight.c | 4 +- drivers/video/ti/Kconfig | 8 + drivers/video/ti/Makefile | 10 + drivers/video/{ => ti}/am335x-fb.c | 342 +------------ drivers/video/{ => ti}/am335x-fb.h | 4 - drivers/video/ti/tilcdc-panel.c | 171 +++++++ drivers/video/ti/tilcdc-panel.h | 14 + drivers/video/ti/tilcdc.c | 438 +++++++++++++++++ drivers/video/ti/tilcdc.h | 38 ++ include/asm-generic/global_data.h | 6 + include/asm-generic/gpio.h | 2 +- include/clk-uclass.h | 8 + include/clk.h | 29 ++ include/dm/read.h | 24 + include/dm/uclass.h | 3 +- include/linux/clk-provider.h | 58 ++- test/dm/clk.c | 22 + test/dm/panel.c | 12 +- test/dm/test-fdt.c | 148 +++++- 89 files changed, 4488 insertions(+), 441 deletions(-) create mode 100644 doc/device-tree-bindings/arm/omap,ctrl.txt create mode 100644 doc/device-tree-bindings/arm/omap,prcm.txt create mode 100644 doc/device-tree-bindings/clock/clock-bindings.txt create mode 100644 doc/device-tree-bindings/clock/gpio-gate-clock.txt create mode 100644 doc/device-tree-bindings/clock/ti,autoidle.txt create mode 100644 doc/device-tree-bindings/clock/ti,clkctrl.txt create mode 100644 doc/device-tree-bindings/clock/ti,clockdomain.txt create mode 100644 doc/device-tree-bindings/clock/ti,divider.txt create mode 100644 doc/device-tree-bindings/clock/ti,dpll.txt create mode 100644 doc/device-tree-bindings/clock/ti,gate.txt create mode 100644 doc/device-tree-bindings/clock/ti,mux.txt create mode 100644 doc/device-tree-bindings/pinctrl/pinctrl-single.txt create mode 100644 doc/device-tree-bindings/pwm/ti,ehrpwm.txt create mode 100644 doc/device-tree-bindings/pwm/ti,pwmss.txt create mode 100644 drivers/clk/ti/Kconfig create mode 100644 drivers/clk/ti/Makefile create mode 100644 drivers/clk/ti/am3-prcm.c create mode 100644 drivers/clk/ti/clk-am3-dpll-x2.c create mode 100644 drivers/clk/ti/clk-am3-dpll.c create mode 100644 drivers/clk/ti/clk-ctrl.c create mode 100644 drivers/clk/ti/clk-divider.c create mode 100644 drivers/clk/ti/clk-gate.c create mode 100644 drivers/clk/ti/clk-mux.c rename drivers/clk/{clk-ti-sci.c => ti/clk-sci.c} (100%) create mode 100644 drivers/clk/ti/clk.c create mode 100644 drivers/clk/ti/clk.h create mode 100644 drivers/clk/ti/omap4-cm.c create mode 100644 drivers/misc/ti-am3-scm.c create mode 100644 drivers/pwm/pwm-ti-ehrpwm.c create mode 100644 drivers/pwm/pwm-ti-pwmss.c create mode 100644 drivers/video/ti/Kconfig create mode 100644 drivers/video/ti/Makefile rename drivers/video/{ => ti}/am335x-fb.c (54%) rename drivers/video/{ => ti}/am335x-fb.h (97%) create mode 100644 drivers/video/ti/tilcdc-panel.c create mode 100644 drivers/video/ti/tilcdc-panel.h create mode 100644 drivers/video/ti/tilcdc.c create mode 100644 drivers/video/ti/tilcdc.h -- 2.17.1

3 11

Function xhci_bulk_tx( ) failed to handle double transfer EVENT TRB case in one call
by Ran Wang 18 Sep '20

18 Sep '20

Hello, On platform LS1028ARDB, we observed USB3.0/2.0 dongle failed to do tftp data transfer and caused system reset, I have some analysis below but still your input for help: =>usb reset&&setenv ethact r8152_eth&&tftp a0000000 test_data resetting USB... Bus usb3@3100000: Register 200017f NbrPorts 2 Starting the controller USB XHCI 1.00 Bus usb3@3110000: Register 200017f NbrPorts 2 Starting the controller USB XHCI 1.00 scanning bus usb3@3100000 for devices... Warning: r8152_eth MAC addresses don't match: Address in ROM is d4:6e:0e:0c:8d:14 Address in environment is 00:0e:c6:c9:5e:0f 2 USB Device(s) found scanning bus usb3@3110000 for devices... 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found Waiting for Ethernet connection... done. Using r8152_eth device TFTP from server 10.192.208.233; our IP address is 10.193.21.125 Filename 'test_data'. Load address: 0xa0000000 Loading: BUG at drivers/usb/host/xhci-ring.c:726/xhci_bulk_tx()! BUG! ### ERROR ### Please RESET the board ### Further debugging shows that is due to xhci_blk_tx() miss handling 2nd event TRB in one call, causing in next call (for different EP), it got that missed event TRB and found ep_index mismatched, then hold system. A typical scenario is shown as below (with my debug prints added): dev=00000000fbb4f3c0, pipe=c0010283, buffer=00000000fbb4fd80, length=2048----------------------------buffer would cross 64KB boundary, so we will send request in more than 1 TRB, this is the key issue trigger condition xhci_bulk_tx()#0.1.running_total:0x280 xhci_bulk_tx()#0.2.trb_buff_len:0x280 xhci_bulk_tx()#0.3.running_total:0x280 xhci_bulk_tx()#0.4.num_trbs:0x2--------------------------2 Transfer TRB xhci_bulk_tx()#0.5.running_total:0x10280 xhci_bulk_tx()#0.start_trb:0x00000000fbb47140 ----------xhci_bulk_tx()#0.&ring->enqueue->generic:0x00000000fbb47140----------Assemble 1st Transfer TRB xhci_bulk_tx()#0.addr:0xfbb4fd80 xhci_bulk_tx()#0.trb_buff_len:0x280 xhci_bulk_tx()#0.running_total:0x280 xhci_bulk_tx()#0.length:0x800 xhci_bulk_tx()#0.TRB_MAX_BUFF_SIZE:0x10000 ----------xhci_bulk_tx()#0.&ring->enqueue->generic:0x00000000fbb47150----------Assemble 2nd Transfer TRB xhci_bulk_tx()#0.addr:0xfbb50000 xhci_bulk_tx()#0.trb_buff_len:0x580 xhci_bulk_tx()#0.running_total:0x800 xhci_bulk_tx()#0.length:0x800 xhci_bulk_tx()#0.TRB_MAX_BUFF_SIZE:0x10000 xhci_bulk_tx()#0.event->trans_event.buffer:0x00000000fbb47140----------------handle event TRB for 1st Transfer TRB xhci_bulk_tx()#0.event->trans_event.transfer_len:0xd000180 xhci_bulk_tx()#0.event->trans_event.flags:0x1058001 xhci_bulk_tx()#0.event->len:384 xhci_bulk_tx()#0.event->complete_code:13 xhci_bulk_tx()#1.field:0x1058001 xhci_bulk_tx()#2.TRB_TO_EP_ENDEX(field):0x4 xhci_bulk_tx()#3.ep_index:0x4----------------------------------------------------------xhci_bulk_tx() return dev=00000000fbb4f3c0, pipe=c0018203, buffer=00000000fbb2f9c0, length=110----------an other call comming, and for different EP (ep_index = 05) xhci_bulk_tx()#0.1.running_total:0x640 xhci_bulk_tx()#0.2.trb_buff_len:0x640 xhci_bulk_tx()#0.3.running_total:0x640 xhci_bulk_tx()#0.4.num_trbs:0x1 xhci_bulk_tx()#0.5.running_total:0x640 xhci_bulk_tx()#0.start_trb:0x00000000fbb47610 ----------xhci_bulk_tx()#0.&ring->enqueue->generic:0x00000000fbb47610---------queue 1st transfer TRB xhci_bulk_tx()#0.addr:0xfbb2f9c0 xhci_bulk_tx()#0.trb_buff_len:0x6e xhci_bulk_tx()#0.running_total:0x6e xhci_bulk_tx()#0.length:0x6e xhci_bulk_tx()#0.TRB_MAX_BUFF_SIZE:0x10000 xhci_bulk_tx()#0.event->trans_event.buffer:0x00000000fbb47150------------hand event TRB, note that this buffer is for last Transfer TRB in last call (see above '2nd Transfer TRB') xhci_bulk_tx()#0.event->trans_event.transfer_len:0x1000000 xhci_bulk_tx()#0.event->trans_event.flags:0x1058000 xhci_bulk_tx()#0.event->len:0 xhci_bulk_tx()#0.event->complete_code:1 xhci_bulk_tx()#1.field:0x1058000 xhci_bulk_tx()#2.TRB_TO_EP_ENDEX(field):0x4----------------ep_index is 4 rather than 5, then cause BUG() xhci_bulk_tx()#3.ep_index:0x5------------------------------------- ep_index mis-match wait for event again!!!!!!!!!---------------------------------- BUG at drivers/usb/host/xhci-ring.c:759/xhci_bulk_tx()! BUG! ### ERROR ### Please RESET the board ### Basing on above analysis, I ever tried to remove below code from this function, issue disappear, which prove my assumption: diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c index 092ed6e..28197ef 100644 --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c @@ -591,14 +591,7 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe, ep_ctx = xhci_get_ep_ctx(ctrl, virt_dev->out_ctx, ep_index); ring = virt_dev->eps[ep_index].ring; - /* - * How much data is (potentially) left before the 64KB boundary? - * XHCI Spec puts restriction( TABLE 49 and 6.4.1 section of XHCI Spec) - * that the buffer should not span 64KB boundary. if so - * we send request in more than 1 TRB by chaining them. - */ - running_total = TRB_MAX_BUFF_SIZE - - (lower_32_bits(val_64) & (TRB_MAX_BUFF_SIZE - 1)); + running_total = length; trb_buff_len = running_total; running_total &= TRB_MAX_BUFF_SIZE - 1; Besides that, I also ever tried to let xhci_bulk_tx() repeatedly handle multiple EVENT TRB in one call. However, things works for several rounds but end up with event TRB Ring hang finally, reason unknow. - Log: dev=00000000fbb4f3c0, pipe=c0010283, buffer=00000000fbb4fd80, length=2048 xhci_bulk_tx()#0.1.running_total:0x280 xhci_bulk_tx()#0.2.trb_buff_len:0x280 xhci_bulk_tx()#0.3.running_total:0x280 xhci_bulk_tx()#0.4.num_trbs:0x2 xhci_bulk_tx()#0.5.running_total:0x10280 xhci_bulk_tx()#0.start_trb:0x00000000fbb47160 ----------xhci_bulk_tx()#0.&ring->enqueue->generic:0x00000000fbb47160---------------1st Transfer TRB ----------xhci_bulk_tx()#0.&ring->enqueue->generic:0x00000000fbb47170-------------2nd TransferTRB xhci_bulk_tx()#0.num_trbs_count:2 num_trbs_count > 1!!!!!!!!!--------------------------------------Here I add code to handle another event TRB xhci_bulk_tx()#0.num_trbs_count:1 xhci_bulk_tx()#0.event->trans_event.buffer:0x00000000fbb47170----------------------Now we got the final event TRB xhci_bulk_tx()#0.event->trans_event.transfer_len:0x1000000 xhci_bulk_tx()#0.event->trans_event.flags:0x1058000 xhci_bulk_tx()#0.event->len:0 xhci_bulk_tx()#0.event->complete_code:1 xhci_bulk_tx()#1.field:0x1058000 xhci_bulk_tx()#2.TRB_TO_EP_ENDEX(field):0x4 xhci_bulk_tx()#3.ep_index:0x4 xhci_bulk_tx()#4.ret:0-------------------------------------Return success ...----------------------------------------------------------------This success can last for several round call for the same EP dev=00000000fbb4f3c0, pipe=c0010283, buffer=00000000fbb4fd80, length=2048--------------The last call when event Ring hang xhci_bulk_tx()#0.1.running_total:0x280 xhci_bulk_tx()#0.2.trb_buff_len:0x280 xhci_bulk_tx()#0.3.running_total:0x280 xhci_bulk_tx()#0.4.num_trbs:0x2 xhci_bulk_tx()#0.5.running_total:0x10280 xhci_bulk_tx()#0.start_trb:0x00000000fbb47180 ----------xhci_bulk_tx()#0.&ring->enqueue->generic:0x00000000fbb47180 xhci_bulk_tx()#0.addr:0xfbb4fd80 xhci_bulk_tx()#0.trb_buff_len:0x280 xhci_bulk_tx()#0.running_total:0x280 xhci_bulk_tx()#0.length:0x800 xhci_bulk_tx()#0.TRB_MAX_BUFF_SIZE:0x10000 ----------xhci_bulk_tx()#0.&ring->enqueue->generic:0x00000000fbb47190 xhci_bulk_tx()#0.addr:0xfbb50000 xhci_bulk_tx()#0.trb_buff_len:0x580 xhci_bulk_tx()#0.running_total:0x800 xhci_bulk_tx()#0.length:0x800 xhci_bulk_tx()#0.TRB_MAX_BUFF_SIZE:0x10000 xhci_bulk_tx()#0.num_trbs_count:2 num_trbs_count > 1!!!!!!!!! XHCI bulk transfer timed out, aborting.................................. Rx: failed to receive: -5 T - Related hacking: diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c index 092ed6e..0b4da26 100644 --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c @@ -558,6 +558,7 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe, int length, void *buffer) { int num_trbs = 0; + int num_trbs_count = 0; struct xhci_generic_trb *start_trb; bool first_trb = false; int start_cycle; @@ -614,6 +615,7 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe, num_trbs++; running_total += TRB_MAX_BUFF_SIZE; } + num_trbs_count = num_trbs; /* * XXX: Calling routine prepare_ring() called in place of @@ -713,7 +715,7 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe, } while (running_total < length); giveback_first_trb(udev, ep_index, start_cycle, start_trb); - +again: event = xhci_wait_for_event(ctrl, TRB_TRANSFER); if (!event) { debug("XHCI bulk transfer timed out, aborting...\n"); @@ -722,6 +724,12 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe, udev->act_len = 0; return -ETIMEDOUT; } + if(num_trbs_count-- > 1) { + printf("num_trbs_count > 1!!!!!!!!!\n"); + xhci_acknowledge_event(ctrl); + goto again; + } + field = le32_to_cpu(event->trans_event.flags); BUG_ON(TRB_TO_SLOT_ID(field) != slot_id); So, any comment? Thanks in advance. Regards, Ran

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[PATCH v2 1/3] armv8: gpio: add gpio feature
by Hui Song 18 Sep '20

18 Sep '20

From: "hui.song" <hui.song_1(a)nxp.com> add one struct mpc8xxx_gpio_plat to enable gpio feature. Signed-off-by: hui.song <hui.song_1(a)nxp.com> --- .../include/asm/arch-fsl-layerscape/gpio.h | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/gpio.h diff --git a/arch/arm/include/asm/arch-fsl-layerscape/gpio.h b/arch/arm/include/asm/arch-fsl-layerscape/gpio.h new file mode 100644 index 0000000000..7ae5eee8b6 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/gpio.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + */ + +/* + * Dummy header file to enable CONFIG_OF_CONTROL. + * If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled. + * It includes <asm/arch/gpio.h> via <asm/gpio.h>, so those SoCs that enable + * OF_CONTROL must have arch/gpio.h. + */ + +#ifndef __ASM_ARCH_MX85XX_GPIO_H +#define __ASM_ARCH_MX85XX_GPIO_H + +struct mpc8xxx_gpio_plat { + ulong addr; + ulong size; + uint ngpios; +}; + +#endif -- 2.17.1

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[PATCH] armv8: dts: fsl-lx2160a: add gpio0 gpio1 gpio3 DT nodes
by Hui Song 18 Sep '20

18 Sep '20

From: "hui.song" <hui.song_1(a)nxp.com> add gpio0 gpio1 gpio3 DT nodes to fsl-lx21600.dtsi Signed-off-by: hui.song <hui.song_1(a)nxp.com> --- arch/arm/dts/fsl-lx2160a.dtsi | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi index dee1e2f215..05ddb5789b 100644 --- a/arch/arm/dts/fsl-lx2160a.dtsi +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -193,6 +193,28 @@ num-cs = <6>; }; + gpio0: gpio@2300000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = <0 36 4>; + gpio-controller; + little-endian; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@2310000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x0 0x2310000 0x0 0x10000>; + interrupts = <0 36 4>; + gpio-controller; + little-endian; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gpio2: gpio@2320000 { compatible = "fsl,qoriq-gpio"; reg = <0x0 0x2320000 0x0 0x10000>; @@ -204,6 +226,17 @@ #interrupt-cells = <2>; }; + gpio3: gpio@2330000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x0 0x2330000 0x0 0x10000>; + interrupts = <0 37 4>; + gpio-controller; + little-endian; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + watchdog@23a0000 { compatible = "arm,sbsa-gwdt"; reg = <0x0 0x23a0000 0 0x1000>, -- 2.17.1

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