August 2020 - U-Boot

[PATCH v1] sysreset: socfpga: agilex: Enable sysreset support
by Chee Hong Ang 05 Aug '20

05 Aug '20

Enable sysreset support for Agilex platform. Signed-off-by: Chee Hong Ang <chee.hong.ang(a)intel.com> --- arch/arm/Kconfig | 2 +- drivers/sysreset/Kconfig | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 6b8a32c38d..105b5f08a9 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -991,7 +991,7 @@ config ARCH_SOCFPGA select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select SYSRESET select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 - select SYSRESET_SOCFPGA_S10 if TARGET_SOCFPGA_STRATIX10 + select SYSRESET_SOCFPGA_S10 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX imply CMD_DM imply CMD_MTDPARTS imply CRC32_VERIFY diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index 6ebc90e1d3..d886d1c933 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -80,11 +80,11 @@ config SYSRESET_SOCFPGA (Cyclone 5, Arria 5 and Arria 10). config SYSRESET_SOCFPGA_S10 - bool "Enable support for Intel SOCFPGA Stratix 10" - depends on ARCH_SOCFPGA && TARGET_SOCFPGA_STRATIX10 + bool "Enable support for Intel SOCFPGA SoC64 family (Stratix10/Agilex)" + depends on ARCH_SOCFPGA && (TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX) help This enables the system reset driver support for Intel SOCFPGA - Stratix SoCs. + SoC64 SoCs. config SYSRESET_TI_SCI bool "TI System Control Interface (TI SCI) system reset driver" -- 2.19.0

3 3

[PATCH] ddr: socfpga: Fix integer overflow that caused DDR size mismatched
by tien.fong.chee＠intel.com 05 Aug '20

05 Aug '20

From: Tien Fong Chee <tien.fong.chee(a)intel.com> Convert the constant integer to 'phys_size_t' to avoid overflow when calculating the SDRAM size. Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> --- drivers/ddr/altera/sdram_soc64.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c index 8cb75fe02a..a862ac8092 100644 --- a/drivers/ddr/altera/sdram_soc64.c +++ b/drivers/ddr/altera/sdram_soc64.c @@ -218,13 +218,14 @@ phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat) { u32 dramaddrw = hmc_readl(plat, DRAMADDRW); - phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) + - DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) + - DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) + - DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) + - DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw)); - - size *= (2 << (hmc_ecc_readl(plat, DDRIOCTRL) & + phys_size_t size = (phys_size_t)1 << + (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) + + DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) + + DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) + + DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) + + DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw)); + + size *= ((phys_size_t)2 << (hmc_ecc_readl(plat, DDRIOCTRL) & DDR_HMC_DDRIOCTRL_IOSIZE_MSK)); return size; -- 2.13.0

2 1

[PATCH v2 0/4] usb: xhci: Prepare xHCI driver for MIPS Octeon big-endian support
by Stefan Roese 05 Aug '20

05 Aug '20

These patches fix a few issues, found while porting the xHCI to the MIPS Octeon platforms. The basic issues here are: - Endianess issues: missing cpu_to_leXX() & leXX_to_cpu() conversions - Use physical (DMA) address for the xHCI DMA controller These patches are the groundwork for the upcoming xHCI Octeon support that will follow soon. Thanks, Stefan Changes in v2: - Add missing (uintptr_t) cast to remove compile time warning Stefan Roese (4): usb: xhci: Add missing endian conversions (cpu_to_leXX / leXX_to_cpu) usb: xhci: xhci_mem_init: Use cpu_to_le64() and not xhci_writeq() usb: usb-uclass.c: Drop le16_to_cpu() as values are already swapped usb: xhci: Add virt_to_phys() to support mapped platforms drivers/usb/host/usb-uclass.c | 8 ++++---- drivers/usb/host/xhci-mem.c | 30 +++++++++++++++--------------- drivers/usb/host/xhci-ring.c | 8 ++++---- drivers/usb/host/xhci.c | 3 +-- 4 files changed, 24 insertions(+), 25 deletions(-) -- 2.27.0

3 8

[PATCH 1/1] riscv: fix building with CONFIG_SPL_SMP=n
by Heinrich Schuchardt 05 Aug '20

05 Aug '20

Building with CONFIG_SPL_SMP=n results in: arch/riscv/lib/spl.c: In function ‘jump_to_image_no_args’: arch/riscv/lib/spl.c:33:6: error: unused variable ‘ret’ [-Werror=unused-variable] 33 | int ret; | ^~~ Define the variable ret as __maybe_unused. Fixes: 191636e44898 ("riscv: Introduce SPL_SMP Kconfig option for U-Boot SPL") Fixes: 8c59f2023cc8 ("riscv: add SPL support") Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- arch/riscv/lib/spl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/lib/spl.c b/arch/riscv/lib/spl.c index c47dcd46ce..ef00ec2bcc 100644 --- a/arch/riscv/lib/spl.c +++ b/arch/riscv/lib/spl.c @@ -30,7 +30,7 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) { typedef void __noreturn (*image_entry_riscv_t)(ulong hart, void *dtb); void *fdt_blob; - int ret; + __maybe_unused int ret; #if CONFIG_IS_ENABLED(LOAD_FIT) || CONFIG_IS_ENABLED(LOAD_FIT_FULL) fdt_blob = spl_image->fdt_addr; -- 2.27.0

4 7

[PATCH v3] fsl-layerscape: enable dwc3 snooping feature
by Ran Wang 05 Aug '20

05 Aug '20

Configure DWC3’s cache type to ‘cacheable’ for better performance. Actually related register definition and values are SoC specific, which means this setting is only applicable to Layerscape SoC, not generic for all platforms which have integrated DWC3 IP. Signed-off-by: Ran Wang <ran.wang_1(a)nxp.com> --- Change in v3: - Add 'if (IS_ENABLED(CONFIG_DM))' to fix compile issue (ls2080a_simu_defconfig) Change in v2: - Move enable_dwc3_snooping() implementation to fix compile issue for ls1043a. arch/arm/cpu/armv8/fsl-layerscape/soc.c | 37 +++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index fde893e..5254cdf 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -36,6 +36,8 @@ #ifdef CONFIG_TFABOOT #include <env_internal.h> #endif +#include <dm.h> +#include <linux/err.h> #if defined(CONFIG_TFABOOT) || defined(CONFIG_GIC_V3_ITS) DECLARE_GLOBAL_DATA_PTR; #endif @@ -897,6 +899,38 @@ __weak int fsl_board_late_init(void) return 0; } +#define DWC3_GSBUSCFG0 0xc100 +#define DWC3_GSBUSCFG0_CACHETYPE_SHIFT 16 +#define DWC3_GSBUSCFG0_CACHETYPE(n) (((n) & 0xffff) \ + << DWC3_GSBUSCFG0_CACHETYPE_SHIFT) + +void enable_dwc3_snooping(void) +{ + int ret; + u32 val; + struct udevice *bus; + struct uclass *uc; + fdt_addr_t dwc3_base; + + ret = uclass_get(UCLASS_USB, &uc); + if (ret) + return; + + uclass_foreach_dev(bus, uc) { + if (!strcmp(bus->driver->of_match->compatible, "fsl,layerscape-dwc3")) { + dwc3_base = devfdt_get_addr(bus); + if (dwc3_base == FDT_ADDR_T_NONE) { + dev_err(bus, "dwc3 regs missing\n"); + continue; + } + val = in_le32(dwc3_base + DWC3_GSBUSCFG0); + val &= ~DWC3_GSBUSCFG0_CACHETYPE(~0); + val |= DWC3_GSBUSCFG0_CACHETYPE(0x2222); + writel(val, dwc3_base + DWC3_GSBUSCFG0); + } + } +} + int board_late_init(void) { #ifdef CONFIG_CHAIN_OF_TRUST @@ -934,6 +968,9 @@ int board_late_init(void) fspi_ahb_init(); #endif + if (IS_ENABLED(CONFIG_DM)) + enable_dwc3_snooping(); + return fsl_board_late_init(); } #endif -- 2.7.4

1 0

[GIT PULL] Pull request: u-boot-imx u-boot-imx-20200804
by Stefano Babic 04 Aug '20

04 Aug '20

Hi Tom, please pull from u-boot-imx, thanks ! The following changes since commit ada61f1ee2a4eaa1b29d699b5ba940483171df8a: Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv (2020-07-24 08:43:08 -0400) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git tags/u-boot-imx-20200804 for you to fetch changes up to 3e980a2d8bd13d0d1c2d5cec9e57a47b6cff8b92: configs: pico-imx6: convert ethernet function to DM_ETH (2020-08-03 17:03:57 +0200) ---------------------------------------------------------------- For 2020.10 ----------- - fixes for Toradex board - fix warnings from previous PR - HAB: reset instead of panic after failure - new board: MYiR Tech MYS-6ULX - mx6cuboxi: use OF_PLATDATA - further changes for DM Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/714513163 ---------------------------------------------------------------- Dan Murphy (1): dm: Fix build error when OF_CONTROL is not set Fabio Estevam (2): imx8m: ddrphy_utils: Improve coding style imx8m: soc: Remove unneeded space Igor Opaniuk (14): imx: mx7: fix DDRC size in A7-M4 mapping table toradex: tdx-cfg-block: add EEPROM read/store wrappers toradex: tdx-cfg-block: add carrier boards and display adapters toradex: tdx-cfg-block: add support for EEPROM toradex: tdx-cfg-clock: add migration routine from PID8 toradex: tdx-cfg-block: add carrier board info printing ARM: dts: imx8mm-verdin: eeprom nodes adjustments verdin-imx8mm: add EEPROM support for carrier board ARM: dts: imx6ull-colibri: move u-boot specific node toradex: common: show boot logo ARM: dts: imx7-colibri: multiple node updates colibri-imx6ull: show boot logo colibri-imx6ull: fix splash screen logo drawing colibri-imx7: fix splash logo drawing Marek Vasut (1): ARM: imx: hab: panic on authentication failure Niel Fourie (1): arm: imx6q: pcm058: Rework SPI NOR configuration Parthiban Nallathambi (1): imx: Add MYiR Tech MYS-6ULX support Peng Fan (1): imx8m: enlarge CONFIG_SYS_BOOTM_LEN Walter Lozano (6): mmc: fsl_esdhc_imx: rename driver name to match ll_entry mmc: fsl_esdhc_imx: add OF_PLATDATA support gpio: mxc_gpio: add OF_PLATDATA support mmc: fsl_esdhc_imx: add CD support when OF_PLATDATA is enabled drivers: rename more drivers to match compatible string mx6cuboxi: enable OF_PLATDATA Wig Cheng (1): configs: pico-imx6: convert ethernet function to DM_ETH arch/arm/Kconfig | 1 + arch/arm/dts/Makefile | 1 + arch/arm/dts/imx6ull-colibri-u-boot.dtsi | 45 +++++++++++++++++++++++++++++++++++++ arch/arm/dts/imx6ull-colibri.dtsi | 43 ----------------------------------- arch/arm/dts/imx6ull-myir-mys-6ulx-eval.dts | 19 ++++++++++++++++ arch/arm/dts/imx6ull-myir-mys-6ulx.dtsi | 238 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/imx6ull-mys-6ulx-u-boot.dtsi | 24 ++++++++++++++++++++ arch/arm/dts/imx7-colibri-emmc.dts | 2 +- arch/arm/dts/imx7-colibri-rawnand.dts | 10 +++++---- arch/arm/dts/imx7-colibri-u-boot.dtsi | 39 ++++++++++++++++++++++++++++++++ arch/arm/dts/imx7-colibri.dtsi | 65 ++++++++++++++++++++++++++--------------------------- arch/arm/dts/imx8mm-verdin.dts | 22 +++++++++++------- arch/arm/mach-imx/imx8m/soc.c | 2 +- arch/arm/mach-imx/mx6/Kconfig | 12 ++++++++++ arch/arm/mach-imx/mx7/soc.c | 2 +- arch/arm/mach-imx/spl.c | 6 ++--- board/myir/mys_6ulx/Kconfig | 12 ++++++++++ board/myir/mys_6ulx/MAINTAINERS | 9 ++++++++ board/myir/mys_6ulx/Makefile | 4 ++++ board/myir/mys_6ulx/README | 52 ++++++++++++++++++++++++++++++++++++++++++ board/myir/mys_6ulx/mys_6ulx.c | 117 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ board/myir/mys_6ulx/spl.c | 206 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ board/phytec/pcm058/README | 20 ++++++++++------- board/toradex/colibri-imx6ull/colibri-imx6ull.c | 40 ++++++--------------------------- board/toradex/colibri_imx7/MAINTAINERS | 1 + board/toradex/colibri_imx7/colibri_imx7.c | 44 ++++++++++-------------------------- board/toradex/common/Kconfig | 18 +++++++++++++++ board/toradex/common/Makefile | 1 + board/toradex/common/tdx-cfg-block.c | 402 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------------------------------- board/toradex/common/tdx-cfg-block.h | 16 +++++++++++++ board/toradex/common/tdx-common.c | 54 ++++++++++++++++++++++++++++++++++++++++++++ board/toradex/common/tdx-common.h | 4 ++++ board/toradex/common/tdx-eeprom.c | 90 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ board/toradex/common/tdx-eeprom.h | 14 ++++++++++++ board/toradex/verdin-imx8mm/Kconfig | 6 +++++ configs/colibri-imx6ull_defconfig | 1 + configs/colibri_imx7_defconfig | 2 ++ configs/colibri_imx7_emmc_defconfig | 2 ++ configs/mx6cuboxi_defconfig | 1 + configs/myir_mys_6ulx_defconfig | 69 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ configs/pcm058_defconfig | 3 ++- configs/pico-imx6_defconfig | 3 +++ configs/verdin-imx8mm_defconfig | 1 + drivers/ddr/imx/imx8m/ddrphy_utils.c | 29 ++++++++++++------------ drivers/gpio/mxc_gpio.c | 27 +++++++++++++++++----- drivers/mmc/fsl_esdhc_imx.c | 92 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++------------- drivers/pinctrl/nxp/pinctrl-imx6.c | 6 +++-- drivers/video/imx/mxc_ipuv3_fb.c | 4 ++-- include/configs/imx8mn_evk.h | 2 ++ include/configs/imx8mp_evk.h | 2 ++ include/configs/imx8mq_evk.h | 2 ++ include/configs/mys_6ulx.h | 76 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ include/dm/read.h | 2 ++ 53 files changed, 1718 insertions(+), 247 deletions(-) create mode 100644 arch/arm/dts/imx6ull-myir-mys-6ulx-eval.dts create mode 100644 arch/arm/dts/imx6ull-myir-mys-6ulx.dtsi create mode 100644 arch/arm/dts/imx6ull-mys-6ulx-u-boot.dtsi create mode 100644 arch/arm/dts/imx7-colibri-u-boot.dtsi create mode 100644 board/myir/mys_6ulx/Kconfig create mode 100644 board/myir/mys_6ulx/MAINTAINERS create mode 100644 board/myir/mys_6ulx/Makefile create mode 100644 board/myir/mys_6ulx/README create mode 100644 board/myir/mys_6ulx/mys_6ulx.c create mode 100644 board/myir/mys_6ulx/spl.c create mode 100644 board/toradex/common/tdx-eeprom.c create mode 100644 board/toradex/common/tdx-eeprom.h create mode 100644 configs/myir_mys_6ulx_defconfig create mode 100644 include/configs/mys_6ulx.h Best regards, Stefano -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic(a)denx.de =====================================================================

2 1

Please pull u-boot-video
by Anatolij Gustschin 04 Aug '20

04 Aug '20

Hi Tom, please pull a few video related fixes. Gitlab CI: https://gitlab.denx.de/u-boot/custodians/u-boot-video/pipelines/4318 Thanks! The following changes since commit 68941e3b2c217907a49aa66af8bb65729b913397: Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86 (2020-08-03 10:25:47 -0400) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-video.git tags/fixes-for-2020.10-rc1 for you to fetch changes up to 3ce83ee0125fdf2908c39970335121909e98b750: video: ipuv3: fix framebuffer base address init with multiple IPUs (2020-08-03 23:37:31 +0200) ---------------------------------------------------------------- - fix tbs2910 vidconsole environment - fix ipuv3 framebuffer output on i.MX6Q/D ---------------------------------------------------------------- Anatolij Gustschin (1): video: ipuv3: fix framebuffer base address init with multiple IPUs Soeren Moch (1): board: tbs2910: Fix video output with existing environments configs/tbs2910_defconfig | 1 + drivers/video/imx/mxc_ipuv3_fb.c | 13 +++++++++---- 2 files changed, 10 insertions(+), 4 deletions(-) -- Anatolij

2 1

[U-Boot] Pull request: u-boot-riscv/master 20200804
by uboot＠andestech.com 04 Aug '20

04 Aug '20

Hi Tom, Please pull some riscv updates: - add DM based reset driver for SiFive SoC's. Thanks Rick https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/714339244 The following changes since commit 68941e3b2c217907a49aa66af8bb65729b913397: Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86 (2020-08-03 10:25:47 -0400) are available in the Git repository at: git@gitlab.denx.de:u-boot/custodians/u-boot-riscv.git for you to fetch changes up to ed50d3fae49b9dad58674b6609913beeac824e42: configs: reset: fu540: enable dm reset framework for SiFive (2020-08-04 09:19:41 +0800) ---------------------------------------------------------------- Sagar Shrikant Kadam (5): dt-bindings: prci: add indexes for reset signals available in prci fu540: prci: use common reset indexes defined in binding header fu540: dtsi: add reset producer and consumer entries sifive: reset: add DM based reset driver for SiFive SoC's configs: reset: fu540: enable dm reset framework for SiFive arch/riscv/dts/fu540-c000-u-boot.dtsi | 12 ++++++++++++ arch/riscv/include/asm/arch-fu540/reset.h | 13 +++++++++++++ configs/sifive_fu540_defconfig | 2 ++ drivers/clk/sifive/fu540-prci.c | 90 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++------------------------- drivers/reset/Kconfig | 9 +++++++++ drivers/reset/Makefile | 1 + drivers/reset/reset-sifive.c | 118 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ include/dt-bindings/reset/sifive-fu540-prci.h | 19 +++++++++++++++++++ 8 files changed, 239 insertions(+), 25 deletions(-) create mode 100644 arch/riscv/include/asm/arch-fu540/reset.h create mode 100644 drivers/reset/reset-sifive.c create mode 100644 include/dt-bindings/reset/sifive-fu540-prci.h

2 1

[PULL] u-boot-mips
by Daniel Schwierzeck 04 Aug '20

04 Aug '20

Hi Tom, please pull some Octeon MIPS64 updates for 2020.10. This contains just new GPIO, CLK ad SPI drivers for Octeon as well as the according DT and defconfig updates. Gitlab CI: https://gitlab.denx.de/u-boot/custodians/u-boot-mips/pipelines/4316 The following changes since commit 68941e3b2c217907a49aa66af8bb65729b913397: Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86 (2020-08-03 10:25:47 -0400) are available in the Git repository at: git@gitlab.denx.de:u-boot/custodians/u-boot-mips.git tags/mips-pull-2020-08-03 for you to fetch changes up to d071ff012e0b3f9e77b54340c96f624d6f115782: mips: octeon: Update EBB7304 defconfig (2020-08-03 21:14:49 +0200) ---------------------------------------------------------------- - doc: fix qemu-mips build instructions - MIPS: add GPIO, CLK and SPI drivers for Octeon MIPS64 ---------------------------------------------------------------- Heinrich Schuchardt (1): doc: qemu-mips build instructions Stefan Roese (8): mips: octeon: mrvl,cn73xx.dtsi: Add GPIO DT nodes mips: octeon: dts: Add I2C DT nodes clk: clk_octeon: Add simple MIPS Octeon clock driver mips: octeon: dts: Add Octeon clock driver DT nodes mips: octeon: mrvl,cn73xx.dtsi: Add SPI DT node mips: octeon: mrvl, octeon-ebb7304.dts: Add SPI flash DT node mips: octeon: Update Octeon Kconfig mips: octeon: Update EBB7304 defconfig Suneel Garapati (2): gpio: octeon_gpio: Add GPIO controller driver for Octeon drivers: spi: Add SPI controller driver for Octeon arch/mips/Kconfig | 6 +- arch/mips/dts/mrvl,cn73xx.dtsi | 66 ++++ arch/mips/dts/mrvl,octeon-ebb7304.dts | 21 +- configs/octeon_ebb7304_defconfig | 12 +- doc/board/emulation/qemu-mips.rst | 8 +- drivers/clk/Kconfig | 7 + drivers/clk/Makefile | 1 + drivers/clk/clk_octeon.c | 72 ++++ drivers/gpio/Kconfig | 10 + drivers/gpio/Makefile | 1 + drivers/gpio/octeon_gpio.c | 242 ++++++++++++ drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/octeon_spi.c | 613 +++++++++++++++++++++++++++++++ include/dt-bindings/clock/octeon-clock.h | 12 + 15 files changed, 1072 insertions(+), 8 deletions(-) create mode 100644 drivers/clk/clk_octeon.c create mode 100644 drivers/gpio/octeon_gpio.c create mode 100644 drivers/spi/octeon_spi.c create mode 100644 include/dt-bindings/clock/octeon-clock.h

2 1

Re: U-Boot POST Memory Test
by Brownlie, Lewis 04 Aug '20

04 Aug '20

Thank you for your helpful response Heinrich. I have a question to further clarify the purpose of post_bootmode_get(). You wrote, > post_bootmode_get() tells you which type of tests should be executed. > For tests after a watchdog reset it also returns the last executed test." This makes sense. So, looking at the following code in post_run (post/post.c): if (post_bootmode_get(&last) & POST_POWERTEST) { ..... if (last < post_list_size && (flags & test_flags[last] & POST_ALWAYS) && (flags & test_flags[last] & POST_MEM)) { .... last is initialized to 62 in the first line shown above; thus, the second if-branch shown is not entered because 62 is not less than post_list_size (which is 1). last returns the last executed test; however, I am confused because this is the first call of post_run(), so I don't know what the "last executed test" would be referring to. Thus, my question is, what "last executed test" is last (and its value of 62) representing in this case, and why is it preventing the code from entering the shown if-branch? Thank you again, -Lewis

1 0