August 2020 - U-Boot

[BUG] DM_VIDEO broken on imx6q
by Soeren Moch 03 Aug '20

03 Aug '20

Hi, unfortunately the patch [1] is only the first part to get DM_VIDEO running properly on tbs2910 for u-boot-2020.10. With this, I get a valid video output signal, but no actual video console output, only a blank screen. After some debugging, no with access to a HDMI monitor, the problem seems to be: imx6q has two ipu units, so DM_VIDEO creates 2 video devices. For these two devices also memory for two framebuffers is reserved in video-uclass, starting from gd->video_top downwards. Then vidconsole correctly uses the first video device (ipu1), but apparently the framebuffer from ipu2 at gd->video_bottom. So I see the empty framebuffer from ipu1 while the console output goes to the framebuffer memory of ipu2. I guess there is the same problem on all imx6q devices with 2 ipu units, while on imx6s/6dl devices with a single ipu everything works fine. Disabling the second ipu in the tbs2910 devicetree also helps, but I think this is not a proper solution. What should be done about this? Only probing the first ipu/video device? Assigning the framebuffer memory bottom-up? Using the assigned framebuffer memory of the active video device for console output (seems to be the correct solution, but maybe not so easy to implement)? Something else? Thanks, Soeren [1] https://patchwork.ozlabs.org/project/uboot/patch/20200730121157.5305-1-smoc…

2 2

[PATCH v2] board: Add support for iMX8QXP AI_ML board
by Manivannan Sadhasivam 03 Aug '20

03 Aug '20

This commit adds initial board support for iMX8QXP AI_ML board from Einfochips. This board is one of the 96Boards Consumer Edition and AI boards of the 96Boards family based on i.MX8QXP SoC from NXP/Freescale. This initial supports contains following peripherals which are tested and known to work: 1. Debug serial via UART2 2. SD card 3. Ethernet More information about this board can be found in arrow website: https://www.arrow.com/en/products/imx8-ai-ml/arrow-development-tools Reviewed-by: Peng Fan <peng.fan(a)nxp.com> Reviewed-by: Fabio Estevam <festevam(a)gmail.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam(a)linaro.org> --- Changes in v2: * Rebased onto u-boot/master and fixed one build issue * Added review from Fabio arch/arm/mach-imx/imx8/Kconfig | 6 ++ board/einfochips/imx8qxp_ai_ml/Kconfig | 21 ++++ board/einfochips/imx8qxp_ai_ml/MAINTAINERS | 6 ++ board/einfochips/imx8qxp_ai_ml/Makefile | 8 ++ board/einfochips/imx8qxp_ai_ml/README | 49 ++++++++++ .../einfochips/imx8qxp_ai_ml/imx8qxp_ai_ml.c | 78 +++++++++++++++ board/einfochips/imx8qxp_ai_ml/imximage.cfg | 24 +++++ board/einfochips/imx8qxp_ai_ml/spl.c | 39 ++++++++ configs/imx8qxp_ai_ml_defconfig | 83 ++++++++++++++++ include/configs/imx8qxp_ai_ml.h | 95 +++++++++++++++++++ 10 files changed, 409 insertions(+) create mode 100644 board/einfochips/imx8qxp_ai_ml/Kconfig create mode 100644 board/einfochips/imx8qxp_ai_ml/MAINTAINERS create mode 100644 board/einfochips/imx8qxp_ai_ml/Makefile create mode 100644 board/einfochips/imx8qxp_ai_ml/README create mode 100644 board/einfochips/imx8qxp_ai_ml/imx8qxp_ai_ml.c create mode 100644 board/einfochips/imx8qxp_ai_ml/imximage.cfg create mode 100644 board/einfochips/imx8qxp_ai_ml/spl.c create mode 100644 configs/imx8qxp_ai_ml_defconfig create mode 100644 include/configs/imx8qxp_ai_ml.h diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 9d1f73dfc7..308122d62a 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -75,6 +75,11 @@ config TARGET_GIEDI select BOARD_LATE_INIT select IMX8QXP +config TARGET_IMX8QXP_AI_ML + bool "Support i.MX8QXP AI_ML board" + select BOARD_EARLY_INIT_F + select IMX8QXP + config TARGET_IMX8QM_MEK bool "Support i.MX8QM MEK board" select BOARD_LATE_INIT @@ -93,6 +98,7 @@ config TARGET_IMX8QXP_MEK endchoice +source "board/einfochips/imx8qxp_ai_ml/Kconfig" source "board/freescale/imx8qm_mek/Kconfig" source "board/freescale/imx8qxp_mek/Kconfig" source "board/advantech/imx8qm_rom7720_a1/Kconfig" diff --git a/board/einfochips/imx8qxp_ai_ml/Kconfig b/board/einfochips/imx8qxp_ai_ml/Kconfig new file mode 100644 index 0000000000..b6806b8859 --- /dev/null +++ b/board/einfochips/imx8qxp_ai_ml/Kconfig @@ -0,0 +1,21 @@ +if TARGET_IMX8QXP_AI_ML + +config SYS_BOARD + default "imx8qxp_ai_ml" + +config SYS_VENDOR + default "einfochips" + +config SYS_CONFIG_NAME + default "imx8qxp_ai_ml" + +config SYS_MALLOC_LEN + default 0x2400000 + +config ENV_SIZE + default 0x1000 + +config ENV_OFFSET + default 0x400000 + +endif diff --git a/board/einfochips/imx8qxp_ai_ml/MAINTAINERS b/board/einfochips/imx8qxp_ai_ml/MAINTAINERS new file mode 100644 index 0000000000..add0bd9431 --- /dev/null +++ b/board/einfochips/imx8qxp_ai_ml/MAINTAINERS @@ -0,0 +1,6 @@ +i.MX8QXP AI_ML BOARD +M: Manivannan Sadhasivam <manivannan.sadhasivam(a)linaro.org> +S: Maintained +F: board/einfochips/imx8qxp_ai_ml/ +F: include/configs/imx8qxp_ai_ml.h +F: configs/imx8qxp_ai_ml_defconfig diff --git a/board/einfochips/imx8qxp_ai_ml/Makefile b/board/einfochips/imx8qxp_ai_ml/Makefile new file mode 100644 index 0000000000..e08774dc6e --- /dev/null +++ b/board/einfochips/imx8qxp_ai_ml/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2019 Linaro Ltd. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8qxp_ai_ml.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/einfochips/imx8qxp_ai_ml/README b/board/einfochips/imx8qxp_ai_ml/README new file mode 100644 index 0000000000..488920580f --- /dev/null +++ b/board/einfochips/imx8qxp_ai_ml/README @@ -0,0 +1,49 @@ +U-Boot for the Einfochips i.MX8QXP AI_ML board + +Quick Start +=========== + +- Get and Build the ARM Trusted firmware +- Get scfw_tcm.bin and ahab-container.img +- Build U-Boot +- Flash the binary into the SD card +- Boot + +Get and Build the ARM Trusted firmware +====================================== + +$ git clone https://source.codeaurora.org/external/imx/imx-atf +$ cd imx-atf/ +$ git checkout origin/imx_4.9.88_imx8qxp_beta2 -b imx_4.9.88_imx8qxp_beta2 +$ make PLAT=imx8qxp bl31 + +Get scfw_tcm.bin and ahab-container.img +======================================= + +$ wget https://raw.githubusercontent.com/96boards-ai-ml/binaries/master/mx8qx-aiml… +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.1.bin +$ chmod +x firmware-imx-8.1.bin +$ ./firmware-imx-8.1.bin + +Copy the following binaries to U-Boot folder: + +$ cp imx-atf/build/imx8qxp/release/bl31.bin . +$ cp firmware-imx-8.1/firmware/seco/mx8qx-ahab-container.img . + +Build U-Boot +============ + +$ make imx8qxp_ai_ml_defconfig +$ make u-boot-dtb.imx + +Flash the binary into the SD card +================================= + +Burn the u-boot-dtb.imx binary to SD card offset 32KB: + +$ sudo dd if=u-boot-dtb.imx of=/dev/sd[x] bs=1024 seek=32 + +Boot +==== + +Set Boot switch SW2: 1100. diff --git a/board/einfochips/imx8qxp_ai_ml/imx8qxp_ai_ml.c b/board/einfochips/imx8qxp_ai_ml/imx8qxp_ai_ml.c new file mode 100644 index 0000000000..7ba014ac07 --- /dev/null +++ b/board/einfochips/imx8qxp_ai_ml/imx8qxp_ai_ml.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Copyright 2019 Linaro Ltd. + */ + +#include <common.h> +#include <errno.h> +#include <linux/libfdt.h> +#include <fsl_esdhc.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/sci/sci.h> +#include <asm/arch/imx8-pins.h> +#include <asm/arch/iomux.h> +#include <asm/arch/sys_proto.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + sc_pm_clock_rate_t rate = SC_80MHZ; + int ret; + + /* Set UART2 clock root to 80 MHz */ + ret = sc_pm_setup_uart(SC_R_UART_2, rate); + if (ret) + return ret; + + return 0; +} + +#if IS_ENABLED(CONFIG_FEC_MXC) +#include <miiphy.h> + +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +int checkboard(void) +{ + puts("Board: iMX8QXP AI_ML\n"); + + build_info(); + print_bootinfo(); + + return 0; +} + +int board_init(void) +{ + return 0; +} + +/* Board specific reset that is system reset */ + +void reset_cpu(ulong addr) +{ + /* TODO */ +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return 0; +} +#endif diff --git a/board/einfochips/imx8qxp_ai_ml/imximage.cfg b/board/einfochips/imx8qxp_ai_ml/imximage.cfg new file mode 100644 index 0000000000..4fc5ade313 --- /dev/null +++ b/board/einfochips/imx8qxp_ai_ml/imximage.cfg @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + * + * Refer doc/README.imx8image for more details about how-to configure + * and create imx8image boot image + */ + +#define __ASSEMBLY__ + +/* Boot from SD, sector size 0x400 */ +BOOT_FROM SD 0x400 +/* SoC type IMX8QX */ +SOC_TYPE IMX8QX +/* Append seco container image */ +APPEND mx8qx-ahab-container.img +/* Create the 2nd container */ +CONTAINER +/* Add scfw image with exec attribute */ +IMAGE SCU mx8qx-aiml-scfw-tcm.bin +/* Add ATF image with exec attribute */ +IMAGE A35 bl31.bin 0x80000000 +/* Add U-Boot image with load attribute */ +DATA A35 u-boot-dtb.bin 0x80020000 diff --git a/board/einfochips/imx8qxp_ai_ml/spl.c b/board/einfochips/imx8qxp_ai_ml/spl.c new file mode 100644 index 0000000000..2e6e0741e5 --- /dev/null +++ b/board/einfochips/imx8qxp_ai_ml/spl.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Copyright 2019 Linaro Ltd. + * + */ + +#include <common.h> +#include <dm.h> +#include <spl.h> +#include <dm/uclass.h> +#include <dm/device.h> +#include <dm/uclass-internal.h> +#include <dm/device-internal.h> +#include <dm/lists.h> + +DECLARE_GLOBAL_DATA_PTR; + +void spl_board_init(void) +{ + arch_cpu_init(); + + timer_init(); + + preloader_console_init(); + + puts("Normal Boot\n"); +} + +void board_init_f(ulong dummy) +{ + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); +} diff --git a/configs/imx8qxp_ai_ml_defconfig b/configs/imx8qxp_ai_ml_defconfig new file mode 100644 index 0000000000..e20a0c783e --- /dev/null +++ b/configs/imx8qxp_ai_ml_defconfig @@ -0,0 +1,83 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_TARGET_IMX8QXP_AI_ML=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=4 +CONFIG_SPL=y +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/einfochips/imx8qxp_ai_ml/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_FAT_WRITE=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-ai_ml" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_DM_GPIO=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/imx8qxp_ai_ml.h b/include/configs/imx8qxp_ai_ml.h new file mode 100644 index 0000000000..bdac710103 --- /dev/null +++ b/include/configs/imx8qxp_ai_ml.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + * Copyright 2019 Linaro Ltd. + */ + +#ifndef __IMX8QXP_AI_ML_H +#define __IMX8QXP_AI_ML_H + +#include <linux/sizes.h> +#include <asm/arch/imx-regs.h> + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_MAX_SIZE (124 * SZ_1K) +#define CONFIG_SYS_MONITOR_LEN (SZ_1K * SZ_1K) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x250 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0 + +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x013E000 +#define CONFIG_SPL_BSS_START_ADDR 0x00128000 +#define CONFIG_SPL_BSS_MAX_SIZE SZ_4K /* 4 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x00120000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */ +#define CONFIG_SERIAL_LPUART_BASE 0x5a080000 +#define CONFIG_MALLOC_F_ADDR 0x00120000 + +#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#define CONFIG_OF_SEPARATE +#endif + +#define CONFIG_REMAKE_ELF + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_BOARD_SETUP + +#define CONFIG_FSL_USDHC + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(DHCP, dhcp, na) + +#include <config_distro_bootcmd.h> +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttyLP2 earlycon\0" \ + "fdt_addr_r=0x83000000\0" \ + "kernel_addr_r=0x81000000\0" \ + "ramdisk_addr_r=0x94400000\0" \ + "scriptaddr=0x89000000\0" \ + "fdtfile=imx8qxp-ai_ml.dtb\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "image=Image\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp" \ + "\0" \ + "nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \ + "imx8qxp-ai_ml/${fdt_file}; booti ${loadaddr} - ${fdt_addr}\0" \ + BOOTENV + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x80280000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + +/* USDHC2 is the SD card interface */ +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 +#define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */ + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +/* Networking */ +#define CONFIG_FEC_XCV_TYPE RGMII +#define FEC_QUIRK_ENET_MAC + +#endif /* __IMX8QXP_AI_ML_H */ -- 2.17.1

2 3

Pull request for UEFI sub-system for efi-2020-10-rc2
by Heinrich Schuchardt 03 Aug '20

03 Aug '20

Dear Tom, the following changes since commit a2d051e7b6a8f87add1067d936bb0c805a47b0df: Merge branch '2020-07-31-more-env-updates' (2020-07-31 10:13:07 -0400) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-efi.git tags/efi-2020-10-rc2 for you to fetch changes up to 5c2227e4956f3287165ef5aac55ee5e96a61a518: efi_selftest: block device test requires CONFIG_DOS_PARTITION (2020-08-01 11:58:39 +0200) No problems were reported by Gitlab CI and Travis CI: https://gitlab.denx.de/u-boot/custodians/u-boot-efi/pipelines/4281 https://travis-ci.org/github/xypron2/u-boot/builds/713953239 ---------------------------------------------------------------- Pull request for UEFI sub-system for efi-2020-10-rc2 This series comprises error corrections for the UEFI subsystem: * make the memory size reserved for the U-Boot stack customizable and reduce it for the MAIX board * correct build dependencies for UEFI unit test * enable read-only UEFI variable are enabled with the TEE backend * add 10 ms wait to sysreset to fix a problem with unit testing ---------------------------------------------------------------- Heinrich Schuchardt (6): x86: rename CONFIG_STACK_SIZE efi_loader: use CONFIG_STACK_SIZE in the UEFI sub-system configs: reduce stack size of Sipeed MAIX dm: sysreset: wait after reset message efi_selftest: SNP test depends on network efi_selftest: block device test requires CONFIG_DOS_PARTITION Ilias Apalodimas (2): efi_loader: Trim output buffer size correctly for tee variables efi_loader: Enable run-time variable support for tee based variables Kconfig | 10 ++++ arch/arm/Kconfig | 17 ------- arch/microblaze/Kconfig | 8 --- arch/x86/Kconfig | 2 +- arch/x86/lib/fsp/fsp_dram.c | 2 +- configs/sipeed_maix_bitm_defconfig | 1 + drivers/sysreset/sysreset-uclass.c | 1 + include/efi_variable.h | 74 +++++++++++++++++++++++++++ lib/efi_loader/Makefile | 2 +- lib/efi_loader/efi_memory.c | 2 +- lib/efi_loader/efi_var_common.c | 22 ++++++++ lib/efi_loader/efi_var_file.c | 25 +++------ lib/efi_loader/efi_var_mem.c | 70 ++++++++++++++++++++++++- lib/efi_loader/efi_variable.c | 101 +------------------------------------ lib/efi_loader/efi_variable_tee.c | 95 +++++++++++++++++----------------- lib/efi_selftest/Kconfig | 2 + lib/efi_selftest/Makefile | 5 +- 17 files changed, 245 insertions(+), 194 deletions(-)

2 1

[PATCH v5 0/6] ARM: arbitrary virtual-physical mappings for RPi4 XHCI support
by Marek Szyprowski 03 Aug '20

03 Aug '20

Hi All, This patchset adds support for creating a mapping for the arbitrary physical address at the given virtual address. This is needed to enable support for XHCI USB controller on PCIe bridge on Raspberry Pi 4 board, on which the USB controller's MMIO area 0x600000000 has to be remapped somewhere to fit in 4GiB virtual address space when running in ARM 32bit mode. This patchset is a continuation of the Raspberry Pi 4 XHCI/PCIe patchset: https://patchwork.ozlabs.org/project/uboot/list/?series=179078 and the following discussion: https://lists.denx.de/pipermail/u-boot/2020-May/411086.html Best regards Marek Szyprowski Samsung R&D Institute Poland Changelog: v5: - fixed issues pointed by Tom Rini (comments style, ifdefs, spdx) v4: https://lists.denx.de/pipermail/u-boot/2020-June/414531.html - added a patch, which moves ADDR_MAP config entry to Kconfig system as requested by Simon Glass - rebased onto v4 of the "USB host support for Raspberry Pi 4 board (64-bit)" patchset v3: https://lists.denx.de/pipermail/u-boot/2020-May/412427.html - fixed broken RPi3 and lack of the identity mapping for map_physmem (for example for the itest command was broken) - added a patch fixing a new build warning v2: https://lists.denx.de/pipermail/u-boot/2020-May/411765.html - fixed ARM64 build v1: https://lists.denx.de/pipermail/u-boot/2020-May/411765.html - initial RFC Patch summary: Marek Szyprowski (5): powerpc: move ADDR_MAP to Kconfig arm: update comments to the common style arm: provide a function for boards init code to modify MMU virtual-physical map rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit) config: Enable support for the XHCI controller on RPI4 board Seung-Woo Kim (1): mmc: bcm283x: fix int to pointer cast arch/arm/include/asm/mmu.h | 8 +++++ arch/arm/include/asm/system.h | 36 ++++++++++++++++------ arch/arm/lib/cache-cp15.c | 24 +++++++++++---- arch/arm/mach-bcm283x/Kconfig | 1 + arch/arm/mach-bcm283x/include/mach/base.h | 8 +++++ arch/arm/mach-bcm283x/init.c | 21 +++++++++++++ configs/B4420QDS_NAND_defconfig | 2 ++ configs/B4420QDS_SPIFLASH_defconfig | 2 ++ configs/B4420QDS_defconfig | 2 ++ configs/B4860QDS_NAND_defconfig | 2 ++ configs/B4860QDS_SECURE_BOOT_defconfig | 2 ++ configs/B4860QDS_SPIFLASH_defconfig | 2 ++ configs/B4860QDS_SRIO_PCIE_BOOT_defconfig | 2 ++ configs/B4860QDS_defconfig | 2 ++ configs/C29XPCIE_NAND_defconfig | 1 + configs/C29XPCIE_NOR_SECBOOT_defconfig | 1 + configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig | 1 + configs/C29XPCIE_SPIFLASH_defconfig | 1 + configs/C29XPCIE_defconfig | 1 + configs/Cyrus_P5020_defconfig | 2 ++ configs/Cyrus_P5040_defconfig | 2 ++ configs/MPC8536DS_36BIT_defconfig | 1 + configs/MPC8548CDS_36BIT_defconfig | 1 + configs/MPC8572DS_36BIT_defconfig | 1 + configs/MPC8641HPCN_36BIT_defconfig | 2 ++ configs/MPC8641HPCN_defconfig | 2 ++ configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig | 1 + configs/P1010RDB-PA_36BIT_NAND_defconfig | 1 + configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig | 1 + configs/P1010RDB-PA_36BIT_NOR_defconfig | 1 + configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 1 + .../P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig | 1 + configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 1 + configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig | 1 + configs/P1010RDB-PB_36BIT_NAND_defconfig | 1 + configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig | 1 + configs/P1010RDB-PB_36BIT_NOR_defconfig | 1 + configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 1 + .../P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig | 1 + configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 1 + configs/P1020MBG-PC_36BIT_SDCARD_defconfig | 1 + configs/P1020MBG-PC_36BIT_defconfig | 1 + configs/P1020RDB-PC_36BIT_NAND_defconfig | 1 + configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 1 + configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_36BIT_defconfig | 1 + configs/P1020UTM-PC_36BIT_SDCARD_defconfig | 1 + configs/P1020UTM-PC_36BIT_defconfig | 1 + configs/P1021RDB-PC_36BIT_NAND_defconfig | 1 + configs/P1021RDB-PC_36BIT_SDCARD_defconfig | 1 + configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig | 1 + configs/P1021RDB-PC_36BIT_defconfig | 1 + configs/P1022DS_36BIT_NAND_defconfig | 1 + configs/P1022DS_36BIT_SDCARD_defconfig | 1 + configs/P1022DS_36BIT_SPIFLASH_defconfig | 1 + configs/P1022DS_36BIT_defconfig | 1 + configs/P1024RDB_36BIT_defconfig | 1 + configs/P1025RDB_36BIT_defconfig | 1 + configs/P2020RDB-PC_36BIT_NAND_defconfig | 1 + configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 1 + configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 1 + configs/P2020RDB-PC_36BIT_defconfig | 1 + configs/P2041RDB_NAND_defconfig | 2 ++ configs/P2041RDB_SDCARD_defconfig | 2 ++ configs/P2041RDB_SECURE_BOOT_defconfig | 2 ++ configs/P2041RDB_SPIFLASH_defconfig | 2 ++ configs/P2041RDB_SRIO_PCIE_BOOT_defconfig | 2 ++ configs/P2041RDB_defconfig | 2 ++ configs/P3041DS_NAND_SECURE_BOOT_defconfig | 2 ++ configs/P3041DS_NAND_defconfig | 2 ++ configs/P3041DS_SDCARD_defconfig | 2 ++ configs/P3041DS_SECURE_BOOT_defconfig | 2 ++ configs/P3041DS_SPIFLASH_defconfig | 2 ++ configs/P3041DS_SRIO_PCIE_BOOT_defconfig | 2 ++ configs/P3041DS_defconfig | 2 ++ configs/P4080DS_SDCARD_defconfig | 2 ++ configs/P4080DS_SECURE_BOOT_defconfig | 2 ++ configs/P4080DS_SPIFLASH_defconfig | 2 ++ configs/P4080DS_SRIO_PCIE_BOOT_defconfig | 2 ++ configs/P4080DS_defconfig | 2 ++ configs/P5020DS_NAND_SECURE_BOOT_defconfig | 2 ++ configs/P5020DS_NAND_defconfig | 2 ++ configs/P5020DS_SDCARD_defconfig | 2 ++ configs/P5020DS_SECURE_BOOT_defconfig | 2 ++ configs/P5020DS_SPIFLASH_defconfig | 2 ++ configs/P5020DS_SRIO_PCIE_BOOT_defconfig | 2 ++ configs/P5020DS_defconfig | 2 ++ configs/P5040DS_NAND_SECURE_BOOT_defconfig | 2 ++ configs/P5040DS_NAND_defconfig | 2 ++ configs/P5040DS_SDCARD_defconfig | 2 ++ configs/P5040DS_SECURE_BOOT_defconfig | 2 ++ configs/P5040DS_SPIFLASH_defconfig | 2 ++ configs/P5040DS_defconfig | 2 ++ configs/T1023RDB_NAND_defconfig | 2 ++ configs/T1023RDB_SDCARD_defconfig | 2 ++ configs/T1023RDB_SECURE_BOOT_defconfig | 2 ++ configs/T1023RDB_SPIFLASH_defconfig | 2 ++ configs/T1023RDB_defconfig | 2 ++ configs/T1024QDS_DDR4_SECURE_BOOT_defconfig | 2 ++ configs/T1024QDS_DDR4_defconfig | 2 ++ configs/T1024QDS_NAND_defconfig | 2 ++ configs/T1024QDS_SDCARD_defconfig | 2 ++ configs/T1024QDS_SECURE_BOOT_defconfig | 2 ++ configs/T1024QDS_SPIFLASH_defconfig | 2 ++ configs/T1024QDS_defconfig | 2 ++ configs/T1024RDB_NAND_defconfig | 2 ++ configs/T1024RDB_SDCARD_defconfig | 2 ++ configs/T1024RDB_SECURE_BOOT_defconfig | 2 ++ configs/T1024RDB_SPIFLASH_defconfig | 2 ++ configs/T1024RDB_defconfig | 2 ++ configs/T1040D4RDB_NAND_defconfig | 2 ++ configs/T1040D4RDB_SDCARD_defconfig | 2 ++ configs/T1040D4RDB_SECURE_BOOT_defconfig | 2 ++ configs/T1040D4RDB_SPIFLASH_defconfig | 2 ++ configs/T1040D4RDB_defconfig | 2 ++ configs/T1040QDS_DDR4_defconfig | 2 ++ configs/T1040QDS_SECURE_BOOT_defconfig | 2 ++ configs/T1040QDS_defconfig | 2 ++ configs/T1040RDB_NAND_defconfig | 2 ++ configs/T1040RDB_SDCARD_defconfig | 2 ++ configs/T1040RDB_SECURE_BOOT_defconfig | 2 ++ configs/T1040RDB_SPIFLASH_defconfig | 2 ++ configs/T1040RDB_defconfig | 2 ++ configs/T1042D4RDB_NAND_defconfig | 2 ++ configs/T1042D4RDB_SDCARD_defconfig | 2 ++ configs/T1042D4RDB_SECURE_BOOT_defconfig | 2 ++ configs/T1042D4RDB_SPIFLASH_defconfig | 2 ++ configs/T1042D4RDB_defconfig | 2 ++ configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig | 2 ++ configs/T1042RDB_PI_NAND_defconfig | 2 ++ configs/T1042RDB_PI_SDCARD_defconfig | 2 ++ configs/T1042RDB_PI_SPIFLASH_defconfig | 2 ++ configs/T1042RDB_PI_defconfig | 2 ++ configs/T1042RDB_SECURE_BOOT_defconfig | 2 ++ configs/T1042RDB_defconfig | 2 ++ configs/T2080QDS_NAND_defconfig | 2 ++ configs/T2080QDS_SDCARD_defconfig | 2 ++ configs/T2080QDS_SECURE_BOOT_defconfig | 2 ++ configs/T2080QDS_SPIFLASH_defconfig | 2 ++ configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 2 ++ configs/T2080QDS_defconfig | 2 ++ configs/T2080RDB_NAND_defconfig | 2 ++ configs/T2080RDB_SDCARD_defconfig | 2 ++ configs/T2080RDB_SECURE_BOOT_defconfig | 2 ++ configs/T2080RDB_SPIFLASH_defconfig | 2 ++ configs/T2080RDB_SRIO_PCIE_BOOT_defconfig | 2 ++ configs/T2080RDB_defconfig | 2 ++ configs/T2081QDS_NAND_defconfig | 2 ++ configs/T2081QDS_SDCARD_defconfig | 2 ++ configs/T2081QDS_SPIFLASH_defconfig | 2 ++ configs/T2081QDS_SRIO_PCIE_BOOT_defconfig | 2 ++ configs/T2081QDS_defconfig | 2 ++ configs/T4160QDS_NAND_defconfig | 2 ++ configs/T4160QDS_SDCARD_defconfig | 2 ++ configs/T4160QDS_SECURE_BOOT_defconfig | 2 ++ configs/T4160QDS_defconfig | 2 ++ configs/T4160RDB_defconfig | 2 ++ configs/T4240QDS_NAND_defconfig | 2 ++ configs/T4240QDS_SDCARD_defconfig | 2 ++ configs/T4240QDS_SECURE_BOOT_defconfig | 2 ++ configs/T4240QDS_SRIO_PCIE_BOOT_defconfig | 2 ++ configs/T4240QDS_defconfig | 2 ++ configs/T4240RDB_SDCARD_defconfig | 2 ++ configs/T4240RDB_defconfig | 2 ++ .../controlcenterd_36BIT_SDCARD_DEVELOP_defconfig | 1 + configs/controlcenterd_36BIT_SDCARD_defconfig | 1 + configs/kmcoge4_defconfig | 2 ++ configs/qemu-ppce500_defconfig | 1 + configs/rpi_4_32b_defconfig | 11 +++++++ drivers/mmc/bcm2835_sdhci.c | 2 +- include/configs/B4860QDS.h | 5 --- include/configs/C29XPCIE.h | 3 -- include/configs/MPC8536DS.h | 5 --- include/configs/MPC8548CDS.h | 5 --- include/configs/MPC8572DS.h | 5 --- include/configs/MPC8641HPCN.h | 2 -- include/configs/P1010RDB.h | 5 --- include/configs/P1022DS.h | 5 --- include/configs/P2041RDB.h | 5 --- include/configs/T102xQDS.h | 5 --- include/configs/T102xRDB.h | 5 --- include/configs/T1040QDS.h | 3 -- include/configs/T104xRDB.h | 3 -- include/configs/T208xQDS.h | 5 --- include/configs/T208xRDB.h | 5 --- include/configs/T4240RDB.h | 3 -- include/configs/controlcenterd.h | 5 --- include/configs/corenet_ds.h | 5 --- include/configs/cyrus.h | 5 --- include/configs/kmp204x.h | 3 -- include/configs/p1_p2_rdb_pc.h | 5 --- include/configs/qemu-ppce500.h | 3 -- include/configs/t4qds.h | 3 -- lib/Kconfig | 13 ++++++++ scripts/config_whitelist.txt | 2 -- 195 files changed, 385 insertions(+), 116 deletions(-) create mode 100644 arch/arm/include/asm/mmu.h -- 1.9.1

4 19

sunxi_nand_spl reading zeros on Cubietruck
by Zahari Zahariev 03 Aug '20

03 Aug '20

Same problem as here: https://lists.denx.de/pipermail/u-boot/2020-February/400350.html SPL read zeros, but u-boot works fine. for Cubietruck sun7i-A20 with HYNIX NAND MLC - H27UCG8T2BTR-BC. regards Zahari Zahariev

1 0

[PATCH 00/13] Add support for USB host and peripheral bootmodes on am65x-idk
by Faiz Abbas 03 Aug '20

03 Aug '20

The following patches add support for USB mass storage and USB dfu bootmodes on am654x-idk. Because of space constrains and the size of the USB stack, there are two different usbmsc and usbdfu defconfigs for building R5 SPL. Fitting both of these into one defconfig requires some changes in the USB subsystem which is a longer term effort Faiz Abbas (13): spl: usb: Create an API spl_usb_load() spl: usb: Only init usb once armv7R: K3: am654: Use full malloc in SPL both pre and post reloc arm: mach-k3: sysfw-loader: Add support to load SYSFW from USB arm: mach-k3: am6_init: Gate mmc related configurations with the appropriate config arm: mach-k3: am6_init: Do USB fixups to facilitate host and device boot modes arm: mach-k3: am6_init: Add support for USB boot mode arm: dts: k3-am654-r5-base-board: Add USB0 nodes arm: dts: k3-am654-base-board: Add support for USB0 in SPL configs: am65x_evm: Add support for DFU related configs configs: am65x_evm_a53: Enable USB Mass storage and DFU boot modes configs: Add new config for supporting USB mass storage boot configs: Add defconfig for USB DFU bootmode arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 27 +++++ arch/arm/dts/k3-am654-r5-base-board.dts | 35 ++++++ arch/arm/mach-k3/am6_init.c | 96 ++++++++++++++- arch/arm/mach-k3/include/mach/am6_hardware.h | 2 + arch/arm/mach-k3/include/mach/am6_spl.h | 3 +- arch/arm/mach-k3/sysfw-loader.c | 11 ++ common/spl/spl_usb.c | 31 +++-- configs/am65x_evm_a53_defconfig | 9 ++ configs/am65x_evm_r5_usbdfu_defconfig | 119 +++++++++++++++++++ configs/am65x_evm_r5_usbmsc_defconfig | 119 +++++++++++++++++++ include/configs/am65x_evm.h | 10 +- include/spl.h | 14 +++ 12 files changed, 461 insertions(+), 15 deletions(-) create mode 100644 configs/am65x_evm_r5_usbdfu_defconfig create mode 100644 configs/am65x_evm_r5_usbmsc_defconfig -- 2.17.1

3 16

Re: [PATCH v2 1/1] riscv: additional crash information
by Rick Chen 03 Aug '20

03 Aug '20

> From: Heinrich Schuchardt [mailto:xypron.glpk@gmx.de] > Sent: Saturday, August 01, 2020 11:16 PM > To: Rick Jian-Zhi Chen(陳建志) > Cc: Simon Glass; Bin Meng; Sean Anderson; u-boot(a)lists.denx.de; Heinrich Schuchardt > Subject: [PATCH v2 1/1] riscv: additional crash information > > If an exception occurs, the relocated program counter and return address are required for an analysis. > > With this patch you get: > > => exception undefined > > Unhandled exception: Illegal instruction > EPC: 0000000080595908 RA: 000000008059c0c6 TVAL: 000000008030c01e > EPC: 0000000080007908 RA: 000000008000e0c6 reloc adjusted > > We can use the relocated addresses to find the involved functions in > u.boot.map: > > .text.do_undefined > 0x0000000080007908 0x8 cmd/built-in.o > .text.cmd_process > 0x000000008000dfcc 0x11a common/built-in.o > 0x000000008000dfcc cmd_process > > If an exception occurs in an UEFI binary additionally the load addresses of the UEFI binaries are needed. With this patch: > > => setenv efi_selftest exception > => bootefi selftest > > Unhandled exception: Illegal instruction > EPC: 000000008042e18a RA: 000000008042e18a TVAL: 000000008030c01e > EPC: 000000007fea018a RA: 000000007fea018a reloc adjusted > > UEFI image [0x0000000000000000:0xffffffffffffffff] '/\selftest' > UEFI image [0x000000008042e000:0x000000008042e43f] pc=0x18a '/bug.efi' > > The value pc=0x18a matches the position of the illegal instruction in efi_selftest_miniapp_exception.efi (loaded as /bug.efi); > > asm volatile (".word 0xffffffff\n"); > > 00000180 93 85 C5 11 1C 64 22 85 82 97 FF FF FF FF 1C 64 > > Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> > Reviewed-by: Sean Anderson <seanga2(a)gmail.com> > Tested-by: Sean Anderson <seanga2(a)gmail.com> > --- > v2: > description of relocated addresses: %s/reloc/reloc adjusted/ > --- > arch/riscv/lib/interrupts.c | 57 +++++++++++++++++++++++-------------- > 1 file changed, 35 insertions(+), 22 deletions(-) > > diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index 074c70ee77..cd47e64487 100644 > --- a/arch/riscv/lib/interrupts.c > +++ b/arch/riscv/lib/interrupts.c > @@ -10,36 +10,43 @@ > */ > > #include <common.h> > +#include <efi_loader.h> > #include <hang.h> > #include <irq_func.h> > #include <asm/ptrace.h> > #include <asm/system.h> > #include <asm/encoding.h> > > +DECLARE_GLOBAL_DATA_PTR; > + > +static void show_efi_loaded_images(uintptr_t epc) { > + efi_print_image_infos((void *)epc); > +} > + > static void show_regs(struct pt_regs *regs) { #ifdef CONFIG_SHOW_REGS > - printf("RA: " REG_FMT " SP: " REG_FMT " GP: " REG_FMT "\n", > - regs->ra, regs->sp, regs->gp); > - printf("TP: " REG_FMT " T0: " REG_FMT " T1: " REG_FMT "\n", > - regs->tp, regs->t0, regs->t1); > - printf("T2: " REG_FMT " S0: " REG_FMT " S1: " REG_FMT "\n", > - regs->t2, regs->s0, regs->s1); > - printf("A0: " REG_FMT " A1: " REG_FMT " A2: " REG_FMT "\n", > - regs->a0, regs->a1, regs->a2); > - printf("A3: " REG_FMT " A4: " REG_FMT " A5: " REG_FMT "\n", > - regs->a3, regs->a4, regs->a5); > - printf("A6: " REG_FMT " A7: " REG_FMT " S2: " REG_FMT "\n", > - regs->a6, regs->a7, regs->s2); > - printf("S3: " REG_FMT " S4: " REG_FMT " S5: " REG_FMT "\n", > - regs->s3, regs->s4, regs->s5); > - printf("S6: " REG_FMT " S7: " REG_FMT " S8: " REG_FMT "\n", > - regs->s6, regs->s7, regs->s8); > - printf("S9: " REG_FMT " S10: " REG_FMT " S11: " REG_FMT "\n", > - regs->s9, regs->s10, regs->s11); > - printf("T3: " REG_FMT " T4: " REG_FMT " T5: " REG_FMT "\n", > - regs->t3, regs->t4, regs->t5); > - printf("T6: " REG_FMT "\n", regs->t6); > + printf("SP: " REG_FMT " GP: " REG_FMT " TP: " REG_FMT "\n", > + regs->sp, regs->gp, regs->tp); > + printf("T0: " REG_FMT " T1: " REG_FMT " T2: " REG_FMT "\n", > + regs->t0, regs->t1, regs->t2); > + printf("S0: " REG_FMT " S1: " REG_FMT " A0: " REG_FMT "\n", > + regs->s0, regs->s1, regs->a0); > + printf("A1: " REG_FMT " A2: " REG_FMT " A3: " REG_FMT "\n", > + regs->a1, regs->a2, regs->a3); > + printf("A4: " REG_FMT " A5: " REG_FMT " A6: " REG_FMT "\n", > + regs->a4, regs->a5, regs->a6); > + printf("A7: " REG_FMT " S2: " REG_FMT " S3: " REG_FMT "\n", > + regs->a7, regs->s2, regs->s3); > + printf("S4: " REG_FMT " S5: " REG_FMT " S6: " REG_FMT "\n", > + regs->s4, regs->s5, regs->s6); > + printf("S7: " REG_FMT " S8: " REG_FMT " S9: " REG_FMT "\n", > + regs->s7, regs->s8, regs->s9); > + printf("S10: " REG_FMT " S11: " REG_FMT " T3: " REG_FMT "\n", > + regs->s10, regs->s11, regs->t3); > + printf("T4: " REG_FMT " T5: " REG_FMT " T6: " REG_FMT "\n\n", > + regs->t4, regs->t5, regs->t6); > #endif > } > > @@ -69,8 +76,14 @@ static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs) > else > printf("Unhandled exception code: %ld\n", code); > > - printf("EPC: " REG_FMT " TVAL: " REG_FMT "\n", epc, tval); > + printf("EPC: " REG_FMT " RA: " REG_FMT " TVAL: " REG_FMT "\n", > + epc, regs->ra, tval); > + if (gd->flags & GD_FLG_RELOC) > + printf("EPC: " REG_FMT " RA: " REG_FMT " reloc adjusted\n\n", > + epc - gd->reloc_off, regs->ra - gd->reloc_off); > + > show_regs(regs); > + show_efi_loaded_images(epc); > hang(); > } > > -- Reviewed-by: Rick Chen <rick(a)andestech.com>

1 0

[PATCH v2 1/1] riscv: additional crash information
by Heinrich Schuchardt 03 Aug '20

03 Aug '20

If an exception occurs, the relocated program counter and return address are required for an analysis. With this patch you get: => exception undefined Unhandled exception: Illegal instruction EPC: 0000000080595908 RA: 000000008059c0c6 TVAL: 000000008030c01e EPC: 0000000080007908 RA: 000000008000e0c6 reloc adjusted We can use the relocated addresses to find the involved functions in u.boot.map: .text.do_undefined 0x0000000080007908 0x8 cmd/built-in.o .text.cmd_process 0x000000008000dfcc 0x11a common/built-in.o 0x000000008000dfcc cmd_process If an exception occurs in an UEFI binary additionally the load addresses of the UEFI binaries are needed. With this patch: => setenv efi_selftest exception => bootefi selftest Unhandled exception: Illegal instruction EPC: 000000008042e18a RA: 000000008042e18a TVAL: 000000008030c01e EPC: 000000007fea018a RA: 000000007fea018a reloc adjusted UEFI image [0x0000000000000000:0xffffffffffffffff] '/\selftest' UEFI image [0x000000008042e000:0x000000008042e43f] pc=0x18a '/bug.efi' The value pc=0x18a matches the position of the illegal instruction in efi_selftest_miniapp_exception.efi (loaded as /bug.efi); asm volatile (".word 0xffffffff\n"); 00000180 93 85 C5 11 1C 64 22 85 82 97 FF FF FF FF 1C 64 Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> Reviewed-by: Sean Anderson <seanga2(a)gmail.com> Tested-by: Sean Anderson <seanga2(a)gmail.com> --- v2: description of relocated addresses: %s/reloc/reloc adjusted/ --- arch/riscv/lib/interrupts.c | 57 +++++++++++++++++++++++-------------- 1 file changed, 35 insertions(+), 22 deletions(-) diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index 074c70ee77..cd47e64487 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -10,36 +10,43 @@ */ #include <common.h> +#include <efi_loader.h> #include <hang.h> #include <irq_func.h> #include <asm/ptrace.h> #include <asm/system.h> #include <asm/encoding.h> +DECLARE_GLOBAL_DATA_PTR; + +static void show_efi_loaded_images(uintptr_t epc) +{ + efi_print_image_infos((void *)epc); +} + static void show_regs(struct pt_regs *regs) { #ifdef CONFIG_SHOW_REGS - printf("RA: " REG_FMT " SP: " REG_FMT " GP: " REG_FMT "\n", - regs->ra, regs->sp, regs->gp); - printf("TP: " REG_FMT " T0: " REG_FMT " T1: " REG_FMT "\n", - regs->tp, regs->t0, regs->t1); - printf("T2: " REG_FMT " S0: " REG_FMT " S1: " REG_FMT "\n", - regs->t2, regs->s0, regs->s1); - printf("A0: " REG_FMT " A1: " REG_FMT " A2: " REG_FMT "\n", - regs->a0, regs->a1, regs->a2); - printf("A3: " REG_FMT " A4: " REG_FMT " A5: " REG_FMT "\n", - regs->a3, regs->a4, regs->a5); - printf("A6: " REG_FMT " A7: " REG_FMT " S2: " REG_FMT "\n", - regs->a6, regs->a7, regs->s2); - printf("S3: " REG_FMT " S4: " REG_FMT " S5: " REG_FMT "\n", - regs->s3, regs->s4, regs->s5); - printf("S6: " REG_FMT " S7: " REG_FMT " S8: " REG_FMT "\n", - regs->s6, regs->s7, regs->s8); - printf("S9: " REG_FMT " S10: " REG_FMT " S11: " REG_FMT "\n", - regs->s9, regs->s10, regs->s11); - printf("T3: " REG_FMT " T4: " REG_FMT " T5: " REG_FMT "\n", - regs->t3, regs->t4, regs->t5); - printf("T6: " REG_FMT "\n", regs->t6); + printf("SP: " REG_FMT " GP: " REG_FMT " TP: " REG_FMT "\n", + regs->sp, regs->gp, regs->tp); + printf("T0: " REG_FMT " T1: " REG_FMT " T2: " REG_FMT "\n", + regs->t0, regs->t1, regs->t2); + printf("S0: " REG_FMT " S1: " REG_FMT " A0: " REG_FMT "\n", + regs->s0, regs->s1, regs->a0); + printf("A1: " REG_FMT " A2: " REG_FMT " A3: " REG_FMT "\n", + regs->a1, regs->a2, regs->a3); + printf("A4: " REG_FMT " A5: " REG_FMT " A6: " REG_FMT "\n", + regs->a4, regs->a5, regs->a6); + printf("A7: " REG_FMT " S2: " REG_FMT " S3: " REG_FMT "\n", + regs->a7, regs->s2, regs->s3); + printf("S4: " REG_FMT " S5: " REG_FMT " S6: " REG_FMT "\n", + regs->s4, regs->s5, regs->s6); + printf("S7: " REG_FMT " S8: " REG_FMT " S9: " REG_FMT "\n", + regs->s7, regs->s8, regs->s9); + printf("S10: " REG_FMT " S11: " REG_FMT " T3: " REG_FMT "\n", + regs->s10, regs->s11, regs->t3); + printf("T4: " REG_FMT " T5: " REG_FMT " T6: " REG_FMT "\n\n", + regs->t4, regs->t5, regs->t6); #endif } @@ -69,8 +76,14 @@ static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs) else printf("Unhandled exception code: %ld\n", code); - printf("EPC: " REG_FMT " TVAL: " REG_FMT "\n", epc, tval); + printf("EPC: " REG_FMT " RA: " REG_FMT " TVAL: " REG_FMT "\n", + epc, regs->ra, tval); + if (gd->flags & GD_FLG_RELOC) + printf("EPC: " REG_FMT " RA: " REG_FMT " reloc adjusted\n\n", + epc - gd->reloc_off, regs->ra - gd->reloc_off); + show_regs(regs); + show_efi_loaded_images(epc); hang(); } -- 2.27.0

2 2

Re: [PATCH v5 0/5] add DM based reset driver for SiFive SoC's
by Rick Chen 03 Aug '20

03 Aug '20

<rick(a)andestech.com> 於 2020年8月3日週一上午11:05寫道： > > > > -----Original Message----- > From: Sagar Kadam [mailto:sagar.kadam@sifive.com] > Sent: Friday, July 31, 2020 9:15 PM > To: u-boot(a)lists.denx.de > Cc: Rick Jian-Zhi Chen(陳建志); Paul Walmsley ( Sifive); palmer(a)dabbelt.com; anup.patel(a)wdc.com; atish.patra(a)wdc.com; lukma(a)denx.de; Pragnesh Patel; bin.meng(a)windriver.com; jagan(a)amarulasolutions.com; sjg(a)chromium.org; twoerner(a)gmail.com; mbrugger(a)suse.com; Eugeniy.Paltsev(a)synopsys.com; seanga2(a)gmail.com; patrick(a)blueri.se; nsaenzjulienne(a)suse.de; weijie.gao(a)mediatek.com; festevam(a)gmail.com > Subject: RE: [PATCH v5 0/5] add DM based reset driver for SiFive SoC's > > Hi Rick, > > > -----Original Message----- > > From: Sagar Kadam <sagar.kadam(a)sifive.com> > > Sent: Wednesday, July 29, 2020 3:06 PM > > To: u-boot(a)lists.denx.de > > Cc: rick(a)andestech.com; Paul Walmsley ( Sifive) > > <paul.walmsley(a)sifive.com>; palmer(a)dabbelt.com; anup.patel(a)wdc.com; > > atish.patra(a)wdc.com; lukma(a)denx.de; Pragnesh Patel > > <pragnesh.patel(a)sifive.com>; bin.meng(a)windriver.com; > > jagan(a)amarulasolutions.com; sjg(a)chromium.org; twoerner(a)gmail.com; > > mbrugger(a)suse.com; Eugeniy.Paltsev(a)synopsys.com; seanga2(a)gmail.com; > > patrick(a)blueri.se; nsaenzjulienne(a)suse.de; weijie.gao(a)mediatek.com; > > festevam(a)gmail.com; Sagar Kadam <sagar.kadam(a)sifive.com> > > Subject: [PATCH v5 0/5] add DM based reset driver for SiFive SoC's > > > > The FU540-C000 support in U-Boot is missing DM based reset driver, and > > is handling reset's to sub-system within the prci driver itself. > > The series here adds a generic DM reset driver for SiFive SoC's so as > > to leverage the U-Boot's reset framework and binds the reset driver with prci driver. > > The PRCI driver takes care of triggering the consumers reset signals > > appropriately. > > > > Patch 1: Add necessary dt indexes for device reset register. > > Patch 2: Update macro's to use common dt indexes from binding header. > > Patch 3: Add reset producer and consumer entries within the device tree. > > Patch 4: Add reset dm driver and bind it within prci module. > > Patch 5: Add Kconfig, Makefile entries and enable the driver > > > > This series is re-based on u-boot-riscv top commit 3b191c56c841 > > ("Merge branch '2020-07-28-Kconfig-migrations'") > > > > History: > > ========================== > > V5: > > -Rebased the series on u-boot-riscv/master. > > > > A gentle reminder to pull in this series. Applied to u-boot-riscv/master! Thanks, Rick

1 0

[PATCH 1/1] timer: dw-apb: fix compiler warnings
by Heinrich Schuchardt 03 Aug '20

03 Aug '20

readl() and writel() expect void *. Do not pass an integer value. Remove unused include include asm/arch/timer.h. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- The driver is needed for the timers of the Kendryte K210 (compatible "snps,dw-apb-timer"). --- drivers/timer/dw-apb-timer.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/timer/dw-apb-timer.c b/drivers/timer/dw-apb-timer.c index 35271b20c8..c8be4417fd 100644 --- a/drivers/timer/dw-apb-timer.c +++ b/drivers/timer/dw-apb-timer.c @@ -14,7 +14,6 @@ #include <dm/device_compat.h> #include <asm/io.h> -#include <asm/arch/timer.h> #define DW_APB_LOAD_VAL 0x0 #define DW_APB_CURR_VAL 0x4 @@ -34,7 +33,7 @@ static int dw_apb_timer_get_count(struct udevice *dev, u64 *count) * requires the count to be incrementing. Invert the * result. */ - *count = timer_conv_64(~readl(priv->regs + DW_APB_CURR_VAL)); + *count = timer_conv_64(~readl((void *)(priv->regs + DW_APB_CURR_VAL))); return 0; } @@ -61,8 +60,8 @@ static int dw_apb_timer_probe(struct udevice *dev) clk_free(&clk); /* init timer */ - writel(0xffffffff, priv->regs + DW_APB_LOAD_VAL); - writel(0xffffffff, priv->regs + DW_APB_CURR_VAL); + writel(0xffffffff, (void *)(priv->regs + DW_APB_LOAD_VAL)); + writel(0xffffffff, (void *)(priv->regs + DW_APB_CURR_VAL)); setbits_le32(priv->regs + DW_APB_CTRL, 0x3); return 0; -- 2.27.0

2 1