July 2020 - U-Boot

[PATCH] configs: ls1012a/ls1046a: Define CONFIG_ENV_OVERWRITE
by Kuldeep Singh 21 Jul '20

21 Jul '20

CONFIG_ENV_OVERWRITE disable write protection on various environment variables like "ethaddr" and "serial". Define the config in LS1046A and LS1012A common header as both of them require this entry. Also, resolve an error while setting multiple values of "ethaddr" variable. Before the change: => setenv ethaddr 00:E0:0C:00:06:0 => setenv ethaddr 00:E0:0C:00:06:1 Error: Can't overwrite "ethaddr" Error inserting "ethaddr" variable, errno=1 After the change: => setenv ethaddr 00:E0:0C:00:06:0 => setenv ethaddr 00:E0:0C:00:06:1 Signed-off-by: Kuldeep Singh <kuldeep.singh(a)nxp.com> --- include/configs/ls1012a_common.h | 2 ++ include/configs/ls1046a_common.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 3bea9a9..b7ad303 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -15,6 +15,8 @@ #define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_ENV_OVERWRITE + #ifdef CONFIG_TFABOOT #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE #else diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 8fe6937..2fdc2d3 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -42,6 +42,8 @@ #define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_ENV_OVERWRITE + #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -- 2.7.4

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[PATCH] Update Winbond SPI NOR Flash ID table
by STLin2＠winbond.com 21 Jul '20

21 Jul '20

>From f76b538a6a8081f9e21012a0de665a263cc6fa16 Mon Sep 17 00:00:00 2001 From: Steam Lin <Stlin2(a)winbond.com> Date: Wed, 8 Jul 2020 16:51:41 +0800 Subject: [PATCH] Update Winbond device ID in ID table Update Winbond SPI NOR Flash id table for uboot Update 512Mbit, 1Gbit device ID and correct JEDEC ID = 0xEF7019 device's name. Signed-off-by: Steam Lin <Stlin2(a)winbond.com> --- drivers/mtd/spi/spi-nor-ids.c | 67 ++++++++++++++++++++++++++++++++++- 1 file changed, 66 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 114ebacde1..37895e714d 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -304,7 +304,72 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, { - INFO("w25q256jw", 0xef7019, 0, 64 * 1024, 512, + INFO("w25q256jvxxIM", 0xef7019, 0, 64 * 1024, 512, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, + { + INFO("w25q256jwxxIM", 0xef8019, 0, 64 * 1024, 512, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, + { + INFO("w25q512jvxxIQ", 0xef4020, 0, 64 * 1024, 1024, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, + { + INFO("w25q512jvxxIM", 0xef7020, 0, 64 * 1024, 1024, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, + { + INFO("w25H512jvxxIM", 0xef9020, 0, 64 * 1024, 1024, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, + { + INFO("w25q512jwxxIQ", 0xef6020, 0, 64 * 1024, 1024, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, + { + INFO("w25q512jvxxIM", 0xef8020, 0, 64 * 1024, 1024, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, + { + INFO("w25H512jvxxIM", 0xefA020, 0, 64 * 1024, 1024, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, + { + INFO("w25q01jvxxIQ", 0xef4021, 0, 64 * 1024, 2048, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, + { + INFO("w25q01jvxxIM", 0xef7021, 0, 64 * 1024, 2048, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, + { + INFO("w25H01jvxxIM", 0xef9021, 0, 64 * 1024, 2048, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, + { + INFO("w25q01jwxxIQ", 0xef6021, 0, 64 * 1024, 2048, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, + { + INFO("w25q01jwxxIM", 0xef8021, 0, 64 * 1024, 2048, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, + { + INFO("w25H01jwxxIM", 0xefA021, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, -- 2.17.1 ________________________________ The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Winbond is strictly prohibited; and any information in this email irrelevant to the official business of Winbond shall be deemed as neither given nor endorsed by Winbond.

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[PATCH 1/1] ls1021a: Add DDR errata num 008109
by jaiprakash.singh＠nxp.com 21 Jul '20

21 Jul '20

From: Jaiprakash Singh <Jaiprakash.singh(a)nxp.com> Signed-off-by: Jaiprakash Singh <Jaiprakash.singh(a)nxp.com> --- arch/arm/cpu/armv7/ls102xa/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 937989b..ba0731d 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -2,6 +2,7 @@ config ARCH_LS1021A bool select SYS_FSL_DDR_BE if SYS_FSL_DDR select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR + select SYS_FSL_ERRATUM_A008109 select SYS_FSL_ERRATUM_A008378 select SYS_FSL_ERRATUM_A008407 select SYS_FSL_ERRATUM_A008850 -- 2.7.4

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[PATCH v1 0/4]
by Stefan Roese 21 Jul '20

21 Jul '20

usb: xhci: Prepare xHCI driver for MIPS Octeon big-endian support These patches fix a few issues, found while porting the xHCI to the MIPS Octeon platforms. The basic issues here are: - Endianess issues: missing cpu_to_leXX() & leXX_to_cpu() conversions - Use physical (DMA) address for the xHCI DMA controller These patches are the groundwork for the upcoming xHCI Octeon support that will follow soon. Thanks, Stefan Stefan Roese (4): usb: xhci: Add missing endian conversions (cpu_to_leXX / leXX_to_cpu) usb: xhci: xhci_mem_init: Use cpu_to_le64() and not xhci_writeq() usb: usb-uclass.c: Drop le16_to_cpu() as values are already swapped usb: xhci: Add virt_to_phys() to support mapped platforms drivers/usb/host/usb-uclass.c | 8 ++++---- drivers/usb/host/xhci-mem.c | 30 +++++++++++++++--------------- drivers/usb/host/xhci-ring.c | 8 ++++---- drivers/usb/host/xhci.c | 3 +-- 4 files changed, 24 insertions(+), 25 deletions(-) -- 2.27.0

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[PATCH] memsize: Make get_ram_size() work with arbitary RAM size
by Bin Meng 21 Jul '20

21 Jul '20

From: Bin Meng <bin.meng(a)windriver.com> Currently get_ram_size() only works with certain RAM size like 1GiB, 2GiB, 4GiB, 8GiB, etc. Chanage the codes to work with any RAM size. Signed-off-by: Bin Meng <bin.meng(a)windriver.com> --- common/memsize.c | 28 +++++++++++++++++----------- 1 file changed, 17 insertions(+), 11 deletions(-) diff --git a/common/memsize.c b/common/memsize.c index e95c682..776737a 100644 --- a/common/memsize.c +++ b/common/memsize.c @@ -6,6 +6,7 @@ #include <common.h> #include <init.h> +#include <linux/bitops.h> DECLARE_GLOBAL_DATA_PTR; @@ -27,14 +28,18 @@ DECLARE_GLOBAL_DATA_PTR; long get_ram_size(long *base, long maxsize) { volatile long *addr; - long save[BITS_PER_LONG - 1]; - long save_base; - long cnt; - long val; - long size; - int i = 0; + long save[BITS_PER_LONG - 1]; + long save_base; + long cnt; + long val; + long size; + int i = 0; + long n = maxsize / sizeof(long); - for (cnt = (maxsize / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) { + n = __ffs(n); + n = BIT(n); + + for (cnt = n >> 1; cnt > 0; cnt >>= 1) { addr = base + cnt; /* pointer arith! */ sync(); save[i++] = *addr; @@ -53,7 +58,7 @@ long get_ram_size(long *base, long maxsize) /* Restore the original data before leaving the function. */ sync(); *base = save_base; - for (cnt = 1; cnt < maxsize / sizeof(long); cnt <<= 1) { + for (cnt = 1; cnt < n; cnt <<= 1) { addr = base + cnt; sync(); *addr = save[--i]; @@ -61,7 +66,7 @@ long get_ram_size(long *base, long maxsize) return (0); } - for (cnt = 1; cnt < maxsize / sizeof(long); cnt <<= 1) { + for (cnt = 1; cnt < n; cnt <<= 1) { addr = base + cnt; /* pointer arith! */ val = *addr; *addr = save[--i]; @@ -72,12 +77,13 @@ long get_ram_size(long *base, long maxsize) * before leaving the function. */ for (cnt <<= 1; - cnt < maxsize / sizeof(long); + cnt < n; cnt <<= 1) { addr = base + cnt; *addr = save[--i]; } - /* warning: don't restore save_base in this case, + /* + * warning: don't restore save_base in this case, * it is already done in the loop because * base and base+size share the same physical memory * and *base is saved after *(base+size) modification -- 2.7.4

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[PATCH 00/16] board: Add new features for ROCKPi N8/N10
by Jagan Teki 21 Jul '20

21 Jul '20

Add new features like USB, HDMI, PCIe on ROCKPi N8/N10 boards. All dts patches are Synced from linux-next and mailing list. Any inputs? Jagan. Jagan Teki (8): ARM: dts: rockchip: Sync ROCKPi N8/N10 dts(i) from Linux ARM: dts: rockchip: Add usb host0 ohci node for rk3288 ARM: dts: rockchip: Add USB for RockPI N8/N10 arm: dts: rockchip: Add HDMI out for RockPI N8/N10 arm64: dts: rockchip: Add PCIe for RockPI N10 rock-pi-n10: Enable PCI/NVME arm64: dts: rockchip: Add u-boot,spl-boot-order for ROCKPi N10 rock-p-n8/n10: Disable RAM_ROCKCHIP_DEBUG Suniel Mahesh (8): arm: dts: rockchip: Sync rk3288 dtsi from linux configs: Enable USB host on Rock-PI-N10 configs: Enable HDMI output configs: Enable USB Gadget for rock-pi-n10 configs: Enable USB 2.0 on Rock-PI-N8 configs: Enable USB Gadget on rock-pi-n8 rk3288: rock-pi-n8: Add console settings configs: Enable HDMI output for rock-pi-n8 arch/arm/dts/rk3288-rock-pi-n8.dts | 2 +- arch/arm/dts/rk3288-vmarc-som.dtsi | 132 +++++++----- arch/arm/dts/rk3288.dtsi | 17 +- .../arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi | 6 + arch/arm/dts/rk3399pro-rock-pi-n10.dts | 6 +- arch/arm/dts/rk3399pro-vmarc-som.dtsi | 201 ++++++++++++++---- .../dts/rockchip-radxa-dalang-carrier.dtsi | 95 ++++++--- configs/rock-pi-n10-rk3399pro_defconfig | 25 +++ configs/rock-pi-n8-rk3288_defconfig | 17 ++ include/configs/evb_rk3288.h | 6 +- 10 files changed, 379 insertions(+), 128 deletions(-) -- 2.25.1

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[PATCH v5 0/6] riscv: sifive/fu540: SPI boot
by Jagan Teki 21 Jul '20

21 Jul '20

Updated series with boot device detection directly on spl_boot_device function instead of having separate board driver. Changes for v5: - rebase on master Changes for v4: - fix typo and unneeded configs. Changes for v3: - fixed env definitions build - added boot device detection in board Changes for v2: - fu540 board driver - runtime bootmode detection - rebase on Pragnesh v11 series Any inputs? Jagan. Jagan Teki (6): sifive: fu540: Add runtime boot mode detection sifive: fu540: Add Booting from SPI env: Enable SPI flash env for SiFive FU540 sifive: fu540: Mark the default env as SPI flash sifive: fu540: Add boot flash script offset, size sifive: fu540: Enable SF distro bootcmd arch/riscv/cpu/fu540/Kconfig | 13 ++++++ .../dts/hifive-unleashed-a00-u-boot.dtsi | 12 ++++++ board/sifive/fu540/Kconfig | 1 + board/sifive/fu540/fu540.c | 25 ++++++++--- configs/sifive_fu540_defconfig | 4 ++ doc/board/sifive/fu540.rst | 41 +++++++++++++++++++ include/configs/sifive-fu540.h | 7 +++- 7 files changed, 96 insertions(+), 7 deletions(-) -- 2.25.1

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[RFC PATCH v2] sunxi: Add UART4 console support for A64
by Nazım Gediz Aydındoğmuş 21 Jul '20

21 Jul '20

UART4 port of A64 was in conflict with R_UART of older SoCs, like A23. This commit adds necessary definitions to use UART4 port on A64. Signed-off-by: Nazım Gediz Aydındoğmuş <gediz.aydindogmus(a)genemek.com> Tested-by: Faruk Kılavuz <faruk.kilavuz(a)genemek.com> --- Changes in v2: - Removed redundant OF_STDOUT_PATH changes - Simplified commit log to meet 80 characters arch/arm/include/asm/arch-sunxi/gpio.h | 1 + arch/arm/mach-sunxi/board.c | 4 ++++ arch/arm/mach-sunxi/clock_sun6i.c | 3 ++- include/configs/sunxi-common.h | 4 ++++ 4 files changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index a646ea6a3c..1407aff25f 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -176,6 +176,7 @@ enum sunxi_gpio_number { #define SUNXI_GPD_LCD0 2 #define SUNXI_GPD_LVDS0 3 #define SUNXI_GPD_PWM 2 +#define SUN50I_GPD_UART4 3 #define SUN5I_GPE_SDC2 3 #define SUN8I_GPE_TWI2 3 diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index f40fccd8f8..7d95b7dd29 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -140,6 +140,10 @@ static int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART); sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART); sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN50I) + sunxi_gpio_set_cfgpin(SUNXI_GPD(2), SUN50I_GPD_UART4); + sunxi_gpio_set_cfgpin(SUNXI_GPD(3), SUN50I_GPD_UART4); + sunxi_gpio_set_pull(SUNXI_GPD(3), SUNXI_GPIO_PULL_UP); #else #error Unsupported console port number. Please fix pin mux settings in board.c #endif diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c index 8e84062bd7..95f8e807f3 100644 --- a/arch/arm/mach-sunxi/clock_sun6i.c +++ b/arch/arm/mach-sunxi/clock_sun6i.c @@ -83,7 +83,8 @@ void clock_init_sec(void) void clock_init_uart(void) { -#if CONFIG_CONS_INDEX < 5 +#if CONFIG_CONS_INDEX < 5 || \ + defined(CONFIG_MACH_SUN50I) && CONFIG_CONS_INDEX < 6 struct sunxi_ccm_reg *const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 5b0bec0561..1324d60f60 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -45,8 +45,12 @@ # define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE # define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE # define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE +#if defined(CONFIG_MACH_SUN50I) +# define CONFIG_SYS_NS16550_COM5 SUNXI_UART4_BASE +#else # define CONFIG_SYS_NS16550_COM5 SUNXI_R_UART_BASE #endif +#endif /* CPU */ #define COUNTER_FREQUENCY 24000000 -- 2.17.1

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[PATCH 1/2] arm64: dts: rockchip: Add ROCKPi 4A/4B support
by Jagan Teki 21 Jul '20

21 Jul '20

Rock PI 4 has 3 variants of hardware platforms called RockPI 4A, 4B, and 4C. - Rock PI 4A has no Wif/BT. - Rock PI 4B has AP6256 Wifi/BT, PoE. - Rock PI 4C has AP6256 Wifi/BT, PoE, miniDP, USB Host enable GPIO pin change compared to 4B, 4C So move common nodes, properties into dtsi file and include on respective variant dts files. Use 4B dts into default rock-pi-4 defconfig until we find any solution for dynamic detection of these variants. Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- Note: Linux dts changes on mailing-list https://lkml.org/lkml/2020/7/20/443 https://lkml.org/lkml/2020/7/20/444 arch/arm/dts/Makefile | 3 +- ...99-rock-pi-4.dts => rk3399-rock-pi-4.dtsi} | 26 ------------ arch/arm/dts/rk3399-rock-pi-4a.dts | 13 ++++++ arch/arm/dts/rk3399-rock-pi-4b-u-boot.dtsi | 6 +++ arch/arm/dts/rk3399-rock-pi-4b.dts | 42 +++++++++++++++++++ configs/rock-pi-4-rk3399_defconfig | 4 +- 6 files changed, 65 insertions(+), 29 deletions(-) rename arch/arm/dts/{rk3399-rock-pi-4.dts => rk3399-rock-pi-4.dtsi} (95%) create mode 100644 arch/arm/dts/rk3399-rock-pi-4a.dts create mode 100644 arch/arm/dts/rk3399-rock-pi-4b-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-rock-pi-4b.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 82e9b18cb8..bcd89af6a5 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -136,7 +136,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-puma-haikou.dtb \ rk3399-roc-pc.dtb \ rk3399-roc-pc-mezzanine.dtb \ - rk3399-rock-pi-4.dtb \ + rk3399-rock-pi-4a.dtb \ + rk3399-rock-pi-4b.dtb \ rk3399-rock960.dtb \ rk3399-rockpro64.dtb \ rk3399pro-rock-pi-n10.dtb diff --git a/arch/arm/dts/rk3399-rock-pi-4.dts b/arch/arm/dts/rk3399-rock-pi-4.dtsi similarity index 95% rename from arch/arm/dts/rk3399-rock-pi-4.dts rename to arch/arm/dts/rk3399-rock-pi-4.dtsi index 3923ec01ef..1c55a4645b 100644 --- a/arch/arm/dts/rk3399-rock-pi-4.dts +++ b/arch/arm/dts/rk3399-rock-pi-4.dtsi @@ -11,9 +11,6 @@ #include "rk3399-opp.dtsi" / { - model = "Radxa ROCK Pi 4"; - compatible = "radxa,rockpi4", "rockchip,rk3399"; - chosen { stdout-path = "serial2:1500000n8"; }; @@ -587,17 +584,6 @@ pinctrl-names = "default"; pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; sd-uhs-sdr104; - status = "okay"; - - brcmf: wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - interrupt-parent = <&gpio0>; - interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>; - interrupt-names = "host-wake"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_l>; - }; }; &sdmmc { @@ -666,18 +652,6 @@ &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; - }; }; &uart2 { diff --git a/arch/arm/dts/rk3399-rock-pi-4a.dts b/arch/arm/dts/rk3399-rock-pi-4a.dts new file mode 100644 index 0000000000..d96dd3ebd3 --- /dev/null +++ b/arch/arm/dts/rk3399-rock-pi-4a.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Akash Gajjar <Akash_Gajjar(a)mentor.com> + * Copyright (c) 2019 Pragnesh Patel <Pragnesh_Patel(a)mentor.com> + */ + +/dts-v1/; +#include "rk3399-rock-pi-4.dtsi" + +/ { + model = "Radxa ROCK Pi 4A"; + compatible = "radxa,rockpi4", "rockchip,rk3399"; +}; diff --git a/arch/arm/dts/rk3399-rock-pi-4b-u-boot.dtsi b/arch/arm/dts/rk3399-rock-pi-4b-u-boot.dtsi new file mode 100644 index 0000000000..85ee5770ad --- /dev/null +++ b/arch/arm/dts/rk3399-rock-pi-4b-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki <jagan(a)amarulasolutions.com> + */ + +#include "rk3399-rock-pi-4-u-boot.dtsi" diff --git a/arch/arm/dts/rk3399-rock-pi-4b.dts b/arch/arm/dts/rk3399-rock-pi-4b.dts new file mode 100644 index 0000000000..4ca970acac --- /dev/null +++ b/arch/arm/dts/rk3399-rock-pi-4b.dts @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Akash Gajjar <Akash_Gajjar(a)mentor.com> + * Copyright (c) 2019 Pragnesh Patel <Pragnesh_Patel(a)mentor.com> + */ + +/dts-v1/; +#include "rk3399-rock-pi-4.dtsi" + +/ { + model = "Radxa ROCK Pi 4B"; + compatible = "radxa,rockpi4", "rockchip,rk3399"; +}; + +&sdio0 { + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; +}; + +&uart0 { + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + }; +}; diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index 98f71a50a5..1d34476825 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -9,7 +9,7 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set -CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4.dtb" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4b.dtb" CONFIG_MISC_INIT_R=y CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set @@ -24,7 +24,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4" +CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4b" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -- 2.25.1

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[PATCH] rockpro64: Enable USB3.0 Host
by Jagan Teki 21 Jul '20

21 Jul '20

Enable USB3.0 Host support for RockPro64 boards. Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- configs/rockpro64-rk3399_defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index 31b3ee2aa4..25cf5c781c 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -49,6 +49,8 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_NVME=y CONFIG_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y @@ -66,6 +68,8 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y -- 2.25.1

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