July 2020 - U-Boot

[PATCH v2] efi_loader: loosen buffer parameter check in efi_file_read
by Stefan Sørensen 22 Jul '20

22 Jul '20

When reading a directory, EFI_BUFFER_TOO_SMALL should be returned when the supplied buffer is too small, so a use-case is to call efi_file_read with *buffer_size=0 and buffer=NULL to obtain the needed size before doing the actual read. So move the buffer!=NULL check to after the buffer size has been checked. This fix allows the Redhat shim fallback to run and e.g. Fedora 32 now boots out of the box. Signed-off-by: Stefan Sørensen <stefan.sorensen(a)spectralink.com> --- lib/efi_loader/efi_file.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/lib/efi_loader/efi_file.c b/lib/efi_loader/efi_file.c index 19afa69f53..44fafae058 100644 --- a/lib/efi_loader/efi_file.c +++ b/lib/efi_loader/efi_file.c @@ -349,6 +349,11 @@ static efi_status_t file_read(struct file_handle *fh, u64 *buffer_size, efi_status_t ret; loff_t file_size; + if (!buffer) { + ret = EFI_INVALID_PARAMETER; + return ret; + } + ret = efi_get_file_size(fh, &file_size); if (ret != EFI_SUCCESS) return ret; @@ -414,6 +419,8 @@ static efi_status_t dir_read(struct file_handle *fh, u64 *buffer_size, fh->dent = dent; return EFI_BUFFER_TOO_SMALL; } + if (!buffer) + return EFI_INVALID_PARAMETER; fh->dent = NULL; *buffer_size = required_size; @@ -443,7 +450,7 @@ static efi_status_t EFIAPI efi_file_read(struct efi_file_handle *file, EFI_ENTRY("%p, %p, %p", file, buffer_size, buffer); - if (!buffer_size || !buffer) { + if (!buffer_size) { ret = EFI_INVALID_PARAMETER; goto error; } -- 2.25.4

2 1

[PATCH] efi_loader: Check for the native OP-TEE result on mm_communicate calls
by Ilias Apalodimas 22 Jul '20

22 Jul '20

Currently we only check for the return value of tee_invoke_func(). Although OP-TEE and StMM will correctly set param[1].u.value.a and we'll eventually return an error, the correct thing to do is check for the OP_TEE return code as well. So let's check for that and move tee_shm_free() and tee_close_session() before exiting with an error to make sure we always clear the registered memory. Fixes: f042e47e8fb43 ("efi_loader: Implement EFI variable handling via OP-TEE") Signed-off-by: Ilias Apalodimas <ilias.apalodimas(a)linaro.org> --- lib/efi_loader/efi_variable_tee.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/efi_loader/efi_variable_tee.c b/lib/efi_loader/efi_variable_tee.c index c0423489388a..346f4c786f28 100644 --- a/lib/efi_loader/efi_variable_tee.c +++ b/lib/efi_loader/efi_variable_tee.c @@ -100,10 +100,10 @@ static efi_status_t optee_mm_communicate(void *comm_buf, ulong dsize) param[1].attr = TEE_PARAM_ATTR_TYPE_VALUE_OUTPUT; rc = tee_invoke_func(conn.tee, &arg, 2, param); - if (rc) - return EFI_INVALID_PARAMETER; tee_shm_free(shm); tee_close_session(conn.tee, conn.session); + if (rc || arg.ret != TEE_SUCCESS) + return EFI_INVALID_PARAMETER; switch (param[1].u.value.a) { case ARM_SMC_MM_RET_SUCCESS: -- 2.28.0.rc1

2 1

[PATCH v2] arm64: zynqmp: Define eeprom fixed partitions in DT
by Michal Simek 22 Jul '20

22 Jul '20

Use fixed partition to cover eeprom content on zynqmp boards. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- Changes in v2: - remove address/size cells from eeprom nodes - it is not needed - Add missing compatible node to zcu102 arch/arm/dts/zynqmp-zcu102-rev1.0.dts | 29 +++++++++++++++------------ arch/arm/dts/zynqmp-zcu104-revA.dts | 23 +++++++++++++++++++-- arch/arm/dts/zynqmp-zcu104-revC.dts | 23 +++++++++++++++++++-- arch/arm/dts/zynqmp-zcu106-revA.dts | 21 +++++++++++++++++++ arch/arm/dts/zynqmp-zcu111-revA.dts | 21 +++++++++++++++++++ arch/arm/dts/zynqmp-zcu1285-revA.dts | 21 +++++++++++++++++++ arch/arm/dts/zynqmp-zcu208-revA.dts | 21 +++++++++++++++++++ arch/arm/dts/zynqmp-zcu216-revA.dts | 21 +++++++++++++++++++ 8 files changed, 163 insertions(+), 17 deletions(-) diff --git a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts index d508f3359943..aed8548bc786 100644 --- a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts +++ b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts @@ -15,22 +15,25 @@ }; &eeprom { - #address-cells = <1>; - #size-cells = <1>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - board_sn: board-sn@0 { - reg = <0x0 0x14>; - }; + board_sn: board-sn@0 { + reg = <0x0 0x14>; + }; - eth_mac: eth-mac@20 { - reg = <0x20 0x6>; - }; + eth_mac: eth-mac@20 { + reg = <0x20 0x6>; + }; - board_name: board-name@d0 { - reg = <0xd0 0x6>; - }; + board_name: board-name@d0 { + reg = <0xd0 0x6>; + }; - board_revision: board-revision@e0 { - reg = <0xe0 0x3>; + board_revision: board-revision@e0 { + reg = <0xe0 0x3>; + }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index a4bd6b800a18..78949c313445 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -128,8 +128,27 @@ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; - #address-cells = <1>; - #size-cells = <1>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + board_sn: board-sn@0 { + reg = <0x0 0x14>; + }; + + eth_mac: eth-mac@20 { + reg = <0x20 0x6>; + }; + + board_name: board-name@d0 { + reg = <0xd0 0x6>; + }; + + board_revision: board-revision@e0 { + reg = <0xe0 0x3>; + }; + }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index d4b3769a27cc..35e4cec15213 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -153,8 +153,27 @@ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; - #address-cells = <1>; - #size-cells = <1>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + board_sn: board-sn@0 { + reg = <0x0 0x14>; + }; + + eth_mac: eth-mac@20 { + reg = <0x20 0x6>; + }; + + board_name: board-name@d0 { + reg = <0xd0 0x6>; + }; + + board_revision: board-revision@e0 { + reg = <0xe0 0x3>; + }; + }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index 221685fd23be..5f4cd17505e1 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -483,6 +483,27 @@ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + board_sn: board-sn@0 { + reg = <0x0 0x14>; + }; + + eth_mac: eth-mac@20 { + reg = <0x20 0x6>; + }; + + board_name: board-name@d0 { + reg = <0xd0 0x6>; + }; + + board_revision: board-revision@e0 { + reg = <0xe0 0x3>; + }; + }; }; }; i2c@1 { diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index 63e285fe9a9a..cae83222bd90 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -379,6 +379,27 @@ eeprom: eeprom@54 { /* u88 */ compatible = "atmel,24c08"; reg = <0x54>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + board_sn: board-sn@0 { + reg = <0x0 0x14>; + }; + + eth_mac: eth-mac@20 { + reg = <0x20 0x6>; + }; + + board_name: board-name@d0 { + reg = <0xd0 0x6>; + }; + + board_revision: board-revision@e0 { + reg = <0xe0 0x3>; + }; + }; }; }; i2c@1 { diff --git a/arch/arm/dts/zynqmp-zcu1285-revA.dts b/arch/arm/dts/zynqmp-zcu1285-revA.dts index d8b9cb1a9e13..3e6737edcfaf 100644 --- a/arch/arm/dts/zynqmp-zcu1285-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1285-revA.dts @@ -152,6 +152,27 @@ eeprom: eeprom@54 { /* u101 */ compatible = "atmel,24c32"; /* 24LC32A */ reg = <0x54>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + board_sn: board-sn@0 { + reg = <0x0 0x14>; + }; + + eth_mac: eth-mac@20 { + reg = <0x20 0x6>; + }; + + board_name: board-name@d0 { + reg = <0xd0 0x6>; + }; + + board_revision: board-revision@e0 { + reg = <0xe0 0x3>; + }; + }; }; }; i2c@3 { diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index 118a2de96b3c..e6e99cf8be96 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -397,6 +397,27 @@ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + board_sn: board-sn@0 { + reg = <0x0 0x14>; + }; + + eth_mac: eth-mac@20 { + reg = <0x20 0x6>; + }; + + board_name: board-name@d0 { + reg = <0xd0 0x6>; + }; + + board_revision: board-revision@e0 { + reg = <0xe0 0x3>; + }; + }; }; }; i2c_si5341: i2c@1 { diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index e454bfcba797..b55defff6e45 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -401,6 +401,27 @@ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + board_sn: board-sn@0 { + reg = <0x0 0x14>; + }; + + eth_mac: eth-mac@20 { + reg = <0x20 0x6>; + }; + + board_name: board-name@d0 { + reg = <0xd0 0x6>; + }; + + board_revision: board-revision@e0 { + reg = <0xe0 0x3>; + }; + }; }; }; i2c_si5341: i2c@1 { -- 2.27.0

1 0

[PATCH] rockchip: rk3328: Add support for FriendlyARM NanoPi R2S
by David Bauer 22 Jul '20

22 Jul '20

This adds support for the NanoPi R2S from FriendlyArm. Rockchip RK3328 SoC 1GB DDR4 RAM Gigabit Ethernet (WAN) Gigabit Ethernet (USB3) (LAN) USB 2.0 Host Port MicroSD slot Reset button WAN - LAN - SYS LED Signed-off-by: David Bauer <mail(a)david-bauer.net> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi | 34 +++ arch/arm/dts/rk3328-nanopi-r2s.dts | 317 +++++++++++++++++++++ board/rockchip/evb_rk3328/MAINTAINERS | 7 + configs/nanopi-r2s-rk3328_defconfig | 99 +++++++ 5 files changed, 458 insertions(+) create mode 100644 arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi create mode 100644 arch/arm/dts/rk3328-nanopi-r2s.dts create mode 100644 configs/nanopi-r2s-rk3328_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index cee10f533f..a6bd8ea0d8 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -107,6 +107,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \ dtb-$(CONFIG_ROCKCHIP_RK3328) += \ rk3328-evb.dtb \ + rk3328-nanopi-r2s.dtb \ rk3328-roc-cc.dtb \ rk3328-rock64.dtb \ rk3328-rock-pi-e.dtb diff --git a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi new file mode 100644 index 0000000000..4159348402 --- /dev/null +++ b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd + * (C) Copyright 2020 David Bauer + */ + +#include "rk3328-u-boot.dtsi" +#include "rk3328-sdram-ddr4-666.dtsi" +/ { + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; + }; +}; + +&gpio0 { + u-boot,dm-spl; +}; + +&pinctrl { + u-boot,dm-spl; +}; + +&sdmmc0m1_gpio { + u-boot,dm-spl; +}; + +&pcfg_pull_up_4ma { + u-boot,dm-spl; +}; + +/* Need this and all the pinctrl/gpio stuff above to set pinmux */ +&vcc_sd { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/rk3328-nanopi-r2s.dts b/arch/arm/dts/rk3328-nanopi-r2s.dts new file mode 100644 index 0000000000..2a3c8b6012 --- /dev/null +++ b/arch/arm/dts/rk3328-nanopi-r2s.dts @@ -0,0 +1,317 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 David Bauer <mail(a)david-bauer.net> + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include "rk3328.dtsi" + +/ { + model = "FriendlyARM NanoPi R2S"; + compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac_clkin: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0m1_gpio>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_rtl8153: vcc-rtl8153-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&rtl8153_en_drv>; + regulator-always-on; + regulator-name = "vcc_rtl8153"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + sys { + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + label = "nanopi-r2s:red:sys"; + }; + + lan { + gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + label = "nanopi-r2s:green:lan"; + }; + + wan { + gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; + label = "nanopi-r2s:green:wan"; + }; + }; + + gpio_keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + pinctrl-names = "default"; + pinctrl-0 = <&button_pins>; + + reset { + label = "Reset Button"; + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + linux,code = <KEY_RESTART>; + debounce-interval = <50>; + }; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&gmac2io { + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; + clock_in_out = "input"; + phy-supply = <&vcc_io>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_pins>; + snps,force_thresh_dma_mode; + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x24>; + rx_delay = <0x18>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + rk805: rk805@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; + interrupt-parent = <&gpio2>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk805-clkout2"; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_io>; + vcc6-supply = <&vcc_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_18: LDO_REG1 { + regulator-name = "vcc_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_emmc: LDO_REG2 { + regulator-name = "vcc18_emmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + }; + }; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vcc_io>; + vccio2-supply = <&vcc18_emmc>; + vccio3-supply = <&vcc_io>; + vccio4-supply = <&vcc_18>; + vccio5-supply = <&vcc_io>; + vccio6-supply = <&vcc_io>; + pmuio-supply = <&vcc_io>; +}; + +&pinctrl { + leds { + led_pins: led_pins { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>, + <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>, + <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + button { + button_pins: button_pins { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + rtl8153_en_drv: rtl8153-en-drv { + rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + status = "okay"; + }; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index e7dd59ff4e..14fda46e8f 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -5,6 +5,13 @@ F: board/rockchip/evb_rk3328 F: include/configs/evb_rk3328.h F: configs/evb-rk3328_defconfig +NANOPI-R2S-RK3328 +M: David Bauer <mail(a)david-bauer.net> +S: Maintained +F: configs/nanopi-r2s-rk3328_defconfig +F: arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi +F: arch/arm/dts/rk3328-nanopi-r2s.dts + ROC-RK3328-CC M: Loic Devulder <ldevulder(a)suse.com> M: Chen-Yu Tsai <wens(a)csie.org> diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig new file mode 100644 index 0000000000..2c028e9d0b --- /dev/null +++ b/configs/nanopi-r2s-rk3328_defconfig @@ -0,0 +1,99 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_ROCKCHIP_RK3328=y +CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_TPL_LIBCOMMON_SUPPORT=y +CONFIG_TPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SMBIOS_PRODUCT_NAME="nanopi_r2s_rk3328" +CONFIG_DEBUG_UART=y +CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2s.dtb" +CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_TPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_TPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2s" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_TPL_OF_PLATDATA=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_TPL_DM=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_TPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_TPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_DM_RESET=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +# CONFIG_TPL_SYSRESET is not set +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC2=y +CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_TPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y +CONFIG_SMBIOS_MANUFACTURER="pine64" -- 2.27.0

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[PATCH] configs: ls2088a: Restore CONFIG_ENV_ADDR to IFC-NOR
by Kuldeep Singh 22 Jul '20

22 Jul '20

Restore CONFIG_ENV_ADDR value to fix boot hang with IFC-NOR as default boot source. Signed-off-by: Ashish Kumar <ashish.kumar(a)nxp.com> Signed-off-by: Kuldeep Singh <kuldeep.singh(a)nxp.com> --- configs/ls2088ardb_tfa_defconfig | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig index b64e3dc..e77ca62 100644 --- a/configs/ls2088ardb_tfa_defconfig +++ b/configs/ls2088ardb_tfa_defconfig @@ -39,8 +39,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi" CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_ENV_ADDR=0x20500000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_ADDR=0x580500000 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y -- 2.7.4

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[PATCH v1 0/6] mips: octeon: Misc Octeon drivers, DT and Kconfig / defconfig updates
by Stefan Roese 22 Jul '20

22 Jul '20

This patchset includes the following parts: - Octeon GPIO driver in v3 - New simple Octeon clk driver - DT updates (GPIO, I2C & CLK nodes) - Kconfig & defconfig updates Thanks, Stefan Changes in v1: - Removed common.h and reduced headers as suggested by Daniel Stefan Roese (5): mips: octeon: mrvl,cn73xx.dtsi: Add GPIO DT nodes mips: octeon: dts: Add I2C DT nodes clk: clk_octeon: Add simple MIPS Octeon clock driver mips: octeon: dts: Add Octeon clock driver DT nodes mips: octeon: Update Octeon Kconfig and EBB7304 defconfig Suneel Garapati (1): gpio: octeon_gpio: Add GPIO controller driver for Octeon arch/mips/Kconfig | 7 +- arch/mips/dts/mrvl,cn73xx.dtsi | 56 +++++ arch/mips/dts/mrvl,octeon-ebb7304.dts | 12 +- configs/octeon_ebb7304_defconfig | 4 + drivers/clk/Kconfig | 7 + drivers/clk/Makefile | 1 + drivers/clk/clk_octeon.c | 72 +++++++ drivers/gpio/Kconfig | 10 + drivers/gpio/Makefile | 1 + drivers/gpio/octeon_gpio.c | 250 +++++++++++++++++++++++ include/dt-bindings/clock/octeon-clock.h | 12 ++ 11 files changed, 429 insertions(+), 3 deletions(-) create mode 100644 drivers/clk/clk_octeon.c create mode 100644 drivers/gpio/octeon_gpio.c create mode 100644 include/dt-bindings/clock/octeon-clock.h -- 2.27.0

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[PATCH 1/1] mtd: cfi_flash: read device tree correctly
by Heinrich Schuchardt 22 Jul '20

22 Jul '20

dev_read_size_cells() and dev_read_addr_cells() do not walk up the device tree to find the number of cells. On error they return 1 and 2 respectively. On qemu_arm64_defconfig this leads to the incorrect detection of address of the second flash bank as 0x400000000000000 instead of 0x4000000. When running qemu-system-aarch64 -machine virt -bios u-boot.bin \ -cpu cortex-a53 -nographic \ -drive if=pflash,format=raw,index=1,file=envstore.img the command 'saveenv' fails with Saving Environment to Flash... Error: start and/or end address not on sector boundary Error: start and/or end address not on sector boundary Failed (1) due to this incorrect address. Use function fdtdec_get_addr_size_auto_noparent() to read the array of flash banks from the device tree. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- drivers/mtd/cfi_flash.c | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index b7289ba539..dfa104bcf0 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -2469,28 +2469,24 @@ unsigned long flash_init(void) static int cfi_flash_probe(struct udevice *dev) { const fdt32_t *cell; - int addrc, sizec; - int len, idx; - - addrc = dev_read_addr_cells(dev); - sizec = dev_read_size_cells(dev); + int len; /* decode regs; there may be multiple reg tuples. */ cell = dev_read_prop(dev, "reg", &len); if (!cell) return -ENOENT; - idx = 0; - len /= sizeof(fdt32_t); - while (idx < len) { + + for (cfi_flash_num_flash_banks = 0; ; ++cfi_flash_num_flash_banks) { phys_addr_t addr; - addr = dev_translate_address(dev, cell + idx); + addr = fdtdec_get_addr_size_auto_noparent( + gd->fdt_blob, dev_of_offset(dev), "reg", + cfi_flash_num_flash_banks, NULL, false); + if (addr == FDT_ADDR_T_NONE) + break; flash_info[cfi_flash_num_flash_banks].dev = dev; flash_info[cfi_flash_num_flash_banks].base = addr; - cfi_flash_num_flash_banks++; - - idx += addrc + sizec; } gd->bd->bi_flashstart = flash_info[0].base; -- 2.27.0

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Pull request: u-boot-spi/master
by Jagan Teki 22 Jul '20

22 Jul '20

Hi Tom, PR for spinand changes. Summary: - add new series Micron SPI NAND devices (Shivamurthy) The following changes since commit 7303ba10a4a39852b9ba356fae5656b43122eec6: Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86 (2020-07-20 09:25:32 -0400) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-spi master for you to fetch changes up to fe48d4f99680ab99d9a6798928eb7c184c61c486: mtd: spinand: micron: Add new Micron SPI NAND devices with multiple dies (2020-07-20 22:29:18 +0530) ---------------------------------------------------------------- Shivamurthy Shastri (6): mtd: spinand: micron: Generalize the OOB layout structure and function names mtd: spinand: micron: Describe the SPI NAND device MT29F2G01ABAGD mtd: spinand: micron: Add new Micron SPI NAND devices mtd: spinand: micron: identify SPI NAND device with Continuous Read mode mtd: spinand: micron: Add M70A series Micron SPI NAND devices mtd: spinand: micron: Add new Micron SPI NAND devices with multiple dies drivers/mtd/nand/spi/micron.c | 150 ++++++++++++++++++++++++++++++++++++++---- include/linux/mtd/spinand.h | 1 + 2 files changed, 137 insertions(+), 14 deletions(-)

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Re: [PATCH v5 0/6] riscv: sifive/fu540: SPI boot
by Rick Chen 22 Jul '20

22 Jul '20

Hi Jagan > From: Jagan Teki [mailto:jagan@amarulasolutions.com] > Sent: Tuesday, July 21, 2020 2:26 PM > To: Rick Jian-Zhi Chen(陳建志); Atish Patra; Palmer Dabbelt; Bin Meng; Paul Walmsley; Anup Patel; Sagar Kadam > Cc: U-Boot-Denx; linux-amarula > Subject: Re: [PATCH v5 0/6] riscv: sifive/fu540: SPI boot > > Hi Rick, > > On Wed, Jul 15, 2020 at 3:39 PM Jagan Teki <jagan(a)amarulasolutions.com> wrote: > > > > Updated series with boot device detection directly on spl_boot_device > > function instead of having separate board driver. > > > > Changes for v5: > > - rebase on master > > Changes for v4: > > - fix typo and unneeded configs. > > Changes for v3: > > - fixed env definitions build > > - added boot device detection in board Changes for v2: > > - fu540 board driver > > - runtime bootmode detection > > - rebase on Pragnesh v11 series > > > > Any inputs? > > Jagan. > > > > Jagan Teki (6): > > sifive: fu540: Add runtime boot mode detection > > sifive: fu540: Add Booting from SPI > > env: Enable SPI flash env for SiFive FU540 > > sifive: fu540: Mark the default env as SPI flash > > sifive: fu540: Add boot flash script offset, size > > sifive: fu540: Enable SF distro bootcmd > > > > arch/riscv/cpu/fu540/Kconfig | 13 ++++++ > > .../dts/hifive-unleashed-a00-u-boot.dtsi | 12 ++++++ > > board/sifive/fu540/Kconfig | 1 + > > board/sifive/fu540/fu540.c | 25 ++++++++--- > > configs/sifive_fu540_defconfig | 4 ++ > > doc/board/sifive/fu540.rst | 41 +++++++++++++++++++ > > include/configs/sifive-fu540.h | 7 +++- > > 7 files changed, 96 insertions(+), 7 deletions(-) > > > > -- > > 2.25.1 > > > > Any chance to pick this? Applied to u-boot-riscv/master ! Thanks, Rick > > Jagan.

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[PATCH 1/1] configs: qemu: enable dfu testing
by Heinrich Schuchardt 21 Jul '20

21 Jul '20

For testing automated updates via dfu and mtd we need the dfu and mtd commands as well as preboot support. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- configs/qemu_arm64_defconfig | 9 +++++++++ configs/qemu_arm_defconfig | 9 +++++++++ 2 files changed, 18 insertions(+) diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig index 53c653df21..21559f8d0b 100644 --- a/configs/qemu_arm64_defconfig +++ b/configs/qemu_arm64_defconfig @@ -10,25 +10,34 @@ CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_PCI_INIT_R=y CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_DFU=y +CONFIG_CMD_MTD=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y +CONFIG_CMD_MTDPARTS=y CONFIG_OF_BOARD=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0x4000000 CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y CONFIG_BLK=y +CONFIG_DFU_TFTP=y +CONFIG_DFU_RAM=y +CONFIG_DFU_MTD=y # CONFIG_MMC is not set +CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_ETH=y CONFIG_E1000=y diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig index a8473988bd..e152bbc69a 100644 --- a/configs/qemu_arm_defconfig +++ b/configs/qemu_arm_defconfig @@ -12,25 +12,34 @@ CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_PCI_INIT_R=y CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_DFU=y +CONFIG_CMD_MTD=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y +CONFIG_CMD_MTDPARTS=y CONFIG_OF_BOARD=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0x4000000 CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y CONFIG_BLK=y +CONFIG_DFU_TFTP=y +CONFIG_DFU_RAM=y +CONFIG_DFU_MTD=y # CONFIG_MMC is not set +CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_ETH=y CONFIG_E1000=y -- 2.27.0

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