July 2020 - U-Boot

RE: [PATCH 2/4] dt-bindings: arm: SCMI bindings documentation
by Peng Fan 24 Jul '20

24 Jul '20

> Subject: [PATCH 2/4] dt-bindings: arm: SCMI bindings documentation Since kernel already has the binding doc, there is no need to add a U-Boot copy. Regards, Peng. > > Dump SCMI DT bindings documentation from Linux kernel source tree > v5.8-rc1. > > Signed-off-by: Etienne Carriere <etienne.carriere(a)linaro.org> > --- > > doc/device-tree-bindings/arm/arm,scmi.txt | 197 > ++++++++++++++++++++++ > 1 file changed, 197 insertions(+) > create mode 100644 doc/device-tree-bindings/arm/arm,scmi.txt > > diff --git a/doc/device-tree-bindings/arm/arm,scmi.txt > b/doc/device-tree-bindings/arm/arm,scmi.txt > new file mode 100644 > index 00000000000..1f293ea24cd > --- /dev/null > +++ b/doc/device-tree-bindings/arm/arm,scmi.txt > @@ -0,0 +1,197 @@ > +System Control and Management Interface (SCMI) Message Protocol > +---------------------------------------------------------- > + > +The SCMI is intended to allow agents such as OSPM to manage various > +functions that are provided by the hardware platform it is running on, > +including power and performance functions. > + > +This binding is intended to define the interface the firmware > +implementing the SCMI as described in ARM document number ARM DEN > 0056A > +("ARM System Control and Management Interface Platform Design > +Document")[0] provide for OSPM in the device tree. > + > +Required properties: > + > +The scmi node with the following properties shall be under the /firmware/ > node. > + > +- compatible : shall be "arm,scmi" or "arm,scmi-smc" for smc/hvc > +transports > +- mboxes: List of phandle and mailbox channel specifiers. It should contain > + exactly one or two mailboxes, one for transmitting messages("tx") > + and another optional for receiving the notifications("rx") if > + supported. > +- shmem : List of phandle pointing to the shared memory(SHM) area as per > + generic mailbox client binding. > +- #address-cells : should be '1' if the device has sub-nodes, maps to > + protocol identifier for a given sub-node. > +- #size-cells : should be '0' as 'reg' property doesn't have any size > + associated with it. > +- arm,smc-id : SMC id required when using smc or hvc transports > + > +Optional properties: > + > +- mbox-names: shall be "tx" or "rx" depending on mboxes entries. > + > +See Documentation/devicetree/bindings/mailbox/mailbox.txt for more > +details about the generic mailbox controller and client driver bindings. > + > +The mailbox is the only permitted method of calling the SCMI firmware. > +Mailbox doorbell is used as a mechanism to alert the presence of a > +messages and/or notification. > + > +Each protocol supported shall have a sub-node with corresponding > +compatible as described in the following sections. If the platform > +supports dedicated communication channel for a particular protocol, the 3 > properties namely: > +mboxes, mbox-names and shmem shall be present in the sub-node > +corresponding to that protocol. > + > +Clock/Performance bindings for the clocks/OPPs based on SCMI Message > +Protocol > +------------------------------------------------------------ > + > +This binding uses the common clock binding[1]. > + > +Required properties: > +- #clock-cells : Should be 1. Contains the Clock ID value used by SCMI > commands. > + > +Power domain bindings for the power domains based on SCMI Message > +Protocol > +------------------------------------------------------------ > + > +This binding for the SCMI power domain providers uses the generic power > +domain binding[2]. > + > +Required properties: > + - #power-domain-cells : Should be 1. Contains the device or the power > + domain ID value used by SCMI commands. > + > +Sensor bindings for the sensors based on SCMI Message Protocol > +-------------------------------------------------------------- > +SCMI provides an API to access the various sensors on the SoC. > + > +Required properties: > +- #thermal-sensor-cells: should be set to 1. This property follows the > + thermal device tree bindings[3]. > + > + Valid cell values are raw identifiers (Sensor ID) > + as used by the firmware. Refer to platform details > + for your implementation for the IDs to use. > + > +Reset signal bindings for the reset domains based on SCMI Message > +Protocol > +------------------------------------------------------------ > + > +This binding for the SCMI reset domain providers uses the generic reset > +signal binding[5]. > + > +Required properties: > + - #reset-cells : Should be 1. Contains the reset domain ID value used > + by SCMI commands. > + > +SRAM and Shared Memory for SCMI > +------------------------------- > + > +A small area of SRAM is reserved for SCMI communication between > +application processors and SCP. > + > +The properties should follow the generic mmio-sram description found in > +[4] > + > +Each sub-node represents the reserved area for SCMI. > + > +Required sub-node properties: > +- reg : The base offset and size of the reserved area with the SRAM > +- compatible : should be "arm,scmi-shmem" for Non-secure SRAM based > + shared memory > + > +[0] > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Finfoce > +nter.arm.com%2Fhelp%2Ftopic%2Fcom.arm.doc.den0056a%2Findex.html& > amp;dat > +a=02%7C01%7Cpeng.fan%40nxp.com%7C94dcac2bc02346684bec08d82a67 > 76b9%7C686 > +ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C637305971145926287&a > mp;sdata=gS > +HhNqZ14iDSv0ws76jZox0JOzAL7Yrg%2BV%2ByH1Szkj4%3D&reserved= > 0 > +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt > +[2] Documentation/devicetree/bindings/power/power-domain.yaml > +[3] Documentation/devicetree/bindings/thermal/thermal.txt > +[4] Documentation/devicetree/bindings/sram/sram.yaml > +[5] Documentation/devicetree/bindings/reset/reset.txt > + > +Example: > + > +sram@50000000 { > + compatible = "mmio-sram"; > + reg = <0x0 0x50000000 0x0 0x10000>; > + > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0x0 0x50000000 0x10000>; > + > + cpu_scp_lpri: scp-shmem@0 { > + compatible = "arm,scmi-shmem"; > + reg = <0x0 0x200>; > + }; > + > + cpu_scp_hpri: scp-shmem@200 { > + compatible = "arm,scmi-shmem"; > + reg = <0x200 0x200>; > + }; > +}; > + > +mailbox@40000000 { > + .... > + #mbox-cells = <1>; > + reg = <0x0 0x40000000 0x0 0x10000>; > +}; > + > +firmware { > + > + ... > + > + scmi { > + compatible = "arm,scmi"; > + mboxes = <&mailbox 0 &mailbox 1>; > + mbox-names = "tx", "rx"; > + shmem = <&cpu_scp_lpri &cpu_scp_hpri>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + scmi_devpd: protocol@11 { > + reg = <0x11>; > + #power-domain-cells = <1>; > + }; > + > + scmi_dvfs: protocol@13 { > + reg = <0x13>; > + #clock-cells = <1>; > + }; > + > + scmi_clk: protocol@14 { > + reg = <0x14>; > + #clock-cells = <1>; > + }; > + > + scmi_sensors0: protocol@15 { > + reg = <0x15>; > + #thermal-sensor-cells = <1>; > + }; > + > + scmi_reset: protocol@16 { > + reg = <0x16>; > + #reset-cells = <1>; > + }; > + }; > +}; > + > +cpu@0 { > + ... > + reg = <0 0>; > + clocks = <&scmi_dvfs 0>; > +}; > + > +hdlcd@7ff60000 { > + ... > + reg = <0 0x7ff60000 0 0x1000>; > + clocks = <&scmi_clk 4>; > + power-domains = <&scmi_devpd 1>; > + resets = <&scmi_reset 10>; > +}; > + > +thermal-zones { > + soc_thermal { > + polling-delay-passive = <100>; > + polling-delay = <1000>; > + /* sensor ID */ > + thermal-sensors = <&scmi_sensors0 3>; > + ... > + }; > +}; > -- > 2.17.1

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RE: [PATCH 1/4] firmware: add new driver for SCMI firmwares
by Peng Fan 24 Jul '20

24 Jul '20

Hi Etienne, +Sudeep > Subject: [PATCH 1/4] firmware: add new driver for SCMI firmwares Thanks for posting this out. > > This change introduces SCMI agent driver in U-Boot in the firmware U-class. > > SCMI agent driver is designed for platforms that embed a SCMI server in a > firmware hosted for example by a companion co-processor or the secure > world of the executing processor. > > SCMI protocols allow an SCMI agent to discover and access external > resources as clock, reset controllers and many more. SCMI agent and server > communicate following the SCMI specification [1]. SCMI agent complies with > the DT bindings defined in the Linux kernel source tree regarding SCMI agent > description since v5.8-rc1. > > These bindings describe 2 supported message transport layer: using mailbox > uclass devices or using Arm SMC invocation instruction. Both use a piece or > shared memory for message data exchange. > > In the current state, the SCMI agent driver does not bind to any SCMI protocol > to a U-Boot device driver. Former changes will implement dedicated driver (i.e. > an SCMI clock driver or an SCMI reset controller > driver) and add bind supported SCMI protocols in scmi_agent_bind(). > > Links: [1] > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fdevelo > per.arm.com%2Farchitectures%2Fsystem-architectures%2Fsoftware-standar > ds%2Fscmi&data=02%7C01%7Cpeng.fan%40nxp.com%7C39c55064be5 > 04bf248a708d82a6775cd%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7 > C0%7C637305971142916174&sdata=5kCgz3kzzk4qHy598u79zz3hV17yV > zdPxM531sOAnUs%3D&reserved=0 > Signed-off-by: Etienne Carriere <etienne.carriere(a)linaro.org> > --- > > drivers/firmware/Kconfig | 15 ++ > drivers/firmware/Makefile | 1 + > drivers/firmware/scmi.c | 439 > ++++++++++++++++++++++++++++++++++++++ > include/scmi.h | 82 +++++++ > 4 files changed, 537 insertions(+) > create mode 100644 drivers/firmware/scmi.c create mode 100644 > include/scmi.h > > diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig index > b70a2063551..f7c7ee7a5aa 100644 > --- a/drivers/firmware/Kconfig > +++ b/drivers/firmware/Kconfig > @@ -1,6 +1,21 @@ > config FIRMWARE > bool "Enable Firmware driver support" > > +config SCMI_FIRMWARE > + bool "Enable SCMI support" > + select FIRMWARE > + select OF_TRANSLATE > + depends on DM_MAILBOX || ARM_SMCCC > + help > + An SCMI agent communicates with a related SCMI server firmware > + located in another sub-system, as a companion micro controller > + or a companion host in the CPU system. > + > + Communications between agent (client) and the SCMI server are > + based on message exchange. Messages can be exchange over tranport > + channels as a mailbox device or an Arm SMCCC service with some > + piece of identified shared memory. > + > config SPL_FIRMWARE > bool "Enable Firmware driver support in SPL" > depends on FIRMWARE > diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile index > a0c250a473e..3965838179f 100644 > --- a/drivers/firmware/Makefile > +++ b/drivers/firmware/Makefile > @@ -2,4 +2,5 @@ obj-$(CONFIG_FIRMWARE) += firmware-uclass.o > obj-$(CONFIG_$(SPL_)ARM_PSCI_FW) += psci.o > obj-$(CONFIG_TI_SCI_PROTOCOL) += ti_sci.o > obj-$(CONFIG_SANDBOX) += firmware-sandbox.o > +obj-$(CONFIG_SCMI_FIRMWARE) += scmi.o > obj-$(CONFIG_ZYNQMP_FIRMWARE) += firmware-zynqmp.o > diff --git a/drivers/firmware/scmi.c b/drivers/firmware/scmi.c new file mode > 100644 index 00000000000..fa8a91c3f3d > --- /dev/null > +++ b/drivers/firmware/scmi.c > @@ -0,0 +1,439 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (c) 2015-2019, Arm Limited and Contributors. All rights > reserved. > + * Copyright (C) 2019-2020 Linaro Limited. > + */ > + > +#include <common.h> > +#include <cpu_func.h> > +#include <dm.h> > +#include <errno.h> > +#include <mailbox.h> > +#include <memalign.h> > +#include <scmi.h> > +#include <asm/system.h> > +#include <asm/types.h> > +#include <dm/device-internal.h> > +#include <dm/devres.h> > +#include <dm/lists.h> > +#include <dm/ofnode.h> > +#include <linux/arm-smccc.h> > +#include <linux/compat.h> > +#include <linux/errno.h> > +#include <linux/io.h> > +#include <linux/ioport.h> > + > +#define TIMEOUT_US_10MS 10000 > + > +struct error_code { > + int scmi; > + int errno; > +}; > + > +static const struct error_code scmi_linux_errmap[] = { > + { .scmi = SCMI_NOT_SUPPORTED, .errno = -EOPNOTSUPP, }, > + { .scmi = SCMI_INVALID_PARAMETERS, .errno = -EINVAL, }, > + { .scmi = SCMI_DENIED, .errno = -EACCES, }, > + { .scmi = SCMI_NOT_FOUND, .errno = -ENOENT, }, > + { .scmi = SCMI_OUT_OF_RANGE, .errno = -ERANGE, }, > + { .scmi = SCMI_BUSY, .errno = -EBUSY, }, > + { .scmi = SCMI_COMMS_ERROR, .errno = -ECOMM, }, > + { .scmi = SCMI_GENERIC_ERROR, .errno = -EIO, }, > + { .scmi = SCMI_HARDWARE_ERROR, .errno = -EREMOTEIO, }, > + { .scmi = SCMI_PROTOCOL_ERROR, .errno = -EPROTO, }, }; > + > +int scmi_to_linux_errno(s32 scmi_code) > +{ > + int n; > + > + if (scmi_code == 0) !scmi_code > + return 0; > + > + for (n = 0; n < ARRAY_SIZE(scmi_linux_errmap); n++) > + if (scmi_code == scmi_linux_errmap[n].scmi) > + return scmi_linux_errmap[1].errno; > + > + return -EPROTO; > +} > + > +struct method_ops { > + int (*process_msg)(struct udevice *dev, struct scmi_msg *msg); > + int (*remove_agent)(struct udevice *dev); }; > + > +struct scmi_agent { > + struct method_ops *method_ops; > + void *method_priv; > +}; > + > +/* > + * Shared Memory based Transport (SMT) message buffer management > + * > + * SMT uses 28 byte header prior message payload to handle the state of > + * the communication channel realized by the shared memory area and > + * to define SCMI protocol information the payload relates to. > + */ > +struct scmi_smt_header { > + __le32 reserved; > + __le32 channel_status; > +#define SCMI_SHMEM_CHAN_STAT_CHANNEL_ERROR BIT(1) > +#define SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE BIT(0) > + __le32 reserved1[2]; > + __le32 flags; > +#define SCMI_SHMEM_FLAG_INTR_ENABLED BIT(0) > + __le32 length; > + __le32 msg_header; > + u8 msg_payload[0]; > +}; > + > +#define SMT_HEADER_TOKEN(token) (((token) << 18) & GENMASK(31, > 18)) > +#define SMT_HEADER_PROTOCOL_ID(proto) (((proto) << 10) & > GENMASK(17, 10)) > +#define SMT_HEADER_MESSAGE_TYPE(type) (((type) << 18) & GENMASK(9, > 8)) > +#define SMT_HEADER_MESSAGE_ID(id) ((id) & GENMASK(7, 0)) > + > +struct scmi_shm_buf { > + u8 *buf; > + size_t size; > +}; > + > +static int get_shm_buffer(struct udevice *dev, struct scmi_shm_buf > +*shm) { > + int rc; > + struct ofnode_phandle_args args; > + struct resource resource; > + fdt32_t faddr; > + phys_addr_t paddr; > + > + rc = dev_read_phandle_with_args(dev, "shmem", NULL, 0, 0, &args); > + if (rc) > + return rc; > + > + rc = ofnode_read_resource(args.node, 0, &resource); > + if (rc) > + return rc; > + > + faddr = cpu_to_fdt32(resource.start); > + paddr = ofnode_translate_address(args.node, &faddr); > + > + shm->size = resource_size(&resource); > + if (shm->size < sizeof(struct scmi_smt_header)) { > + dev_err(dev, "Shared memory buffer too small\n"); > + return -EINVAL; > + } > + > + shm->buf = devm_ioremap(dev, paddr, shm->size); > + if (!shm->buf) > + return -ENOMEM; > + > + if (dcache_status()) > + mmu_set_region_dcache_behaviour((uintptr_t)shm->buf, > + shm->size, DCACHE_OFF); Could dev_read_addr be used to replace the upper code block? > + > + return 0; > +} > + > +static int write_msg_to_smt(struct udevice *dev, struct scmi_shm_buf > *shm_buf, > + struct scmi_msg *msg) > +{ > + struct scmi_smt_header *hdr = (void *)shm_buf->buf; > + > + if ((!msg->in_msg && msg->in_msg_sz) || > + (!msg->out_msg && msg->out_msg_sz)) > + return -EINVAL; > + > + if (!(hdr->channel_status & > SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE)) { > + dev_dbg(dev, "Channel busy\n"); > + return -EBUSY; > + } > + > + if (shm_buf->size < (sizeof(*hdr) + msg->in_msg_sz) || > + shm_buf->size < (sizeof(*hdr) + msg->out_msg_sz)) { > + dev_dbg(dev, "Buffer too small\n"); > + return -ETOOSMALL; > + } > + > + /* Load message in shared memory */ > + hdr->channel_status &= ~SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE; > + hdr->length = msg->in_msg_sz + sizeof(hdr->msg_header); > + hdr->msg_header = SMT_HEADER_TOKEN(0) | > + SMT_HEADER_MESSAGE_TYPE(0) | > + SMT_HEADER_PROTOCOL_ID(msg->protocol_id) | > + SMT_HEADER_MESSAGE_ID(msg->message_id); > + > + memcpy(hdr->msg_payload, msg->in_msg, msg->in_msg_sz); memcpy_toio? > + > + return 0; > +} > + > +static int read_resp_from_smt(struct udevice *dev, struct scmi_shm_buf > *shm_buf, > + struct scmi_msg *msg) > +{ > + struct scmi_smt_header *hdr = (void *)shm_buf->buf; > + > + if (!(hdr->channel_status & > SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE)) { > + dev_err(dev, "Channel unexpectedly busy\n"); > + return -EBUSY; > + } > + > + if (hdr->channel_status & SCMI_SHMEM_CHAN_STAT_CHANNEL_ERROR) > { > + dev_err(dev, "Channel error reported, reset channel\n"); > + return -ECOMM; > + } > + > + if (hdr->length > msg->out_msg_sz + sizeof(hdr->msg_header)) { > + dev_err(dev, "Buffer to small\n"); > + return -ETOOSMALL; > + } > + > + /* Get the data */ > + msg->out_msg_sz = hdr->length - sizeof(hdr->msg_header); > + memcpy(msg->out_msg, hdr->msg_payload, msg->out_msg_sz); > + > + return 0; > +} > + > +static void clear_smt_channel(struct scmi_shm_buf *shm_buf) { > + struct scmi_smt_header *hdr = (void *)shm_buf->buf; > + > + hdr->channel_status &= > ~SCMI_SHMEM_CHAN_STAT_CHANNEL_ERROR; > +} > + > +struct scmi_mbox_channel { > + struct scmi_shm_buf shm_buf; > + struct mbox_chan mbox; > + ulong timeout_us; > +}; > + > +static int mbox_process_msg(struct udevice *dev, struct scmi_msg *msg) > +{ > + struct scmi_agent *agent = dev_get_priv(dev); > + struct scmi_mbox_channel *chan = agent->method_priv; > + int rc; > + > + rc = write_msg_to_smt(dev, &chan->shm_buf, msg); > + if (rc) > + return rc; > + > + /* Give shm addr to mbox in case it is meaningful */ > + rc = mbox_send(&chan->mbox, chan->shm_buf.buf); > + if (rc) { > + dev_err(dev, "Message send failed: %d\n", rc); > + goto out; > + } > + > + /* Receive the response */ > + rc = mbox_recv(&chan->mbox, chan->shm_buf.buf, chan->timeout_us); > + if (rc) { > + dev_err(dev, "Response failed: %d, abort\n", rc); > + goto out; > + } > + > + rc = read_resp_from_smt(dev, &chan->shm_buf, msg); > + > +out: > + clear_smt_channel(&chan->shm_buf); > + > + return rc; > +} > + > +struct method_ops mbox_channel_ops = { > + .process_msg = mbox_process_msg, > +}; > + > +static int probe_mailbox_channel(struct udevice *dev) { > + struct scmi_agent *agent = dev_get_priv(dev); > + struct scmi_mbox_channel *chan; > + int rc; > + > + chan = devm_kzalloc(dev, sizeof(*chan), GFP_KERNEL); > + if (!chan) > + return -ENOMEM; > + > + chan->timeout_us = TIMEOUT_US_10MS; > + > + rc = mbox_get_by_index(dev, 0, &chan->mbox); > + if (rc) { > + dev_err(dev, "Failed to find mailbox: %d\n", rc); > + goto out; > + } > + > + rc = get_shm_buffer(dev, &chan->shm_buf); > + if (rc) > + dev_err(dev, "Failed to get shm resources: %d\n", rc); > + > +out: > + if (rc) { > + devm_kfree(dev, chan); > + } else { > + agent->method_ops = &mbox_channel_ops; > + agent->method_priv = (void *)chan; > + } > + > + return rc; > +} > + > +struct scmi_arm_smc_channel { > + ulong func_id; > + struct scmi_shm_buf shm_buf; > +}; > + > +#define SMCCC_RET_NOT_SUPPORTED ((unsigned long)-1) > + > +static int arm_smc_process_msg(struct udevice *dev, struct scmi_msg > +*msg) { > + struct scmi_agent *agent = dev_get_priv(dev); > + struct scmi_arm_smc_channel *chan = agent->method_priv; > + struct arm_smccc_res res; > + int rc; > + > + rc = write_msg_to_smt(dev, &chan->shm_buf, msg); > + if (rc) > + return rc; > + > + arm_smccc_smc(chan->func_id, 0, 0, 0, 0, 0, 0, 0, &res); > + if (res.a0 == SMCCC_RET_NOT_SUPPORTED) > + rc = -EINVAL; > + else > + rc = read_resp_from_smt(dev, &chan->shm_buf, msg); > + > + clear_smt_channel(&chan->shm_buf); Should the clear be done in firmware side? > + > + return rc; > +} > + > +struct method_ops arm_smc_channel_ops = { > + .process_msg = arm_smc_process_msg, > +}; > + > +static int probe_arm_smc_channel(struct udevice *dev) { > + struct scmi_agent *agent = dev_get_priv(dev); > + struct scmi_arm_smc_channel *chan; > + ofnode node = dev_ofnode(dev); > + u32 func_id; > + int rc; > + > + chan = devm_kzalloc(dev, sizeof(*chan), GFP_KERNEL); > + if (!chan) > + return -ENOMEM; > + > + if (ofnode_read_u32(node, "arm,smc-id", &func_id)) { > + dev_err(dev, "Missing property func-id\n"); > + return -EINVAL; > + } > + > + chan->func_id = func_id; > + > + rc = get_shm_buffer(dev, &chan->shm_buf); > + if (rc) { > + dev_err(dev, "Failed to get shm resources: %d\n", rc); > + return rc; > + } > + > + agent->method_ops = &arm_smc_channel_ops; > + agent->method_priv = (void *)chan; > + > + return rc; > +} > + > +/* > + * Exported functions by the SCMI agent */ > + > +int scmi_send_and_process_msg(struct udevice *dev, struct scmi_msg > +*msg) { > + struct scmi_agent *agent = dev_get_priv(dev); > + > + return agent->method_ops->process_msg(dev, msg); } > + > +static int scmi_remove(struct udevice *dev) { > + struct scmi_agent *agent = dev_get_priv(dev); > + > + if (agent->method_ops->remove_agent) > + return agent->method_ops->remove_agent(dev); > + > + return 0; > +} > + > +enum scmi_transport_channel { > + SCMI_MAILBOX_TRANSPORT, > + SCMI_ARM_SMCCC_TRANSPORT, > +}; > + > +static int scmi_probe(struct udevice *dev) { > + switch (dev_get_driver_data(dev)) { > + case SCMI_MAILBOX_TRANSPORT: > + if (IS_ENABLED(CONFIG_DM_MAILBOX)) > + return probe_mailbox_channel(dev); > + break; > + case SCMI_ARM_SMCCC_TRANSPORT: > + if (IS_ENABLED(CONFIG_ARM_SMCCC)) > + return probe_arm_smc_channel(dev); > + break; > + default: > + break; > + } > + > + return -EINVAL; > +} > + > +static int scmi_bind(struct udevice *dev) { > + int rc = 0; > + ofnode node; > + struct driver *drv; > + > + dev_for_each_subnode(node, dev) { > + u32 protocol_id; > + > + if (!ofnode_is_available(node)) > + continue; > + > + if (ofnode_read_u32(node, "reg", &protocol_id)) > + continue; > + > + switch (protocol_id) { > + default: > + dev_info(dev, "Ignore unsupported SCMI protocol %u\n", > + protocol_id); > + continue; > + } > + > + rc = device_bind_ofnode(dev, drv, ofnode_get_name(node), > + NULL, node, NULL); > + if (rc) > + break; > + } > + > + if (rc) > + device_unbind(dev); > + > + return rc; > +} > + > +static const struct udevice_id scmi_ids[] = { #ifdef CONFIG_DM_MAILBOX > + { .compatible = "arm,scmi", .data = SCMI_MAILBOX_TRANSPORT }, > #endif > +#ifdef CONFIG_ARM_SMCCC > + { .compatible = "arm,scmi-smc", .data = > SCMI_ARM_SMCCC_TRANSPORT }, > +#endif To minimize the code base, how about following Linux kernel to split mailbox and smc to different files? Regards, Peng. > + { } > +}; > + > +U_BOOT_DRIVER(scmi) = { > + .name = "scmi", > + .id = UCLASS_FIRMWARE, > + .of_match = scmi_ids, > + .priv_auto_alloc_size = sizeof(struct scmi_agent), > + .bind = scmi_bind, > + .probe = scmi_probe, > + .remove = scmi_remove, > + .flags = DM_FLAG_OS_PREPARE, > +}; > diff --git a/include/scmi.h b/include/scmi.h new file mode 100644 index > 00000000000..e12e322991d > --- /dev/null > +++ b/include/scmi.h > @@ -0,0 +1,82 @@ > +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ > +/* > + * Copyright (c) 2015-2019, Arm Limited and Contributors. All rights > reserved. > + * Copyright (C) 2019, Linaro Limited > + */ > +#ifndef SCMI_H > +#define SCMI_H > + > +#include <asm/types.h> > + > +/** > + * An SCMI agent represent on communication path from a device driver > +to > + * the remote SCMI server which driver sends messages to and receives > + * response messages from. > + */ > +struct scmi_agent; > + > +enum scmi_std_protocol { > + SCMI_PROTOCOL_ID_BASE = 0x10, > + SCMI_PROTOCOL_ID_POWER_DOMAIN = 0x11, > + SCMI_PROTOCOL_ID_SYSTEM = 0x12, > + SCMI_PROTOCOL_ID_PERF = 0x13, > + SCMI_PROTOCOL_ID_CLOCK = 0x14, > + SCMI_PROTOCOL_ID_SENSOR = 0x15, > + SCMI_PROTOCOL_ID_RESET_DOMAIN = 0x16, > +}; > + > +enum scmi_status_code { > + SCMI_SUCCESS = 0, > + SCMI_NOT_SUPPORTED = -1, > + SCMI_INVALID_PARAMETERS = -2, > + SCMI_DENIED = -3, > + SCMI_NOT_FOUND = -4, > + SCMI_OUT_OF_RANGE = -5, > + SCMI_BUSY = -6, > + SCMI_COMMS_ERROR = -7, > + SCMI_GENERIC_ERROR = -8, > + SCMI_HARDWARE_ERROR = -9, > + SCMI_PROTOCOL_ERROR = -10, > +}; > + > +/* > + * struct scmi_msg - Context of a SCMI message sent and the response > +received > + * > + * @protocol_id: SCMI protocol ID > + * @message_id: SCMI message ID for a defined protocol ID > + * @in_msg: pointer to the message payload sent by the driver > + * @in_msg_sz: byte size of the message payload sent > + * @out_msg: pointer to buffer to store response message payload > + * @out_msg_size: Byte size of the response buffer or payload */ > +struct scmi_msg { > + unsigned int protocol_id; > + unsigned int message_id; > + u8 *in_msg; > + size_t in_msg_sz; > + u8 *out_msg; > + size_t out_msg_sz; > +}; > + > +/** > + * scmi_send_and_process_msg() - send and process a SCMI message > + * > + * Send a message to a SCMI server through a target SCMI agent device. > + * Caller sets scmi_msg::out_msg_sz to the output message buffer size. > + * On return, scmi_msg::out_msg_sz stores the response payload size. > + * > + * @dev: SCMI agent device > + * @msg: Message structure reference > + * @return 0 on success, a negative errno otherwise */ int > +scmi_send_and_process_msg(struct udevice *dev, struct scmi_msg *msg); > + > +/** > + * scmi_to_linux_errno() - Convert an SCMI error code into a Linux > +errno code > + * > + * @scmi_errno: SCMI error code value > + * @return 0 for successful status and a negative errno otherwise */ > +int scmi_to_linux_errno(s32 scmi_errno); > + > +#endif /* SCMI_H */ > -- > 2.17.1

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[PATCH 1/3] armv8: gpio: add gpio feature
by Hui Song 24 Jul '20

24 Jul '20

From: "hui.song" <hui.song_1(a)nxp.com> add one struct mpc8xxx_gpio_plat to enable gpio feature. Signed-off-by: hui.song <hui.song_1(a)nxp.com> --- .../include/asm/arch-fsl-layerscape/gpio.h | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/gpio.h diff --git a/arch/arm/include/asm/arch-fsl-layerscape/gpio.h b/arch/arm/include/asm/arch-fsl-layerscape/gpio.h new file mode 100644 index 0000000000..7ae5eee8b6 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/gpio.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + */ + +/* + * Dummy header file to enable CONFIG_OF_CONTROL. + * If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled. + * It includes <asm/arch/gpio.h> via <asm/gpio.h>, so those SoCs that enable + * OF_CONTROL must have arch/gpio.h. + */ + +#ifndef __ASM_ARCH_MX85XX_GPIO_H +#define __ASM_ARCH_MX85XX_GPIO_H + +struct mpc8xxx_gpio_plat { + ulong addr; + ulong size; + uint ngpios; +}; + +#endif -- 2.17.1

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[PATCH] arm64: zynqmp: Fix zynqmp mini qspi max frequency
by Michal Simek 24 Jul '20

24 Jul '20

From: T Karthik Reddy <t.karthik.reddy(a)xilinx.com> For zynqmp qspi, frequencies up to 40MHz will work irrespective of feedback clock enabled or disabled. If we want higher than 40Mhz the feedback clock should be enabled. With spi-max-frequency 108MHz it is not working when the feedback clock is disabled. Change it to 40MHz so that it works irrespective of feedback clock enabled or disabled. Signed-off-by: T Karthik Reddy <t.karthik.reddy(a)xilinx.com> Acked-by: Ashok Reddy Soma <ashok.reddy.soma(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/dts/zynqmp-mini-qspi.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/zynqmp-mini-qspi.dts b/arch/arm/dts/zynqmp-mini-qspi.dts index a76e6404661e..9b4320fe6e20 100644 --- a/arch/arm/dts/zynqmp-mini-qspi.dts +++ b/arch/arm/dts/zynqmp-mini-qspi.dts @@ -70,7 +70,7 @@ reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; - spi-max-frequency = <108000000>; + spi-max-frequency = <40000000>; }; }; -- 2.27.0

1 0

Re: [PATCH v4] riscv: Make SiFive HiFive Unleashed board boot again
by Rick Chen 24 Jul '20

24 Jul '20

Hi Bin > From: Bin Meng [mailto:bmeng.cn@gmail.com] > Sent: Friday, July 24, 2020 11:26 AM > To: Leo Yu-Chi Liang(梁育齊); Rick Jian-Zhi Chen(陳建志) > Cc: U-Boot Mailing List > Subject: Re: [PATCH v4] riscv: Make SiFive HiFive Unleashed board boot again > > Hi Rick, > > On Tue, Jul 21, 2020 at 4:30 PM Leo Liang <ycliang(a)andestech.com> wrote: > > > > On Sun, Jul 19, 2020 at 11:17:07PM -0700, Bin Meng wrote: > > > From: Bin Meng <bin.meng(a)windriver.com> > > > > > > Commit 40686c394e53 ("riscv: Clean up IPI initialization code") > > > caused U-Boot failed to boot on SiFive HiFive Unleashed board. > > > > > > The codes inside arch_cpu_init_dm() may call U-Boot timer APIs > > > before the call to riscv_init_ipi(). At that time the timer register > > > base (e.g.: the SiFive CLINT device in this case) is unknown yet. > > > > > > It might be the name riscv_init_ipi() that misleads people to only > > > consider it is related to IPI, but in fact the timer capability is > > > provided by the same SiFive CLINT device that provides the IPI. > > > Timer capability is needed for both UP and SMP. > > > > > > Considering that the original refactor does have benefits, that it > > > makes the IPI code more similar to U-Boot initialization idioms. > > > It also removes some quite ugly macros. Let's do the minimal revert > > > instead of a complete revert, plus a fixes to arch_cpu_init_dm() to > > > consider the SPL case. > > > > > > Fixes: 40686c394e53 ("riscv: Clean up IPI initialization code") > > > Signed-off-by: Bin Meng <bin.meng(a)windriver.com> > > > Reviewed-by: Sean Anderson <seanga2(a)gmail.com> > > > --- > > > > > > Changes in v4: > > > - Include Sean's "Reviewed-by" tag > > > > > > Changes in v3: > > > - Simply call riscv_init_ipi() in clint timer functions to avoid > > > some duplications > > > > > > Changes in v2: > > > - Do the minimal partial revert instead of a complete revert, enough > > > to make HiFive Unleashed board boot again. > > > > > > arch/riscv/cpu/cpu.c | 2 +- > > > arch/riscv/lib/sifive_clint.c | 16 ++++++++++++---- > > > common/spl/spl_opensbi.c | 5 ----- > > > 3 files changed, 13 insertions(+), 10 deletions(-) > > > > > > diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index > > > bbd6c15..bfa2d4a 100644 > > > --- a/arch/riscv/cpu/cpu.c > > > +++ b/arch/riscv/cpu/cpu.c > > > @@ -107,7 +107,7 @@ int arch_cpu_init_dm(void) #endif > > > } > > > > > > -#ifdef CONFIG_SMP > > > +#if CONFIG_IS_ENABLED(SMP) > > > ret = riscv_init_ipi(); > > > if (ret) > > > return ret; > > > diff --git a/arch/riscv/lib/sifive_clint.c > > > b/arch/riscv/lib/sifive_clint.c index 78fc6c8..b9a2c64 100644 > > > --- a/arch/riscv/lib/sifive_clint.c > > > +++ b/arch/riscv/lib/sifive_clint.c > > > @@ -26,6 +26,9 @@ DECLARE_GLOBAL_DATA_PTR; > > > > > > int riscv_get_time(u64 *time) > > > { > > > + /* ensure timer register base has a sane value */ > > > + riscv_init_ipi(); > > > + > > > *time = readq((void __iomem *)MTIME_REG(gd->arch.clint)); > > > > > > return 0; > > > @@ -33,6 +36,9 @@ int riscv_get_time(u64 *time) > > > > > > int riscv_set_timecmp(int hart, u64 cmp) { > > > + /* ensure timer register base has a sane value */ > > > + riscv_init_ipi(); > > > + > > > writeq(cmp, (void __iomem *)MTIMECMP_REG(gd->arch.clint, > > > hart)); > > > > > > return 0; > > > @@ -40,11 +46,13 @@ int riscv_set_timecmp(int hart, u64 cmp) > > > > > > int riscv_init_ipi(void) > > > { > > > - long *ret = syscon_get_first_range(RISCV_SYSCON_CLINT); > > > + if (!gd->arch.clint) { > > > + long *ret = > > > + syscon_get_first_range(RISCV_SYSCON_CLINT); > > > > > > - if (IS_ERR(ret)) > > > - return PTR_ERR(ret); > > > - gd->arch.clint = ret; > > > + if (IS_ERR(ret)) > > > + return PTR_ERR(ret); > > > + gd->arch.clint = ret; > > > + } > > > > > > return 0; > > > } > > > diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c > > > index 3440bc0..14f335f 100644 > > > --- a/common/spl/spl_opensbi.c > > > +++ b/common/spl/spl_opensbi.c > > > @@ -79,11 +79,6 @@ void spl_invoke_opensbi(struct spl_image_info *spl_image) > > > invalidate_icache_all(); > > > > > > #ifdef CONFIG_SPL_SMP > > > - /* Initialize the IPI before we use it */ > > > - ret = riscv_init_ipi(); > > > - if (ret) > > > - hang(); > > > - > > > /* > > > * Start OpenSBI on all secondary harts and wait for acknowledgment. > > > * > > > -- > > > 2.7.4 > > > > > > > Tested-by: Leo Liang <ycliang(a)andestech.com> > > Could we get this applied soon, since it's broken in u-boot/master? OK. I am preparing to send a PR later today. Thanks, Rick > > Regards, > Bin

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[PATCH 0/1] Fix SPL_EARLY_BSS applying to normal build
by Brian Moyer 24 Jul '20

24 Jul '20

SPL_CLEAR_BSS is called regardless of build type if CONFIG_SPL_EARLY_BSS is defined. This seems to break u-boot proper and doesn't seem like the correct behavior. Brian Moyer (1): arm: Add SPL build check to SPL early bss clear arch/arm/lib/crt0.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.1

1 2

[PATCH v3 0/2] Basic Kontron SMARC-sAL28 board support
by Michael Walle 24 Jul '20

24 Jul '20

Add basic board support for the Kontron SMARC-sAL28 board. Please note, that this board doesn't support TF-a (yet). Therefore, the u-boot SPL is the first code which is run and it has to set up the RAM. changes since v3: - add variant 4 support. Since the atheros PHY dt bindings were merged into master, we can now use them - add environment section in include/configs/kontron_sl28.h - add cover letter changes since v1: - fix watchdog device tree reference Michael Walle (2): armv8: ls1028a: move FSL_LAYERSCAPE to kconfig board: kontron: add sl28 support arch/arm/Kconfig | 10 ++ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 1 + arch/arm/dts/Makefile | 3 + .../arm/dts/fsl-ls1028a-kontron-sl28-var3.dts | 14 ++ .../arm/dts/fsl-ls1028a-kontron-sl28-var4.dts | 42 ++++++ arch/arm/dts/fsl-ls1028a-kontron-sl28.dts | 128 ++++++++++++++++++ board/kontron/sl28/Kconfig | 18 +++ board/kontron/sl28/MAINTAINERS | 6 + board/kontron/sl28/Makefile | 8 ++ board/kontron/sl28/README | 63 +++++++++ board/kontron/sl28/common.c | 10 ++ board/kontron/sl28/ddr.c | 98 ++++++++++++++ board/kontron/sl28/sl28.c | 92 +++++++++++++ board/kontron/sl28/spl.c | 9 ++ configs/kontron_sl28_defconfig | 102 ++++++++++++++ include/configs/kontron_sl28.h | 119 ++++++++++++++++ include/configs/ls1028a_common.h | 1 - 17 files changed, 723 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-var3.dts create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28.dts create mode 100644 board/kontron/sl28/Kconfig create mode 100644 board/kontron/sl28/MAINTAINERS create mode 100644 board/kontron/sl28/Makefile create mode 100644 board/kontron/sl28/README create mode 100644 board/kontron/sl28/common.c create mode 100644 board/kontron/sl28/ddr.c create mode 100644 board/kontron/sl28/sl28.c create mode 100644 board/kontron/sl28/spl.c create mode 100644 configs/kontron_sl28_defconfig create mode 100644 include/configs/kontron_sl28.h -- 2.20.1

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[PATCH v4] riscv: Make SiFive HiFive Unleashed board boot again
by Bin Meng 24 Jul '20

24 Jul '20

From: Bin Meng <bin.meng(a)windriver.com> Commit 40686c394e53 ("riscv: Clean up IPI initialization code") caused U-Boot failed to boot on SiFive HiFive Unleashed board. The codes inside arch_cpu_init_dm() may call U-Boot timer APIs before the call to riscv_init_ipi(). At that time the timer register base (e.g.: the SiFive CLINT device in this case) is unknown yet. It might be the name riscv_init_ipi() that misleads people to only consider it is related to IPI, but in fact the timer capability is provided by the same SiFive CLINT device that provides the IPI. Timer capability is needed for both UP and SMP. Considering that the original refactor does have benefits, that it makes the IPI code more similar to U-Boot initialization idioms. It also removes some quite ugly macros. Let's do the minimal revert instead of a complete revert, plus a fixes to arch_cpu_init_dm() to consider the SPL case. Fixes: 40686c394e53 ("riscv: Clean up IPI initialization code") Signed-off-by: Bin Meng <bin.meng(a)windriver.com> Reviewed-by: Sean Anderson <seanga2(a)gmail.com> --- Changes in v4: - Include Sean's "Reviewed-by" tag Changes in v3: - Simply call riscv_init_ipi() in clint timer functions to avoid some duplications Changes in v2: - Do the minimal partial revert instead of a complete revert, enough to make HiFive Unleashed board boot again. arch/riscv/cpu/cpu.c | 2 +- arch/riscv/lib/sifive_clint.c | 16 ++++++++++++---- common/spl/spl_opensbi.c | 5 ----- 3 files changed, 13 insertions(+), 10 deletions(-) diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index bbd6c15..bfa2d4a 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -107,7 +107,7 @@ int arch_cpu_init_dm(void) #endif } -#ifdef CONFIG_SMP +#if CONFIG_IS_ENABLED(SMP) ret = riscv_init_ipi(); if (ret) return ret; diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c index 78fc6c8..b9a2c64 100644 --- a/arch/riscv/lib/sifive_clint.c +++ b/arch/riscv/lib/sifive_clint.c @@ -26,6 +26,9 @@ DECLARE_GLOBAL_DATA_PTR; int riscv_get_time(u64 *time) { + /* ensure timer register base has a sane value */ + riscv_init_ipi(); + *time = readq((void __iomem *)MTIME_REG(gd->arch.clint)); return 0; @@ -33,6 +36,9 @@ int riscv_get_time(u64 *time) int riscv_set_timecmp(int hart, u64 cmp) { + /* ensure timer register base has a sane value */ + riscv_init_ipi(); + writeq(cmp, (void __iomem *)MTIMECMP_REG(gd->arch.clint, hart)); return 0; @@ -40,11 +46,13 @@ int riscv_set_timecmp(int hart, u64 cmp) int riscv_init_ipi(void) { - long *ret = syscon_get_first_range(RISCV_SYSCON_CLINT); + if (!gd->arch.clint) { + long *ret = syscon_get_first_range(RISCV_SYSCON_CLINT); - if (IS_ERR(ret)) - return PTR_ERR(ret); - gd->arch.clint = ret; + if (IS_ERR(ret)) + return PTR_ERR(ret); + gd->arch.clint = ret; + } return 0; } diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c index 3440bc0..14f335f 100644 --- a/common/spl/spl_opensbi.c +++ b/common/spl/spl_opensbi.c @@ -79,11 +79,6 @@ void spl_invoke_opensbi(struct spl_image_info *spl_image) invalidate_icache_all(); #ifdef CONFIG_SPL_SMP - /* Initialize the IPI before we use it */ - ret = riscv_init_ipi(); - if (ret) - hang(); - /* * Start OpenSBI on all secondary harts and wait for acknowledgment. * -- 2.7.4

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[PATCH] board: ti: am65x: Update fdt fixup logic for interconnect nodes
by Suman Anna 24 Jul '20

24 Jul '20

The DT nodes on AM65x SoCs currently use a node name "interconnect" for the various interconnects. This name is not following the DT schema, and should simply be "bus". Update the fdt fixup logic to use both the current and the expected corrected path names so that this logic won't be broken with newer kernels. The logic also corrects the crypto node name as the DT node unit-addresses are all expected to be lower case. Signed-off-by: Suman Anna <s-anna(a)ti.com> --- Hi Lokesh, This patch provides backward compatibility while adjusting for the new node names, and is needed for the equivalent kernel dts updates. regards Suman board/ti/am65x/evm.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c index 2eb8235c6988..119859d5f565 100644 --- a/board/ti/am65x/evm.c +++ b/board/ti/am65x/evm.c @@ -100,8 +100,13 @@ int board_fit_config_name_match(const char *name) int ft_board_setup(void *blob, struct bd_info *bd) { int ret; + bool legacy_path = false; - ret = fdt_fixup_msmc_ram(blob, "/interconnect@100000", "sram@70000000"); + ret = fdt_fixup_msmc_ram(blob, "/bus@100000", "sram@70000000"); + if (ret < 0) { + ret = fdt_fixup_msmc_ram(blob, "/interconnect@100000", "sram@70000000"); + legacy_path = true; + } if (ret) { printf("%s: fixing up msmc ram failed %d\n", __func__, ret); return ret; @@ -109,7 +114,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) #if defined(CONFIG_TI_SECURE_DEVICE) /* Make Crypto HW reserved for secure world use */ - ret = fdt_disable_node(blob, "/interconnect@100000/crypto@4E00000"); + if (legacy_path) + ret = fdt_disable_node(blob, "/interconnect@100000/crypto@4E00000"); + else + ret = fdt_disable_node(blob, "/bus@100000/crypto@4e00000"); if (ret) printf("%s: disabling SA2UL failed %d\n", __func__, ret); #endif -- 2.26.0

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[PATCH] dm: Fix build error when OF_CONTROL is not set
by Dan Murphy 23 Jul '20

23 Jul '20

With OF_CONTROL disabled the build fails for include/dm/read.h:932:10: error: ‘ENOTSUPP’ undeclared (first use in this function) Fixes: 134f3c366d78 ("dm: core: gracefully handle alias seq without of") Signed-off-by: Dan Murphy <dmurphy(a)ti.com> --- include/dm/read.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dm/read.h b/include/dm/read.h index f02ec9595413..b1a610854403 100644 --- a/include/dm/read.h +++ b/include/dm/read.h @@ -9,6 +9,8 @@ #ifndef _DM_READ_H #define _DM_READ_H +#include <linux/errno.h> + #include <dm/fdtaddr.h> #include <dm/ofnode.h> #include <dm/uclass.h> -- 2.27.0

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