July 2020 - U-Boot

[PATCH v2 00/14] toradex: imx: fixes and updates for v2020.10
by Igor Opaniuk 27 Jul '20

27 Jul '20

This is the common combined patch-series, which superseeds [1], [2], [3]. Includes: 1. Fixes for splash screen logo drawing in Colibri iMX7/iMX6ULL. 2. Support for EEPROM as a storage for the main Toradex config block and additional config blocks on extra EEPROM chips (on carrier board or video adapters). 3. DDRC size fixes in A7-M4 mapping table for bootaux command. v2: - Сombine [1], [2], [3] into one patch-series. - Correct strings for carrier board names/adapters. - Fix display timings, sync with downstream Toradex Linux. [1]: https://patchwork.ozlabs.org/project/uboot/list/?series=185024 [2]: https://patchwork.ozlabs.org/project/uboot/list/?series=185100 [3]: https://patchwork.ozlabs.org/project/uboot/list/?series=185354 Igor Opaniuk (14): imx: mx7: fix DDRC size in A7-M4 mapping table toradex: tdx-cfg-block: add EEPROM read/store wrappers toradex: tdx-cfg-block: add carrier boards and display adapters toradex: tdx-cfg-block: add support for EEPROM toradex: tdx-cfg-clock: add migration routine from PID8 toradex: tdx-cfg-block: add carrier board info printing ARM: dts: imx8mm-verdin: eeprom nodes adjustments verdin-imx8mm: add EEPROM support for carrier board ARM: dts: imx6ull-colibri: move u-boot specific node toradex: common: show boot logo ARM: dts: imx7-colibri: multiple node updates colibri-imx6ull: show boot logo colibri-imx6ull: fix splash screen logo drawing colibri-imx7: fix splash logo drawing arch/arm/dts/imx6ull-colibri-u-boot.dtsi | 45 ++ arch/arm/dts/imx6ull-colibri.dtsi | 43 -- arch/arm/dts/imx7-colibri-emmc.dts | 2 +- arch/arm/dts/imx7-colibri-rawnand.dts | 10 +- arch/arm/dts/imx7-colibri-u-boot.dtsi | 39 ++ arch/arm/dts/imx7-colibri.dtsi | 65 ++- arch/arm/dts/imx8mm-verdin.dts | 22 +- arch/arm/mach-imx/mx7/soc.c | 2 +- .../toradex/colibri-imx6ull/colibri-imx6ull.c | 40 +- board/toradex/colibri_imx7/MAINTAINERS | 1 + board/toradex/colibri_imx7/colibri_imx7.c | 44 +- board/toradex/common/Kconfig | 18 + board/toradex/common/Makefile | 1 + board/toradex/common/tdx-cfg-block.c | 402 ++++++++++++++++-- board/toradex/common/tdx-cfg-block.h | 16 + board/toradex/common/tdx-common.c | 54 +++ board/toradex/common/tdx-common.h | 4 + board/toradex/common/tdx-eeprom.c | 90 ++++ board/toradex/common/tdx-eeprom.h | 14 + board/toradex/verdin-imx8mm/Kconfig | 6 + configs/colibri-imx6ull_defconfig | 1 + configs/colibri_imx7_defconfig | 2 + configs/colibri_imx7_emmc_defconfig | 2 + configs/verdin-imx8mm_defconfig | 1 + 24 files changed, 730 insertions(+), 194 deletions(-) create mode 100644 arch/arm/dts/imx7-colibri-u-boot.dtsi create mode 100644 board/toradex/common/tdx-eeprom.c create mode 100644 board/toradex/common/tdx-eeprom.h -- 2.17.1

4 33

[PATCH 1/2] imx8m: ddrphy_utils: Improve coding style
by Fabio Estevam 27 Jul '20

27 Jul '20

Currently checkpatch is not happy about this file: total: 14 errors, 2 warnings, 7 checks, 359 lines checked Improve the coding style so that it can now report: total: 0 errors, 0 warnings, 6 checks, 360 lines checked Reported-by: Tom Rini <trini(a)konsulko.com> Signed-off-by: Fabio Estevam <festevam(a)gmail.com> --- drivers/ddr/imx/imx8m/ddrphy_utils.c | 29 ++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/ddr/imx/imx8m/ddrphy_utils.c b/drivers/ddr/imx/imx8m/ddrphy_utils.c index 20ae47bfb5..0f8baefb1f 100644 --- a/drivers/ddr/imx/imx8m/ddrphy_utils.c +++ b/drivers/ddr/imx/imx8m/ddrphy_utils.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* -* Copyright 2018 NXP -*/ + * Copyright 2018 NXP + */ #include <common.h> #include <errno.h> @@ -201,7 +201,7 @@ unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr) } unsigned int look_for_max(unsigned int data[], - unsigned int addr_start, unsigned int addr_end) + unsigned int addr_start, unsigned int addr_end) { unsigned int i, imax = 0; @@ -233,9 +233,9 @@ void get_trained_CDD(u32 fsp) if (i == 0) { cdd_cha[0] = (tmp >> 8) & 0xff; } else if (i == 6) { - cdd_cha[11]=tmp & 0xff; + cdd_cha[11] = tmp & 0xff; } else { - cdd_chb[ i * 2 - 1] = tmp & 0xff; + cdd_chb[i * 2 - 1] = tmp & 0xff; cdd_chb[i * 2] = (tmp >> 8) & 0xff; } } @@ -254,7 +254,8 @@ void get_trained_CDD(u32 fsp) g_cdd_ww_max[fsp] = cdd_cha_ww_max > cdd_chb_ww_max ? cdd_cha_ww_max : cdd_chb_ww_max; } else { unsigned int ddr4_cdd[64]; - for( i = 0; i < 29; i++) { + + for (i = 0; i < 29; i++) { tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x54012 + i) * 4); ddr4_cdd[i * 2] = tmp & 0xff; ddr4_cdd[i * 2 + 1] = (tmp >> 8) & 0xff; @@ -269,18 +270,18 @@ void get_trained_CDD(u32 fsp) void update_umctl2_rank_space_setting(unsigned int pstat_num) { - unsigned int i,ddr_type; + unsigned int i, ddr_type; unsigned int addr_slot, rdata, tmp, tmp_t; - unsigned int ddrc_w2r,ddrc_r2w,ddrc_wr_gap,ddrc_rd_gap; + unsigned int ddrc_w2r, ddrc_r2w, ddrc_wr_gap, ddrc_rd_gap; ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f; for (i = 0; i < pstat_num; i++) { addr_slot = i ? (i + 1) * 0x1000 : 0; if (ddr_type == 0x20) { /* update r2w:[13:8], w2r:[5:0] */ - rdata=reg32_read(DDRC_DRAMTMG2(0) + addr_slot); + rdata = reg32_read(DDRC_DRAMTMG2(0) + addr_slot); ddrc_w2r = rdata & 0x3f; - if(is_imx8mp()) + if (is_imx8mp()) tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1); else tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1) + 1; @@ -297,7 +298,7 @@ void update_umctl2_rank_space_setting(unsigned int pstat_num) reg32_write((DDRC_DRAMTMG2(0) + addr_slot), tmp_t); } else { /* update w2r:[5:0] */ - rdata=reg32_read(DDRC_DRAMTMG9(0) + addr_slot); + rdata = reg32_read(DDRC_DRAMTMG9(0) + addr_slot); ddrc_w2r = rdata & 0x3f; if (is_imx8mp()) tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1); @@ -310,7 +311,7 @@ void update_umctl2_rank_space_setting(unsigned int pstat_num) /* update r2w:[13:8] */ rdata = reg32_read(DDRC_DRAMTMG2(0) + addr_slot); ddrc_r2w = (rdata >> 8) & 0x3f; - if(is_imx8mp()) + if (is_imx8mp()) tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1); else tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1) + 1; @@ -324,7 +325,7 @@ void update_umctl2_rank_space_setting(unsigned int pstat_num) /* update rankctl: wr_gap:11:8; rd:gap:7:4; quasi-dymic, doc wrong(static) */ rdata = reg32_read(DDRC_RANKCTL(0) + addr_slot); ddrc_wr_gap = (rdata >> 8) & 0xf; - if(is_imx8mp()) + if (is_imx8mp()) tmp = ddrc_wr_gap + (g_cdd_ww_max[i] >> 1); else tmp = ddrc_wr_gap + (g_cdd_ww_max[i] >> 1) + 1; @@ -342,7 +343,7 @@ void update_umctl2_rank_space_setting(unsigned int pstat_num) } } - if(is_imx8mq()) { + if (is_imx8mq()) { /* update rankctl: wr_gap:11:8; rd:gap:7:4; quasi-dymic, doc wrong(static) */ rdata = reg32_read(DDRC_RANKCTL(0)); ddrc_wr_gap = (rdata >> 8) & 0xf; -- 2.17.1

4 7

[U-Boot] [PATCH] board: Add support for iMX8QXP AI_ML board
by Manivannan Sadhasivam 27 Jul '20

27 Jul '20

This commit adds initial board support for iMX8QXP AI_ML board from Einfochips. This board is one of the 96Boards Consumer Edition and AI boards of the 96Boards family based on i.MX8QXP SoC from NXP/Freescale. This initial supports contains following peripherals which are tested and known to work: 1. Debug serial via UART2 2. SD card 3. Ethernet More information about this board can be found in arrow website: https://www.arrow.com/en/products/imx8-ai-ml/arrow-development-tools Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam(a)linaro.org> Reviewed-by: Peng Fan <peng.fan(a)nxp.com> --- arch/arm/mach-imx/imx8/Kconfig | 6 ++ board/einfochips/imx8qxp_ai_ml/Kconfig | 21 ++++ board/einfochips/imx8qxp_ai_ml/MAINTAINERS | 6 ++ board/einfochips/imx8qxp_ai_ml/Makefile | 8 ++ board/einfochips/imx8qxp_ai_ml/README | 49 ++++++++++ .../einfochips/imx8qxp_ai_ml/imx8qxp_ai_ml.c | 78 +++++++++++++++ board/einfochips/imx8qxp_ai_ml/imximage.cfg | 24 +++++ board/einfochips/imx8qxp_ai_ml/spl.c | 39 ++++++++ configs/imx8qxp_ai_ml_defconfig | 83 ++++++++++++++++ include/configs/imx8qxp_ai_ml.h | 95 +++++++++++++++++++ 10 files changed, 409 insertions(+) create mode 100644 board/einfochips/imx8qxp_ai_ml/Kconfig create mode 100644 board/einfochips/imx8qxp_ai_ml/MAINTAINERS create mode 100644 board/einfochips/imx8qxp_ai_ml/Makefile create mode 100644 board/einfochips/imx8qxp_ai_ml/README create mode 100644 board/einfochips/imx8qxp_ai_ml/imx8qxp_ai_ml.c create mode 100644 board/einfochips/imx8qxp_ai_ml/imximage.cfg create mode 100644 board/einfochips/imx8qxp_ai_ml/spl.c create mode 100644 configs/imx8qxp_ai_ml_defconfig create mode 100644 include/configs/imx8qxp_ai_ml.h diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index cdb78afacf..25fe4e2be0 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -55,6 +55,11 @@ config TARGET_COLIBRI_IMX8X select BOARD_LATE_INIT select IMX8QXP +config TARGET_IMX8QXP_AI_ML + bool "Support i.MX8QXP AI_ML board" + select BOARD_EARLY_INIT_F + select IMX8QXP + config TARGET_IMX8QM_MEK bool "Support i.MX8QM MEK board" select BOARD_LATE_INIT @@ -73,6 +78,7 @@ config TARGET_IMX8QXP_MEK endchoice +source "board/einfochips/imx8qxp_ai_ml/Kconfig" source "board/freescale/imx8qm_mek/Kconfig" source "board/freescale/imx8qxp_mek/Kconfig" source "board/advantech/imx8qm_rom7720_a1/Kconfig" diff --git a/board/einfochips/imx8qxp_ai_ml/Kconfig b/board/einfochips/imx8qxp_ai_ml/Kconfig new file mode 100644 index 0000000000..b6806b8859 --- /dev/null +++ b/board/einfochips/imx8qxp_ai_ml/Kconfig @@ -0,0 +1,21 @@ +if TARGET_IMX8QXP_AI_ML + +config SYS_BOARD + default "imx8qxp_ai_ml" + +config SYS_VENDOR + default "einfochips" + +config SYS_CONFIG_NAME + default "imx8qxp_ai_ml" + +config SYS_MALLOC_LEN + default 0x2400000 + +config ENV_SIZE + default 0x1000 + +config ENV_OFFSET + default 0x400000 + +endif diff --git a/board/einfochips/imx8qxp_ai_ml/MAINTAINERS b/board/einfochips/imx8qxp_ai_ml/MAINTAINERS new file mode 100644 index 0000000000..add0bd9431 --- /dev/null +++ b/board/einfochips/imx8qxp_ai_ml/MAINTAINERS @@ -0,0 +1,6 @@ +i.MX8QXP AI_ML BOARD +M: Manivannan Sadhasivam <manivannan.sadhasivam(a)linaro.org> +S: Maintained +F: board/einfochips/imx8qxp_ai_ml/ +F: include/configs/imx8qxp_ai_ml.h +F: configs/imx8qxp_ai_ml_defconfig diff --git a/board/einfochips/imx8qxp_ai_ml/Makefile b/board/einfochips/imx8qxp_ai_ml/Makefile new file mode 100644 index 0000000000..e08774dc6e --- /dev/null +++ b/board/einfochips/imx8qxp_ai_ml/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2019 Linaro Ltd. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8qxp_ai_ml.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/einfochips/imx8qxp_ai_ml/README b/board/einfochips/imx8qxp_ai_ml/README new file mode 100644 index 0000000000..488920580f --- /dev/null +++ b/board/einfochips/imx8qxp_ai_ml/README @@ -0,0 +1,49 @@ +U-Boot for the Einfochips i.MX8QXP AI_ML board + +Quick Start +=========== + +- Get and Build the ARM Trusted firmware +- Get scfw_tcm.bin and ahab-container.img +- Build U-Boot +- Flash the binary into the SD card +- Boot + +Get and Build the ARM Trusted firmware +====================================== + +$ git clone https://source.codeaurora.org/external/imx/imx-atf +$ cd imx-atf/ +$ git checkout origin/imx_4.9.88_imx8qxp_beta2 -b imx_4.9.88_imx8qxp_beta2 +$ make PLAT=imx8qxp bl31 + +Get scfw_tcm.bin and ahab-container.img +======================================= + +$ wget https://raw.githubusercontent.com/96boards-ai-ml/binaries/master/mx8qx-aiml… +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.1.bin +$ chmod +x firmware-imx-8.1.bin +$ ./firmware-imx-8.1.bin + +Copy the following binaries to U-Boot folder: + +$ cp imx-atf/build/imx8qxp/release/bl31.bin . +$ cp firmware-imx-8.1/firmware/seco/mx8qx-ahab-container.img . + +Build U-Boot +============ + +$ make imx8qxp_ai_ml_defconfig +$ make u-boot-dtb.imx + +Flash the binary into the SD card +================================= + +Burn the u-boot-dtb.imx binary to SD card offset 32KB: + +$ sudo dd if=u-boot-dtb.imx of=/dev/sd[x] bs=1024 seek=32 + +Boot +==== + +Set Boot switch SW2: 1100. diff --git a/board/einfochips/imx8qxp_ai_ml/imx8qxp_ai_ml.c b/board/einfochips/imx8qxp_ai_ml/imx8qxp_ai_ml.c new file mode 100644 index 0000000000..465fea65f8 --- /dev/null +++ b/board/einfochips/imx8qxp_ai_ml/imx8qxp_ai_ml.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Copyright 2019 Linaro Ltd. + */ + +#include <common.h> +#include <errno.h> +#include <linux/libfdt.h> +#include <fsl_esdhc.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/sci/sci.h> +#include <asm/arch/imx8-pins.h> +#include <asm/arch/iomux.h> +#include <asm/arch/sys_proto.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + sc_pm_clock_rate_t rate = SC_80MHZ; + int ret; + + /* Set UART2 clock root to 80 MHz */ + ret = sc_pm_setup_uart(SC_R_UART_2, rate); + if (ret) + return ret; + + return 0; +} + +#if IS_ENABLED(CONFIG_FEC_MXC) +#include <miiphy.h> + +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +int checkboard(void) +{ + puts("Board: iMX8QXP AI_ML\n"); + + build_info(); + print_bootinfo(); + + return 0; +} + +int board_init(void) +{ + return 0; +} + +/* Board specific reset that is system reset */ + +void reset_cpu(ulong addr) +{ + /* TODO */ +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + return 0; +} +#endif diff --git a/board/einfochips/imx8qxp_ai_ml/imximage.cfg b/board/einfochips/imx8qxp_ai_ml/imximage.cfg new file mode 100644 index 0000000000..4fc5ade313 --- /dev/null +++ b/board/einfochips/imx8qxp_ai_ml/imximage.cfg @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + * + * Refer doc/README.imx8image for more details about how-to configure + * and create imx8image boot image + */ + +#define __ASSEMBLY__ + +/* Boot from SD, sector size 0x400 */ +BOOT_FROM SD 0x400 +/* SoC type IMX8QX */ +SOC_TYPE IMX8QX +/* Append seco container image */ +APPEND mx8qx-ahab-container.img +/* Create the 2nd container */ +CONTAINER +/* Add scfw image with exec attribute */ +IMAGE SCU mx8qx-aiml-scfw-tcm.bin +/* Add ATF image with exec attribute */ +IMAGE A35 bl31.bin 0x80000000 +/* Add U-Boot image with load attribute */ +DATA A35 u-boot-dtb.bin 0x80020000 diff --git a/board/einfochips/imx8qxp_ai_ml/spl.c b/board/einfochips/imx8qxp_ai_ml/spl.c new file mode 100644 index 0000000000..2e6e0741e5 --- /dev/null +++ b/board/einfochips/imx8qxp_ai_ml/spl.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Copyright 2019 Linaro Ltd. + * + */ + +#include <common.h> +#include <dm.h> +#include <spl.h> +#include <dm/uclass.h> +#include <dm/device.h> +#include <dm/uclass-internal.h> +#include <dm/device-internal.h> +#include <dm/lists.h> + +DECLARE_GLOBAL_DATA_PTR; + +void spl_board_init(void) +{ + arch_cpu_init(); + + timer_init(); + + preloader_console_init(); + + puts("Normal Boot\n"); +} + +void board_init_f(ulong dummy) +{ + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); +} diff --git a/configs/imx8qxp_ai_ml_defconfig b/configs/imx8qxp_ai_ml_defconfig new file mode 100644 index 0000000000..e20a0c783e --- /dev/null +++ b/configs/imx8qxp_ai_ml_defconfig @@ -0,0 +1,83 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_TARGET_IMX8QXP_AI_ML=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=4 +CONFIG_SPL=y +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/einfochips/imx8qxp_ai_ml/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_FAT_WRITE=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-ai_ml" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_DM_GPIO=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/imx8qxp_ai_ml.h b/include/configs/imx8qxp_ai_ml.h new file mode 100644 index 0000000000..bdac710103 --- /dev/null +++ b/include/configs/imx8qxp_ai_ml.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + * Copyright 2019 Linaro Ltd. + */ + +#ifndef __IMX8QXP_AI_ML_H +#define __IMX8QXP_AI_ML_H + +#include <linux/sizes.h> +#include <asm/arch/imx-regs.h> + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_MAX_SIZE (124 * SZ_1K) +#define CONFIG_SYS_MONITOR_LEN (SZ_1K * SZ_1K) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x250 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0 + +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x013E000 +#define CONFIG_SPL_BSS_START_ADDR 0x00128000 +#define CONFIG_SPL_BSS_MAX_SIZE SZ_4K /* 4 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x00120000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */ +#define CONFIG_SERIAL_LPUART_BASE 0x5a080000 +#define CONFIG_MALLOC_F_ADDR 0x00120000 + +#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#define CONFIG_OF_SEPARATE +#endif + +#define CONFIG_REMAKE_ELF + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_BOARD_SETUP + +#define CONFIG_FSL_USDHC + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(DHCP, dhcp, na) + +#include <config_distro_bootcmd.h> +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttyLP2 earlycon\0" \ + "fdt_addr_r=0x83000000\0" \ + "kernel_addr_r=0x81000000\0" \ + "ramdisk_addr_r=0x94400000\0" \ + "scriptaddr=0x89000000\0" \ + "fdtfile=imx8qxp-ai_ml.dtb\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "image=Image\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp" \ + "\0" \ + "nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \ + "imx8qxp-ai_ml/${fdt_file}; booti ${loadaddr} - ${fdt_addr}\0" \ + BOOTENV + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x80280000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + +/* USDHC2 is the SD card interface */ +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 +#define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */ + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +/* Networking */ +#define CONFIG_FEC_XCV_TYPE RGMII +#define FEC_QUIRK_ENET_MAC + +#endif /* __IMX8QXP_AI_ML_H */ -- 2.17.1

3 3

[PULL] u-boot-sh/net
by Marek Vasut 27 Jul '20

27 Jul '20

More networking DM conversion (this is the last driver). Any news on Joe ? The following changes since commit ada61f1ee2a4eaa1b29d699b5ba940483171df8a: Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv (2020-07-24 08:43:08 -0400) are available in the Git repository at: git://git.denx.de/u-boot-sh.git net for you to fetch changes up to f23a785cfb451f3fcb457ed1f9141907dce7dd77: net: dc2114x: Add DM support (2020-07-25 14:20:56 +0200) ---------------------------------------------------------------- Marek Vasut (12): net: dc2114x: Use PCI_DEVICE() to define PCI device compat list net: dc2114x: Support all DC2114x net: dc2114x: Add Kconfig entries net: dc2114x: Drop update_srom() net: dc2114x: Use standard I/O accessors net: dc2114x: Introduce private data net: dc2114x: Pass private data around net: dc2114x: Pass PCI BDF into phys_to_bus() net: dc2114x: Add RX/TX rings into the private data net: dc2114x: Split RX path net: dc2114x: Split common parts of non-DM functions out net: dc2114x: Add DM support README | 3 - configs/integratorap_cm720t_defconfig | 1 + configs/integratorap_cm920t_defconfig | 1 + configs/integratorap_cm926ejs_defconfig | 1 + configs/integratorap_cm946es_defconfig | 1 + drivers/net/Kconfig | 6 + drivers/net/dc2114x.c | 611 ++++++++++++++++++++++++++++++++++++++++++++++++++++++--------------------------------------- include/configs/MPC8349EMDS.h | 1 - include/configs/MPC8349EMDS_SDRAM.h | 1 - include/configs/MPC8540ADS.h | 1 - include/configs/MPC8541CDS.h | 1 - include/configs/MPC8544DS.h | 1 - include/configs/MPC8548CDS.h | 1 - include/configs/MPC8555CDS.h | 1 - include/configs/MPC8560ADS.h | 1 - include/configs/MPC8568MDS.h | 1 - include/configs/MPC8569MDS.h | 1 - include/configs/MPC8572DS.h | 1 - include/configs/MPC8641HPCN.h | 1 - include/configs/TQM834x.h | 1 - include/configs/caddy2.h | 1 - include/configs/integratorap.h | 1 - include/configs/sbc8349.h | 1 - include/configs/sbc8548.h | 1 - include/configs/sbc8641d.h | 1 - include/configs/vme8349.h | 1 - scripts/config_whitelist.txt | 1 - 27 files changed, 366 insertions(+), 278 deletions(-)

3 3

[PULL] u-boot-sh/master
by Marek Vasut 27 Jul '20

27 Jul '20

The following changes since commit ada61f1ee2a4eaa1b29d699b5ba940483171df8a: Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv (2020-07-24 08:43:08 -0400) are available in the Git repository at: git://git.denx.de/u-boot-sh.git master for you to fetch changes up to 59028798ab5a1242cc9d578fa5c50a9f057630b2: ARM: rmobile: Add Beacon EmbeddedWorks RZG2M Dev Kit (2020-07-25 14:19:26 +0200) ---------------------------------------------------------------- Adam Ford (6): ARM: renesas: Add basic R8A774A1 Support ARM: dts: r8a774a1: Import DTS from Linux 5.8-rc1 clk: renesas: Add R8A774A1 clock tables pinctrl: renesas: Enable R8A774A1 PFC tables mmc: renesas-sdhi: Enable support for R8A774A1 ARM: rmobile: Add Beacon EmbeddedWorks RZG2M Dev Kit arch/arm/dts/Makefile | 1 + arch/arm/dts/beacon-renesom-baseboard.dtsi | 597 ++++++++++++++++++ arch/arm/dts/beacon-renesom-som.dtsi | 312 +++++++++ arch/arm/dts/r8a774a1-beacon-rzg2m-kit-u-boot.dtsi | 34 + arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts | 15 + arch/arm/dts/r8a774a1.dtsi | 2787 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-rmobile/Kconfig.64 | 9 + board/beacon/beacon-rzg2m/Kconfig | 15 + board/beacon/beacon-rzg2m/MAINTAINERS | 6 + board/beacon/beacon-rzg2m/Makefile | 9 + board/beacon/beacon-rzg2m/beacon-rzg2m.c | 52 ++ configs/r8a774a1_beacon_defconfig | 64 ++ drivers/clk/renesas/Kconfig | 7 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r8a774a1-cpg-mssr.c | 339 ++++++++++ drivers/clk/renesas/rcar-gen3-cpg.h | 2 + drivers/mmc/renesas-sdhi.c | 2 +- drivers/pinctrl/renesas/Kconfig | 10 + drivers/pinctrl/renesas/Makefile | 1 + drivers/pinctrl/renesas/pfc.c | 11 + drivers/pinctrl/renesas/sh_pfc.h | 1 + include/configs/beacon-rzg2m.h | 89 +++ include/dt-bindings/clock/r8a774a1-cpg-mssr.h | 65 ++ include/dt-bindings/power/r8a774a1-sysc.h | 33 + 24 files changed, 4461 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/beacon-renesom-baseboard.dtsi create mode 100644 arch/arm/dts/beacon-renesom-som.dtsi create mode 100644 arch/arm/dts/r8a774a1-beacon-rzg2m-kit-u-boot.dtsi create mode 100644 arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts create mode 100644 arch/arm/dts/r8a774a1.dtsi create mode 100644 board/beacon/beacon-rzg2m/Kconfig create mode 100644 board/beacon/beacon-rzg2m/MAINTAINERS create mode 100644 board/beacon/beacon-rzg2m/Makefile create mode 100644 board/beacon/beacon-rzg2m/beacon-rzg2m.c create mode 100644 configs/r8a774a1_beacon_defconfig create mode 100644 drivers/clk/renesas/r8a774a1-cpg-mssr.c create mode 100644 include/configs/beacon-rzg2m.h create mode 100644 include/dt-bindings/clock/r8a774a1-cpg-mssr.h create mode 100644 include/dt-bindings/power/r8a774a1-sysc.h

2 1

[PATCH] travis: Update to python3-pyelftools
by Tom Rini 27 Jul '20

27 Jul '20

With the migration to python3 for all of our tests, we need python3-pyelftools and not python2-pyelftools to be installed. Signed-off-by: Tom Rini <trini(a)konsulko.com> --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 96fd55fe1ef1..0bb5aeaeb192 100644 --- a/.travis.yml +++ b/.travis.yml @@ -23,7 +23,7 @@ addons: - build-essential - libsdl2-dev - python - - python-pyelftools + - python3-pyelftools - python3-sphinx - python3-virtualenv - python3-pip -- 2.17.1

1 0

Please pull u-boot-dm
by Simon Glass 27 Jul '20

27 Jul '20

Hi Tom, https://gitlab.denx.de/u-boot/custodians/u-boot-dm/pipelines/4139 The following changes since commit 7303ba10a4a39852b9ba356fae5656b43122eec6: Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86 (2020-07-20 09:25:32 -0400) are available in the Git repository at: git://git.denx.de/u-boot-dm.git tags/dm-pull-20jul20 for you to fetch changes up to 60e7fa8b3b8538aae1e644dac61d5e4076901edb: treewide: convert devfdt_get_addr() to dev_read_addr() (2020-07-20 11:37:47 -0600) ---------------------------------------------------------------- binman support for FIT new UCLASS_SOC patman switch 'test' command minor fdt fixes patman usability improvements ---------------------------------------------------------------- Dave Gerlach (9): doc: Add new doc for soc ID driver model dm: soc: Introduce UCLASS_SOC for SOC ID and attribute matching test: Add tests for SOC uclass dm: soc: Introduce soc_ti_k3 driver for TI K3 SoCs arm: dts: k3-am65-wakeup: Introduce chipid node arm: dts: k3-j721e-mcu-wakeup: Introduce chipid node configs: am65x_evm: Enable CONFIG_SOC_DEVICE and CONFIG_SOC_DEVICE_TI_K3 configs: j721e_evm: Enable CONFIG_SOC_DEVICE and CONFIG_SOC_DEVICE_TI_K3 arm: mach-k3: Use SOC driver for device identification Heinrich Schuchardt (1): test/dm: check if devices exist Masahiro Yamada (6): fdt_support: add static to fdt_node_set_part_info() fdt_support: call mtdparts_init() after finding MTD node to fix up fdt_support: skip MTD node with "disabled" in fdt_fixup_mtdparts() treewide: convert (void *)devfdt_get_addr() to dev_read_addr_ptr() treewide: remove (phys_addr_t) casts from devfdt_get_addr() treewide: convert devfdt_get_addr() to dev_read_addr() Michal Simek (3): ARM: rmobile: Switch back to fdtdec_setup_memory/banksize_fdt() Revert "lib: fdt: Split fdtdec_setup_memory_banksize()" Revert "lib: fdt: Split fdtdec_setup_mem_size_base()" Nicolas Boichat (2): patman: Make sure sendemail.suppresscc is (un)set correctly patman: When no tracking branch is provided, tell the user Patrick Delaunay (2): patman: Detect unexpected END Add information for skipped commit options Philippe Reynes (1): lib: libfdt: fdt_region: avoid NULL pointer access Simon Glass (34): patman: Use test_util to show test results patman: Move main code out to a control module patman: Add a test that uses gitpython patman: Allow creating patches for another branch patman: Allow skipping patches at the end patman: Convert to ArgumentParser patman: Allow different commands patman: Add a 'test' subcommand patman: Allow disabling 'bright' mode with Print output patman: Support collecting response tags in Patchstream patman: Add a -D option to enable debugging dm: core Fix long line in device_bind_common() .gitignore: Ignore Python 3 cache directories binman: Output errors to stderr binman: cbfs: Fix IFWI typo binman: Correct the search patch for pylibfdt binman: Specify the toolpath when running test coverage binman: Set a default toolpath binman: Add support for calling mkimage binman: Fix a few typos in the entry docs binman: Adjust pylibfdt for incremental build binman: Re-enable concurrent tests binman: Use super() instead of specifying parent type binman: Add an etype for external binary blobs binman: Convert existing binary blobs to blob_ext binman: Allow external binaries to be missing patman: Update errors and warnings to use stderr binman: Detect when valid images are not produced binman: Allow missing Intel blobs binman: Allow zero-length entries to overlap mkimage: Allow updating the FIT timestamp dtoc: Allow adding variable-sized data to a dtb binman: Add support for generating a FIT cpu: Convert the methods to use a const udevice * .azure-pipelines.yml | 2 +- .gitignore | 3 + .gitlab-ci.yml | 2 +- .travis.yml | 2 +- arch/arm/dts/k3-am65-wakeup.dtsi | 5 + arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 4 + .../arm/dts/k3-j721e-common-proc-board-u-boot.dtsi | 4 + arch/arm/dts/k3-j721e-mcu-wakeup.dtsi | 5 + arch/arm/mach-k3/common.c | 48 ++--- arch/arm/mach-k3/common.h | 6 - arch/arm/mach-k3/include/mach/hardware.h | 1 - arch/arm/mach-snapdragon/clock-snapdragon.c | 2 +- arch/arm/mach-snapdragon/pinctrl-snapdragon.c | 2 +- arch/nios2/cpu/cpu.c | 8 +- arch/sandbox/dts/test.dts | 4 + arch/x86/cpu/apollolake/cpu.c | 2 +- arch/x86/cpu/baytrail/cpu.c | 4 +- arch/x86/cpu/broadwell/cpu_full.c | 4 +- arch/x86/cpu/cpu_x86.c | 6 +- arch/x86/cpu/ivybridge/model_206ax.c | 5 +- arch/x86/cpu/qemu/cpu.c | 4 +- arch/x86/include/asm/cpu_x86.h | 6 +- board/renesas/rcar-common/common.c | 4 +- common/fdt_region.c | 2 + common/fdt_support.c | 32 ++-- configs/am65x_evm_a53_defconfig | 2 + configs/am65x_evm_r5_defconfig | 2 + configs/am65x_hs_evm_a53_defconfig | 2 + configs/am65x_hs_evm_r5_defconfig | 2 + configs/j721e_evm_a72_defconfig | 2 + configs/j721e_evm_r5_defconfig | 2 + configs/j721e_hs_evm_a72_defconfig | 2 + configs/j721e_hs_evm_r5_defconfig | 2 + configs/sandbox64_defconfig | 1 + configs/sandbox_defconfig | 1 + configs/sandbox_flattree_defconfig | 1 + configs/sandbox_spl_defconfig | 1 + doc/driver-model/index.rst | 1 + doc/driver-model/soc-framework.rst | 68 +++++++ doc/mkimage.1 | 9 + drivers/adc/exynos-adc.c | 2 +- drivers/ata/dwc_ahci.c | 2 +- drivers/clk/altera/clk-agilex.c | 2 +- drivers/clk/altera/clk-arria10.c | 2 +- drivers/clk/exynos/clk-exynos7420.c | 4 +- drivers/clk/renesas/clk-rcar-gen2.c | 2 +- drivers/clk/renesas/clk-rcar-gen3.c | 2 +- drivers/clk/uniphier/clk-uniphier-core.c | 2 +- drivers/core/device.c | 3 +- drivers/cpu/bmips_cpu.c | 8 +- drivers/cpu/cpu-uclass.c | 8 +- drivers/cpu/cpu_sandbox.c | 8 +- drivers/cpu/imx8_cpu.c | 8 +- drivers/cpu/mpc83xx_cpu.c | 26 +-- drivers/cpu/riscv_cpu.c | 8 +- drivers/dma/ti-edma3.c | 2 +- drivers/gpio/altera_pio.c | 2 +- drivers/gpio/atmel_pio4.c | 2 +- drivers/gpio/bcm2835_gpio.c | 2 +- drivers/gpio/da8xx_gpio.c | 2 +- drivers/gpio/gpio-rcar.c | 2 +- drivers/gpio/gpio-rza1.c | 2 +- drivers/gpio/gpio-uniphier.c | 2 +- drivers/gpio/msm_gpio.c | 2 +- drivers/gpio/mvebu_gpio.c | 2 +- drivers/gpio/mxc_gpio.c | 2 +- drivers/gpio/mxs_gpio.c | 2 +- drivers/gpio/omap_gpio.c | 4 +- drivers/gpio/pm8916_gpio.c | 2 +- drivers/gpio/s5p_gpio.c | 4 +- drivers/gpio/sifive-gpio.c | 2 +- drivers/gpio/sunxi_gpio.c | 2 +- drivers/gpio/vybrid_gpio.c | 2 +- drivers/i2c/at91_i2c.c | 2 +- drivers/i2c/davinci_i2c.c | 2 +- drivers/i2c/exynos_hs_i2c.c | 2 +- drivers/i2c/i2c-uniphier-f.c | 2 +- drivers/i2c/i2c-uniphier.c | 2 +- drivers/i2c/imx_lpi2c.c | 2 +- drivers/i2c/iproc_i2c.c | 2 +- drivers/i2c/mxc_i2c.c | 2 +- drivers/i2c/omap24xx_i2c.c | 2 +- drivers/i2c/s3c24x0_i2c.c | 2 +- drivers/input/tegra-kbc.c | 2 +- drivers/mailbox/tegra-hsp.c | 2 +- drivers/misc/altera_sysid.c | 2 +- drivers/misc/imx8/scu.c | 2 +- drivers/misc/microchip_flexcom.c | 2 +- drivers/mmc/aspeed_sdhci.c | 2 +- drivers/mmc/atmel_sdhci.c | 2 +- drivers/mmc/bcm2835_sdhci.c | 2 +- drivers/mmc/bcm2835_sdhost.c | 2 +- drivers/mmc/bcmstb_sdhci.c | 2 +- drivers/mmc/ftsdc010_mci.c | 2 +- drivers/mmc/hi6220_dw_mmc.c | 2 +- drivers/mmc/iproc_sdhci.c | 2 +- drivers/mmc/jz_mmc.c | 2 +- drivers/mmc/meson_gx_mmc.c | 2 +- drivers/mmc/msm_sdhci.c | 2 +- drivers/mmc/mv_sdhci.c | 2 +- drivers/mmc/omap_hsmmc.c | 4 +- drivers/mmc/sdhci-cadence.c | 2 +- drivers/mmc/sh_mmcif.c | 2 +- drivers/mmc/sh_sdhi.c | 2 +- drivers/mmc/socfpga_dw_mmc.c | 2 +- drivers/mmc/sti_sdhci.c | 2 +- drivers/mmc/tangier_sdhci.c | 2 +- drivers/mmc/tmio-common.c | 2 +- drivers/mmc/xenon_sdhci.c | 2 +- drivers/net/ag7xxx.c | 2 +- drivers/net/dwc_eth_qos.c | 4 +- drivers/net/ethoc.c | 2 +- drivers/net/fec_mxc.c | 2 +- drivers/net/fsl_mcdmafec.c | 2 +- drivers/net/ftgmac100.c | 2 +- drivers/net/ftmac100.c | 2 +- drivers/net/ks8851_mll.c | 2 +- drivers/net/mcffec.c | 2 +- drivers/net/mtk_eth.c | 2 +- drivers/net/mvgbe.c | 2 +- drivers/net/mvneta.c | 2 +- drivers/net/ravb.c | 2 +- drivers/net/sh_eth.c | 2 +- drivers/net/smc911x.c | 2 +- drivers/net/sni_ave.c | 2 +- drivers/net/sun8i_emac.c | 2 +- drivers/net/sunxi_emac.c | 2 +- drivers/net/ti/keystone_net.c | 2 +- drivers/net/xilinx_axi_emac.c | 2 +- drivers/net/xilinx_emaclite.c | 2 +- drivers/pci_endpoint/pcie-cadence-ep.c | 2 +- drivers/pinctrl/ath79/pinctrl_ar933x.c | 2 +- drivers/pinctrl/ath79/pinctrl_qca953x.c | 2 +- drivers/pinctrl/exynos/pinctrl-exynos.c | 2 +- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 2 +- drivers/pinctrl/pinctrl-at91-pio4.c | 2 +- drivers/pinctrl/renesas/pfc-r7s72100.c | 2 +- drivers/pinctrl/renesas/pfc.c | 2 +- drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 2 +- drivers/pwm/exynos_pwm.c | 2 +- drivers/pwm/pwm-imx.c | 2 +- drivers/pwm/pwm-mtk.c | 2 +- drivers/pwm/sunxi_pwm.c | 2 +- drivers/reset/reset-uniphier.c | 2 +- drivers/rtc/mvrtc.c | 2 +- drivers/serial/altera_jtag_uart.c | 2 +- drivers/serial/altera_uart.c | 2 +- drivers/serial/atmel_usart.c | 2 +- drivers/serial/serial_ar933x.c | 2 +- drivers/serial/serial_arc.c | 2 +- drivers/serial/serial_bcm283x_mu.c | 2 +- drivers/serial/serial_lpuart.c | 2 +- drivers/serial/serial_mcf.c | 2 +- drivers/serial/serial_meson.c | 2 +- drivers/serial/serial_msm.c | 2 +- drivers/serial/serial_mxc.c | 2 +- drivers/serial/serial_pl01x.c | 2 +- drivers/serial/serial_s5p.c | 2 +- drivers/serial/serial_sh.c | 2 +- drivers/serial/serial_sti_asc.c | 2 +- drivers/serial/serial_stm32.c | 2 +- drivers/serial/serial_uniphier.c | 2 +- drivers/serial/serial_xuartlite.c | 2 +- drivers/soc/Kconfig | 16 ++ drivers/soc/Makefile | 3 + drivers/soc/soc-uclass.c | 102 +++++++++++ drivers/soc/soc_sandbox.c | 56 ++++++ drivers/soc/soc_ti_k3.c | 124 +++++++++++++ drivers/spi/altera_spi.c | 2 +- drivers/spi/atcspi200_spi.c | 2 +- drivers/spi/ath79_spi.c | 2 +- drivers/spi/atmel_spi.c | 2 +- drivers/spi/cf_spi.c | 2 +- drivers/spi/davinci_spi.c | 2 +- drivers/spi/designware_spi.c | 2 +- drivers/spi/exynos_spi.c | 2 +- drivers/spi/fsl_dspi.c | 2 +- drivers/spi/kirkwood_spi.c | 2 +- drivers/spi/mtk_snfi_spi.c | 2 +- drivers/spi/mvebu_a3700_spi.c | 2 +- drivers/spi/mxc_spi.c | 2 +- drivers/spi/omap3_spi.c | 2 +- drivers/spi/spi-sunxi.c | 2 +- drivers/spi/tegra20_sflash.c | 2 +- drivers/spi/tegra20_slink.c | 2 +- drivers/spi/ti_qspi.c | 2 +- drivers/spi/zynq_spi.c | 2 +- drivers/spi/zynqmp_gqspi.c | 4 +- drivers/spmi/spmi-msm.c | 2 +- drivers/timer/ag101p_timer.c | 2 +- drivers/timer/altera_timer.c | 2 +- drivers/timer/atcpit100_timer.c | 2 +- drivers/timer/omap-timer.c | 2 +- drivers/usb/dwc3/dwc3-uniphier.c | 2 +- drivers/usb/host/ehci-atmel.c | 2 +- drivers/usb/host/ehci-exynos.c | 2 +- drivers/usb/host/ehci-fsl.c | 2 +- drivers/usb/host/ehci-marvell.c | 2 +- drivers/usb/host/ehci-mx5.c | 2 +- drivers/usb/host/ehci-mx6.c | 4 +- drivers/usb/host/ehci-omap.c | 2 +- drivers/usb/host/ehci-vf.c | 2 +- drivers/usb/host/ohci-da8xx.c | 2 +- drivers/usb/host/ohci-generic.c | 2 +- drivers/usb/host/xhci-exynos5.c | 2 +- drivers/usb/host/xhci-fsl.c | 2 +- drivers/usb/host/xhci-mvebu.c | 2 +- drivers/usb/host/xhci-rcar.c | 2 +- drivers/video/atmel_hlcdfb.c | 2 +- drivers/video/exynos/exynos_dp.c | 2 +- drivers/video/exynos/exynos_fb.c | 2 +- drivers/video/tegra.c | 2 +- drivers/w1/mxc_w1.c | 2 +- drivers/watchdog/omap_wdt.c | 2 +- drivers/watchdog/stm32mp_wdt.c | 2 +- include/cpu.h | 16 +- include/dm/uclass-id.h | 1 + include/fdtdec.h | 39 ---- include/soc.h | 145 +++++++++++++++ lib/fdtdec.c | 29 +-- scripts/dtc/pylibfdt/Makefile | 3 + test/dm/Makefile | 1 + test/dm/acpi.c | 3 + test/dm/core.c | 10 +- test/dm/devres.c | 1 + test/dm/soc.c | 120 +++++++++++++ test/dm/test-fdt.c | 2 + test/dm/virtio.c | 7 + test/run | 2 +- tools/binman/README.entries | 76 ++++++++ tools/binman/cmdline.py | 2 + tools/binman/control.py | 19 +- tools/binman/entry.py | 21 +++ tools/binman/etype/_testing.py | 9 +- tools/binman/etype/blob.py | 2 +- tools/binman/etype/blob_dtb.py | 6 +- tools/binman/etype/blob_ext.py | 39 ++++ tools/binman/etype/blob_named_by_arg.py | 2 +- tools/binman/etype/cbfs.py | 16 +- tools/binman/etype/cros_ec_rw.py | 4 +- tools/binman/etype/fdtmap.py | 2 +- tools/binman/etype/files.py | 2 +- tools/binman/etype/fill.py | 4 +- tools/binman/etype/fit.py | 164 +++++++++++++++++ tools/binman/etype/fmap.py | 2 +- tools/binman/etype/gbb.py | 2 +- tools/binman/etype/image_header.py | 4 +- tools/binman/etype/intel_cmc.py | 7 +- tools/binman/etype/intel_descriptor.py | 15 +- tools/binman/etype/intel_fit.py | 8 +- tools/binman/etype/intel_fit_ptr.py | 8 +- tools/binman/etype/intel_fsp.py | 7 +- tools/binman/etype/intel_fsp_m.py | 7 +- tools/binman/etype/intel_fsp_s.py | 7 +- tools/binman/etype/intel_fsp_t.py | 7 +- tools/binman/etype/intel_ifwi.py | 25 ++- tools/binman/etype/intel_me.py | 9 +- tools/binman/etype/intel_mrc.py | 7 +- tools/binman/etype/intel_refcode.py | 7 +- tools/binman/etype/intel_vbt.py | 7 +- tools/binman/etype/intel_vga.py | 7 +- tools/binman/etype/mkimage.py | 62 +++++++ .../etype/powerpc_mpc85xx_bootpg_resetvec.py | 5 +- tools/binman/etype/section.py | 58 ++++-- tools/binman/etype/text.py | 2 +- tools/binman/etype/u_boot.py | 2 +- tools/binman/etype/u_boot_dtb.py | 2 +- tools/binman/etype/u_boot_dtb_with_ucode.py | 4 +- tools/binman/etype/u_boot_elf.py | 4 +- tools/binman/etype/u_boot_img.py | 2 +- tools/binman/etype/u_boot_nodtb.py | 2 +- tools/binman/etype/u_boot_spl.py | 2 +- tools/binman/etype/u_boot_spl_bss_pad.py | 2 +- tools/binman/etype/u_boot_spl_dtb.py | 2 +- tools/binman/etype/u_boot_spl_elf.py | 2 +- tools/binman/etype/u_boot_spl_nodtb.py | 2 +- tools/binman/etype/u_boot_spl_with_ucode_ptr.py | 2 +- tools/binman/etype/u_boot_tpl.py | 2 +- tools/binman/etype/u_boot_tpl_dtb.py | 2 +- tools/binman/etype/u_boot_tpl_dtb_with_ucode.py | 2 +- tools/binman/etype/u_boot_tpl_elf.py | 2 +- tools/binman/etype/u_boot_tpl_with_ucode_ptr.py | 2 +- tools/binman/etype/u_boot_ucode.py | 2 +- tools/binman/etype/u_boot_with_ucode_ptr.py | 2 +- tools/binman/etype/vblock.py | 2 +- tools/binman/etype/x86_reset16.py | 2 +- tools/binman/etype/x86_reset16_spl.py | 2 +- tools/binman/etype/x86_reset16_tpl.py | 2 +- tools/binman/etype/x86_start16.py | 2 +- tools/binman/etype/x86_start16_spl.py | 2 +- tools/binman/etype/x86_start16_tpl.py | 2 +- tools/binman/ftest.py | 140 ++++++++++++++- tools/binman/image.py | 12 +- tools/binman/main.py | 18 +- tools/binman/test/156_mkimage.dts | 23 +++ tools/binman/test/157_blob_ext.dts | 14 ++ tools/binman/test/158_blob_ext_missing.dts | 16 ++ tools/binman/test/159_blob_ext_missing_sect.dts | 23 +++ tools/binman/test/160_pack_overlap_zero.dts | 18 ++ tools/binman/test/161_fit.dts | 62 +++++++ tools/binman/test/162_fit_external.dts | 64 +++++++ tools/dtoc/fdt.py | 17 +- tools/dtoc/test_fdt.py | 4 + tools/fit_image.c | 2 +- tools/imagetool.h | 1 + tools/mkimage.c | 5 +- tools/patman/checkpatch.py | 6 + tools/patman/commit.py | 14 ++ tools/patman/control.py | 178 +++++++++++++++++++ tools/patman/func_test.py | 169 +++++++++++++++++- tools/patman/gitutil.py | 48 ++++- tools/patman/main.py | 196 +++++++++------------ tools/patman/patchstream.py | 36 +++- tools/patman/series.py | 2 +- tools/patman/settings.py | 10 +- tools/patman/terminal.py | 4 +- tools/patman/test_util.py | 21 ++- tools/patman/tools.py | 12 +- tools/patman/tout.py | 6 +- 319 files changed, 2506 insertions(+), 656 deletions(-) create mode 100644 doc/driver-model/soc-framework.rst create mode 100644 drivers/soc/soc-uclass.c create mode 100644 drivers/soc/soc_sandbox.c create mode 100644 drivers/soc/soc_ti_k3.c create mode 100644 include/soc.h create mode 100644 test/dm/soc.c create mode 100644 tools/binman/etype/blob_ext.py create mode 100644 tools/binman/etype/fit.py create mode 100644 tools/binman/etype/mkimage.py create mode 100644 tools/binman/test/156_mkimage.dts create mode 100644 tools/binman/test/157_blob_ext.dts create mode 100644 tools/binman/test/158_blob_ext_missing.dts create mode 100644 tools/binman/test/159_blob_ext_missing_sect.dts create mode 100644 tools/binman/test/160_pack_overlap_zero.dts create mode 100644 tools/binman/test/161_fit.dts create mode 100644 tools/binman/test/162_fit_external.dts create mode 100644 tools/patman/control.py Regards, Simon

3 6

[PATCH] imx: Add MYiR Tech MYS-6ULX support
by Parthiban Nallathambi 27 Jul '20

27 Jul '20

MYS-6ULX is single board computer (SBC) comes with eMMC or NAND based on imx6ULL SoC from NXP and provision for expansion board. This commit adds support only for SBC with NAND. CPU: Freescale i.MX6ULL rev1.1 528 MHz (running at 396 MHz) CPU: Commercial temperature grade (0C to 95C) at 45C Reset cause: WDOG Model: MYiR i.MX6ULL MYS-6ULX Single Board Computer with NAND Board: MYiR MYS-6ULX 6ULL Single Board Computer DRAM: 256 MiB NAND: 256 MiB MMC: FSL_SDHC: 0 In: serial@2020000 Out: serial@2020000 Err: serial@2020000 Net: FEC0 Working: - Eth0 - MMC/SD - NAND - UART 1 - USB host Signed-off-by: Parthiban Nallathambi <parthiban(a)linumiz.com> --- arch/arm/Kconfig | 1 + arch/arm/dts/Makefile | 1 + arch/arm/dts/imx6ull-myir-mys-6ulx-eval.dts | 20 ++ arch/arm/dts/imx6ull-myir-mys-6ulx.dtsi | 238 ++++++++++++++++++++ arch/arm/dts/imx6ull-mys-6ulx-u-boot.dtsi | 24 ++ arch/arm/mach-imx/mx6/Kconfig | 12 + board/myir/mys_6ulx/Kconfig | 12 + board/myir/mys_6ulx/MAINTAINERS | 9 + board/myir/mys_6ulx/Makefile | 4 + board/myir/mys_6ulx/README | 52 +++++ board/myir/mys_6ulx/mys_6ulx.c | 146 ++++++++++++ board/myir/mys_6ulx/spl.c | 206 +++++++++++++++++ configs/myir_mys_6ulx_defconfig | 66 ++++++ include/configs/mys_6ulx.h | 80 +++++++ 14 files changed, 871 insertions(+) create mode 100644 arch/arm/dts/imx6ull-myir-mys-6ulx-eval.dts create mode 100644 arch/arm/dts/imx6ull-myir-mys-6ulx.dtsi create mode 100644 arch/arm/dts/imx6ull-mys-6ulx-u-boot.dtsi create mode 100644 board/myir/mys_6ulx/Kconfig create mode 100644 board/myir/mys_6ulx/MAINTAINERS create mode 100644 board/myir/mys_6ulx/Makefile create mode 100644 board/myir/mys_6ulx/README create mode 100644 board/myir/mys_6ulx/mys_6ulx.c create mode 100644 board/myir/mys_6ulx/spl.c create mode 100644 configs/myir_mys_6ulx_defconfig create mode 100644 include/configs/mys_6ulx.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 54d65f8488..24767198e8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1905,6 +1905,7 @@ source "board/hisilicon/hikey/Kconfig" source "board/hisilicon/hikey960/Kconfig" source "board/hisilicon/poplar/Kconfig" source "board/isee/igep003x/Kconfig" +source "board/myir/mys_6ulx/Kconfig" source "board/silica/pengwyn/Kconfig" source "board/spear/spear300/Kconfig" source "board/spear/spear310/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9900b44274..4e06c83234 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -710,6 +710,7 @@ dtb-$(CONFIG_MX6UL) += \ dtb-$(CONFIG_MX6ULL) += \ imx6ull-14x14-evk.dtb \ imx6ull-colibri.dtb \ + imx6ull-myir-mys-6ulx-eval.dtb \ imx6ull-phytec-segin-ff-rdk-emmc.dtb \ imx6ull-dart-6ul.dtb \ imx6ull-somlabs-visionsom.dtb \ diff --git a/arch/arm/dts/imx6ull-myir-mys-6ulx-eval.dts b/arch/arm/dts/imx6ull-myir-mys-6ulx-eval.dts new file mode 100644 index 0000000000..6bc2d80837 --- /dev/null +++ b/arch/arm/dts/imx6ull-myir-mys-6ulx-eval.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Linumiz + * Author: Parthiban Nallathambi <parthiban(a)linumiz.com> + */ + +/dts-v1/; +#include "imx6ull.dtsi" +#include "imx6ull-myir-mys-6ulx.dtsi" +#include "imx6ull-mys-6ulx-u-boot.dtsi" + +/ { + model = "MYiR i.MX6ULL MYS-6ULX Single Board Computer with NAND"; + compatible = "myir,imx6ull-mys-6ulx-eval", "myir,imx6ull-mys-6ulx", + "fsl,imx6ull"; +}; + +&gpmi { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6ull-myir-mys-6ulx.dtsi b/arch/arm/dts/imx6ull-myir-mys-6ulx.dtsi new file mode 100644 index 0000000000..03365a1ca8 --- /dev/null +++ b/arch/arm/dts/imx6ull-myir-mys-6ulx.dtsi @@ -0,0 +1,238 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Linumiz + * Author: Parthiban Nallathambi <parthiban(a)linumiz.com> + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pwm/pwm.h> + +/ { + model = "MYiR MYS-6ULX Single Board Computer"; + compatible = "myir,imx6ull-mys-6ulx", "fsl,imx6ull"; + + chosen { + stdout-path = &uart1; + }; + + reg_vdd_5v: regulator-vdd-5v { + compatible = "regulator-fixed"; + regulator-name = "VDD_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_vdd_3v3: regulator-vdd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&reg_vdd_5v>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <&ethphy0>; + phy-supply = <&reg_vdd_3v3>; + status = "okay"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&gpio5>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + dr_mode = "otg"; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <&reg_vdd_3v3>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <8>; + non-removable; + keep-power-in-suspend; + vmmc-supply = <&reg_vdd_3v3>; +}; + +&iomuxc { + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 + >; + }; +}; diff --git a/arch/arm/dts/imx6ull-mys-6ulx-u-boot.dtsi b/arch/arm/dts/imx6ull-mys-6ulx-u-boot.dtsi new file mode 100644 index 0000000000..cd15d9ba86 --- /dev/null +++ b/arch/arm/dts/imx6ull-mys-6ulx-u-boot.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Linumiz + * Author: Parthiban Nallathambi <parthiban(a)linumiz.com> + */ + +&pinctrl_uart1 { + u-boot,dm-pre-reloc; +}; + +&gpmi { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&usdhc1 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&usdhc2 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index fa6e1112e6..8dc5d54a92 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -460,6 +460,18 @@ config TARGET_MX6ULL_14X14_EVK select MX6ULL imply CMD_DM +config TARGET_MYS_6ULX + bool "MYiR MYS-6ULX" + select MX6ULL + select DM + select DM_ETH + select DM_GPIO + select DM_I2C + select DM_MMC + select DM_SERIAL + select DM_THERMAL + select SUPPORT_SPL + config TARGET_NITROGEN6X bool "nitrogen6x" imply USB_ETHER_ASIX diff --git a/board/myir/mys_6ulx/Kconfig b/board/myir/mys_6ulx/Kconfig new file mode 100644 index 0000000000..cbf72c6eca --- /dev/null +++ b/board/myir/mys_6ulx/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MYS_6ULX + +config SYS_BOARD + default "mys_6ulx" + +config SYS_VENDOR + default "myir" + +config SYS_CONFIG_NAME + default "mys_6ulx" + +endif diff --git a/board/myir/mys_6ulx/MAINTAINERS b/board/myir/mys_6ulx/MAINTAINERS new file mode 100644 index 0000000000..d4ee661182 --- /dev/null +++ b/board/myir/mys_6ulx/MAINTAINERS @@ -0,0 +1,9 @@ +MYS_6ULX BOARD +M: Parthiban Nallathambi <parthiban(a)linumiz.com> +S: Maintained +F: arch/arm/dts/imx6ull-myir-mys-6ulx-nand.dts +F: arch/arm/dts/imx6ull-myir-mys-6ulx.dtsi +F: arch/arm/dts/imx6ull-mys-6ulx-u-boot.dtsi +F: board/myir/mys_6ulx/ +F: configs/myir_mys_6ulx_defconfig +F: include/configs/mys_6ulx.h diff --git a/board/myir/mys_6ulx/Makefile b/board/myir/mys_6ulx/Makefile new file mode 100644 index 0000000000..3c63e439ab --- /dev/null +++ b/board/myir/mys_6ulx/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y := mys_6ulx.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/myir/mys_6ulx/README b/board/myir/mys_6ulx/README new file mode 100644 index 0000000000..a0996659c9 --- /dev/null +++ b/board/myir/mys_6ulx/README @@ -0,0 +1,52 @@ +How to use U-Boot on MYiR MYS-6ULX Single Board Computer +-------------------------------------------------------- + +- Configure and build U-Boot for MYS-6ULX iMX6ULL: + + $ make mrproper + $ make myir_mys_6ulx_defconfig + $ make + + This will generate SPL and u-boot-dtb.img images. + +Boot from MMC/SD: +- The SPL and u-boot-dtb.img images need to be flashed into the micro SD card: + + $ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync + $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync + +- Boot mode settings: + + Boot switch position: SW1 -> 0 + SW2 -> 1 + SW3 -> 0 + SW4 -> 1 + +Boot from NAND: +- Boot the board using SD/MMC or Serial download and load the SPL into memory +either from SD/MMC or TFTP. + +Default MTD layout is 512k(spl),1m(uboot),1m(uboot-dup),-(ubi) + +Flash SPL to NAND from SD/MMC, + + $ ext4load mmc 0:2 $loadaddr SPL + $ nand erase.part spl + $ nandbcb init $loadaddr 0x0 $filesize + +Flash u-boot proper to NAND from SD/MMC, + + $ ext4load mmc 0:2 $loadaddr u-boot-dtb.img + $ nand erase.part uboot + $ nand write $loadaddr uboot $filesize + +- Boot mode settings: + + Boot switch position: SW1 -> 1 + SW2 -> 0 + SW3 -> 0 + SW4 -> 1 + +- Connect the Serial cable to UART0 and the PC for the console. + +- Reset the board using and U-Boot should boot from NAND. diff --git a/board/myir/mys_6ulx/mys_6ulx.c b/board/myir/mys_6ulx/mys_6ulx.c new file mode 100644 index 0000000000..dd6206833b --- /dev/null +++ b/board/myir/mys_6ulx/mys_6ulx.c @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Linumiz + * Author: Parthiban Nallathambi <parthiban(a)linumiz.com> + */ + +#include <init.h> +#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <fsl_esdhc_imx.h> +#include <linux/bitops.h> +#include <miiphy.h> +#include <netdev.h> +#include <usb.h> +#include <usb/ehci-ci.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS) + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const uart5_pads[] = { + MX6_PAD_UART5_TX_DATA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART5_RX_DATA__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); + imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads)); +} + +#ifdef CONFIG_FEC_MXC + +#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | \ + PAD_CTL_SRE_FAST) +#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_ODE) + +static iomux_v3_cfg_t const fec1_pads[] = { + MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), + MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); +} + +static int setup_fec(void) +{ + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + int ret; + + /* + * Use 50M anatop loopback REF_CLK1 for ENET1, + * clear gpr1[13], set gpr1[17]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + + ret = enable_fec_anatop_clock(0, ENET_50MHZ); + if (ret) + return ret; + + enable_enet_clk(1); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + /* + * Defaults + Enable status LEDs (LED1: Activity, LED0: Link) & select + * 50 MHz RMII clock mode. + */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif /* CONFIG_FEC_MXC */ + +int board_early_init_f(void) +{ + setup_iomux_uart(); +#ifdef CONFIG_FEC_MXC + setup_iomux_fec(); +#endif + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + return 0; +} + +int checkboard(void) +{ + u32 cpurev = get_cpu_rev(); + + printf("Board: MYiR MYS-6ULX %s Single Board Computer\n", + get_imx_type((cpurev & 0xFF000) >> 12)); + + return 0; +} diff --git a/board/myir/mys_6ulx/spl.c b/board/myir/mys_6ulx/spl.c new file mode 100644 index 0000000000..72e9012832 --- /dev/null +++ b/board/myir/mys_6ulx/spl.c @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Linumiz + * Author: Parthiban Nallathambi <parthiban(a)linumiz.com> + */ + +#include <common.h> +#include <init.h> +#include <spl.h> +#include <asm/arch/clock.h> +#include <asm/io.h> +#include <asm/arch/mx6-ddr.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/sys_proto.h> +#include <fsl_esdhc_imx.h> + +/* Configuration for Micron MT41K128M16JT-125, 32M x 16 x 8 -> 256MiB */ + +static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { + .grp_addds = 0x00000030, + .grp_ddrmode_ctl = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_ctlds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_ddrpke = 0x00000000, + .grp_ddrmode = 0x00020000, + .grp_ddr_type = 0x000c0000, +}; + +static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_dqm0 = 0x00000030, + .dram_dqm1 = 0x00000030, + .dram_ras = 0x00000030, + .dram_cas = 0x00000030, + .dram_odt0 = 0x00000030, + .dram_odt1 = 0x00000030, + .dram_sdba2 = 0x00000000, + .dram_sdclk_0 = 0x00000030, + .dram_sdqs0 = 0x00000030, + .dram_sdqs1 = 0x00000030, + .dram_reset = 0x00000030, +}; + +static struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x00000000, + .p0_mpdgctrl0 = 0x41480148, + .p0_mprddlctl = 0x40403E42, + .p0_mpwrdlctl = 0x40405852, +}; + +struct mx6_ddr_sysinfo ddr_sysinfo = { + .dsize = 0, /* Bus size = 16bit */ + .cs_density = 32, + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 1, + .rtt_nom = 1, + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .pd_fast_exit = 1, + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .ddr_type = DDR_TYPE_DDR3, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ +}; + +/* MT41K128M16JT-125 (2Gb density) */ +static struct mx6_ddr3_cfg mem_ddr = { + .mem_speed = 1600, + .density = 2, + .width = 16, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0xFFFFFFFF, &ccm->CCGR0); + writel(0xFFFFFFFF, &ccm->CCGR1); + writel(0xFFFFFFFF, &ccm->CCGR2); + writel(0xFFFFFFFF, &ccm->CCGR3); + writel(0xFFFFFFFF, &ccm->CCGR4); + writel(0xFFFFFFFF, &ccm->CCGR5); + writel(0xFFFFFFFF, &ccm->CCGR6); +} + +static void spl_dram_init(void) +{ + mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); +} + +#ifdef CONFIG_FSL_ESDHC_IMX + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS) + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_UART1_RTS_B__USDHC1_CD_B | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +#ifndef CONFIG_NAND_MXS +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; +#endif + +static struct fsl_esdhc_cfg usdhc_cfg[] = { + { + .esdhc_base = USDHC1_BASE_ADDR, + .max_bus_width = 4, + }, +#ifndef CONFIG_NAND_MXS + { + .esdhc_base = USDHC2_BASE_ADDR, + .max_bus_width = 8, + }, +#endif +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; +} + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + SETUP_IOMUX_PADS(usdhc1_pads); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; +#ifndef CONFIG_NAND_MXS + case 1: + SETUP_IOMUX_PADS(usdhc2_pads); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; +#endif + default: + printf("Warning - USDHC%d controller not supporting\n", + i + 1); + return 0; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} + +#endif /* CONFIG_FSL_ESDHC_IMX */ + +void board_init_f(ulong dummy) +{ + ccgr_init(); + + /* Setup AIPS and disable watchdog */ + arch_cpu_init(); + + /* Setup iomux and fec */ + board_early_init_f(); + + /* Setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); +} diff --git a/configs/myir_mys_6ulx_defconfig b/configs/myir_mys_6ulx_defconfig new file mode 100644 index 0000000000..dff27e694f --- /dev/null +++ b/configs/myir_mys_6ulx_defconfig @@ -0,0 +1,66 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_SIZE=0x4000 +CONFIG_TARGET_MYS_6ULX=y +CONFIG_SPL_TEXT_BASE=0x908000 +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_NR_DRAM_BANKS=8 +CONFIG_SPL=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" +CONFIG_BOOTDELAY=3 +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_DMA=y +CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +# CONFIG_RANDOM_UUID is not set +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" +CONFIG_MTDPARTS_DEFAULT="gpmi-nand:512k(spl),1m(uboot),1m(uboot-dup),-(ubi)" +CONFIG_CMD_UBI=y +# CONFIG_ISO_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-myir-mys-6ulx-eval" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_I2C_GPIO=y +CONFIG_SYS_I2C_MXC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y +CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y +CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 +CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x180000 +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_GADGET=y +CONFIG_SMBIOS_MANUFACTURER="MYiR" diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h new file mode 100644 index 0000000000..d3bba40271 --- /dev/null +++ b/include/configs/mys_6ulx.h @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (C) 2020 Linumiz + * Author: Parthiban Nallathambi <parthiban(a)linumiz.com> + */ + +#ifndef __MYS_6ULX_H +#define __MYS_6ULX_H + +#include <linux/sizes.h> +#include "mx6_common.h" + +/* SPL options */ +#include "imx6_spl.h" + +#define CONFIG_SYS_FSL_USDHC_NUM 1 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +/* Console configs */ +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000000) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_SIZE SZ_256M + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* NAND */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 + +/* USB Configs */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +#define CONFIG_IMX_THERMAL + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttymxc0,115200n8\0" \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "fdt_addr_r=0x82000000\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "kernel_addr_r=0x81000000\0" \ + "pxefile_addr_r=0x87100000\0" \ + "ramdisk_addr_r=0x82100000\0" \ + "scriptaddr=0x87000000\0" \ + BOOTENV + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(UBIFS, ubifs, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#include <config_distro_bootcmd.h> + +#endif /* __MYS_6ULX_H */ -- 2.27.0

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[RESEND PATCH v5 0/4] cmd: env: add option for quiet output on env info
by Patrick Delaunay 27 Jul '20

27 Jul '20

Hi, It is a V5 for [1] serie. RESEND without "stm32mp1: use the command env info -q in env_check" sent in separate serie [4]. I add the -q option for 'env info' command and I also add pytest for this command. Test for ENV_IS_IN_DEVICE is included in separate serie [2] (I will activate ENV_IS_IN_EXT4 support in sandbox) To avoid compilation warning, I add prototype for env_get_location for the patch 3/7 "cmd: env: check real location for env info command" as it is done in [3]. [1] http://patchwork.ozlabs.org/project/uboot/list/?series=183438 [2] http://patchwork.ozlabs.org/project/uboot/list/?series=158160 [3] http://patchwork.ozlabs.org/patch/1230200/ [4] http://patchwork.ozlabs.org/project/uboot/list/?series=183450 Changes in v5: - allow to execute cmd_nvedit_info on real board - rename test_env_info_quiet to test_env_info_sandbox Changes in v4: - rebase on master branch - move 5/7 stm32mp1: configs: activate CMD_ERASEENV in a new serie 183380 - move 2/7 and 4/7 in a new serie 183387 Changes in v3: - update commit message (sub-commandi) - rename test_env_info_test to test_env_info_quiet Changes in v2: - update prototype in env_internal.h as done in "env: add prototypes for weak function" - remove comment change in env.c (implementation information) - move env_location declaration - activate env info command in sandbox (new) - add pytest test_env_info and test_env_info_test (new) Patrick Delaunay (4): cmd: env: add option for quiet output on env info cmd: env: check real location for env info command configs: sandbox: Enable sub command 'env info' test: env: add test for env info sub-command cmd/Kconfig | 1 + cmd/nvedit.c | 37 ++++++++++++++---- configs/sandbox64_defconfig | 1 + configs/sandbox_defconfig | 1 + configs/sandbox_flattree_defconfig | 1 + configs/sandbox_spl_defconfig | 1 + include/env_internal.h | 11 ++++++ test/py/tests/test_env.py | 63 ++++++++++++++++++++++++++++++ 8 files changed, 108 insertions(+), 8 deletions(-) -- 2.17.1

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[RESEND PATCH 0/3] env: mmc: allow support of mmc_get_env_dev with OF_CONTROL
by Patrick Delaunay 27 Jul '20

27 Jul '20

Hi Joe, It is a resend of previous serie [1] after rebase. This serie provides several corrections on ENV suport in MMC partition. No code modification on this RESEND, tested on STM32MP157C-EV1. [1] http://patchwork.ozlabs.org/project/uboot/list/?series=165325 Regards Patrick Patrick Delaunay (3): env: mmc: allow support of mmc_get_env_dev with OF_CONTROL env: mmc: correct the offset returned by mmc_offset_try_partition env: mmc: add redundancy support in mmc_offset_try_partition env/mmc.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) -- 2.17.1

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