June 2020 - U-Boot

[PATCH 1/1] Dockerfile: add libguestfs-tools package
by Heinrich Schuchardt 19 Jun '20

19 Jun '20

In some of our Python tests we build disk images. Currently this involves using the sudo command for losetup and mount. For some tests sudo is not necessary if the command guestmount of package libguestfs-tools is available. Another useful tool in libguestfs-tools is virt-make-fs. Generally we should get rid of using a root user for building and testing. As a first step install libguestfs-tools in our Docker image. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- Dockerfile | 1 + 1 file changed, 1 insertion(+) diff --git a/Dockerfile b/Dockerfile index 4138415..20a861f 100644 --- a/Dockerfile +++ b/Dockerfile @@ -57,6 +57,7 @@ RUN apt-get update && apt-get install -y \ iasl \ imagemagick \ iputils-ping \ + libguestfs-tools \ libisl15 \ liblz4-tool \ libpixman-1-dev \ -- 2.26.2

3 4

[PATCH v5 0/5] cmd: env: add option for quiet output on env info
by Patrick Delaunay 19 Jun '20

19 Jun '20

Hi, It is a V5 for [1] serie. I add the -q option for 'env info' command and I also add pytest for this command. Test for ENV_IS_IN_DEVICE is included in separate serie [2] (I will activate ENV_IS_IN_EXT4 support in sandbox) To avoid compilation warning, I add prototype for env_get_location for the patch 3/7 "cmd: env: check real location for env info command" as it is done in [3]. [1] http://patchwork.ozlabs.org/project/uboot/list/?series=183438 [2] http://patchwork.ozlabs.org/project/uboot/list/?series=158160 [3] http://patchwork.ozlabs.org/patch/1230200/ Changes in v5: - allow to execute cmd_nvedit_info on real board - rename test_env_info_quiet to test_env_info_sandbox Changes in v4: - rebase on master branch - move 5/7 stm32mp1: configs: activate CMD_ERASEENV in a new serie 183380 - move 2/7 and 4/7 in a new serie 183387 Changes in v3: - update commit message (sub-commandi) - rename test_env_info_test to test_env_info_quiet Changes in v2: - update prototype in env_internal.h as done in "env: add prototypes for weak function" - remove comment change in env.c (implementation information) - move env_location declaration - activate env info command in sandbox (new) - add pytest test_env_info and test_env_info_test (new) Patrick Delaunay (5): stm32mp1: use the command env info in env_check cmd: env: add option for quiet output on env info cmd: env: check real location for env info command configs: sandbox: Enable sub command 'env info' test: env: add test for env info sub-command arch/arm/mach-stm32mp/Kconfig | 1 + cmd/Kconfig | 1 + cmd/nvedit.c | 37 ++++++++++++++---- configs/sandbox64_defconfig | 1 + configs/sandbox_defconfig | 1 + configs/sandbox_flattree_defconfig | 1 + configs/sandbox_spl_defconfig | 1 + include/configs/stm32mp1.h | 4 +- include/env_internal.h | 11 ++++++ test/py/tests/test_env.py | 63 ++++++++++++++++++++++++++++++ 10 files changed, 110 insertions(+), 11 deletions(-) -- 2.17.1

1 5

Mainlining advice for new (MStar/SigmaStar) ARMv7 SoC family
by Daniel Palmer 19 Jun '20

19 Jun '20

Hi all, I'm attempting to get initial support for MStar/Sigmastar's family of ARMv7 chips into Linux and I thought I should probably at least attempt to mainling the u-boot support while I'm at it. I did some googling and couldn't find a "how to mainline a new SoC" guide for u-boot so if possible could I get some advice on how I should go about this. Right now I have a very janky tree that can either piggy back the vendor's second stage bootloader (bootloader after bootrom) or on some of the chips produce an SPL that can run straight after the bootrom exits. I need to chop it up into acceptable parts but I'm not sure how that would look. For Linux I'm attempting to get in a small patch set[0] that adds the initial device tree prefixes and then adds just enough machine specific bits to get to a shell from an initramfs. For u-boot would enough to load a kernel very slowly via loady be a good target? As the platform is device tree based do I need to wait until my prefixes get accepted to even start? Thanks, Daniel 0 - https://lore.kernel.org/linux-arm-kernel/20200616121525.1409790-1-daniel@0x…

2 2

Re: [PATCH v3 0/4] update clock handler and proper cpu features
by Rick Chen 19 Jun '20

19 Jun '20

Hi Sagar > From: Sagar Shrikant Kadam [mailto:sagar.kadam@sifive.com] > Sent: Thursday, June 04, 2020 6:45 PM > To: u-boot(a)lists.denx.de; Rick Jian-Zhi Chen(陳建志); lukma(a)denx.de > Cc: bmeng.cn(a)gmail.com; jagan(a)amarulasolutions.com; pragnesh.patel(a)sifive.com; anup.patel(a)wdc.com; sjg(a)chromium.org; seanga2(a)gmail.com; Sagar Shrikant Kadam > Subject: [PATCH v3 0/4] update clock handler and proper cpu features > > U-Boot cmd "cpu detail" shows inconsistent CPU features and is missing clk_request and free handlers. > The current "cpu detail" sometimes shows "Microcode" as a feature, which is not the case with FU540-C000 on HiFive Unleashed board. > > Patch 1: add clk request handler to check if valid clock id is requested. > Patch 2: add cpu node aliases. > Patch 3: Correctly parse and update mmu-type. > > RISC-V core's on FU540-C000 SoC have separate instruction and data (split) > L1 cache. > Patch 4:Use i-cache-size dt property as one of identifier to indicate a > split cache is available. > > I have picked few dependent patches from Sean's and Pragnesh's latest series from here [1]...[5]. > > These have applied on mainline U-Boot commit 0d8f35b58cc8 ("Merge https://gitlab.denx.de/u-boot/custodians/u-boot-spi") > > Patch history: > ============================================= > V3: > 1. Included the cosmetic change as suggested > s/L1 feature/L1 cache feature/ > 2. Added Reviewed-By tags > > V2: > 1. Incorporate review comments from Bin and Sean Anderson. > and dropped 2nd patch as similar work was already done in [1] and [2] > 2 Add cpu node aliases to display cpu node's in sequence. > 3. Add fix to show mmu as available cpu feature. > 4. Check and append L1 cache feature. > > V1: Base version > Thanks to Vincent Chen <vincent.chen(a)sifive.com> for testing the V1 > version of this series. > > [1] https://patchwork.ozlabs.org/patch/1295345 > [2] https://patchwork.ozlabs.org/patch/1295346 > [3] https://patchwork.ozlabs.org/patch/1300369 > [4] https://patchwork.ozlabs.org/patch/1300370 > [5] https://patchwork.ozlabs.org/patch/1300373 > > All these together is available here: > https://github.com/sagsifive/u-boot/commits/dev/sagark/clk-v3 > > Sagar Shrikant Kadam (4): > fu540: prci: add request and free clock handlers > riscv: dts: hifive-unleashed-a00: add cpu aliases > riscv: cpu: fixes to display proper CPU features > riscv: cpu: check and append L1 cache to cpu features > > arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 5 +++++ > drivers/clk/sifive/fu540-prci.c | 21 +++++++++++++++++++++ > drivers/cpu/riscv_cpu.c | 10 +++++++++- > 3 files changed, 35 insertions(+), 1 deletion(-) I am trying to apply to u-boot/master, but it fail as below: Applying: fu540: prci: add request and free clock handlers error: patch failed: drivers/clk/sifive/fu540-prci.c:581 error: drivers/clk/sifive/fu540-prci.c: patch does not apply Patch failed at 0001 fu540: prci: add request and free clock handlers Please rebase master, I will sync to master later. Thanks, Rick > > -- > 2.7.4 >

2 1

[PATCH v2 00/12] mips: Add initial Octeon MIPS64 base support
by Stefan Roese 19 Jun '20

19 Jun '20

This patch adds very basic support for the Octeon III SoCs. Only CFI parallel UART, reset and NOR flash are supported for now. Please note that the basic Octeon port does not include the DDR3/4 initialization yet. This will be added in some follow-up patches later. To still use U-Boot on with this port, the L2 cache (4MiB on Octeon III CN73xx) is used as RAM. This way, U-Boot can boot to the prompt on such boards. Thanks, Stefan Changes in v2: - New patch - New patch - Restructure patch by adding empty functions to asm/cm.h instead - New patch - New patch - Move bit macro definition to mipsregs.h - Remove custom start.S and use common start.S. Minimal custom lowlevel init code is currently added in the custom lowlevel_init.S. This needs to be extended with necessary code, like errata handling etc. But for a very first basic port, this seems to be all thats needed to boot on the EBB7304 to the prompt. - Removed select CREATE_ARCH_SYMLINK - Removed Octeon II support, as its currently no added in this patchset - Added cache.c to add the platform specific cache functions as no-ops for Octeon as the platform is cache coherent - Removed CONFIG_MIPS_CACHE_COHERENT - Added CONFIG_CPU_CAVIUM_OCTEON to Kconfig and selected it for Octeon to enable better sync with the Linux files in the future - Add get_tbclk() -> no need to define CONFIG_SYS_MIPS_TIMER_FREQ any more - Removed CONFIG_SYS_MIPS_TIMER_FREQ Aaron Williams (2): mips: mipsregs.h: Add more register macros for Octeon port mips: octeon: Initial minimal support for the Marvell Octeon SoC Stefan Roese (10): mips: start.S: Add CONFIG_MIPS_INIT_JUMP_OFFSET mips: start.S: Don't call mips_cache_reset() on ARCH_OCTEON mips: cache: Allow using CONFIG_MIPS_L2_CACHE without CONFIG_MIPS_CM mips: cache: Make flush_cache() weak to enable overwrite mips: time: Only compile the weak get_tbclk() when needed mips: traps: Set WG bit in EBase register on Octeon mips: mipsregs.h: Sync with linux v5.7.0-rc3 version sysreset: Add Octeon sysreset driver mips: octeon: dts: Add Octeon 3 cn73xx base dtsi file mips: octeon: Add minimal Octeon 3 EBB7304 EVK support MAINTAINERS | 7 ++ arch/mips/Kconfig | 43 +++++++++ arch/mips/Makefile | 3 + arch/mips/cpu/start.S | 6 ++ arch/mips/cpu/time.c | 2 + arch/mips/dts/Makefile | 1 + arch/mips/dts/mrvl,cn73xx.dtsi | 64 +++++++++++++ arch/mips/dts/mrvl,octeon-ebb7304.dts | 96 +++++++++++++++++++ arch/mips/include/asm/cm.h | 12 +++ arch/mips/include/asm/mipsregs.h | 64 +++++++++---- arch/mips/lib/cache.c | 4 +- arch/mips/lib/traps.c | 4 + arch/mips/mach-octeon/Kconfig | 67 +++++++++++++ arch/mips/mach-octeon/Makefile | 10 ++ arch/mips/mach-octeon/cache.c | 20 ++++ arch/mips/mach-octeon/clock.c | 27 ++++++ arch/mips/mach-octeon/cpu.c | 55 +++++++++++ arch/mips/mach-octeon/dram.c | 27 ++++++ arch/mips/mach-octeon/include/ioremap.h | 30 ++++++ arch/mips/mach-octeon/include/mach/cavm-reg.h | 42 ++++++++ arch/mips/mach-octeon/include/mach/clock.h | 24 +++++ arch/mips/mach-octeon/lowlevel_init.S | 75 +++++++++++++++ board/Marvell/octeon_ebb7304/Kconfig | 19 ++++ board/Marvell/octeon_ebb7304/MAINTAINERS | 7 ++ board/Marvell/octeon_ebb7304/Makefile | 8 ++ board/Marvell/octeon_ebb7304/board.c | 12 +++ configs/octeon_ebb7304_defconfig | 34 +++++++ drivers/sysreset/Kconfig | 7 ++ drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_octeon.c | 52 ++++++++++ include/configs/octeon_common.h | 25 +++++ include/configs/octeon_ebb7304.h | 20 ++++ scripts/config_whitelist.txt | 1 - 33 files changed, 846 insertions(+), 23 deletions(-) create mode 100644 arch/mips/dts/mrvl,cn73xx.dtsi create mode 100644 arch/mips/dts/mrvl,octeon-ebb7304.dts create mode 100644 arch/mips/mach-octeon/Kconfig create mode 100644 arch/mips/mach-octeon/Makefile create mode 100644 arch/mips/mach-octeon/cache.c create mode 100644 arch/mips/mach-octeon/clock.c create mode 100644 arch/mips/mach-octeon/cpu.c create mode 100644 arch/mips/mach-octeon/dram.c create mode 100644 arch/mips/mach-octeon/include/ioremap.h create mode 100644 arch/mips/mach-octeon/include/mach/cavm-reg.h create mode 100644 arch/mips/mach-octeon/include/mach/clock.h create mode 100644 arch/mips/mach-octeon/lowlevel_init.S create mode 100644 board/Marvell/octeon_ebb7304/Kconfig create mode 100644 board/Marvell/octeon_ebb7304/MAINTAINERS create mode 100644 board/Marvell/octeon_ebb7304/Makefile create mode 100644 board/Marvell/octeon_ebb7304/board.c create mode 100644 configs/octeon_ebb7304_defconfig create mode 100644 drivers/sysreset/sysreset_octeon.c create mode 100644 include/configs/octeon_common.h create mode 100644 include/configs/octeon_ebb7304.h -- 2.26.2

2 27

[v4 1/3] Watchdog: introduce ARM SBSA watchdog driver
by Biwen Li 19 Jun '20

19 Jun '20

From: Zhao Qiang <qiang.zhao(a)nxp.com> According to Server Base System Architecture (SBSA) specification, the SBSA Generic Watchdog has two stage timeouts: the first signal (WS0) is for alerting the system by interrupt, the second one (WS1) is a real hardware reset. More details about the hardware specification of this device: ARM DEN0029B - Server Base System Architecture (SBSA) This driver can operate ARM SBSA Generic Watchdog as a single stage In the single stage mode, when the timeout is reached, your system will be reset by WS1. The first signal (WS0) is ignored. Signed-off-by: Zhao Qiang <qiang.zhao(a)nxp.com> Signed-off-by: Biwen Li <biwen.li(a)nxp.com> Reviewed-by: Stefan Roese <sr(a)denx.de> --- Change in v4: - remove unused variable load_value Change in v3: - add description - remove empty line Change in v2: - fix copyright MAINTAINERS | 1 + drivers/watchdog/Kconfig | 9 +++ drivers/watchdog/Makefile | 1 + drivers/watchdog/sbsa_gwdt.c | 130 +++++++++++++++++++++++++++++++++++ 4 files changed, 141 insertions(+) create mode 100644 drivers/watchdog/sbsa_gwdt.c diff --git a/MAINTAINERS b/MAINTAINERS index db8cecd5e0..9bda8dbe76 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -686,6 +686,7 @@ M: Priyanka Jain <priyanka.jain(a)nxp.com> S: Maintained T: git https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq.git F: drivers/watchdog/sp805_wdt.c +F: drivers/watchdog/sbsa_gwdt.c I2C M: Heiko Schocher <hs(a)denx.de> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index bf06180cdd..6d5c4fcfeb 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -163,6 +163,15 @@ config WDT_SANDBOX can be probed and supports all of the methods of WDT, but does not really do anything. +config WDT_SBSA + bool "SBSA watchdog timer support" + depends on WDT + help + Select this to enable SBSA watchdog timer. + This driver can operate ARM SBSA Generic Watchdog as a single stage. + In the single stage mode, when the timeout is reached, your system + will be reset by WS1. The first signal (WS0) is ignored. + config WDT_SP805 bool "SP805 watchdog timer support" depends on WDT diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 519bbd3a40..0f0b2eb5bc 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o obj-$(CONFIG_WDT_MTK) += mtk_wdt.o obj-$(CONFIG_WDT_OMAP3) += omap_wdt.o +obj-$(CONFIG_WDT_SBSA) += sbsa_gwdt.o obj-$(CONFIG_WDT_SP805) += sp805_wdt.o obj-$(CONFIG_WDT_STM32MP) += stm32mp_wdt.o obj-$(CONFIG_WDT_TANGIER) += tangier_wdt.o diff --git a/drivers/watchdog/sbsa_gwdt.c b/drivers/watchdog/sbsa_gwdt.c new file mode 100644 index 0000000000..c7394a1148 --- /dev/null +++ b/drivers/watchdog/sbsa_gwdt.c @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Watchdog driver for SBSA + * + * Copyright 2020 NXP + */ + +#include <asm/io.h> +#include <common.h> +#include <dm/device.h> +#include <dm/fdtaddr.h> +#include <dm/read.h> +#include <linux/bitops.h> +#include <watchdog.h> +#include <wdt.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* SBSA Generic Watchdog register definitions */ +/* refresh frame */ +#define SBSA_GWDT_WRR 0x000 + +/* control frame */ +#define SBSA_GWDT_WCS 0x000 +#define SBSA_GWDT_WOR 0x008 +#define SBSA_GWDT_WCV 0x010 + +/* refresh/control frame */ +#define SBSA_GWDT_W_IIDR 0xfcc +#define SBSA_GWDT_IDR 0xfd0 + +/* Watchdog Control and Status Register */ +#define SBSA_GWDT_WCS_EN BIT(0) +#define SBSA_GWDT_WCS_WS0 BIT(1) +#define SBSA_GWDT_WCS_WS1 BIT(2) + +struct sbsa_gwdt_priv { + void __iomem *reg_refresh; + void __iomem *reg_control; +}; + +static int sbsa_gwdt_reset(struct udevice *dev) +{ + struct sbsa_gwdt_priv *priv = dev_get_priv(dev); + + writel(0, priv->reg_refresh + SBSA_GWDT_WRR); + + return 0; +} + +static int sbsa_gwdt_start(struct udevice *dev, u64 timeout, ulong flags) +{ + struct sbsa_gwdt_priv *priv = dev_get_priv(dev); + u32 clk; + + /* + * it work in the single stage mode in u-boot, + * The first signal (WS0) is ignored, + * the timeout is (WOR * 2), so the WOR should be configured + * to half value of timeout. + */ + clk = get_tbclk(); + writel(clk / 2 * timeout, + priv->reg_control + SBSA_GWDT_WOR); + + /* writing WCS will cause an explicit watchdog refresh */ + writel(SBSA_GWDT_WCS_EN, priv->reg_control + SBSA_GWDT_WCS); + + return 0; +} + +static int sbsa_gwdt_stop(struct udevice *dev) +{ + struct sbsa_gwdt_priv *priv = dev_get_priv(dev); + + writel(0, priv->reg_control + SBSA_GWDT_WCS); + + return 0; +} + +static int sbsa_gwdt_expire_now(struct udevice *dev, ulong flags) +{ + sbsa_gwdt_start(dev, 0, flags); + + return 0; +} + +static int sbsa_gwdt_probe(struct udevice *dev) +{ + debug("%s: Probing wdt%u (sbsa-gwdt)\n", __func__, dev->seq); + + return 0; +} + +static int sbsa_gwdt_ofdata_to_platdata(struct udevice *dev) +{ + struct sbsa_gwdt_priv *priv = dev_get_priv(dev); + + priv->reg_control = (void __iomem *)dev_read_addr_index(dev, 0); + if (IS_ERR(priv->reg_control)) + return PTR_ERR(priv->reg_control); + + priv->reg_refresh = (void __iomem *)dev_read_addr_index(dev, 1); + if (IS_ERR(priv->reg_refresh)) + return PTR_ERR(priv->reg_refresh); + + return 0; +} + +static const struct wdt_ops sbsa_gwdt_ops = { + .start = sbsa_gwdt_start, + .reset = sbsa_gwdt_reset, + .stop = sbsa_gwdt_stop, + .expire_now = sbsa_gwdt_expire_now, +}; + +static const struct udevice_id sbsa_gwdt_ids[] = { + { .compatible = "arm,sbsa-gwdt" }, + {} +}; + +U_BOOT_DRIVER(sbsa_gwdt) = { + .name = "sbsa_gwdt", + .id = UCLASS_WDT, + .of_match = sbsa_gwdt_ids, + .probe = sbsa_gwdt_probe, + .priv_auto_alloc_size = sizeof(struct sbsa_gwdt_priv), + .ofdata_to_platdata = sbsa_gwdt_ofdata_to_platdata, + .ops = &sbsa_gwdt_ops, +}; -- 2.17.1

1 2

[PATCH v2 1/1] cmd: bootefi: Honor the address & size cells properties correctly
by Heinrich Schuchardt 19 Jun '20

19 Jun '20

From: Atish Patra <atish.patra(a)wdc.com> fdtdec_get_addr_size reads the uses a fixed value for address & size cell properties which may not be correct always. Use the auto variant of the function which automatically reads #address-cells & #size-cells from parent and uses to read the "reg" property. Signed-off-by: Atish Patra <atish.patra(a)wdc.com> On 32 bit systems fdt_addr_t may be 4 bytes long but size is defined as u64. Avoid filling the upper 4 bytes of the sizep parameter of fdtdec_get_addr_size_auto_parent() with random bytes from the stack by defining a separate variable fdt_size. Reviewed-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- cmd/bootefi.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/cmd/bootefi.c b/cmd/bootefi.c index 0f6d0f7750..ac713cad1b 100644 --- a/cmd/bootefi.c +++ b/cmd/bootefi.c @@ -189,16 +189,19 @@ static void efi_carve_out_dt_rsv(void *fdt) if (nodeoffset >= 0) { subnode = fdt_first_subnode(fdt, nodeoffset); while (subnode >= 0) { + fdt_addr_t fdt_addr, fdt_size; + /* check if this subnode has a reg property */ - addr = fdtdec_get_addr_size(fdt, subnode, "reg", - (fdt_size_t *)&size); + fdt_addr = fdtdec_get_addr_size_auto_parent( + fdt, nodeoffset, subnode, + "reg", 0, &fdt_size, false); /* * The /reserved-memory node may have children with * a size instead of a reg property. */ if (addr != FDT_ADDR_T_NONE && fdtdec_get_is_enabled(fdt, subnode)) - efi_reserve_memory(addr, size); + efi_reserve_memory(fdt_addr, fdt_size); subnode = fdt_next_subnode(fdt, subnode); } } -- 2.27.0

1 0

[PATCH 0/5] Add Basic support for R8A774A1 (RZ/G2M)
by Adam Ford 18 Jun '20

18 Jun '20

The R8A774A1 (RZ/G2M) a commercial SoC based off the automotive R8A7796 SoC. This series will start the foundation to support this SoC by importing porting the device tree and bindings from Linux 5.8-rc1, then porting the clock driver, pinctrl driver, and sdhi drivers from Renesas' RZG2M repo found: https://github.com/renesas-rz/renesas-u-boot-cip/tree/v2018.09/rzg2 Adam Ford (5): ARM: renesas: Add basic R8A774A1 Support ARM: dts: r8a774a1: Import DTS from Linux 5.8-rc1 clk: renesas: Add R8A774A1 clock tables pinctrl: renesas: Add R8A774A1 PFC tables mmc: renesas-sdhi: Enable support for R8A774A1 arch/arm/dts/r8a774a1.dtsi | 2787 ++++++++ arch/arm/mach-rmobile/Kconfig.64 | 3 + drivers/clk/renesas/Kconfig | 7 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r8a774a1-cpg-mssr.c | 343 + drivers/mmc/renesas-sdhi.c | 2 +- drivers/pinctrl/renesas/Kconfig | 10 + drivers/pinctrl/renesas/Makefile | 1 + drivers/pinctrl/renesas/pfc-r8a774a1.c | 6196 +++++++++++++++++ include/dt-bindings/clock/r8a774a1-cpg-mssr.h | 65 + include/dt-bindings/power/r8a774a1-sysc.h | 33 + 11 files changed, 9447 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/r8a774a1.dtsi create mode 100644 drivers/clk/renesas/r8a774a1-cpg-mssr.c create mode 100644 drivers/pinctrl/renesas/pfc-r8a774a1.c create mode 100644 include/dt-bindings/clock/r8a774a1-cpg-mssr.h create mode 100644 include/dt-bindings/power/r8a774a1-sysc.h -- 2.25.1

2 7

GPIO request failures for Renesas rcar-gen3
by Adam Ford 18 Jun '20

18 Jun '20

I am trying to port U-Boot to a new product based on a Renesas RZ/G2M (rcar-gen3). We're have this working with Renesas' version from 2018.09, but I am trying to integrate it with U-Boot 2020.07-rc4 What's happening is that it seems like all GPIO are failing to be requested, so things like regulator-gpio fail, reset-gpios, etc. all return errors. The dm tree and gpio status commands all appear to show gpio banks are enumerating, but since nothing can use the GPIO's it seems like the common thread is the gpio driver for the rcar3. I was hoping someone might have some thoughts of things I could try or investigate. In order to properly set the voltage for the MMC card, I need "regulator-gpio" to operate correctly. The gpio regulator node looks like: vccq_sdhi0: regulator-vccq-sdhi0 { compatible = "regulator-gpio"; regulator-name = "SDHI0 VccQ"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; gpios-states = <1>; states = <3300000 1>, <1800000 0>; regulator-always-on; }; Log Below with some debugging turned on. U-Boot 2020.07-rc4-00060-g9cb895203a-dirty (Jun 18 2020 - 15:27:00 -0500) CPU: Renesas Electronics R8A7796 rev 2.1 Model: Beacon Embedded Works RZ/G2M Development Kit DRAM: 3.9 GiB Bank #0: 0x048000000 - 0x0bfffffff, 1.9 GiB Bank #1: 0x600000000 - 0x67fffffff, 2 GiB MMC: gpio_request_tail: dm_gpio_requestf failed gpio_request_tail: Node 'regulator-vccq-sdhi0', property 'gpios', failed to request GPIO index 0: -19 regulator gpio - not found! Error: -19gpio_request_tail: Node 'regulator-vccq-sdhi0', property 'enable-gpios', failed to request GPIO index 0: -2 gpio@e6055400: set_value: error: gpio gpio@e605540030 not reserved Can't set regulator-gpio : regulator-vccq-sdhi0 gpio to: 1 gpio_request_tail: Node 'regulator0', property 'gpio', failed to request GPIO index 0: -2 sd@ee100000: 0, sd@ee160000: 1 Loading Environment from MMC... gpio_request_tail: Node 'regulator1', property 'gpio', failed to request GPIO index 0: -2 OK In: serial@e6e88000 Out: serial@e6e88000 Err: serial@e6e88000 Net: gpio_request_tail: dm_gpio_requestf failed gpio_request_tail: Node 'ethernet-phy@0', property 'reset-gpios', failed to request GPIO index 0: -19 gpio@e6052000: set_value: error: gpio gpio@e605200010 not reserved gpio@e6052000: set_value: error: gpio gpio@e605200010 not reserved Error: ethernet@e6800000 address not set. No ethernet found. Hit any key to stop autoboot: 0 =>

2 6

[PATCH v2 1/4] phy: atheros: ar8035: Fix clock output calculation
by Fabio Estevam 18 Jun '20

18 Jun '20

The clock ouput frequency is calculated incorrectly for AR8035 due to wrong masking of priv->clk_25m_reg and priv->clk_25m_mask. This same issue has been already fixed in the kernel by: commit b1f4c209d84057b6d40b939b6e4404854271d797 Author: Oleksij Rempel <o.rempel(a)pengutronix.de> Date: Wed Apr 1 11:57:32 2020 +0200 net: phy: at803x: fix clock sink configuration on ATH8030 and ATH8035 The masks in priv->clk_25m_reg and priv->clk_25m_mask are one-bits-set for the values that comprise the fields, not zero-bits-set. This patch fixes the clock frequency configuration for ATH8030 and ATH8035 Atheros PHYs by removing the erroneous "~". To reproduce this bug, configure the PHY with the device tree binding "qca,clk-out-frequency" and remove the machine specific PHY fixups. Fixes: 2f664823a47021 ("net: phy: at803x: add device tree binding") Signed-off-by: Oleksij Rempel <o.rempel(a)pengutronix.de> Reported-by: Russell King <rmk+kernel(a)armlinux.org.uk> Reviewed-by: Russell King <rmk+kernel(a)armlinux.org.uk> Tested-by: Russell King <rmk+kernel(a)armlinux.org.uk> Signed-off-by: David S. Miller <davem(a)davemloft.net> Apply the same fix in the U-Boot driver. Tested on a i.MX6 Hummingboard. Signed-off-by: Fabio Estevam <festevam(a)gmail.com> Reviewed-by: Michael Walle <michael(a)walle.cc> Tested-by: Tom Rini <trini(a)konsulko.com> --- Changes since v1: - None drivers/net/phy/atheros.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 13f7275d17..f922fecd6b 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -275,11 +275,10 @@ static int ar803x_of_init(struct phy_device *phydev) * Fixup for the AR8035 which only has two bits. The two * remaining bits map to the same frequencies. */ - if (phydev->drv->uid == AR8035_PHY_ID) { - u16 clear = AR803x_CLK_25M_MASK & AR8035_CLK_25M_MASK; - priv->clk_25m_mask &= ~clear; - priv->clk_25m_reg &= ~clear; + if (phydev->drv->uid == AR8035_PHY_ID) { + priv->clk_25m_reg &= AR8035_CLK_25M_MASK; + priv->clk_25m_mask &= AR8035_CLK_25M_MASK; } } -- 2.17.1

2 5