May 2020 - U-Boot

[U-Boot] u-boot Marvell ethernet switch development
by Dennis Jacobs 26 May '20

26 May '20

Dear U-boot mailing list, Its the first time I make use of this U-boot mailing list. I am here for a problem I am having recently with u-boot which is part of my graduation project. I am developing firmware for a Marvell Ethernet switch chip (98DX3336) on the RD-XC3-24G4XG-B (Marvell Ethernet switch). Marvell has provided me with U-boot binary files for UART, SPI etc. I managed to load the U-boot UART binary file trough the UART interface. Showing: [cid:image003.png@01D3E22C.D21A6560] Ok so that is good... now I need to set up my own u-boot environment to add some changes. So I did. I Downloaded u-boot 2013.01 and added marvell configurations. I was able to compile and load the U-boot Uart binary trough the UART interface. The terminal is showing the following: [cid:image004.png@01D3E22D.C73E7040] So ok its loads! But now... I can not perform any commands. All commands are Unknown... So what I did was checking the configurations and I found out that I have set the CMD configurations. Like CMD_NET etc etc [cid:image005.png@01D3E22E.7D8A6070] Anny one that could help me here? I would really appreciate it. I am struggling with this problem for almost 2 full days now. Actions I have been taken - Tested if help command was realy executed and no other invisible fragments where added. - Tested the compilation with 7 different armv7-marvell cross compilers Left binary is the working one the second binary is mine. It only differs 26 bytes. I noticed that a different cross compiler also changes the size. Sometime more sometimes less. All of the binarys I compiled where executing correctly but not reacting on anny commands [cid:image006.png@01D3E22F.61EE8C00] Please help me. Kind regards, Dennis Jacobs Designer [Prodrive B.V.]<http://www.prodrive-technologies.com/> Mobile +31 62 57 28 194 Phone +31 40 26 76 200 www.prodrive-technologies.com<http://www.prodrive-technologies.com> [cid:image002.png@01D3E22B.A33384D0] Disclaimer: The content of this e-mail is intended solely for the use of the Individual or entity to whom it is addressed. If you have received this communication in error, be aware that forwarding it, copying it, or in any way disclosing its content to any other person, is strictly prohibited. If you have received this communication in error, please notify the author by replying to this e-mail immediately.

3 2

[RFC PATCH] imx: skip unused compatible strings in drivers
by Anatolij Gustschin 26 May '20

26 May '20

Converting to DM increases binary size and breaks building some boards (i.e. tbs2910, gcc 9.2). The approach to address this issue via cutting off unused properties/nodes in device tree via custom u-boot.dtsi was not welcome, even if the affected boards do not pass the built-in device tree to the kernel. Try to drop not required compatible strings in drivers when building for different iMX variants. This saves a few bytes when building for i.MX6, with current buildman default GCC 9.2: all -843.0 bss +8.0 data -40.0 rodata -547.0 text -264.0 Signed-off-by: Anatolij Gustschin <agust(a)denx.de> Cc: Heiko Schocher <hs(a)denx.de> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Joe Hershberger <joe.hershberger(a)ni.com> Cc: Lukasz Majewski <lukma(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> Cc: Stefano Babic <sbabic(a)denx.de> --- drivers/i2c/mxc_i2c.c | 3 +++ drivers/mmc/fsl_esdhc_imx.c | 18 ++++++++++++++++++ drivers/net/fec_mxc.c | 16 ++++++++++++++++ drivers/pinctrl/nxp/pinctrl-imx6.c | 14 ++++++++++++++ drivers/serial/serial_mxc.c | 10 ++++++++++ 5 files changed, 61 insertions(+) diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index 3b0d27e6cd..abef9d888e 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -1058,7 +1058,10 @@ static const struct dm_i2c_ops mxc_i2c_ops = { static const struct udevice_id mxc_i2c_ids[] = { { .compatible = "fsl,imx21-i2c", }, +#if defined(CONFIG_VF610) || defined(CONFIG_FSL_LSCH2) || \ + defined(CONFIG_FSL_LSCH3) || defined(CONFIG_ARCH_LS1021A) { .compatible = "fsl,vf610-i2c", .data = I2C_QUIRK_FLAG, }, +#endif {} }; diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 588d6a9d76..6943e4867e 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -1601,31 +1601,49 @@ static const struct dm_mmc_ops fsl_esdhc_ops = { }; #endif +#if defined(CONFIG_ARCH_MX7) static struct esdhc_soc_data usdhc_imx7d_data = { .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 | ESDHC_FLAG_HS400, }; +#endif +#if defined(CONFIG_ARCH_IMX8) || defined(CONFIG_ARCH_IMX8M) static struct esdhc_soc_data usdhc_imx8qm_data = { .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES, }; +#endif static const struct udevice_id fsl_esdhc_ids[] = { +#ifdef CONFIG_ARCH_MX5 { .compatible = "fsl,imx53-esdhc", }, +#endif +#ifdef CONFIG_ARCH_MX6 { .compatible = "fsl,imx6ul-usdhc", }, { .compatible = "fsl,imx6sx-usdhc", }, { .compatible = "fsl,imx6sl-usdhc", }, { .compatible = "fsl,imx6q-usdhc", }, +#endif +#ifdef CONFIG_ARCH_MX7 { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,}, +#endif +#ifdef CONFIG_ARCH_MX7ULP { .compatible = "fsl,imx7ulp-usdhc", }, +#endif +#ifdef CONFIG_ARCH_IMX8 { .compatible = "fsl,imx8qm-usdhc", .data = (ulong)&usdhc_imx8qm_data,}, +#endif +#ifdef CONFIG_ARCH_IMX8M { .compatible = "fsl,imx8mm-usdhc", .data = (ulong)&usdhc_imx8qm_data,}, { .compatible = "fsl,imx8mn-usdhc", .data = (ulong)&usdhc_imx8qm_data,}, { .compatible = "fsl,imx8mq-usdhc", .data = (ulong)&usdhc_imx8qm_data,}, +#endif +#ifdef CONFIG_ARCH_IMXRT { .compatible = "fsl,imxrt-usdhc", }, +#endif { .compatible = "fsl,esdhc", }, { /* sentinel */ } }; diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 9ae2db033e..d829b5b5ba 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -1574,14 +1574,30 @@ static int fecmxc_ofdata_to_platdata(struct udevice *dev) } static const struct udevice_id fecmxc_ids[] = { +#ifdef CONFIG_ARCH_MX28 { .compatible = "fsl,imx28-fec" }, +#endif +#ifdef CONFIG_ARCH_MX6 { .compatible = "fsl,imx6q-fec" }, +#endif +#ifdef CONFIG_MX6SL { .compatible = "fsl,imx6sl-fec" }, +#endif +#ifdef CONFIG_MX6SX { .compatible = "fsl,imx6sx-fec" }, +#endif +#ifdef CONFIG_MX6UL { .compatible = "fsl,imx6ul-fec" }, +#endif +#ifdef CONFIG_ARCH_MX5 { .compatible = "fsl,imx53-fec" }, +#endif +#ifdef CONFIG_ARCH_MX7 { .compatible = "fsl,imx7d-fec" }, +#endif +#ifdef CONFIG_ARCH_VF610 { .compatible = "fsl,mvf600-fec" }, +#endif { } }; diff --git a/drivers/pinctrl/nxp/pinctrl-imx6.c b/drivers/pinctrl/nxp/pinctrl-imx6.c index aafa3057ad..dff4954344 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx6.c +++ b/drivers/pinctrl/nxp/pinctrl-imx6.c @@ -12,14 +12,18 @@ static struct imx_pinctrl_soc_info imx6_pinctrl_soc_info __section(".data"); +#ifdef CONFIG_MX6UL /* FIXME Before reloaction, BSS is overlapped with DT area */ static struct imx_pinctrl_soc_info imx6ul_pinctrl_soc_info = { .flags = ZERO_OFFSET_VALID, }; +#endif +#if defined(CONFIG_MX6SLL) || defined(CONFIG_MX6ULL) static struct imx_pinctrl_soc_info imx6_snvs_pinctrl_soc_info = { .flags = ZERO_OFFSET_VALID, }; +#endif static int imx6_pinctrl_probe(struct udevice *dev) { @@ -32,12 +36,22 @@ static int imx6_pinctrl_probe(struct udevice *dev) static const struct udevice_id imx6_pinctrl_match[] = { { .compatible = "fsl,imx6q-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info }, { .compatible = "fsl,imx6dl-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info }, +#ifdef CONFIG_MX6SL { .compatible = "fsl,imx6sl-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info }, +#endif +#ifdef CONFIG_MX6SLL { .compatible = "fsl,imx6sll-iomuxc-snvs", .data = (ulong)&imx6_snvs_pinctrl_soc_info }, { .compatible = "fsl,imx6sll-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info }, +#endif +#ifdef CONFIG_MX6SX { .compatible = "fsl,imx6sx-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info }, +#endif +#ifdef CONFIG_MX6UL { .compatible = "fsl,imx6ul-iomuxc", .data = (ulong)&imx6ul_pinctrl_soc_info }, +#endif +#ifdef CONFIG_MX6ULL { .compatible = "fsl,imx6ull-iomuxc-snvs", .data = (ulong)&imx6_snvs_pinctrl_soc_info }, +#endif { /* sentinel */ } }; diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index 42abb96a26..f4a0d56e09 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -343,11 +343,21 @@ static int mxc_serial_ofdata_to_platdata(struct udevice *dev) static const struct udevice_id mxc_serial_ids[] = { { .compatible = "fsl,imx21-uart" }, +#ifdef CONFIG_ARCH_MX5 { .compatible = "fsl,imx53-uart" }, +#endif +#ifdef CONFIG_ARCH_MX6SX { .compatible = "fsl,imx6sx-uart" }, +#endif +#if defined(CONFIG_ARCH_MX6UL) || defined(CONFIG_ARCH_MX6ULL) { .compatible = "fsl,imx6ul-uart" }, +#endif +#ifdef CONFIG_ARCH_MX7 { .compatible = "fsl,imx7d-uart" }, +#endif +#if defined(CONFIG_ARCH_MX6) || defined(CONFIG_ARCH_MX6SL) || defined(CONFIG_ARCH_MX6SLL) { .compatible = "fsl,imx6q-uart" }, +#endif { } }; #endif -- 2.17.1

4 9

[U-Boot] is it mandatory for SPL to support DM
by Jagan Teki 26 May '20

26 May '20

SPL has a foot-print constraint, so fully switching a particular subsystem like SPI or SPI Flash to DM would increase the size of it. Possible areas to look at are (assume SPL_DM supported) 1) platdata 2) implement board or platform specific spl device driver which bypassed the actual framework ex: spl_spi_sunxi.c Do we have any other solutions? or any arguments on above step 2? Jagan.

4 16

[PATCH v1] gpio: octeon_gpio: Add GPIO controller driver for Octeon
by Stefan Roese 26 May '20

26 May '20

From: Suneel Garapati <sgarapati(a)marvell.com> Add support for GPIO controllers found on Octeon II/III and Octeon TX TX2 SoC platforms. Signed-off-by: Aaron Williams <awilliams(a)marvell.com> Signed-off-by: Suneel Garapati <sgarapati(a)marvell.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Daniel Schwierzeck <daniel.schwierzeck(a)gmail.com> Cc: Aaron Williams <awilliams(a)marvell.com> Cc: Chandrakala Chavva <cchavva(a)marvell.com> --- RFC -> v1 (Stefan) - Separated this patch from the OcteonTX/TX2 RFC patch series into a single patch. This is useful, as the upcoming MIPS Octeon support will use this GPIO driver. - Added MIPS Octeon II/III support (big endian). Rename driver and its function names from "octeontx" to "octeon" to better match all Octeon platforms. - Moved from union to defines / bitmasks. This makes the driver usage on little- and big-endian platforms much easier. - Used clrbits_64() instead of clrbits_le64() and friends to support usage on little- and big-endian systems - Removed dev->req_seq assignment - Enhanced Kconfig text - Rewrote GPIO_BIT macro - Dropped many macros to calculate the registers offsets and implemented simple functions for this (easier to read) - Used GENMASK_ULL and FIELD_GET helpers - Minor cosmetic changes (dropped brackets etc) - Reword commit text and subject drivers/gpio/Kconfig | 10 ++ drivers/gpio/Makefile | 1 + drivers/gpio/octeon_gpio.c | 241 +++++++++++++++++++++++++++++++++++++ 3 files changed, 252 insertions(+) create mode 100644 drivers/gpio/octeon_gpio.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 2081520f42..9c72930268 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -316,6 +316,16 @@ config PIC32_GPIO help Say yes here to support Microchip PIC32 GPIOs. +config OCTEON_GPIO + bool "Octeon II/III/TX/TX2 GPIO driver" + depends on DM_GPIO && (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) + default y + help + Add support for the Marvell Octeon GPIO driver. This is used with + various Octeon parts such as Octeon II/III and OcteonTX/TX2. + Octeon II/III has 32 GPIOs (count defined via DT) and OcteonTX/TX2 + has 64 GPIOs (count defined via internal register). + config STM32_GPIO bool "ST STM32 GPIO driver" depends on DM_GPIO && (STM32 || ARCH_STM32MP) diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 7638259007..eb6364adb4 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -58,6 +58,7 @@ obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o obj-$(CONFIG_HSDK_CREG_GPIO) += hsdk-creg-gpio.o obj-$(CONFIG_IMX_RGPIO2P) += imx_rgpio2p.o obj-$(CONFIG_PIC32_GPIO) += pic32_gpio.o +obj-$(CONFIG_OCTEON_GPIO) += octeon_gpio.o obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o obj-$(CONFIG_MSM_GPIO) += msm_gpio.o obj-$(CONFIG_$(SPL_)PCF8575_GPIO) += pcf8575_gpio.o diff --git a/drivers/gpio/octeon_gpio.c b/drivers/gpio/octeon_gpio.c new file mode 100644 index 0000000000..8079f6c5d9 --- /dev/null +++ b/drivers/gpio/octeon_gpio.c @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * (C) Copyright 2011 + * eInfochips Ltd. <www.einfochips.com> + * Written-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> + * + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <fdtdec.h> +#include <pci_ids.h> +#include <asm/bitops.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <linux/bitfield.h> +#include <dt-bindings/gpio/gpio.h> + +/* Returns the bit value to write or read based on the offset */ +#define GPIO_BIT(x) BIT_ULL((x) & 0x3f) + +/* Some offsets which are different on Octeon & OcteonTX/TX2 */ +#if defined(CONFIG_ARCH_OCTEON) +#define REG_OFFS 0x80 +#define GPIO_BIT_CFG_OFFS 0x100 +#else +#define REG_OFFS 0x00 +#define GPIO_BIT_CFG_OFFS 0x400 +#endif + +#define GPIO_RX_DAT (REG_OFFS + 0x00) +#define GPIO_TX_SET (REG_OFFS + 0x08) +#define GPIO_TX_CLR (REG_OFFS + 0x10) +#define GPIO_CONST (REG_OFFS + 0x90) /* OcteonTX only */ + +/* Offset to register-set for 2nd GPIOs (> 63), OcteonTX only */ +#define GPIO1_OFFSET 0x1400 + +/* GPIO_CONST register bits */ +#define GPIO_CONST_GPIOS_MASK GENMASK_ULL(7, 0) + +/* GPIO_BIT_CFG register bits */ +#define GPIO_BIT_CFG_TX_OE BIT_ULL(0) +#define GPIO_BIT_CFG_PIN_XOR BIT_ULL(1) +#define GPIO_BIT_CFG_INT_EN BIT_ULL(2) +#define GPIO_BIT_CFG_PIN_SEL_MASK GENMASK_ULL(26, 16) + +struct octeon_gpio { + void __iomem *base; +}; + +/* Returns the offset to the output register based on the offset and value */ +static u32 gpio_tx_reg(int offset, int value) +{ + u32 ret; + + ret = value ? GPIO_TX_SET : GPIO_TX_CLR; + if (offset > 63) + ret += GPIO1_OFFSET; + + return ret; +} + +/* Returns the offset to the input data register based on the offset */ +static u32 gpio_rx_dat_reg(int offset) +{ + u32 ret; + + ret = GPIO_RX_DAT; + if (offset > 63) + ret += GPIO1_OFFSET; + + return ret; +} + +/* Returns the bit configuration register based on the offset */ +static u32 gpio_bit_cfg_reg(int offset) +{ + return GPIO_BIT_CFG_OFFS + 8 * offset; +} + +static int octeon_gpio_dir_input(struct udevice *dev, unsigned int offset) +{ + struct octeon_gpio *gpio = dev_get_priv(dev); + + debug("%s(%s, %u)\n", __func__, dev->name, offset); + clrbits_64(gpio->base + gpio_bit_cfg_reg(offset), + GPIO_BIT_CFG_TX_OE | GPIO_BIT_CFG_PIN_XOR | + GPIO_BIT_CFG_INT_EN | GPIO_BIT_CFG_PIN_SEL_MASK); + + return 0; +} + +static int octeon_gpio_dir_output(struct udevice *dev, unsigned int offset, + int value) +{ + struct octeon_gpio *gpio = dev_get_priv(dev); + + debug("%s(%s, %u, %d)\n", __func__, dev->name, offset, value); + writeq(GPIO_BIT(offset), gpio->base + gpio_tx_reg(offset, value)); + + clrsetbits_64(gpio->base + gpio_bit_cfg_reg(offset), + GPIO_BIT_CFG_PIN_SEL_MASK | GPIO_BIT_CFG_INT_EN, + GPIO_BIT_CFG_TX_OE); + + return 0; +} + +static int octeon_gpio_get_value(struct udevice *dev, unsigned int offset) +{ + struct octeon_gpio *gpio = dev_get_priv(dev); + u64 reg = readq(gpio->base + gpio_rx_dat_reg(offset)); + + debug("%s(%s, %u): value: %d\n", __func__, dev->name, offset, + !!(reg & GPIO_BIT(offset))); + + return !!(reg & GPIO_BIT(offset)); +} + +static int octeon_gpio_set_value(struct udevice *dev, + unsigned int offset, int value) +{ + struct octeon_gpio *gpio = dev_get_priv(dev); + + debug("%s(%s, %u, %d)\n", __func__, dev->name, offset, value); + writeq(GPIO_BIT(offset), gpio->base + gpio_tx_reg(offset, value)); + + return 0; +} + +static int octeon_gpio_get_function(struct udevice *dev, unsigned int offset) +{ + struct octeon_gpio *gpio = dev_get_priv(dev); + u64 val = readq(gpio->base + gpio_bit_cfg_reg(offset)); + int pin_sel; + + debug("%s(%s, %u): GPIO_BIT_CFG: 0x%llx\n", __func__, dev->name, + offset, val); + pin_sel = FIELD_GET(GPIO_BIT_CFG_PIN_SEL_MASK, val); + if (pin_sel) + return GPIOF_FUNC; + else if (val & GPIO_BIT_CFG_TX_OE) + return GPIOF_OUTPUT; + else + return GPIOF_INPUT; +} + +static int octeon_gpio_xlate(struct udevice *dev, struct gpio_desc *desc, + struct ofnode_phandle_args *args) +{ + if (args->args_count < 1) + return -EINVAL; + + desc->offset = args->args[0]; + desc->flags = 0; + if (args->args_count > 1) { + if (args->args[1] & GPIO_ACTIVE_LOW) + desc->flags |= GPIOD_ACTIVE_LOW; + /* In the future add tri-state flag support */ + } + return 0; +} + +static const struct dm_gpio_ops octeon_gpio_ops = { + .direction_input = octeon_gpio_dir_input, + .direction_output = octeon_gpio_dir_output, + .get_value = octeon_gpio_get_value, + .set_value = octeon_gpio_set_value, + .get_function = octeon_gpio_get_function, + .xlate = octeon_gpio_xlate, +}; + +static int octeon_gpio_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct octeon_gpio *priv = dev_get_priv(dev); + char *end; +#if !defined(CONFIG_ARCH_OCTEON) + pci_dev_t bdf = dm_pci_get_bdf(dev); +#endif + +#if !defined(CONFIG_ARCH_OCTEON) + priv->base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, + PCI_REGION_MEM); +#else + priv->base = dev_remap_addr(dev); +#endif + if (!priv->base) { + debug("%s(%s): Could not get base address\n", + __func__, dev->name); + return -1; + } + +#if !defined(CONFIG_ARCH_OCTEON) + uc_priv->gpio_count = readq(priv->base + GPIO_CONST) & + GPIO_CONST_GPIOS_MASK; +#else + uc_priv->gpio_count = ofnode_read_u32_default(dev->node, + "nr-gpios", 32); +#endif + + uc_priv->bank_name = strdup(dev->name); + end = strchr(uc_priv->bank_name, '@'); + end[0] = 'A' + dev->seq; + end[1] = '\0'; + + debug("%s(%s): base address: %p, pin count: %d\n", + __func__, dev->name, priv->base, uc_priv->gpio_count); + + return 0; +} + +static const struct udevice_id octeon_gpio_ids[] = { + { .compatible = "cavium,thunder-8890-gpio" }, + { .compatible = "cavium,octeon-7890-gpio" }, + { } +}; + +U_BOOT_DRIVER(octeon_gpio) = { + .name = "octeon_gpio", + .id = UCLASS_GPIO, + .of_match = of_match_ptr(octeon_gpio_ids), + .probe = octeon_gpio_probe, + .priv_auto_alloc_size = sizeof(struct octeon_gpio), + .ops = &octeon_gpio_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +#if !defined(CONFIG_ARCH_OCTEON) +static struct pci_device_id octeon_gpio_supported[] = { + { PCI_VDEVICE(CAVIUM, PCI_DEVICE_ID_CAVIUM_GPIO) }, + { }, +}; + +U_BOOT_PCI_DEVICE(octeon_gpio, octeontx_gpio_supported); +#endif -- 2.26.2

2 2

[PATCH 00/11] Fixes for Nokia RX-51
by Pali Rohár 26 May '20

26 May '20

This patch series contain fixes for Nokia RX-51 board (aka N900). After these changes it is possible to run U-Boot in qemu emulator again. And U-Boot can boot kernel image from RAM, eMMC or OneNAND memory without problem. Pali Rohár (11): Nokia RX-51: Update my email address Nokia RX-51: Add README.nokia_rx51 file to MAINTAINERS Nokia RX-51: Move comment about CONFIG_SYS_TEXT_BASE to correct place Nokia RX-51: Move code from defconfig back to C header file Nokia RX-51: Revert back onenand defitions Nokia RX-51: Remove PART* macros Nokia RX-51: Remember setup_console_atag option Nokia RX-51: Enable CONFIG_CONSOLE_MUX Nokia RX-51: Disable some unused features to decrease size of u-boot binary Nokia RX-51: Update README.nokia_rx51 Nokia RX-51: Add automated test for running RX-51 build in qemu .travis.yml | 10 ++ board/nokia/rx51/MAINTAINERS | 3 +- board/nokia/rx51/lowlevel_init.S | 11 +- board/nokia/rx51/rx51.c | 43 ++++--- board/nokia/rx51/rx51.h | 2 +- board/nokia/rx51/tag_omap.h | 4 +- cmd/bootmenu.c | 2 +- configs/nokia_rx51_defconfig | 27 +++- doc/README.bootmenu | 2 +- doc/README.nokia_rx51 | 32 +++-- include/ansi.h | 2 +- include/configs/nokia_rx51.h | 88 ++++--------- test/rx51_test.sh | 208 +++++++++++++++++++++++++++++++ 13 files changed, 327 insertions(+), 107 deletions(-) create mode 100755 test/rx51_test.sh -- 2.20.1

5 68

[PATCH 1/2] riscv: Avoid the reserved memory fixup if src and dst point to the same place
by Bin Meng 26 May '20

26 May '20

From: Bin Meng <bin.meng(a)windriver.com> The copy of reserved memory node from source dtb to destination dtb can be avoided if they point to the same place. This is useful when OF_PRIOR_STAGE is used. Signed-off-by: Bin Meng <bin.meng(a)windriver.com> --- arch/riscv/lib/fdt_fixup.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/riscv/lib/fdt_fixup.c b/arch/riscv/lib/fdt_fixup.c index 6db48ad..5f523f0 100644 --- a/arch/riscv/lib/fdt_fixup.c +++ b/arch/riscv/lib/fdt_fixup.c @@ -82,10 +82,9 @@ int riscv_fdt_copy_resv_mem_node(const void *src, void *dst) * @fdt: Pointer to the device tree in which reserved memory node needs to be * added. * - * In RISC-V, any board compiled with OF_SEPARATE needs to copy the reserved - * memory node from the device tree provided by the firmware to the device tree - * used by U-Boot. This is a common function that individual board fixup - * functions can invoke. + * In RISC-V, any board needs to copy the reserved memory node from the device + * tree provided by the firmware to the device tree used by U-Boot. This is a + * common function that individual board fixup functions can invoke. * * Return: 0 on success or error otherwise. */ @@ -95,6 +94,11 @@ int riscv_board_reserved_mem_fixup(void *fdt) void *src_fdt_addr; src_fdt_addr = map_sysmem(gd->arch.firmware_fdt_addr, 0); + + /* avoid the copy if we are using the same device tree */ + if (src_fdt_addr == fdt) + return 0; + err = riscv_fdt_copy_resv_mem_node(src_fdt_addr, fdt); if (err < 0) return err; -- 2.7.4

1 2

Re: [U-Boot] Pull request: u-boot-riscv/master
by Rick Chen 26 May '20

26 May '20

Hi Tom > From: Tom Rini [mailto:trini@konsulko.com] > Sent: Monday, May 25, 2020 11:40 PM > To: Open Source Project uboot > Cc: u-boot(a)lists.denx.de; Rick Jian-Zhi Chen(陳建志) > Subject: Re: [U-Boot] Pull request: u-boot-riscv/master > > On Mon, May 25, 2020 at 04:01:08PM +0800, uboot(a)andestech.com wrote: > > > Hi Tom, > > > > Please pull some riscv updates: > > > > - Add Sipeed Maix support. > > - sifive: fix palmer's email address. > > - Move all SMP related SBI calls to SBI_v01. > > > > https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/690778926 > > > > Thanks > > Rick > > > > > > The following changes since commit 9c5fef577494769e3ff07952a85f9b7125ef765b: > > > > Merge git://git.denx.de/u-boot-usb (2020-05-22 22:58:50 -0400) > > > > are available in the Git repository at: > > > > git@gitlab.denx.de:u-boot/custodians/u-boot-riscv.git > > > > for you to fetch changes up to 421c4eb2dcf39f65c31c1804369267ed8a7b5607: > > > > riscv: Add Sipeed Maix support (2020-05-25 10:01:21 +0800) > > > > There's too many generic changes in this PR for this late in the cycle, for things I gather related to the Maix platform. All of the clk and DM changes impact virtually all platforms. Please re-do this PR to drop the Maix platform support for now, and resubmit that for -next, which I will be opening shortly. Everything else however is good for master. Thanks for your explanations. Actually I have the same concern with you before sending this PR. I have tried to ask Sean don't mix all codes together in one patchset. He shall separate and send them individually, If they are not highly dependent. Following are my suggestions from those patch-work: Re: [PATCH v2 01/11] clk: Always use the supplied struct clk https://patchwork.ozlabs.org/project/uboot/patch/da401261-b73f-afae-0702-ad… Re: [PATCH v4 07/17] spi: dw: Add mem_ops https://patchwork.ozlabs.org/project/uboot/patch/20200211060425.1619471-8-s… Re: [PATCH v5 33/33] riscv: Add Sipeed Maix support http://u-boot.10912.n7.nabble.com/PATCH-v5-00-33-riscv-Add-Sipeed-Maix-supp… Re: [PATCH v6 04/19] clk: Add functions to register CCF clock structs https://patchwork.ozlabs.org/project/uboot/patch/20200305181308.944595-5-se… I will drop the Maix platform support in next PR and re-send again. Thanks, Rick > Sorry. > > -- > Tom

1 0

[PATCH v2] x86: chromebook_coral: Fix a build error
by Simon Glass 26 May '20

26 May '20

At present coral does not build due to a missing header file. The need for this was introduced recently on master. Fix it. Fixes: e9a32698517 ("x86: apl: Use devicetree for FSP-M configuration") Signed-off-by: Simon Glass <sjg(a)chromium.org> --- Changes in v2: - Add Fixes tag for the first commit that showed this problem arch/x86/cpu/apollolake/fsp_bindings.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/cpu/apollolake/fsp_bindings.c b/arch/x86/cpu/apollolake/fsp_bindings.c index 501cbb7ef3..66f85b0d95 100644 --- a/arch/x86/cpu/apollolake/fsp_bindings.c +++ b/arch/x86/cpu/apollolake/fsp_bindings.c @@ -5,6 +5,7 @@ #include <common.h> #include <dm.h> +#include <log.h> #include <asm/arch/fsp_bindings.h> /** -- 2.27.0.rc0.183.gde8f92d652-goog

2 1

[PATCH v5 00/16] Add Rockchip RK3399 USB3.0 Host support
by Frank Wang 26 May '20

26 May '20

This series add quirks for DWC3 and add Rockchip RK3399 USB3.0 host support. The function has been tested pass on rk3399-evb and roc-rk3399-pc board. For V5 update: - Fix dwc3-generic driver followed Marek's comments for [PATCH v4 12/16]. - Add 'Reviewed-by' and 'Tested-by' tag for [PATCH v4 07/16] and [PATCH v4 08/16]. For V4 update: - Collect Jagan's all fixed patches [1]. - Amend specific u-boot changes from dts to dtsi for [PATCH v3 6/7]. For V3 update: - Fix compile error for [PATCH v2 1/9]. - Use Jagan's Type-C driver instead of [PATCH v2 5/9]. - Cleanup dts changes for [PATCH v2 7/9]. - Cleanup config changes for [PATCH v2 8/9] and [PATCH v2 9/9]. For V2 update: - Amend type-c driver followed Jagan's comments for [PATCH 5/8]. - Fix dts commit for [PATCH 7/8]. - Split RK3399 default config for [PATCH 8/8]. - Add 'Reviewed-by' tag for [PATCH 1/8], [PATCH 2/8] and [PATCH 3/8]. [1] https://patchwork.ozlabs.org/project/uboot/cover/20200506075025.1677-1-jaga… BR, Frank Frank Wang (7): usb: dwc3: add dis_enblslpm_quirk usb: dwc3: add dis_u2_freeclk_exists_quirk usb: dwc3: amend UTMI/UTMIW phy interface setup usb: dwc3: add make compatible for rockchip platform driver: usb: drop legacy rockchip xhci driver ARM: dts: rk3399-evb: usb3.0 host support configs: evb-rk3399: update support usb3.0 host Jagan Teki (9): clk: rk3399: Enable/Disable the USB2PHY clk clk: rk3399: Set empty for TCPHY assigned-clocks clk: rk3399: Enable/Disable TCPHY clocks phy: rockchip: Add Rockchip USB2PHY driver arm64: dts: rk3399: Move u2phy into root port phy: rockchip: Add Rockchip USB TypeC PHY driver usb: dwc3: Add disable u2mac linestate check quirk usb: dwc3: Enable AutoRetry feature in the controller roc-rk3399-pc: Enable USB3.0 Host arch/arm/dts/rk3399-evb-u-boot.dtsi | 13 + arch/arm/dts/rk3399.dtsi | 108 +-- configs/evb-rk3399_defconfig | 6 + configs/roc-pc-mezzanine-rk3399_defconfig | 5 + configs/roc-pc-rk3399_defconfig | 6 + drivers/Makefile | 1 + drivers/clk/rockchip/clk_rk3399.c | 38 + drivers/phy/Kconfig | 1 + drivers/phy/rockchip/Kconfig | 21 + drivers/phy/rockchip/Makefile | 7 + drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 312 +++++++ drivers/phy/rockchip/phy-rockchip-typec.c | 796 ++++++++++++++++++ drivers/usb/common/common.c | 25 + drivers/usb/dwc3/core.c | 106 ++- drivers/usb/dwc3/core.h | 19 + drivers/usb/dwc3/dwc3-generic.c | 33 +- drivers/usb/host/Kconfig | 9 - drivers/usb/host/Makefile | 1 - drivers/usb/host/xhci-rockchip.c | 196 ----- include/dwc3-uboot.h | 3 + include/linux/usb/phy.h | 18 + 21 files changed, 1427 insertions(+), 297 deletions(-) create mode 100644 drivers/phy/rockchip/Kconfig create mode 100644 drivers/phy/rockchip/Makefile create mode 100644 drivers/phy/rockchip/phy-rockchip-inno-usb2.c create mode 100644 drivers/phy/rockchip/phy-rockchip-typec.c delete mode 100644 drivers/usb/host/xhci-rockchip.c -- 2.17.1

4 36

[PATCH u-boot 0/2] eth/r8152: minor corrections
by Hayes Wang 26 May '20

26 May '20

These are minor corrections for r8152 driver. Hayes Wang (2): eth/r8152: fix assigning the wrong endpoint eth/r8152: fix typo in register name drivers/usb/eth/r8152.c | 22 ++++++++++++---------- drivers/usb/eth/r8152.h | 4 ++-- 2 files changed, 14 insertions(+), 12 deletions(-) -- 2.21.1

2 12