May 2020 - U-Boot

[PATCH] rockchip: rockpro64: Set cooling levels for pwm-fan
by Kurt Miller 01 Jun '20

01 Jun '20

The cooling levels are tuned to the fan that comes with the rockpro64 NAS case. A gpu_thermal zone was not added because having two active cooling maps control one physical fan causes them to compete for the fan speed which results in erratic fan behavior. Signed-off-by: Kurt Miller <kurt(a)intricatesoftware.com> --- arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 43 +++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi index deaa3efd39..c0e0396758 100644 --- a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi @@ -13,6 +13,49 @@ chosen { u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; }; + + fan: pwm-fan { + cooling-levels = <0 40 80 255>; + }; +}; + +&cpu_thermal { + trips { + cpu_warm: cpu_warm { + temperature = <50000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_med: cpu_med { + temperature = <60000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_hot: cpu_hot { + temperature = <65000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map2 { + trip = <&cpu_warm>; + cooling-device = <&fan THERMAL_NO_LIMIT 1>; + }; + + map3 { + trip = <&cpu_med>; + cooling-device = <&fan THERMAL_NO_LIMIT 2>; + }; + + map4 { + trip = <&cpu_hot>; + cooling-device = <&fan 2 THERMAL_NO_LIMIT>; + }; + }; }; &vdd_center { -- 2.26.2

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[PATCH 1/3] spl: fit: Minimally parse OS properties with FIT_IMAGE_TINY
by Samuel Holland 01 Jun '20

01 Jun '20

Some boards, specifically 64-bit Allwinner boards (sun50i), are extremely limited on SPL size. One strategy that was used to make space was to remove the FIT "os" property parsing code, because it uses a rather large lookup table. However, this forces the legacy FIT parsing code path, which requires the "firmware" entry in the FIT to reference the U-Boot binary, even if U-Boot is not the next binary in the boot sequence (for example, on sun50i boards, ATF is run first). This prevents the same FIT image from being used with a SPL with CONFIG_SPL_FIT_IMAGE_TINY=n and CONFIG_SPL_ATF=y, because the boot method selection code looks at `spl_image.os`, which is only set from the "firmware" entry's "os" property. To be able to use CONFIG_SPL_ATF=y, the "firmware" entry in the FIT must be ATF, and U-Boot must be a loadable. For this to work, we need to parse the "os" property just enough to tell U-Boot from other images, so we can find it in the loadables list to append the FDT, and so we don't try to append the FDT to ATF (which could clobber adjacent firmware). So add the minimal code necessary to distinguish U-Boot/non-U-Boot loadables with CONFIG_SPL_FIT_IMAGE_TINY=y. This adds about 300 bytes, much less than the 7400 bytes added by CONFIG_SPL_FIT_IMAGE_TINY=n. Signed-off-by: Samuel Holland <samuel(a)sholland.org> --- common/spl/Kconfig | 4 +--- common/spl/spl_fit.c | 17 ++++++++++++++++- 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 9feadb5e43..f2fa12354d 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -448,9 +448,7 @@ config SPL_FIT_IMAGE_TINY Enable this to reduce the size of the FIT image loading code in SPL, if space for the SPL binary is very tight. - This removes the detection of image types (which forces the - first image to be treated as having a U-Boot style calling - convention) and skips the recording of each loaded payload + This skips the recording of each loaded payload (i.e. loadable) into the FDT (modifying the loaded FDT to ensure this information is available to the next image invoked). diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index c51e4beb1c..b9dd4211aa 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -464,7 +464,22 @@ static int spl_fit_record_loadable(const void *fit, int images, int index, static int spl_fit_image_get_os(const void *fit, int noffset, uint8_t *os) { #if CONFIG_IS_ENABLED(FIT_IMAGE_TINY) && !defined(CONFIG_SPL_OS_BOOT) - return -ENOTSUPP; + const char *name = fdt_getprop(fit, noffset, FIT_OS_PROP, NULL); + + if (!name) + return -ENOENT; + + /* + * We don't care what the type of the image actually is, + * only whether or not it is U-Boot. This saves some + * space by omitting the large table of OS types. + */ + if (!strcmp(name, "u-boot")) + *os = IH_OS_U_BOOT; + else + *os = IH_OS_INVALID; + + return 0; #else return fit_image_get_os(fit, noffset, os); #endif -- 2.24.1

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[PATCH 1/3] net: sun8i_emac: Use consistent clock bitfield definitions
by Samuel Holland 01 Jun '20

01 Jun '20

While the R40 uses a different register for EMAC clock configuration than other chips, the register has a very similar layout. Reuse the existing bitfield definitions in this file, since they match. This allows the driver to compile on the H6 platform, where the CCM_GMAC_CTRL definitions are not present. Signed-off-by: Samuel Holland <samuel(a)sholland.org> --- drivers/net/sun8i_emac.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index 1ae776b446..dcd18833a2 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -296,9 +296,9 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata, if (priv->variant == R40_GMAC) { /* Select RGMII for R40 */ reg = readl(priv->sysctl_reg + 0x164); - reg |= CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII | - CCM_GMAC_CTRL_GPIT_RGMII | - CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY); + reg |= SC_ETCS_INT_GMII | + SC_EPIT | + (CONFIG_GMAC_TX_DELAY << SC_ETXDC_OFFSET); writel(reg, priv->sysctl_reg + 0x164); return 0; -- 2.24.1

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[PATCH] sunxi: Silence warning about non-static inline function
by Samuel Holland 01 Jun '20

01 Jun '20

When compiling with CONFIG_SPL_SERIAL=n, gcc warns about mbus_configure_port not being marked as static: In file included from include/common.h:34, from arch/arm/mach-sunxi/dram_sunxi_dw.c:11: include/log.h:185:4: warning: 'printf' is static but used in inline function 'mbus_configure_port' which is not static 185 | printf(pr_fmt(fmt), ##args); \ | ^~~~~~ include/log.h:192:2: note: in expansion of macro 'debug_cond' 192 | debug_cond(_DEBUG, fmt, ##args) | ^~~~~~~~~~ arch/arm/mach-sunxi/dram_sunxi_dw.c:100:2: note: in expansion of macro 'debug' 100 | debug("MBUS port %d cfg0 %08x cfg1 %08x\n", port, cfg0, cfg1); | ^~~~~ Fix this by updating the function accordingly. Signed-off-by: Samuel Holland <samuel(a)sholland.org> --- arch/arm/mach-sunxi/dram_sunxi_dw.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c index 85e7a1874e..f8d4b32e37 100644 --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c @@ -76,15 +76,15 @@ enum { MBUS_QOS_HIGHEST }; -inline void mbus_configure_port(u8 port, - bool bwlimit, - bool priority, - u8 qos, /* MBUS_QOS_LOWEST .. MBUS_QOS_HIGEST */ - u8 waittime, /* 0 .. 0xf */ - u8 acs, /* 0 .. 0xff */ - u16 bwl0, /* 0 .. 0xffff, bandwidth limit in MB/s */ - u16 bwl1, - u16 bwl2) +static inline void mbus_configure_port(u8 port, + bool bwlimit, + bool priority, + u8 qos, /* MBUS_QOS_LOWEST .. MBUS_QOS_HIGEST */ + u8 waittime, /* 0 .. 0xf */ + u8 acs, /* 0 .. 0xff */ + u16 bwl0, /* 0 .. 0xffff, bandwidth limit in MB/s */ + u16 bwl1, + u16 bwl2) { struct sunxi_mctl_com_reg * const mctl_com = (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; -- 2.24.1

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[PATCH] phy: sun4i-usb: Align H6 initialization logic with the kernel
by Roman Stratiienko 01 Jun '20

01 Jun '20

H6 SOC needs additional initialization of PHY registers. Corresponding changes can be found in the kernel patch [1]. Without this changes there is no enumeration of 'musb' gadget. [1] - https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?… Fixes: 35fa673e0e5f ("sunxi: phy: Add USB PHY support for Allwinner H6") Signed-off-by: Roman Stratiienko <r.stratiienko(a)gmail.com> --- CC: Ondrej Jirman <megous(a)megous.com> CC: Icenowy Zheng <icenowy(a)aosc.io> CC: Marek Vasut <marex(a)denx.de> CC: linux-sunxi(a)googlegroups.com --- drivers/phy/allwinner/phy-sun4i-usb.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c index 612c428cf5..688ee7d4cc 100644 --- a/drivers/phy/allwinner/phy-sun4i-usb.c +++ b/drivers/phy/allwinner/phy-sun4i-usb.c @@ -279,7 +279,8 @@ static int sun4i_usb_phy_init(struct phy *phy) return ret; } - if (data->cfg->type == sun8i_a83t_phy) { + if (data->cfg->type == sun8i_a83t_phy || + data->cfg->type == sun50i_h6_phy) { if (phy->id == 0) { val = readl(data->base + data->cfg->phyctl_offset); val |= PHY_CTL_VBUSVLDEXT; @@ -321,7 +322,8 @@ static int sun4i_usb_phy_exit(struct phy *phy) int ret; if (phy->id == 0) { - if (data->cfg->type == sun8i_a83t_phy) { + if (data->cfg->type == sun8i_a83t_phy || + data->cfg->type == sun50i_h6_phy) { void __iomem *phyctl = data->base + data->cfg->phyctl_offset; -- 2.25.1

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[PATCH 0/1] Add support for booting into userspace fastboot
by Roman Kovalivskyi 01 Jun '20

01 Jun '20

Android 10 adds support for dynamic partitions and in order to support them userspace fastboot must be used[1]. New tool called fastbootd is included into recovery image. Userspace fastboot works from recovery and is launched if: 1) - Dynamic partitioning is enabled 2) - Boot control block has 'boot-fastboot' value into command field The bootloader is expected[2] to load and boot into the recovery image upon seeing boot-fastboot in the BCB command. Recovery then parses the BCB message and switches to fastbootd mode. Please note that boot script is expected to handle 'boot-fastboot' command in BCB and load into recovery mode. Bootloader must support[3] 'reboot fastboot' command which should reboot device into userspace fastboot to accomodate those changes. Another command that bootloader must support[3] is 'reboot recovery'. This command should simply reboot device into recovery mode. [1] - https://source.android.com/devices/bootloader/fastbootd [2] - https://source.android.com/devices/bootloader/fastbootd#unified_fastboot_an… [3] - https://source.android.com/devices/bootloader/fastbootd#modifications_to_th… Roman Stratiienko (1): fastboot: add support for 'reboot fastboot' command drivers/fastboot/fb_command.c | 42 +++++++++++++++++++++++++++++++++ drivers/fastboot/fb_common.c | 31 ++++++++++++++++++++++++ drivers/usb/gadget/f_fastboot.c | 2 ++ include/fastboot.h | 9 +++++++ 4 files changed, 84 insertions(+) -- 2.17.1

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Pull request: u-boot-rockchip-20200531
by Kever Yang 01 Jun '20

01 Jun '20

Hi Tom, Please pull the rockchip updates/fixes: - Fix mmc of path after syncfrom kernel dts; - Add dwc3 host support with DM for rk3399; - Add usb2phy and typec phy for rockchip platform; - Migrate board list doc to rockchip.rst; - Add rk3399 Pinebook Pro board support; - Update dram_init in board_init and add memory node in SPL; Gitlab ci: https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip/pipelines/3509 Thanks, - Kever The following changes since commit ab80137cc436e977ef91a154372ae5aeae3f4fb0: Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell (2020-05-27 10:56:25 -0400) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip.git tags/u-boot-rockchip-20200531 for you to fetch changes up to a343b4fe739a56ef248f01d96d80d080228b4068: spl: add fixed memory node in target fdt also when loading ATF (2020-05-31 22:22:07 +0800) ---------------------------------------------------------------- Frank Wang (8): arm: mach-rockchip: bind sub-nodes for rk3399_syscon usb: dwc3: add dis_enblslpm_quirk usb: dwc3: add dis_u2_freeclk_exists_quirk usb: dwc3: amend UTMI/UTMIW phy interface setup usb: dwc3: add make compatible for rockchip platform driver: usb: drop legacy rockchip xhci driver ARM: dts: rk3399-evb: usb3.0 host support configs: evb-rk3399: update support usb3.0 host Heiko Stuebner (2): rockchip: spl: do full dram_init instead of only probing spl: add fixed memory node in target fdt also when loading ATF Jagan Teki (13): rockchip: Fix spl mmc boot device ofpath clk: rk3399: Fix eMMC get_clk reg offset arm64: dts: rk3399-nanopi4: Add u-boot,spl-boot-order nanopc-t4: Enable USB Gadget doc: rockchip: Document eMMC program steps clk: rk3399: Enable/Disable the USB2PHY clk clk: rk3399: Set empty for TCPHY assigned-clocks clk: rk3399: Enable/Disable TCPHY clocks phy: rockchip: Add Rockchip USB2PHY driver phy: rockchip: Add Rockchip USB TypeC PHY driver usb: dwc3: Add disable u2mac linestate check quirk usb: dwc3: Enable AutoRetry feature in the controller roc-rk3399-pc: Enable USB3.0 Host Marcin Juszkiewicz (2): rockchip: enable USB OHCI host for RockPro64 rockchip: rockpro64: enable DM_KEYBOARD Mark Kettenis (2): pci: Make Rockchip PCIe voltage regulators optional rk3399: Enable NVMe distro bootcmd Peter Robinson (3): dt-bindings: input: adopt Linux gpio-keys binding constants arm: dts: rockchip: Add initial DT for Pinebook Pro rockchip: Add initial support for the Pinebook Pro laptop from Pine64. Walter Lozano (3): doc: board: rockchip: Improve supported board list format doc: board: rockchip: Add missing supported boards doc: rockchip: Remove list of supported boards arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-evb-u-boot.dtsi | 15 +- arch/arm/dts/rk3399-ficus-u-boot.dtsi | 2 +- arch/arm/dts/rk3399-nanopi4-u-boot.dtsi | 6 + arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi | 43 + arch/arm/dts/rk3399-pinebook-pro.dts | 1096 ++++++++++++++++++++ arch/arm/dts/rk3399-rock960-u-boot.dtsi | 2 +- arch/arm/mach-rockchip/rk3399/Kconfig | 8 + arch/arm/mach-rockchip/rk3399/rk3399.c | 4 +- arch/arm/mach-rockchip/rk3399/syscon_rk3399.c | 3 + arch/arm/mach-rockchip/spl.c | 9 +- board/pine64/pinebook-pro-rk3399/Kconfig | 15 + board/pine64/pinebook-pro-rk3399/MAINTAINERS | 8 + board/pine64/pinebook-pro-rk3399/Makefile | 1 + .../pinebook-pro-rk3399/pinebook-pro-rk3399.c | 75 ++ board/theobroma-systems/puma_rk3399/puma-rk3399.c | 4 +- common/spl/spl.c | 19 +- configs/evb-rk3399_defconfig | 6 + configs/nanopc-t4-rk3399_defconfig | 3 + configs/pinebook-pro-rk3399_defconfig | 84 ++ configs/roc-pc-mezzanine-rk3399_defconfig | 5 + configs/roc-pc-rk3399_defconfig | 6 + configs/rockpro64-rk3399_defconfig | 3 + doc/README.rockchip | 72 +- doc/board/rockchip/rockchip.rst | 116 ++- drivers/Makefile | 1 + drivers/clk/rockchip/clk_rk3399.c | 40 +- drivers/pci/pcie_rockchip.c | 33 +- drivers/phy/Kconfig | 1 + drivers/phy/rockchip/Kconfig | 21 + drivers/phy/rockchip/Makefile | 7 + drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 312 ++++++ drivers/phy/rockchip/phy-rockchip-typec.c | 796 ++++++++++++++ drivers/usb/common/common.c | 25 + drivers/usb/dwc3/core.c | 106 +- drivers/usb/dwc3/core.h | 19 + drivers/usb/dwc3/dwc3-generic.c | 34 +- drivers/usb/host/Kconfig | 9 - drivers/usb/host/Makefile | 1 - drivers/usb/host/xhci-rockchip.c | 197 ---- include/configs/pinebook-pro-rk3399.h | 28 + include/configs/rockchip-common.h | 7 + include/configs/rockpro64_rk3399.h | 2 + include/dt-bindings/input/gpio-keys.h | 13 + include/dwc3-uboot.h | 3 + include/linux/usb/phy.h | 18 + 46 files changed, 2899 insertions(+), 380 deletions(-) create mode 100644 arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-pinebook-pro.dts create mode 100644 board/pine64/pinebook-pro-rk3399/Kconfig create mode 100644 board/pine64/pinebook-pro-rk3399/MAINTAINERS create mode 100644 board/pine64/pinebook-pro-rk3399/Makefile create mode 100644 board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c create mode 100644 configs/pinebook-pro-rk3399_defconfig create mode 100644 drivers/phy/rockchip/Kconfig create mode 100644 drivers/phy/rockchip/Makefile create mode 100644 drivers/phy/rockchip/phy-rockchip-inno-usb2.c create mode 100644 drivers/phy/rockchip/phy-rockchip-typec.c delete mode 100644 drivers/usb/host/xhci-rockchip.c create mode 100644 include/configs/pinebook-pro-rk3399.h create mode 100644 include/dt-bindings/input/gpio-keys.h

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[PATCH v2] drivers: crypto: mod_exp_sw: Re-add DM_FLAG_PRE_RELOC
by Jan Kiszka 01 Jun '20

01 Jun '20

From: Jan Kiszka <jan.kiszka(a)siemens.com> This driver is safe to use in SPL without relocation. Denying DM_FLAG_PRE_RELOC prevents its usability for verifying the main U-Boot or other artifacts from the SPL unless needless enabling the full driver set (SPL_OF_PLATDATA). Fixes: 17e117408571 ("drivers: crypto: rsa_mod_exp: avoid DM_FLAG_PRE_RELOC") CC: Heinrich Schuchardt <xypron.glpk(a)gmx.de> CC: Marek Vasut <marex(a)denx.de> Signed-off-by: Jan Kiszka <jan.kiszka(a)siemens.com> --- Changes in v2: - patch the file I actually meant to patch (was papered over by a local queue) drivers/crypto/rsa_mod_exp/mod_exp_sw.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/crypto/rsa_mod_exp/mod_exp_sw.c b/drivers/crypto/rsa_mod_exp/mod_exp_sw.c index c9b571a461..46b9f1825c 100644 --- a/drivers/crypto/rsa_mod_exp/mod_exp_sw.c +++ b/drivers/crypto/rsa_mod_exp/mod_exp_sw.c @@ -31,6 +31,7 @@ U_BOOT_DRIVER(mod_exp_sw) = { .name = "mod_exp_sw", .id = UCLASS_MOD_EXP, .ops = &mod_exp_ops_sw, + .flags = DM_FLAG_PRE_RELOC, }; U_BOOT_DEVICE(mod_exp_sw) = { -- 2.26.1

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[PATCHv5][2/2] rockchip: rk3328: add rock-pi-e-rk3328_defconfig file
by b.l.huang 01 Jun '20

01 Jun '20

This commit add the default configuration file and relevant description for rock-pi-e board Signed-off-by: Banglang Huang <banglang.huang(a)foxmail.com> --- board/rockchip/evb_rk3328/MAINTAINERS | 7 ++ configs/rock-pi-e-rk3328_defconfig | 104 ++++++++++++++++++++++++++ doc/board/rockchip/rockchip.rst | 1 + 3 files changed, 112 insertions(+) create mode 100644 configs/rock-pi-e-rk3328_defconfig diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index 89becf41c5..e7dd59ff4e 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -17,3 +17,10 @@ M: Matwey V. Kornilov <matwey.kornilov(a)gmail.com> S: Maintained F: configs/rock64-rk3328_defconfig F: arch/arm/dts/rk3328-rock64-u-boot.dtsi + +ROCKPIE-RK3328 +M: Banglang Huang <banglang.huang(a)foxmail.com> +S: Maintained +F: configs/rock-pi-e-rk3328_defconfig +F: arch/arm/dts/rk3328-rock-pi-e.dts +F: arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig new file mode 100644 index 0000000000..759838775f --- /dev/null +++ b/configs/rock-pi-e-rk3328_defconfig @@ -0,0 +1,104 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_ROCKCHIP_RK3328=y +CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_TPL_LIBCOMMON_SUPPORT=y +CONFIG_TPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x4000000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SMBIOS_PRODUCT_NAME="rock-pi-e_rk3328" +CONFIG_DEBUG_UART=y +CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock-pi-e.dtb" +CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_TPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL_DRIVERS_MISC_SUPPORT=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_TPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock-pi-e" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_TPL_OF_PLATDATA=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_TPL_DM=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_TPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_TPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_DM_RESET=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYSRESET=y +# CONFIG_TPL_SYSRESET is not set +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC2=y +CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_TPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y +CONFIG_SMBIOS_MANUFACTURER="radxa" diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 7b72fab496..e7dee7d0ac 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -48,6 +48,7 @@ List of mainline supported rockchip boards: - Rockchip Evb-RK3328 (evb-rk3328) - Pine64 Rock64 (rock64-rk3328) - Firefly-RK3328 (roc-cc-rk3328) + - Radxa Rockpi E (rock-pi-e-rk3328) * rk3368 - GeekBox (geekbox) - PX5 EVB (evb-px5) -- 2.17.1

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[PATCHv5][1/2] rockchip: rk3328: add rock-pi-e dts file
by b.l.huang 01 Jun '20

01 Jun '20

The ROCK-PI-E is a credit card size SBC based on Rockchip RK3328 Quad-Core ARM Cortex A53. Net - Dual ethernet port, 1 X Gbe, 1 X 100M USB - USB 3.0 DC - USB-Type C, 5V 2A Storage - TF card, eMMC Just build idbloader.img and u-boot.itb for Rockpi E board and follow the blow steps to replace the relevant partition. dd if=idbloader.img of=/dev/sdcard seek=64 conv=notrunc dd if=u-boot.itb of=/dev/sdcard seek=16384 conv=notrunc Signed-off-by: Banglang Huang <banglang.huang(a)foxmail.com> --- Changes for v5 - Update the board information to doc/board/rockchip/rockchip.rst Changes for v4 - separate dts file to another commit - fix bootup on tpl / spl mode Changes for v3 - rename to rock-pi-e Changes for v2 - add introduction for rockpie in doc/README.rockchip - enable CONFIG_MISC_INIT_R, CONFIG_SMBIOS_MANUFACTURER, and CONFIG_SMBIOS_PRODUCT_NAME --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi | 33 +++ arch/arm/dts/rk3328-rock-pi-e.dts | 267 ++++++++++++++++++++++ 3 files changed, 302 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi create mode 100644 arch/arm/dts/rk3328-rock-pi-e.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 12ec6c71dc..67d1adea2d 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -107,7 +107,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \ dtb-$(CONFIG_ROCKCHIP_RK3328) += \ rk3328-evb.dtb \ rk3328-roc-cc.dtb \ - rk3328-rock64.dtb + rk3328-rock64.dtb \ + rk3328-rock-pi-e.dtb dtb-$(CONFIG_ROCKCHIP_RK3368) += \ rk3368-lion.dtb \ diff --git a/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi b/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi new file mode 100644 index 0000000000..bf5b1f3adc --- /dev/null +++ b/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2020 Radxa + */ + +#include "rk3328-u-boot.dtsi" +#include "rk3328-sdram-ddr3-666.dtsi" + +&gpio0 { + u-boot,dm-spl; +}; + +&pinctrl { + u-boot,dm-spl; +}; + +&sdmmc0m1_gpio { + u-boot,dm-spl; +}; + +&pcfg_pull_up_4ma { + u-boot,dm-spl; +}; + +&usb_host0_xhci { + vbus-supply = <&vcc5v0_host_xhci>; + status = "okay"; +}; + +/* Need this and all the pinctrl/gpio stuff above to set pinmux */ +&vcc_sd { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/rk3328-rock-pi-e.dts b/arch/arm/dts/rk3328-rock-pi-e.dts new file mode 100644 index 0000000000..21656b64a2 --- /dev/null +++ b/arch/arm/dts/rk3328-rock-pi-e.dts @@ -0,0 +1,267 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2020 Radxa + */ + +/dts-v1/; +#include "rk3328.dtsi" + +/ { + model = "Radxa Rockpi E"; + compatible = "radxa,rock-pi-e", "rockchip,rk3328"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac_clkin: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0m1_gpio>; + regulator-name = "vcc_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io>; + }; + + vcc5v0_host_xhci: vcc5v0-host-xhci-drv { + compatible = "regulator-fixed"; + enable-active-high; + regulator-name = "vcc5v0_host_xhci"; + gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + supports-emmc; + disable-wp; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc18_emmc>; + status = "okay"; +}; + +&gmac2io { + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; + clock_in_out = "input"; + phy-supply = <&vcc_io>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_pins>; + snps,force_thresh_dma_mode; + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x26>; + rx_delay = <0x11>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + rk805: rk805@18 { + compatible = "rockchip,rk805"; + status = "okay"; + reg = <0x18>; + interrupt-parent = <&gpio2>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk805-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_io>; + vcc6-supply = <&vcc_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_18: LDO_REG1 { + regulator-name = "vcc_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_emmc: LDO_REG2 { + regulator-name = "vcc18_emmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + }; + }; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vcc_io>; + vccio2-supply = <&vcc18_emmc>; + vccio3-supply = <&vcc_io>; + vccio4-supply = <&vcc_io>; + vccio5-supply = <&vcc_io>; + vccio6-supply = <&vcc_io>; + pmuio-supply = <&vcc_io>; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + max-frequency = <150000000>; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; + supports-sd; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb20_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; -- 2.17.1

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