November 2020 - U-Boot

U-Boot 2020.07 seems confused by valid GPT partition tables
by Dennis Clarke 05 Nov '20

05 Nov '20

I am trying to boot a reasonable qemu instance that was running for about a dozen hours. I have four qemu raw disk images which have valid GPT partition labels and filesystem regions therein thus : deimos_rv64gc$ ls -lap total 18886740 drwxr-xr-x 7 riscv riscv 4096 Nov 3 20:40 ./ drwxr-xr-x 7 root root 4096 Nov 2 16:04 ../ -rw------- 1 riscv riscv 150 Jan 8 2020 .Xauthority -rw------- 1 riscv riscv 14399 Nov 2 19:52 .bash_history -rw-r--r-- 1 riscv riscv 220 Apr 18 2019 .bash_logout -rw-r--r-- 1 riscv riscv 3984 Aug 28 2019 .bashrc drwx------ 3 riscv riscv 4096 Oct 14 2019 .config/ drwx------ 3 riscv riscv 4096 Aug 28 2019 .gnupg/ drwx------ 2 riscv riscv 4096 Nov 2 17:18 .irssi/ -rw-r--r-- 1 riscv riscv 807 Aug 28 2019 .profile drwxr-xr-x 2 riscv riscv 4096 Nov 2 19:14 .ssh/ -rw------- 1 riscv riscv 10986 Nov 3 20:09 .viminfo -rw-r--r-- 1 riscv riscv 265 Nov 18 2019 .vimrc -rw-r--r-- 1 riscv riscv 5402802688 Nov 4 12:40 FreeBSD-13.0-CURRENT-riscv-riscv64.raw -rw-r--r-- 1 riscv riscv 577 Jan 26 2020 freebsd_email_config -rw-r--r-- 1 riscv riscv 34359738368 Nov 4 12:40 freebsd_zpool_1.raw -rw-r--r-- 1 riscv riscv 34359738368 Nov 4 12:40 freebsd_zpool_2.raw -rw-r--r-- 1 riscv riscv 34359738368 Nov 4 12:40 freebsd_zpool_3.raw -rw-r--r-- 1 riscv riscv 34359738368 Nov 3 20:13 freebsd_zpool_4.raw -rw-r--r-- 1 riscv riscv 40 Dec 19 2019 pi.dat drwxr-xr-x 6 riscv riscv 4096 Nov 27 2019 qemu/ -rw-r--r-- 1 riscv riscv 22946 Nov 3 20:40 readme.mhorne -rwxr-xr-x 1 riscv riscv 1039 Nov 3 19:44 rv64imafdc.sh -rw-r--r-- 1 riscv riscv 921 Nov 19 2019 t132s -rw-r--r-- 1 riscv riscv 551064 Nov 3 17:26 u-boot-qemu-riscv64.bin deimos_rv64gc$ deimos_rv64gc$ fdisk FreeBSD-13.0-CURRENT-riscv-riscv64.raw Welcome to fdisk (util-linux 2.33.1). Changes will remain in memory only, until you decide to write them. Be careful before using the write command. Command (m for help): p Disk FreeBSD-13.0-CURRENT-riscv-riscv64.raw: 5 GiB, 5402802688 bytes, 10552349 sectors Units: sectors of 1 * 512 = 512 bytes Sector size (logical/physical): 512 bytes / 512 bytes I/O size (minimum/optimal): 512 bytes / 512 bytes Disklabel type: gpt Disk identifier: 9E0C31F4-163C-11EB-BC34-94C6911BAC8D Device Start End Sectors Size Type FreeBSD-13.0-CURRENT-riscv-riscv64.raw1 3 66586 66584 32.5M EFI System FreeBSD-13.0-CURRENT-riscv-riscv64.raw2 66587 2163738 2097152 1G FreeBSD swap FreeBSD-13.0-CURRENT-riscv-riscv64.raw3 2163739 10552346 8388608 4G FreeBSD UFS Command (m for help): q deimos_rv64gc$ fdisk freebsd_zpool_1.raw Welcome to fdisk (util-linux 2.33.1). Changes will remain in memory only, until you decide to write them. Be careful before using the write command. Command (m for help): p Disk freebsd_zpool_1.raw: 32 GiB, 34359738368 bytes, 67108864 sectors Units: sectors of 1 * 512 = 512 bytes Sector size (logical/physical): 512 bytes / 512 bytes I/O size (minimum/optimal): 512 bytes / 512 bytes Disklabel type: gpt Disk identifier: BB2C71A1-1E10-11EB-A047-D56582AA2475 Device Start End Sectors Size Type freebsd_zpool_1.raw1 2048 67106815 67104768 32G FreeBSD ZFS Command (m for help): q deimos_rv64gc$ fdisk freebsd_zpool_2.raw Welcome to fdisk (util-linux 2.33.1). Changes will remain in memory only, until you decide to write them. Be careful before using the write command. Command (m for help): p Disk freebsd_zpool_2.raw: 32 GiB, 34359738368 bytes, 67108864 sectors Units: sectors of 1 * 512 = 512 bytes Sector size (logical/physical): 512 bytes / 512 bytes I/O size (minimum/optimal): 512 bytes / 512 bytes Disklabel type: gpt Disk identifier: BCB44094-1E10-11EB-A047-D56582AA2475 Device Start End Sectors Size Type freebsd_zpool_2.raw1 2048 67106815 67104768 32G FreeBSD ZFS Command (m for help): q deimos_rv64gc$ fdisk freebsd_zpool_2.raw Welcome to fdisk (util-linux 2.33.1). Changes will remain in memory only, until you decide to write them. Be careful before using the write command. Command (m for help): p Disk freebsd_zpool_2.raw: 32 GiB, 34359738368 bytes, 67108864 sectors Units: sectors of 1 * 512 = 512 bytes Sector size (logical/physical): 512 bytes / 512 bytes I/O size (minimum/optimal): 512 bytes / 512 bytes Disklabel type: gpt Disk identifier: BCB44094-1E10-11EB-A047-D56582AA2475 Device Start End Sectors Size Type freebsd_zpool_2.raw1 2048 67106815 67104768 32G FreeBSD ZFS Command (m for help): q deimos_rv64gc$ fdisk freebsd_zpool_3.raw Welcome to fdisk (util-linux 2.33.1). Changes will remain in memory only, until you decide to write them. Be careful before using the write command. Command (m for help): p Disk freebsd_zpool_3.raw: 32 GiB, 34359738368 bytes, 67108864 sectors Units: sectors of 1 * 512 = 512 bytes Sector size (logical/physical): 512 bytes / 512 bytes I/O size (minimum/optimal): 512 bytes / 512 bytes Disklabel type: gpt Disk identifier: BD69AAB4-1E10-11EB-A047-D56582AA2475 Device Start End Sectors Size Type freebsd_zpool_3.raw1 2048 67106815 67104768 32G FreeBSD ZFS Command (m for help): q deimos_rv64gc$ fdisk freebsd_zpool_4.raw Welcome to fdisk (util-linux 2.33.1). Changes will remain in memory only, until you decide to write them. Be careful before using the write command. Command (m for help): p Disk freebsd_zpool_4.raw: 32 GiB, 34359738368 bytes, 67108864 sectors Units: sectors of 1 * 512 = 512 bytes Sector size (logical/physical): 512 bytes / 512 bytes I/O size (minimum/optimal): 512 bytes / 512 bytes Disklabel type: gpt Disk identifier: BE1134F9-1E10-11EB-A047-D56582AA2475 Device Start End Sectors Size Type freebsd_zpool_4.raw1 2048 67106815 67104768 32G FreeBSD ZFS Command (m for help): q deimos_rv64gc$ However u-boot blows up with a complaint about the filesystem type ?? deimos_rv64gc$ deimos_rv64gc$ ./rv64imafdc.sh OpenSBI v0.8 ____ _____ ____ _____ / __ \ / ____| _ \_ _| | | | |_ __ ___ _ __ | (___ | |_) || | | | | | '_ \ / _ \ '_ \ \___ \| _ < | | | |__| | |_) | __/ | | |____) | |_) || |_ \____/| .__/ \___|_| |_|_____/|____/_____| | | |_| Platform Name : riscv-virtio,qemu Platform Features : timer,mfdeleg Platform HART Count : 2 Boot HART ID : 0 Boot HART ISA : rv64imafdcsu BOOT HART Features : pmp,scounteren,mcounteren,time BOOT HART PMP Count : 16 Firmware Base : 0x80000000 Firmware Size : 100 KB Runtime SBI Version : 0.2 MIDELEG : 0x0000000000000222 MEDELEG : 0x000000000000b109 PMP0 : 0x0000000080000000-0x000000008001ffff (A) PMP1 : 0x0000000000000000-0xffffffffffffffff (A,R,W,X) U-Boot 2020.07 (Oct 25 2020 - 12:59:03 +0000) CPU: rv64imafdcsu Model: riscv-virtio,qemu DRAM: 8 GiB In: uart@10000000 Out: uart@10000000 Err: uart@10000000 Net: Warning: virtio-net#6 using MAC address from ROM eth0: virtio-net#6 Hit any key to stop autoboot: 0 Device 0: QEMU VirtIO Block Device Type: Hard Disk Capacity: 5152.5 MB = 5.0 GB (10552349 x 512) ... is now current device Scanning virtio 0:1... ** Unable to read file / ** Found EFI removable media binary efi/boot/bootriscv64.efi libfdt fdt_check_header(): FDT_ERR_BADMAGIC Scanning disk virtio-blk#1... ** Unrecognized filesystem type ** ** Unrecognized filesystem type ** Scanning disk virtio-blk#2... Unhandled exception: Store/AMO access fault EPC: 00000000fff6f9fa TVAL: 0000000000000018 ### ERROR ### Please RESET the board ### qemu-system-riscv64: terminating on signal 1 from pid 9968 (-bash) deimos_rv64gc$ deimos_rv64gc$ Is there an update to u-boot that recognizes the valid GPT partition labels ? -- Dennis Clarke RISC-V/SPARC/PPC/ARM/CISC UNIX and Linux spoken GreyBeard and suspenders optional

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[PATCH] arch: Move NEEDS_MANUAL_RELOC symbol to Kconfig
by Michal Simek 04 Nov '20

04 Nov '20

CONFIG_NEEDS_MANUAL_RELOC macro was out of Kconfig. Move it there to be able to use compile-time checks to reduce the number of build paths. Fixes: f9a882438966 ("dm: core: Convert #ifdef to if() in root.c") for Microblaze Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/Kconfig | 5 +++++ arch/m68k/include/asm/config.h | 2 -- arch/microblaze/include/asm/config.h | 4 ---- scripts/config_whitelist.txt | 1 - 4 files changed, 5 insertions(+), 7 deletions(-) diff --git a/arch/Kconfig b/arch/Kconfig index 683e38431906..3b9fcce980ab 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -4,6 +4,9 @@ config CREATE_ARCH_SYMLINK config HAVE_ARCH_IOREMAP bool +config NEEDS_MANUAL_RELOC + bool + choice prompt "Architecture select" default SANDBOX @@ -26,12 +29,14 @@ config ARM config M68K bool "M68000 architecture" select HAVE_PRIVATE_LIBGCC + select NEEDS_MANUAL_RELOC select SYS_BOOT_GET_CMDLINE select SYS_BOOT_GET_KBD select SUPPORT_OF_CONTROL config MICROBLAZE bool "MicroBlaze architecture" + select NEEDS_MANUAL_RELOC select SUPPORT_OF_CONTROL imply CMD_IRQ diff --git a/arch/m68k/include/asm/config.h b/arch/m68k/include/asm/config.h index c7363c0b5113..7ea443673ad5 100644 --- a/arch/m68k/include/asm/config.h +++ b/arch/m68k/include/asm/config.h @@ -6,8 +6,6 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -#define CONFIG_NEEDS_MANUAL_RELOC - #define CONFIG_LMB #define CONFIG_SYS_BOOT_RAMDISK_HIGH diff --git a/arch/microblaze/include/asm/config.h b/arch/microblaze/include/asm/config.h index 112427291526..3ae71b3e010f 100644 --- a/arch/microblaze/include/asm/config.h +++ b/arch/microblaze/include/asm/config.h @@ -8,10 +8,6 @@ #define CONFIG_LMB -#ifndef CONFIG_SPL_BUILD -#define CONFIG_NEEDS_MANUAL_RELOC -#endif - #define CONFIG_SYS_BOOT_RAMDISK_HIGH #endif diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index a9508448d43e..0aabe7a45165 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1154,7 +1154,6 @@ CONFIG_NCEL2C100_BASE CONFIG_NCEMIC100_BASE CONFIG_NDS_DLM1_BASE CONFIG_NDS_DLM2_BASE -CONFIG_NEEDS_MANUAL_RELOC CONFIG_NEO CONFIG_NET2BIG_V2 CONFIG_NETCONSOLE_BUFFER_SIZE -- 2.29.2

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[PATCH] mmc: fsl_esdhc_imx: add wait_dat0() support
by haibo.chen＠nxp.com 04 Nov '20

04 Nov '20

From: Haibo Chen <haibo.chen(a)nxp.com> Add wait_dat0() support, upper layer will use this callback. Signed-off-by: Haibo Chen <haibo.chen(a)nxp.com> --- drivers/mmc/fsl_esdhc_imx.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 22040c67a8..dc6a6006fa 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -1646,6 +1646,28 @@ static int fsl_esdhc_set_enhanced_strobe(struct udevice *dev) } #endif +static int fsl_esdhc_wait_dat0(struct udevice *dev, int state, + int timeout_us) +{ + int ret = -ETIMEDOUT; + bool dat0_high; + bool target_dat0_high = !!state; + struct fsl_esdhc_priv *priv = dev_get_priv(dev); + struct fsl_esdhc *regs = priv->esdhc_regs; + + timeout_us = DIV_ROUND_UP(timeout_us, 10); /* check every 10 us. */ + while (timeout_us--) { + dat0_high = !!(esdhc_read32(&regs->prsstat) & PRSSTAT_DAT0); + if (dat0_high == target_dat0_high) { + ret = 0; + break; + } + udelay(10); + } + + return ret; +} + static const struct dm_mmc_ops fsl_esdhc_ops = { .get_cd = fsl_esdhc_get_cd, .send_cmd = fsl_esdhc_send_cmd, @@ -1656,6 +1678,7 @@ static const struct dm_mmc_ops fsl_esdhc_ops = { #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT) .set_enhanced_strobe = fsl_esdhc_set_enhanced_strobe, #endif + .wait_dat0 = fsl_esdhc_wait_dat0, }; #endif -- 2.17.1

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[PATCH 1/1] efi_selftest: add tool to download dtb
by Heinrich Schuchardt 04 Nov '20

04 Nov '20

For validating the fixed up device tree we need a tool to need to save it to a file. dtbdump.efi copies the configuration table with the device tree to a file on the same partition from which dtbdump.efi was invoked. The file name can be entered on the console. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- lib/efi_selftest/Makefile | 5 + lib/efi_selftest/dtbdump.c | 215 +++++++++++++++++++++++++++++++++++++ 2 files changed, 220 insertions(+) create mode 100644 lib/efi_selftest/dtbdump.c diff --git a/lib/efi_selftest/Makefile b/lib/efi_selftest/Makefile index 06d66cfdd1..aabb743ecb 100644 --- a/lib/efi_selftest/Makefile +++ b/lib/efi_selftest/Makefile @@ -8,6 +8,8 @@ asflags-y += -DHOST_ARCH="$(HOST_ARCH)" ccflags-y += -DHOST_ARCH="$(HOST_ARCH)" +CFLAGS_dtbdump_exit.o := $(CFLAGS_EFI) -Os -ffreestanding +CFLAGS_REMOVE_dtbdump.o := $(CFLAGS_NON_EFI) CFLAGS_efi_selftest_miniapp_exit.o := $(CFLAGS_EFI) -Os -ffreestanding CFLAGS_REMOVE_efi_selftest_miniapp_exit.o := $(CFLAGS_NON_EFI) CFLAGS_efi_selftest_miniapp_return.o := $(CFLAGS_EFI) -Os -ffreestanding @@ -76,6 +78,9 @@ efi_selftest_miniapp_exception.efi \ efi_selftest_miniapp_exit.efi \ efi_selftest_miniapp_return.efi +always += \ +dtbdump.efi + $(obj)/efi_miniapp_file_image_exception.h: $(obj)/efi_selftest_miniapp_exception.efi $(obj)/../../tools/file2include $(obj)/efi_selftest_miniapp_exception.efi > \ $(obj)/efi_miniapp_file_image_exception.h diff --git a/lib/efi_selftest/dtbdump.c b/lib/efi_selftest/dtbdump.c new file mode 100644 index 0000000000..d90e3eb768 --- /dev/null +++ b/lib/efi_selftest/dtbdump.c @@ -0,0 +1,215 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020, Heinrich Schuchardt <xypron.glpk(a)gmx.de> + * + * dtbdump.efi saves the device tree provided as a configuration table + * to a file. + */ + +#include <common.h> +#include <efi_api.h> + +#define BUFFER_SIZE 64 +#define ESC 0x17 +#define DEFAULT_FILENAME L"dtb.dtb" + +static struct efi_simple_text_output_protocol *cerr; +static struct efi_simple_text_output_protocol *cout; +static struct efi_simple_text_input_protocol *cin; +static struct efi_boot_services *bs; +static const efi_guid_t fdt_guid = EFI_FDT_GUID; +static const efi_guid_t loaded_image_guid = EFI_LOADED_IMAGE_PROTOCOL_GUID; +static const efi_guid_t guid_simple_file_system_protocol = + EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID; + +/** + * input() - read string from console + * + * @buffer: input buffer + * @buffer_size: buffer size + * Return: status code + */ +static efi_status_t efi_input(u16 *buffer, efi_uintn_t buffer_size) +{ + struct efi_input_key key = {0}; + efi_uintn_t index; + efi_uintn_t pos = 0; + u16 outbuf[2] = L" "; + efi_status_t ret; + + /* Drain the console input */ + ret = cin->reset(cin, true); + for (;;) { + ret = bs->wait_for_event(1, &cin->wait_for_key, &index); + if (ret != EFI_SUCCESS) + continue; + ret = cin->read_key_stroke(cin, &key); + if (ret != EFI_SUCCESS) + continue; + switch (key.scan_code) { + case 0x17: /* Escape */ + cout->output_string(cout, L"\nAborted\n"); + return EFI_ABORTED; + default: + break; + } + switch (key.unicode_char) { + case 0x08: /* Backspace */ + if (pos) { + buffer[pos--] = 0; + cout->output_string(cout, L"\b \b"); + } + break; + case 0x0a: /* Linefeed */ + case 0x0d: /* Carriage return */ + return EFI_SUCCESS; + default: + break; + } + /* Ignore surrogate codes */ + if (key.unicode_char >= 0xD800 && key.unicode_char <= 0xDBFF) + continue; + if (key.unicode_char >= 0x20 && + pos < buffer_size - 1) { + *outbuf = key.unicode_char; + buffer[pos++] = key.unicode_char; + cout->output_string(cout, outbuf); + } + } +} + +/* + * Convert FDT value to host endianness. + * + * @val FDT value + * @return converted value + */ +static u32 f2h(fdt32_t val) +{ + char *buf = (char *)&val; + char i; + + /* Swap the bytes */ + i = buf[0]; buf[0] = buf[3]; buf[3] = i; + i = buf[1]; buf[1] = buf[2]; buf[2] = i; + return *(u32 *)buf; +} + +/** + * get_dtb() - get device tree + * + * @systable: system table + * Return: device tree or NULL + */ +void *get_dtb(struct efi_system_table *systable) +{ + void *dtb = NULL; + efi_uintn_t i; + + for (i = 0; i < systable->nr_tables; ++i) { + if (!memcmp(&systable->tables[i].guid, &fdt_guid, + sizeof(efi_guid_t))) { + dtb = systable->tables[i].table; + break; + } + } + return dtb; +} + +/** + * efi_main() - entry point of the EFI application. + * + * @handle: handle of the loaded image + * @systable: system table + * @return: status code + */ +efi_status_t EFIAPI efi_main(efi_handle_t handle, + struct efi_system_table *systable) +{ + efi_uintn_t ret; + u16 filename[BUFFER_SIZE] = {0}; + efi_uintn_t dtb_size; + struct efi_loaded_image *loaded_image; + struct efi_simple_file_system_protocol *file_system; + struct efi_file_handle *root, *file; + struct fdt_header *dtb; + + cerr = systable->std_err; + cout = systable->con_out; + cin = systable->con_in; + bs = systable->boottime; + + cout->set_attribute(cout, EFI_LIGHTGRAY | EFI_BACKGROUND_BLACK); + cout->clear_screen(cout); + cout->set_attribute(cout, EFI_YELLOW | EFI_BACKGROUND_BLACK); + cout->output_string(cout, L"DTB Dump\n\n"); + cout->set_attribute(cout, EFI_LIGHTGRAY | EFI_BACKGROUND_BLACK); + + dtb = get_dtb(systable); + if (!dtb) { + cerr->output_string(cout, L"DTB not found\n"); + return EFI_NOT_FOUND; + } + if (f2h(dtb->magic) != FDT_MAGIC) { + cerr->output_string(cout, L"Wrong device tree magic\n"); + return EFI_NOT_FOUND; + } + dtb_size = f2h(dtb->totalsize); + + cout->output_string(cout, L"Filename (" DEFAULT_FILENAME ")?\n"); + ret = efi_input(filename, sizeof(filename)); + if (ret != EFI_SUCCESS) + return ret; + if (!*filename) + memcpy(filename, DEFAULT_FILENAME, sizeof(DEFAULT_FILENAME)); + + cout->output_string(cout, L"\n"); + + ret = bs->open_protocol(handle, &loaded_image_guid, + (void **)&loaded_image, NULL, NULL, + EFI_OPEN_PROTOCOL_GET_PROTOCOL); + if (ret != EFI_SUCCESS) { + cerr->output_string(cout, + L"Loaded image protocol not found\n"); + return ret; + } + + /* Open the simple file system protocol */ + ret = bs->open_protocol(loaded_image->device_handle, + &guid_simple_file_system_protocol, + (void **)&file_system, NULL, NULL, + EFI_OPEN_PROTOCOL_GET_PROTOCOL); + if (ret != EFI_SUCCESS) { + cerr->output_string( + cout, L"Failed to open simple file system protocol\n"); + return ret; + } + + /* Open volume */ + ret = file_system->open_volume(file_system, &root); + if (ret != EFI_SUCCESS) { + cerr->output_string(cerr, L"Failed to open volume\n"); + return ret; + } + /* Create file */ + ret = root->open(root, &file, filename, + EFI_FILE_MODE_READ | EFI_FILE_MODE_WRITE | + EFI_FILE_MODE_CREATE, EFI_FILE_ARCHIVE); + if (ret == EFI_SUCCESS) { + /* Write file */ + ret = file->write(file, &dtb_size, dtb); + if (ret != EFI_SUCCESS) + cerr->output_string(cerr, L"Failed to write file\n"); + file->close(file); + } else { + cerr->output_string(cerr, L"Failed to open file\n"); + } + root->close(root); + + if (ret == EFI_SUCCESS) { + cout->output_string(cout, filename); + cout->output_string(cout, L" written\n"); + } + + return ret; +} -- 2.28.0

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stm32mp: The purpose of "!tee_find_device()"
by Alex G. 04 Nov '20

04 Nov '20

Hi I'm trying to wrap my head around the purpose of the following lines in ft_system_setup(): if (!CONFIG_IS_ENABLED(OPTEE) || !tee_find_device(NULL, NULL, NULL, NULL)) stm32_fdt_disable_optee(blob); My interpretation is "if optee is not running, delete the FDT node". The problem is that tee_find_device() invokes device_probe(). This in turn does an SMC call. This call results in an abort and reboot if optee is not running in the first place. So I don't think that tee_find_device() can be used as a check for "Is optee running?". Exhibit B: Outside of mach-stm32mp, tee_find_device() is used to obtain of a _working_ TEE node, not to ask if "is optee running?". My problem is that trying to start linux with CONFIG_OPTEE=y will cause the bootm command to crash (log in appendix A): load mmc 0:7 $loadaddr boot/uImage load mmc 0:7 $fdt_addr_r boot/stm32mp157c-dk2.dtb load mmc 0:7 0xc8000000 boot/utee setenv bootm_boot_mode sec bootm 0xc8000000 - $fdt_addr_r What is the intent of calling tee_find_device() in an FDT fixup function? Do you have any ideas how to make it not crash (short of commenting out the problem lines) ? Alex Appendix A: u-boot log after bootm command ## Booting kernel from Legacy Image at c8000000 ... Image Name: Created: 2020-09-28 20:58:56 UTC Image Type: ARM Trusted Execution Environment Kernel Image (uncompressed) Data Size: 349276 Bytes = 341.1 KiB Load Address: fdffffe4 Entry Point: fe000000 Verifying Checksum ... OK Loading Kernel Image ## Flattened Device Tree blob at c4000000 Booting using the fdt blob at 0xc4000000 Loading Device Tree to cffef000, end cffff5e2 ... OK <BOARD RESETS WITHOUT USER INPUT> U-Boot SPL 2020.10-rc4 (Sep 20 2020 - 23:46:47 +0000) Model: STMicroelectronics STM32MP157C-DK2 Discovery Board

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[PATCH v4 00/13] x86: Updates to SMBIOS
by Simon Glass 04 Nov '20

04 Nov '20

At present there are a few Kconfig options which allow SMBIOS fields to be specified at build time. Not all fields are supported. Also, defining these at build-time is limiting since a factory system cannot insert values for particular boards or models without rebuilding U-Boot. This series adds a way to set SMBIOS properties using the devicetree. With this approach, more fields are supported and it is easy to update values in the devicetree in the factory. It also updates existing boards to use devicetree and drops the CONFIG options, using a new default sysinfo driver. Changes in v4: - Fix build error with vexpress_ca9x4 Changes in v3: - Use a different binding with subnodes for each table type - Add onto the sysinfo binding Changes in v2: - Move dm.h header file to avoid build error on qemu-arm - Deal with boards that don't use of-control Simon Glass (13): board: Rename uclass to sysinfo doc: Add a binding for sysinfo x86: Pass an ofnode into each SMBIOS function smbios: Allow properties to come from the device tree smbios: Add more properties smbios: Add documentation and devicetree binding sysinfo: Provide a default driver to set SMBIOS values rockchip: Use devicetree for SMBIOS settings imx: Use devicetree for SMBIOS settings on MYiR MYS-6ULX odroid-c2: Use devicetree for SMBIOS settings arm64: mvebu: Use devicetree for SMBIOS settings on uDPU x86: galileo: Use devicetree for SMBIOS settings smbios: Drop the unused Kconfig options arch/arm/dts/armada-3720-uDPU-u-boot.dtsi | 20 +++ .../dts/imx6ull-myir-mys-6ulx-eval-u-boot.dts | 25 ++++ arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi | 23 +++ arch/arm/dts/rk3328-roc-cc-u-boot.dtsi | 21 +++ arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi | 23 +++ arch/arm/dts/rk3328-rock64-u-boot.dtsi | 21 +++ arch/arm/dts/rk3368-lion-u-boot.dtsi | 20 +++ arch/powerpc/dts/gdsys/gazerbeam-uboot.dtsi | 2 +- arch/sandbox/dts/test.dts | 8 +- arch/x86/dts/galileo.dts | 18 +++ board/gdsys/common/cmd_ioloop.c | 12 +- board/gdsys/mpc8308/gazerbeam.c | 47 ++++--- board/google/chromebook_coral/coral.c | 2 +- board/intel/galileo/Kconfig | 11 -- common/spl/spl_fit.c | 15 +- configs/chromebook_coral_defconfig | 2 +- configs/clearfog_gt_8k_defconfig | 2 - configs/gazerbeam_defconfig | 4 +- configs/lion-rk3368_defconfig | 4 +- configs/mt7622_rfb_defconfig | 1 - configs/mvebu_db_armada8k_defconfig | 2 - configs/myir_mys_6ulx_defconfig | 3 +- configs/odroid-c2_defconfig | 4 +- configs/r8a774a1_beacon_defconfig | 2 - configs/r8a77970_eagle_defconfig | 2 - configs/r8a77980_condor_defconfig | 2 - configs/r8a77990_ebisu_defconfig | 2 - configs/r8a77995_draak_defconfig | 2 - configs/rcar3_salvator-x_defconfig | 2 - configs/rcar3_ulcb_defconfig | 2 - configs/roc-cc-rk3328_defconfig | 4 +- configs/rock-pi-e-rk3328_defconfig | 4 +- configs/rock64-rk3328_defconfig | 4 +- configs/sandbox64_defconfig | 8 +- configs/sandbox_defconfig | 8 +- configs/sandbox_flattree_defconfig | 4 +- configs/sandbox_spl_defconfig | 4 +- configs/uDPU_defconfig | 3 +- doc/arch/x86.rst | 8 ++ .../gdsys,sysinfo_gazerbeam.txt} | 8 +- doc/device-tree-bindings/sysinfo/smbios.txt | 77 ++++++++++ doc/device-tree-bindings/sysinfo/sysinfo.txt | 18 +++ drivers/Kconfig | 4 +- drivers/Makefile | 2 +- drivers/board/Kconfig | 25 ---- drivers/board/Makefile | 7 - drivers/board/board-uclass.c | 71 ---------- drivers/sysinfo/Kconfig | 33 +++++ drivers/sysinfo/Makefile | 8 ++ drivers/{board => sysinfo}/gazerbeam.c | 74 +++++----- drivers/{board => sysinfo}/gazerbeam.h | 0 drivers/{board => sysinfo}/sandbox.c | 50 +++---- drivers/{board => sysinfo}/sandbox.h | 0 drivers/sysinfo/smbios.c | 24 ++++ drivers/sysinfo/sysinfo-uclass.c | 71 ++++++++++ drivers/timer/mpc83xx_timer.c | 10 +- include/dm/uclass-id.h | 2 +- include/smbios.h | 5 +- include/{board.h => sysinfo.h} | 80 +++++------ lib/Kconfig | 17 +-- lib/smbios.c | 133 +++++++++++++----- test/dm/Makefile | 2 +- test/dm/board.c | 59 -------- test/dm/sysinfo.c | 59 ++++++++ 64 files changed, 767 insertions(+), 423 deletions(-) create mode 100644 arch/arm/dts/imx6ull-myir-mys-6ulx-eval-u-boot.dts rename doc/device-tree-bindings/{board/gdsys,board_gazerbeam.txt => sysinfo/gdsys,sysinfo_gazerbeam.txt} (90%) create mode 100644 doc/device-tree-bindings/sysinfo/smbios.txt create mode 100644 doc/device-tree-bindings/sysinfo/sysinfo.txt delete mode 100644 drivers/board/Kconfig delete mode 100644 drivers/board/Makefile delete mode 100644 drivers/board/board-uclass.c create mode 100644 drivers/sysinfo/Kconfig create mode 100644 drivers/sysinfo/Makefile rename drivers/{board => sysinfo}/gazerbeam.c (69%) rename drivers/{board => sysinfo}/gazerbeam.h (100%) rename drivers/{board => sysinfo}/sandbox.c (50%) rename drivers/{board => sysinfo}/sandbox.h (100%) create mode 100644 drivers/sysinfo/smbios.c create mode 100644 drivers/sysinfo/sysinfo-uclass.c rename include/{board.h => sysinfo.h} (65%) delete mode 100644 test/dm/board.c create mode 100644 test/dm/sysinfo.c -- 2.29.0.rc1.297.gfa9743e501-goog

2 29

[PATCH v2 00/30] x86: Allow Coral to boot into Chrome OS
by Simon Glass 04 Nov '20

04 Nov '20

This series adds various minor features and tweaks to allow Coral to boot into Chrome OS from U-Boot. It relies on three other series which have been recently sent: - smbios (u-boot-dm/smbios-working) - bootm (u-boot-dm/bootm-working) - misca (u-boot-dm/misca-working) This should provide a solid base for using ACPI on other Intel Apollo Lake (APL) devices. Changes in v2: - Rename update_fixed_mtrss() to update_fixed_mtrrs() - Add comments to enable_pm_timer_emulation() and cpu_mca_configure() - Convert tabs to spaces for consistency - Use log_err() to report error - Rename struct chromeos_acpi to struct chromeos_acpi_gnvs - Fix comment style - Define CONFIG_CHROMEOS_VBOOT in the Kconfig too - Correct a bisect build error - Drop patch "Store the FADT so we can avoid searching for it" - Drop patch "Move ROM_TABLE_ADDR into the C file" Simon Glass (30): Add an assembly guard around linux/bitops.h x86: apl: Add core init for the SoC x86: Add a layout for Chrome OS verified boot x86: Add support for private files x86: Allow writing tables to fail x86: acpi: Store the ACPI context in global_data x86: Don't bother clearing global NVS x86: coral: Drop the duplicate PCIe settings x86: Add SMBIOS info for Coral x86: coral: Correct max98357 file x86: Use if instead of #ifdef in write_tables() x86: Allow putting some tables in the bloblist x86: nhlt: Correct output of bytes and 16-bit data x86: nhlt: Fix a few bugs in the table generation x86: Show the interrupt pointer with 'irqinfo' x86: sound: Correct error handling acpi: Correct reset handling in acpi_device_add_power_res() x86: acpi: Allow the SSDT to be empty x86: acpi: Put the generated code first in DSDT acpi: Don't reset the tables with every new generation x86: Define the Chrome OS GNVS region x86: Use CONFIG_CHROMEOS_VBOOT for verified boot x86: Set up Chrome OS to boot into developer mode x86: Boot coral into Chrome OS by default x86: fsp: Convert fsp_dram to use log_debug() x86: Silence some logging statements x86: acpi: Include the TPMv1 table only if needed x86: acpi: Don't show the UART address by default x86: pinctrl: Silence the warning when a pin is not found x86: fsp: Adjust calculations for MTRR range and DRAM top Kconfig | 17 ++++ arch/x86/cpu/apollolake/acpi.c | 25 ++++-- arch/x86/cpu/apollolake/cpu.c | 84 +++++++++++++++++ arch/x86/cpu/apollolake/cpu_common.c | 25 ++++++ arch/x86/cpu/apollolake/cpu_spl.c | 20 ----- arch/x86/cpu/apollolake/fsp_s.c | 8 +- arch/x86/cpu/cpu.c | 9 +- arch/x86/cpu/i386/interrupt.c | 14 +-- arch/x86/cpu/intel_common/acpi.c | 1 - arch/x86/cpu/intel_common/cpu.c | 19 ++++ arch/x86/cpu/intel_common/intel_opregion.c | 2 +- arch/x86/cpu/intel_common/itss.c | 8 +- arch/x86/dts/chromebook_coral.dts | 12 ++- arch/x86/dts/chromebook_samus.dts | 2 +- arch/x86/dts/u-boot.dtsi | 4 + arch/x86/include/asm/acpi/vbnv_layout.h | 38 ++++++++ arch/x86/include/asm/arch-apollolake/cpu.h | 14 +++ arch/x86/include/asm/cpu_common.h | 9 ++ arch/x86/include/asm/intel_gnvs.h | 54 ++++++++++- arch/x86/include/asm/interrupt.h | 17 ++++ arch/x86/include/asm/msr-index.h | 20 ++++- arch/x86/include/asm/tables.h | 4 +- arch/x86/lib/acpi_nhlt.c | 19 ++-- arch/x86/lib/acpi_table.c | 78 ++++++++++------ arch/x86/lib/fsp/fsp_dram.c | 35 +++++--- arch/x86/lib/fsp/fsp_graphics.c | 2 +- arch/x86/lib/fsp2/fsp_dram.c | 8 +- arch/x86/lib/interrupts.c | 3 + arch/x86/lib/tables.c | 85 +++++++++++++----- arch/x86/lib/tpl.c | 2 +- .../max98357-render-2ch-48khz-24b.dat | Bin 0 -> 116 bytes configs/chromebook_coral_defconfig | 13 ++- drivers/core/acpi.c | 10 ++- drivers/pinctrl/intel/pinctrl.c | 2 +- drivers/sound/da7219.c | 4 +- drivers/sound/max98357a.c | 2 +- include/acpi/acpi_table.h | 10 +++ include/asm-generic/global_data.h | 5 ++ include/configs/chromebook_coral.h | 9 +- include/dm/acpi.h | 9 ++ include/linux/bitops.h | 4 +- lib/Kconfig | 9 ++ lib/acpi/acpi_device.c | 2 +- lib/acpi/acpi_table.c | 4 +- test/dm/acpi.c | 4 + 45 files changed, 585 insertions(+), 140 deletions(-) create mode 100644 arch/x86/include/asm/acpi/vbnv_layout.h -- 2.29.0.rc1.297.gfa9743e501-goog

2 38

[PATCH v3 0/2] imx: support for conga-QMX8 board
by Oliver Graute 04 Nov '20

04 Nov '20

Second patch is still needed for booting. Tipps to get rid of that patch would be helpfull. Between u-boot-imx-20200511 and u-boot-imx-20200609 something more is broken, I run into this issue: U-Boot 2020.07-rc3-00002-gbf3f929aa6 (Jun 16 2020 - 14:36:58 +0200) CPU: NXP i.MX8QM RevB A53 at 1200 MHz Model: Congatec QMX8 Qseven series Board: conga-QMX8 Build: SCFW 494c97f3, SECO-FW d7523fe8, ATF 09c5cc9 Boot: SD2 DRAM: 6 GiB Device 'gpio@5d090000': seq 0 is in use by 'gpio@5d080000' Device 'gpio@5d0a0000': seq 1 is in use by 'gpio@5d090000' MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial@5a060000 Out: serial@5a060000 Err: serial@5a060000 "Synchronous Abort" handler, esr 0x96000004 elr: 000000008005cf48 lr : 0000000080022f94 (reloc) elr: 00000000fff22f48 lr : 00000000ffee8f94 x0 : fffffffffdaf3540 x1 : 00000000fff2d8a0 x2 : 0000000000000000 x3 : 0000000000000000 x4 : 0000000000000000 x5 : fffffffffdaf3540 x6 : 00000000fff068a8 x7 : 00000000fff3bca0 x8 : 00000000fdaf3ac0 x9 : 0000000000000008 x10: 00000000fdaecb30 x11: 00000000fdaefdd0 x12: 0000000000000000 x13: 0000000000000200 x14: 00000000fdadebf8 x15: 00000000ffffffff x16: 0000000000001080 x17: 0000000000000000 x18: 00000000fdae4da0 x19: 0000000000000002 x20: 00000000fff3b000 x21: 000000007fec6000 x22: 0000000000000000 x23: 0000000000000000 x24: 0000000000000000 x25: 0000000000000000 x26: 0000000000000000 x27: 0000000000000000 x28: 0000000000000000 x29: 00000000fdadfd90 Code: aa0503e4 17fffff2 aa0003e5 d2800003 (386368a4) Resetting CPU ... resetting ... Oliver Graute (2): imx: support for conga-QMX8 board hack to boot with 2020.01 arch/arm/dts/Makefile | 1 + arch/arm/dts/imx8qm-cgtqmx8.dts | 427 +++++++++++++++++++++++++ arch/arm/mach-imx/imx8/Kconfig | 7 + board/congatec/cgtqmx8/Kconfig | 14 + board/congatec/cgtqmx8/MAINTAINERS | 6 + board/congatec/cgtqmx8/Makefile | 11 + board/congatec/cgtqmx8/README | 46 +++ board/congatec/cgtqmx8/cgtqmx8.c | 479 ++++++++++++++++++++++++++++ board/congatec/cgtqmx8/imximage.cfg | 21 ++ board/congatec/cgtqmx8/spl.c | 76 +++++ board/congatec/common/Kconfig | 48 +++ board/congatec/common/Makefile | 23 ++ board/congatec/common/mmc.c | 50 +++ configs/cgtqmx8_defconfig | 82 +++++ drivers/core/device.c | 7 +- include/configs/cgtqmx8.h | 194 +++++++++++ 16 files changed, 1487 insertions(+), 5 deletions(-) create mode 100644 arch/arm/dts/imx8qm-cgtqmx8.dts create mode 100644 board/congatec/cgtqmx8/Kconfig create mode 100644 board/congatec/cgtqmx8/MAINTAINERS create mode 100644 board/congatec/cgtqmx8/Makefile create mode 100644 board/congatec/cgtqmx8/README create mode 100644 board/congatec/cgtqmx8/cgtqmx8.c create mode 100644 board/congatec/cgtqmx8/imximage.cfg create mode 100644 board/congatec/cgtqmx8/spl.c create mode 100644 board/congatec/common/Kconfig create mode 100644 board/congatec/common/Makefile create mode 100644 board/congatec/common/mmc.c create mode 100644 configs/cgtqmx8_defconfig create mode 100644 include/configs/cgtqmx8.h -- 2.17.1

4 5

[PATCH v1] imx: support i.MX8QM DMSSE20 a1 board
by Oliver Graute 04 Nov '20

04 Nov '20

Add i.MX8QM DMSSE20 a1 board support U-Boot 2020.10-rc3-00177-g316f823505 (Aug 31 2020 - 16:08:37 +0200) Model: Advantech iMX8QM DMSSE20 Board: DMS-SE20A1 8GB Build: SCFW 494c97f3, SECO-FW d7523fe8, ATF 09c5cc9 Boot: USB DRAM: 8 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... Card did not respond to voltage select! *** Warning - No block device, using default environment In: serial@5a060000 Out: serial@5a060000 Err: serial@5a060000 Net: Warning: ethernet@5b040000 (eth0) using random MAC address - 0e:db:c9:1a:a4:a7 eth0: ethernet@5b040000 [PRIME] Warning: ethernet@5b050000 (eth1) using random MAC address - d2:38:f7:68:ce:91 , eth1: ethernet@5b050000 Hit any key to stop autoboot: 0 Signed-off-by: Oliver Graute <oliver.graute(a)kococonnector.com> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Ye Li <ye.li(a)nxp.com> Cc: uboot-imx <uboot-imx(a)nxp.com> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/imx8qm-dmsse20-a1.dts | 345 ++++++++++++++++++ arch/arm/mach-imx/imx8/Kconfig | 7 + board/advantech/imx8qm_dmsse20_a1/Kconfig | 14 + board/advantech/imx8qm_dmsse20_a1/MAINTAINERS | 6 + board/advantech/imx8qm_dmsse20_a1/Makefile | 8 + board/advantech/imx8qm_dmsse20_a1/README | 61 ++++ .../imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c | 188 ++++++++++ .../advantech/imx8qm_dmsse20_a1/imximage.cfg | 21 ++ board/advantech/imx8qm_dmsse20_a1/spl.c | 217 +++++++++++ common/Kconfig | 2 +- configs/imx8qm_dmsse20a1_defconfig | 86 +++++ include/configs/imx8qm_dmsse20.h | 219 +++++++++++ 13 files changed, 1174 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx8qm-dmsse20-a1.dts create mode 100644 board/advantech/imx8qm_dmsse20_a1/Kconfig create mode 100644 board/advantech/imx8qm_dmsse20_a1/MAINTAINERS create mode 100644 board/advantech/imx8qm_dmsse20_a1/Makefile create mode 100644 board/advantech/imx8qm_dmsse20_a1/README create mode 100644 board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c create mode 100644 board/advantech/imx8qm_dmsse20_a1/imximage.cfg create mode 100644 board/advantech/imx8qm_dmsse20_a1/spl.c create mode 100644 configs/imx8qm_dmsse20a1_defconfig create mode 100644 include/configs/imx8qm_dmsse20.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index f8f529435b..986d1969da 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -752,6 +752,7 @@ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \ dtb-$(CONFIG_ARCH_IMX8) += \ fsl-imx8qm-apalis.dtb \ fsl-imx8qm-mek.dtb \ + imx8qm-dmsse20-a1.dtb \ imx8qm-rom7720-a1.dtb \ fsl-imx8qxp-ai_ml.dtb \ fsl-imx8qxp-colibri.dtb \ diff --git a/arch/arm/dts/imx8qm-dmsse20-a1.dts b/arch/arm/dts/imx8qm-dmsse20-a1.dts new file mode 100644 index 0000000000..6f4f795e99 --- /dev/null +++ b/arch/arm/dts/imx8qm-dmsse20-a1.dts @@ -0,0 +1,345 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017 NXP + */ + +/dts-v1/; + +/* First 128KB is for PSCI ATF. */ +/memreserve/ 0x80000000 0x00020000; + +#include "fsl-imx8qm.dtsi" + +/ { + model = "Advantech iMX8QM DMSSE20"; + compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; + + aliases { + mmc0 = &usdhc1; + mmc2 = &usdhc3; + }; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + stdout-path = &lpuart0; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "sw-3p3-sd1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + busfreq { + status = "disabled"; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx8qm-mek { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000048 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 + SC_P_ENET1_MDC_CONN_ENET1_MDC 0x06000020 + SC_P_ENET1_MDIO_CONN_ENET1_MDIO 0x06000020 + SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 + SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 + SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 + SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 + SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 + SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 + SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 + SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 + SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 + SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 + SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 + SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_DMA_UART0_RX 0x06000020 + SC_P_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000020 + SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO08 0x00000020 + >; + }; + + pinctrl_usdhc3_gpio: usdhc3grpgpio { + fsl,pins = < + SC_P_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021 + SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020 + >; + }; + }; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <&reg_usdhc2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default","state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>; + bus-width = <4>; + cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; + no-1-8-v; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <&ethphy0>; + fsl,ar8031-phy-fixup; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-id"; + phy-handle = <&ethphy1>; + fsl,ar8031-phy-fixup; + fsl,magic-packet; + status = "okay"; + fsl,mii-exclusive; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + }; + }; +}; + +&lpuart0 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 9d1f73dfc7..ee6781c6f7 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -86,6 +86,12 @@ config TARGET_IMX8QM_ROM7720_A1 select SUPPORT_SPL select IMX8QM +config TARGET_IMX8QM_DMSSE20_A1 + bool "Support i.MX8QM DMS-SE20-A1 board" + select BOARD_LATE_INIT + select SUPPORT_SPL + select IMX8QM + config TARGET_IMX8QXP_MEK bool "Support i.MX8QXP MEK board" select BOARD_LATE_INIT @@ -95,6 +101,7 @@ endchoice source "board/freescale/imx8qm_mek/Kconfig" source "board/freescale/imx8qxp_mek/Kconfig" +source "board/advantech/imx8qm_dmsse20_a1/Kconfig" source "board/advantech/imx8qm_rom7720_a1/Kconfig" source "board/toradex/apalis-imx8/Kconfig" source "board/toradex/colibri-imx8x/Kconfig" diff --git a/board/advantech/imx8qm_dmsse20_a1/Kconfig b/board/advantech/imx8qm_dmsse20_a1/Kconfig new file mode 100644 index 0000000000..1d5e68a96f --- /dev/null +++ b/board/advantech/imx8qm_dmsse20_a1/Kconfig @@ -0,0 +1,14 @@ +if TARGET_IMX8QM_DMSSE20_A1 + +config SYS_BOARD + default "imx8qm_dmsse20_a1" + +config SYS_VENDOR + default "advantech" + +config SYS_CONFIG_NAME + default "imx8qm_dmsse20" + +source "board/freescale/common/Kconfig" + +endif diff --git a/board/advantech/imx8qm_dmsse20_a1/MAINTAINERS b/board/advantech/imx8qm_dmsse20_a1/MAINTAINERS new file mode 100644 index 0000000000..c1e8048bbb --- /dev/null +++ b/board/advantech/imx8qm_dmsse20_a1/MAINTAINERS @@ -0,0 +1,6 @@ +i.MX8QM ROM DMSSE20 a1 BOARD +M: Oliver Graute <oliver.graute(a)kococonnector.com> +S: Maintained +F: board/advantech/imx8qm_dmsse20_a1/ +F: include/configs/imx8qm_dmsse20.h +F: configs/imx8qm_dmsse20a1_defconfig diff --git a/board/advantech/imx8qm_dmsse20_a1/Makefile b/board/advantech/imx8qm_dmsse20_a1/Makefile new file mode 100644 index 0000000000..262ffcd683 --- /dev/null +++ b/board/advantech/imx8qm_dmsse20_a1/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2017 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8qm_dmsse20_a1.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/advantech/imx8qm_dmsse20_a1/README b/board/advantech/imx8qm_dmsse20_a1/README new file mode 100644 index 0000000000..2105e9c425 --- /dev/null +++ b/board/advantech/imx8qm_dmsse20_a1/README @@ -0,0 +1,61 @@ +U-Boot for the NXP i.MX8QM DMSSE20-a1 board + +Quick Start +=========== + +- Build the ARM Trusted firmware binary +- Get scfw_tcm.bin and ahab-container.img +- Get imx-mkimage +- Build U-Boot +- Build imx-mkimage +- Flash the binary into the SD card +- Boot + +Get and Build the ARM Trusted firmware +====================================== + +$ git clone https://source.codeaurora.org/external/imx/imx-atf +$ cd imx-atf/ +$ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga +$ make PLAT=imx8qm bl31 + +Get scfw_tcm.bin and ahab-container.img +============================== + +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.1.bin +$ chmod +x imx-sc-firmware-1.1.bin +$ ./imx-sc-firmware-1.1.bin +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin +$ chmod +x firmware-imx-8.0.bin +$ ./firmware-imx-8.0.bin + +Or use this to avoid running random scripts from the internet, +but note that you must agree to the license the script displays: + +$ dd if=imx-sc-firmware-1.1.bin of=imx-sc-firmware-1.1.tar.bz2 bs=37185 skip=1 +$ tar -xf imx-sc-firmware-1.1.tar.bz2 +$ cp imx-sc-firmware-1.1/mx8qm-val-scfw-tcm.bin $(builddir) + +$ dd if=firmware-imx-8.0.bin of=firmware-imx-8.0.tar.bz2 bs=37180 skip=1 +$ tar -xf firmware-imx-8.0.tar.bz2 +$ cp firmware-imx-8.0/firmware/seco/mx8qm-ahab-container.img $(builddir) + +Build U-Boot +============ + +$ export ATF_LOAD_ADDR=0x80000000 +$ export BL33_LOAD_ADDR=0x80020000 +$ make imx8qm_dmsse20a1_defconfig +$ make u-boot.bin +$ make flash.bin + +Flash the binary into the SD card +================================= + +Burn the flash.bin binary to SD card offset 32KB: + +$ sudo dd if=flash.bin of=/dev/sd[x] bs=1k seek=32 conv=fsync + +Boot +==== +Set Boot switch SW1: 011100. diff --git a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c new file mode 100644 index 0000000000..b93d2046f5 --- /dev/null +++ b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2018 NXP + * Copyright (C) 2020 Oliver Graute <oliver.graute(a)kococonnector.com> + */ + +#include <common.h> +#include <errno.h> +#include <linux/libfdt.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/clock.h> +#include <asm/arch/sci/sci.h> +#include <asm/arch/imx8-pins.h> +#include <asm/arch/iomux.h> +#include <asm/arch/sys_proto.h> +/* #include <power-domain.h> */ + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +static iomux_cfg_t uart0_pads[] = { + SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads)); +} + +int board_early_init_f(void) +{ + sc_pm_clock_rate_t rate = SC_80MHZ; + int ret; + + /* Set UART0 clock root to 80 MHz */ + ret = sc_pm_setup_uart(SC_R_UART_0, rate); + if (ret) + return ret; + + setup_iomux_uart(); + + /* This is needed to because Kernel do not Power Up DC_0 */ + sc_pm_set_resource_power_mode(-1, SC_R_DC_0, SC_PM_PW_MODE_ON); + sc_pm_set_resource_power_mode(-1, SC_R_GPIO_5, SC_PM_PW_MODE_ON); + + return 0; +} + +#if IS_ENABLED(CONFIG_FEC_MXC) +#include <miiphy.h> + +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +#ifdef CONFIG_MXC_GPIO + +#define LVDS_ENABLE IMX_GPIO_NR(1, 6) +#define MIPI_ENABLE IMX_GPIO_NR(1, 7) + +#define BB_GPIO_3V3_1 IMX_GPIO_NR(4, 20) +#define BB_GPIO_3V3_2 IMX_GPIO_NR(4, 24) +#define BB_GPIO_3V3_3 IMX_GPIO_NR(4, 23) + +static void board_gpio_init(void) +{ + /* Enable BB 3V3 */ + gpio_request(BB_GPIO_3V3_1, "bb_3v3_1"); + gpio_direction_output(BB_GPIO_3V3_1, 1); + gpio_request(BB_GPIO_3V3_2, "bb_3v3_2"); + gpio_direction_output(BB_GPIO_3V3_2, 1); + gpio_request(BB_GPIO_3V3_3, "bb_3v3_3"); + gpio_direction_output(BB_GPIO_3V3_3, 1); + + /* enable LVDS SAS boards */ + gpio_request(LVDS_ENABLE, "lvds_enable"); + gpio_direction_output(LVDS_ENABLE, 1); + + /* enable MIPI SAS boards */ + gpio_request(MIPI_ENABLE, "mipi_enable"); + gpio_direction_output(MIPI_ENABLE, 1); +} +#endif + +int checkboard(void) +{ + puts("Board: DMS-SE20A1 8GB\n"); + build_info(); + print_bootinfo(); + + return 0; +} + +int board_init(void) +{ + if (IS_ENABLED(CONFIG_XEN)) + return 0; + +#ifdef CONFIG_MXC_GPIO + board_gpio_init(); +#endif + + return 0; +} + +void board_quiesce_devices(void) +{ + if (IS_ENABLED(CONFIG_XEN)) { + /* Clear magic number to let xen know uboot is over */ + writel(0x0, (void __iomem *)0x80000000); + return; + } +} + +void detail_board_ddr_info(void) +{ + puts("\nDDR "); +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ + puts("SCI reboot request"); + + while (1) + putc('.'); +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return 0; +} +#endif + +int board_mmc_get_env_dev(int devno) +{ + /* Use EMMC */ + if (IS_ENABLED(CONFIG_XEN)) + return 0; + + return devno; +} + +int mmc_map_to_kernel_blk(int dev_no) +{ + /* Use EMMC */ + if (IS_ENABLED(CONFIG_XEN)) + return 0; + + return dev_no; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "DMS-SE20A1"); + env_set("board_rev", "iMX8QM"); +#endif + + env_set("sec_boot", "no"); +#ifdef CONFIG_AHAB_BOOT + env_set("sec_boot", "yes"); +#endif + + return 0; +} diff --git a/board/advantech/imx8qm_dmsse20_a1/imximage.cfg b/board/advantech/imx8qm_dmsse20_a1/imximage.cfg new file mode 100644 index 0000000000..e324c7ca37 --- /dev/null +++ b/board/advantech/imx8qm_dmsse20_a1/imximage.cfg @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#define __ASSEMBLY__ + +/* Boot from SD, sector size 0x400 */ +BOOT_FROM SD 0x400 +/* SoC type IMX8QM */ +SOC_TYPE IMX8QM +/* Append seco container image */ +APPEND mx8qm-ahab-container.img +/* Create the 2nd container */ +CONTAINER +/* Add scfw image with exec attribute */ +IMAGE SCU mx8qm-val-scfw-tcm.bin +/* Add ATF image with exec attribute */ +IMAGE A35 bl31.bin 0x80000000 +/* Add U-Boot image with load attribute */ +DATA A35 u-boot-dtb.bin 0x80020000 diff --git a/board/advantech/imx8qm_dmsse20_a1/spl.c b/board/advantech/imx8qm_dmsse20_a1/spl.c new file mode 100644 index 0000000000..8eb3d53c91 --- /dev/null +++ b/board/advantech/imx8qm_dmsse20_a1/spl.c @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2018 NXP + */ +#include <common.h> +#include <dm.h> +#include <spl.h> +#include <fsl_esdhc.h> + +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/clock.h> +#include <asm/arch/sci/sci.h> +#include <asm/arch/imx8-pins.h> +#include <asm/arch/iomux.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define ESDHC_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ESDHC_CLK_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define FSPI_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define I2C_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) +#ifdef CONFIG_FSL_ESDHC_IMX + +#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 22) +#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 12) + +static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { + {USDHC1_BASE_ADDR, 0, 8}, + {USDHC3_BASE_ADDR, 0, 4}, +}; + +static iomux_cfg_t emmc0[] = { + SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), + SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL), +}; + +static iomux_cfg_t usdhc2_sd[] = { + SC_P_USDHC2_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), + SC_P_USDHC2_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_WP | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL), +}; + +int board_mmc_init(struct bd_info *bis) +{ + int i, ret; + + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + * mmc2 USDHC3 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + return ret; + + imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0)); + init_clk_usdhc(0); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_2, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + return ret; + ret = sc_pm_set_resource_power_mode(-1, SC_R_GPIO_4, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + return ret; + + imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd)); + init_clk_usdhc(2); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + gpio_request(USDHC2_CD_GPIO, "sd2_cd"); + gpio_direction_input(USDHC2_CD_GPIO); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return 0; + } + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = 1; + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + } + + return ret; +} + +#endif /* CONFIG_FSL_ESDHC_IMX */ + +void spl_board_init(void) +{ +#if defined(CONFIG_SPL_SPI_SUPPORT) + if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) { + if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_ON)) + puts("Warning: failed to initialize FSPI0\n"); + } +#endif + + puts("Normal Boot\n"); +} + +void spl_board_prepare_for_boot(void) +{ +#if defined(CONFIG_SPL_SPI_SUPPORT) + if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) { + if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_OFF)) + puts("Warning: failed to turn off FSPI0\n"); + } +#endif +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + arch_cpu_init(); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); +} diff --git a/common/Kconfig b/common/Kconfig index c58f08ba91..538dda1c10 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -896,7 +896,7 @@ config BOARD_LATE_INIT config DISPLAY_CPUINFO bool "Display information about the CPU during start up" - default y if ARC|| ARM || NIOS2 || X86 || XTENSA || M68K + default y if ARC || ARM || NIOS2 || X86 || XTENSA || M68K help Display information about the CPU that U-Boot is running on when U-Boot starts up. The function print_cpuinfo() is called diff --git a/configs/imx8qm_dmsse20a1_defconfig b/configs/imx8qm_dmsse20a1_defconfig new file mode 100644 index 0000000000..242b817733 --- /dev/null +++ b/configs/imx8qm_dmsse20a1_defconfig @@ -0,0 +1,86 @@ +CONFIG_ARM=y +CONFIG_SPL_SYS_ICACHE_OFF=y +CONFIG_SPL_SYS_DCACHE_OFF=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_TARGET_IMX8QM_DMSSE20_A1=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_ENV_OFFSET=0x400000 +CONFIG_SPL=y +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/advantech/imx8qm_dmsse20_a1/imximage.cfg" +CONFIG_OF_CONTROL=y +CONFIG_CI_UDC=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_IMX_BOOTAUX=y +CONFIG_FS_FAT=y +CONFIG_FS_EXT4=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_MMC_BROKEN_CD=y +CONFIG_CMD_SF=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_EXT4=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx8qm-dmsse20-a1" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +# CONFIG_EFI_LOADER is not set +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_MISC=y +CONFIG_SMC_FUSE=y +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 +# CONFIG_DISPLAY_CPUINFO is not set diff --git a/include/configs/imx8qm_dmsse20.h b/include/configs/imx8qm_dmsse20.h new file mode 100644 index 0000000000..e1e0bc6e38 --- /dev/null +++ b/include/configs/imx8qm_dmsse20.h @@ -0,0 +1,219 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2019 NXP + */ + +#ifndef __IMX8QM_DMSSE20_H +#define __IMX8QM_DMSSE20_H + +#include <linux/sizes.h> +#include <asm/arch/imx-regs.h> +#define CONFIG_REMAKE_ELF + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_MAX_SIZE (124 * 1024) +#define CONFIG_SPL_BSS_START_ADDR 0x00128000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ +#endif + +#define CONFIG_NR_DRAM_BANKS 4 + +/* #define CONFIG_ARCH_MISC_INIT */ + +/* #define CONFIG_CMD_READ */ + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_BOARD_SETUP + +/* #undef CONFIG_CMD_EXPORTENV */ +/* #undef CONFIG_CMD_IMPORTENV */ +/* #undef CONFIG_CMD_IMLS */ + +/* #undef CONFIG_CMD_CRC32 */ +#undef CONFIG_BOOTM_NETBSD + +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5B010000 +#define USDHC2_BASE_ADDR 0x5B020000 +#define USDHC3_BASE_ADDR 0x5B030000 + +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +/* FUSE command */ +#define CONFIG_CMD_FUSE + +#define CONFIG_FEC_XCV_TYPE RGMII +#define FEC_QUIRK_ENET_MAC + +#define CONFIG_PHY_GIGE /* Support for 1000BASE-X */ + +/* ENET0 connects AR8031 on CPU board */ +#define CONFIG_FEC1_ENET_DEV 0 + +/* ENET1 connects AR8031 on CPU board */ +#define CONFIG_FEC2_ENET_DEV 1 +#define CONFIG_FEC_MXC_PHYADDR 0x4 +#define IMX_FEC_BASE 0x5B040000 +/* FEC1 */ +#define IMX_FEC1_BASE 0x5B040000 +#define CONFIG_FEC1_MXC_PHYADDR 0x4 +#define CONFIG_ETHPRIME "eth0" +/* FEC2 */ +#define IMX_FEC2_BASE 0x5B050000 +#define CONFIG_FEC2_MXC_PHYADDR 0x4 +#define CONFIG_ETHPRIME1 "eth1" + +/* Boot M4 */ +#define M4_BOOT_ENV \ + "m4_0_image=m4_0.bin\0" \ + "m4_1_image=m4_1.bin\0" \ + "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \ + "loadm4image_1=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \ + "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ + "m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" \ + +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) " +#else +#define MFG_NAND_PARTITION "" +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "initrd_addr=0x83100000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "emmc_dev=0\0" \ + "sd_dev=1\0" \ + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + M4_BOOT_ENV \ + "script=boot.scr\0" \ + "image=Image\0" \ + "panel=NULL\0" \ + "console=ttyLP0\0" \ + "earlycon=lpuart32,0x5a060000\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "boot_fdt=try\0" \ + "fdt_file=imx8qm-dmsse20-a1.dtb\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp mac=${ethaddr} nfsroot=${serverip}:${nfsroot},v3,tcp rw\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x80280000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + +/* Default environment is in SD */ + +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#else +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#endif + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 0 + +#define CONFIG_SYS_MMC_ENV_DEV 2 /* USDHC3 */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC3 */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x080000000 +#define PHYS_SDRAM_1 0x080000000 +#define PHYS_SDRAM_2 0x880000000 +#define PHYS_SDRAM_1_SIZE 0x080000000 /* 2 GB */ +#define PHYS_SDRAM_2_SIZE 0x180000000 /* 6 GB */ + +#define CONFIG_SYS_MEMTEST_START 0xA0000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_1_SIZE >> 2)) + +/* Serial */ +#define CONFIG_BAUDRATE 115200 + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +#define CONFIG_IMX_SMMU + +/* MT35XU512ABA1G12 has only one Die, so QSPI0 B won't work */ +#ifdef CONFIG_FSL_FSPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define FSL_FSPI_FLASH_SIZE SZ_64M +#define FSL_FSPI_FLASH_NUM 1 +#define FSPI0_BASE_ADDR 0x5d120000 +#define FSPI0_AMBA_BASE 0 +#define CONFIG_SYS_FSL_FSPI_AHB +#endif + +/* #define CONFIG_OF_SYSTEM_SETUP */ + +#endif /* __IMX8QM_DMSSE20_H */ -- 2.17.1

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[PATCH 0/6] microblaze: Cleanup series
by Michal Simek 04 Nov '20

04 Nov '20

Hi, I looked at microblaze configs and clean up some things. All changes were done in connection to detect nor flash based on information taken from DT. Thanks Michal Michal Simek (6): microblaze: Clean config file from ifdef mess microblaze: Simplify cache handling microblaze: Get rid of xparameters.h microblaze: Remove CONFIG_SYS_FDT_SIZE microblaze: Get rid of setting for SPL_NOR/XIP support microblaze: Detect NOR flash based on DT board/xilinx/microblaze-generic/xparameters.h | 18 ---- configs/microblaze-generic_defconfig | 2 + include/configs/microblaze-generic.h | 86 ++----------------- scripts/config_whitelist.txt | 1 - 4 files changed, 8 insertions(+), 99 deletions(-) delete mode 100644 board/xilinx/microblaze-generic/xparameters.h -- 2.29.2

1 6