November 2020 - U-Boot

[PATCH v6 00/14] x86: Updates to SMBIOS
by Simon Glass 06 Nov '20

06 Nov '20

At present there are a few Kconfig options which allow SMBIOS fields to be specified at build time. Not all fields are supported. Also, defining these at build-time is limiting since a factory system cannot insert values for particular boards or models without rebuilding U-Boot. This series adds a way to set SMBIOS properties using the devicetree. With this approach, more fields are supported and it is easy to update values in the devicetree in the factory. It also updates existing boards to use devicetree and drops the CONFIG options, using a new default sysinfo driver. Changes in v6: - Fix 'manuafacture' typo in Kconfig - Add new patch to provide default SMBIOS manufacturer/product Changes in v5: - Fix "sysinfo_gazerbeam" compatible string to use a hyphen - Add a note as to why the patch does not just rename some files - Fix up the example for the binding - Fix "manufactuer" typo - Fix "Informaiton" typo - Update commit message to explain why family does not have a default - Fix 'manuafacture' typo in commit message - Move the Kconfig comment into the devicetree - Rename smbios_add_prop_default() to smbios_add_prop() Changes in v4: - Fix build error with vexpress_ca9x4 Changes in v3: - Use a different binding with subnodes for each table type - Add onto the sysinfo binding Changes in v2: - Move dm.h header file to avoid build error on qemu-arm - Deal with boards that don't use of-control Simon Glass (14): board: Rename uclass to sysinfo doc: Add a binding for sysinfo x86: Pass an ofnode into each SMBIOS function smbios: Allow properties to come from the device tree smbios: Add more properties smbios: Add documentation and devicetree binding sysinfo: Provide a default driver to set SMBIOS values rockchip: Use devicetree for SMBIOS settings imx: Use devicetree for SMBIOS settings on MYiR MYS-6ULX odroid-c2: Use devicetree for SMBIOS settings arm64: mvebu: Use devicetree for SMBIOS settings on uDPU x86: galileo: Use devicetree for SMBIOS settings x86: Provide default SMBIOS manufacturer/product smbios: Drop the unused Kconfig options arch/Kconfig | 2 + arch/arm/dts/armada-3720-uDPU-u-boot.dtsi | 20 +++ .../dts/imx6ull-myir-mys-6ulx-eval-u-boot.dts | 25 ++++ arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi | 23 ++++ arch/arm/dts/rk3328-roc-cc-u-boot.dtsi | 21 +++ arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi | 23 ++++ arch/arm/dts/rk3328-rock64-u-boot.dtsi | 21 +++ arch/arm/dts/rk3368-lion-u-boot.dtsi | 20 +++ arch/powerpc/dts/gdsys/gazerbeam-uboot.dtsi | 2 +- arch/sandbox/dts/test.dts | 8 +- arch/x86/dts/bayleybay.dts | 2 + arch/x86/dts/baytrail_som-db5800-som-6867.dts | 2 + arch/x86/dts/cherryhill.dts | 2 + arch/x86/dts/chromebook_link.dts | 2 + arch/x86/dts/chromebook_samus.dts | 2 + arch/x86/dts/chromebox_panther.dts | 2 + arch/x86/dts/conga-qeval20-qa3-e3845.dts | 2 + arch/x86/dts/cougarcanyon2.dts | 2 + arch/x86/dts/crownbay.dts | 2 + arch/x86/dts/dfi-bt700.dtsi | 2 + arch/x86/dts/edison.dts | 2 + arch/x86/dts/galileo.dts | 28 ++++ arch/x86/dts/minnowmax.dts | 2 + arch/x86/dts/qemu-x86_i440fx.dts | 2 + arch/x86/dts/qemu-x86_q35.dts | 2 + arch/x86/dts/smbios.dtsi | 32 +++++ board/gdsys/common/cmd_ioloop.c | 12 +- board/gdsys/mpc8308/gazerbeam.c | 47 +++---- board/google/chromebook_coral/coral.c | 2 +- board/intel/galileo/Kconfig | 11 -- common/spl/spl_fit.c | 15 ++- configs/chromebook_coral_defconfig | 2 +- configs/clearfog_gt_8k_defconfig | 2 - configs/gazerbeam_defconfig | 4 +- configs/lion-rk3368_defconfig | 4 +- configs/mt7622_rfb_defconfig | 1 - configs/mvebu_db_armada8k_defconfig | 2 - configs/myir_mys_6ulx_defconfig | 3 +- configs/odroid-c2_defconfig | 4 +- configs/r8a774a1_beacon_defconfig | 2 - configs/r8a77970_eagle_defconfig | 2 - configs/r8a77980_condor_defconfig | 2 - configs/r8a77990_ebisu_defconfig | 2 - configs/r8a77995_draak_defconfig | 2 - configs/rcar3_salvator-x_defconfig | 2 - configs/rcar3_ulcb_defconfig | 2 - configs/roc-cc-rk3328_defconfig | 4 +- configs/rock-pi-e-rk3328_defconfig | 4 +- configs/rock64-rk3328_defconfig | 4 +- configs/sandbox64_defconfig | 4 +- configs/sandbox_defconfig | 4 +- configs/sandbox_flattree_defconfig | 4 +- configs/sandbox_spl_defconfig | 4 +- configs/uDPU_defconfig | 3 +- doc/arch/x86.rst | 8 ++ .../gdsys,sysinfo_gazerbeam.txt} | 8 +- doc/device-tree-bindings/sysinfo/smbios.txt | 77 +++++++++++ doc/device-tree-bindings/sysinfo/sysinfo.txt | 19 +++ drivers/Kconfig | 4 +- drivers/Makefile | 2 +- drivers/board/Kconfig | 25 ---- drivers/board/Makefile | 7 - drivers/board/board-uclass.c | 71 ----------- drivers/sysinfo/Kconfig | 33 +++++ drivers/sysinfo/Makefile | 8 ++ drivers/{board => sysinfo}/gazerbeam.c | 74 +++++------ drivers/{board => sysinfo}/gazerbeam.h | 0 drivers/{board => sysinfo}/sandbox.c | 50 ++++---- drivers/{board => sysinfo}/sandbox.h | 0 drivers/sysinfo/smbios.c | 24 ++++ drivers/sysinfo/sysinfo-uclass.c | 71 +++++++++++ drivers/timer/mpc83xx_timer.c | 10 +- include/dm/uclass-id.h | 2 +- include/smbios.h | 5 +- include/{board.h => sysinfo.h} | 80 ++++++------ lib/Kconfig | 17 +-- lib/smbios.c | 120 +++++++++++++----- test/dm/Makefile | 2 +- test/dm/board.c | 59 --------- test/dm/sysinfo.c | 59 +++++++++ 80 files changed, 823 insertions(+), 419 deletions(-) create mode 100644 arch/arm/dts/imx6ull-myir-mys-6ulx-eval-u-boot.dts create mode 100644 arch/x86/dts/smbios.dtsi rename doc/device-tree-bindings/{board/gdsys,board_gazerbeam.txt => sysinfo/gdsys,sysinfo_gazerbeam.txt} (90%) create mode 100644 doc/device-tree-bindings/sysinfo/smbios.txt create mode 100644 doc/device-tree-bindings/sysinfo/sysinfo.txt delete mode 100644 drivers/board/Kconfig delete mode 100644 drivers/board/Makefile delete mode 100644 drivers/board/board-uclass.c create mode 100644 drivers/sysinfo/Kconfig create mode 100644 drivers/sysinfo/Makefile rename drivers/{board => sysinfo}/gazerbeam.c (69%) rename drivers/{board => sysinfo}/gazerbeam.h (100%) rename drivers/{board => sysinfo}/sandbox.c (50%) rename drivers/{board => sysinfo}/sandbox.h (100%) create mode 100644 drivers/sysinfo/smbios.c create mode 100644 drivers/sysinfo/sysinfo-uclass.c rename include/{board.h => sysinfo.h} (65%) delete mode 100644 test/dm/board.c create mode 100644 test/dm/sysinfo.c -- 2.29.1.341.ge80a0c044ae-goog

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[PATCH] efi_loader: Add missing newline to log_{err,warning}
by Paulo Alcantara 06 Nov '20

06 Nov '20

Add missing newline to log messages in efi_rng_register() otherwise something like below would be shown Scanning disk virtio-blk#31... Found 2 disks Missing RNG device for EFI_RNG_PROTOCOLNo EFI system partition Signed-off-by: Paulo Alcantara (SUSE) <pc(a)cjr.nz> --- lib/efi_loader/efi_rng.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/efi_loader/efi_rng.c b/lib/efi_loader/efi_rng.c index a8a87007b65f..8bdadad0a953 100644 --- a/lib/efi_loader/efi_rng.c +++ b/lib/efi_loader/efi_rng.c @@ -166,13 +166,13 @@ efi_status_t efi_rng_register(void) ret = platform_get_rng_device(&dev); if (ret != EFI_SUCCESS) { - log_warning("Missing RNG device for EFI_RNG_PROTOCOL"); + log_warning("Missing RNG device for EFI_RNG_PROTOCOL\n"); return EFI_SUCCESS; } ret = efi_add_protocol(efi_root, &efi_guid_rng_protocol, (void *)&efi_rng_protocol); if (ret != EFI_SUCCESS) - log_err("Cannot install EFI_RNG_PROTOCOL"); + log_err("Cannot install EFI_RNG_PROTOCOL\n"); return ret; } -- 2.29.1

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[PULL u-boot] Please pull u-boot-amlogic-20201105
by Neil Armstrong 06 Nov '20

06 Nov '20

Hi Tom, This PR fixes some documentation and the android early logo boot flow. The CI job is at https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic/pipelines/5274 Thanks, Neil The following changes since commit cdeb7b8f984e6d9bcdc5a6fdda6107af156d47bf: configs: Resync with savedefconfig (2020-10-29 10:48:01 -0400) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic.git tags/u-boot-amlogic-20201105 for you to fetch changes up to 014b9f96762d17d04038d8902d419b6476753e4f: configs: meson64: relocate config_distro_bootcmmd header (2020-11-05 16:27:31 +0100) ---------------------------------------------------------------- - meson64_android: don't show logo on ROM USB boot - doc: update support matrix and fix vim3/l build instructions - meson64: relocate config_distro_bootcmmd header ---------------------------------------------------------------- Guillaume La Roque (1): configs: meson64_android: don't show logo on ROM USB boot Jaehoon Chung (1): configs: meson64: relocate config_distro_bootcmmd header Neil Armstrong (2): doc: board: amlogic: Update support matrix doc: board: vim3: Fix build instructions doc/board/amlogic/index.rst | 8 +++++--- doc/board/amlogic/khadas-vim3.rst | 9 +++++---- doc/board/amlogic/khadas-vim3l.rst | 11 +++++++---- include/configs/meson64.h | 3 ++- include/configs/meson64_android.h | 11 +++++++---- 5 files changed, 26 insertions(+), 16 deletions(-)

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Please pull u-boot-x86
by Bin Meng 06 Nov '20

06 Nov '20

Hi Tom, This PR includes the following changes for v2021.01 release: - Add a new SMBIOS parser and enable it when booting from coreboot - Fix up various driver names to avoid dtoc warnings - Fully enable ACPI support on Google Chromebook Coral - Add a way to set SMBIOS properties using the devicetree - Update existing boards to use devicetree for SMBIOS using a new default sysinfo driver Azure results: PASS https://dev.azure.com/bmeng/GitHub/_build/results?buildId=299&view=results The following changes since commit 35b7ca768f7d826b77d5d3d6ccd6b1b8ed21f186: arch: Move NEEDS_MANUAL_RELOC symbol to Kconfig (2020-11-04 10:13:44 -0500) are available in the git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-x86 for you to fetch changes up to e4f8e543f1a905857a753a1d411997a81f4f52aa: smbios: Drop the unused Kconfig options (2020-11-06 10:26:32 +0800) ---------------------------------------------------------------- Christian Gmeiner (2): smbios: add parsing API coreboot: make use of smbios parser Simon Glass (48): cros_ec: Fix up driver names to avoid dtoc warnings x86: Fix up driver names to avoid dtoc warnings Add an assembly guard around linux/bitops.h x86: apl: Add core init for the SoC x86: Add a layout for Chrome OS verified boot x86: Add support for private files x86: Allow writing tables to fail x86: acpi: Store the ACPI context in global_data x86: Don't bother clearing global NVS x86: coral: Drop the duplicate PCIe settings x86: Add SMBIOS info for Coral x86: Use if instead of #ifdef in write_tables() x86: Allow putting some tables in the bloblist x86: nhlt: Correct output of bytes and 16-bit data x86: nhlt: Fix a few bugs in the table generation x86: Show the interrupt pointer with 'irqinfo' x86: sound: Correct error handling acpi: Correct reset handling in acpi_device_add_power_res() x86: acpi: Allow the SSDT to be empty x86: acpi: Put the generated code first in DSDT acpi: Don't reset the tables with every new generation x86: Define the Chrome OS GNVS region x86: Use CONFIG_CHROMEOS_VBOOT for verified boot x86: Set up Chrome OS to boot into developer mode x86: Boot coral into Chrome OS by default x86: fsp: Convert fsp_dram to use log_debug() x86: Silence some logging statements x86: acpi: Include the TPMv1 table only if needed x86: acpi: Don't show the UART address by default x86: pinctrl: Silence the warning when a pin is not found x86: fsp: Adjust calculations for MTRR range and DRAM top x86: zimage: Add a little more logging x86: zimage: Sanity-check the kernel version before printing it x86: zimage: Quieten down the zimage boot process board: Rename uclass to sysinfo doc: Add a binding for sysinfo x86: Pass an ofnode into each SMBIOS function smbios: Allow properties to come from the device tree smbios: Add more properties smbios: Add documentation and devicetree binding sysinfo: Provide a default driver to set SMBIOS values rockchip: Use devicetree for SMBIOS settings imx: Use devicetree for SMBIOS settings on MYiR MYS-6ULX odroid-c2: Use devicetree for SMBIOS settings arm64: mvebu: Use devicetree for SMBIOS settings on uDPU x86: galileo: Use devicetree for SMBIOS settings x86: Provide default SMBIOS manufacturer/product smbios: Drop the unused Kconfig options arch/Kconfig | 2 ++ arch/arm/dts/armada-3720-uDPU-u-boot.dtsi | 20 +++++++++++ arch/arm/dts/imx6ull-myir-mys-6ulx-eval-u-boot.dts | 25 ++++++++++++++ arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi | 23 +++++++++++++ arch/arm/dts/rk3328-roc-cc-u-boot.dtsi | 21 ++++++++++++ arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi | 23 +++++++++++++ arch/arm/dts/rk3328-rock64-u-boot.dtsi | 21 ++++++++++++ arch/arm/dts/rk3368-lion-u-boot.dtsi | 20 +++++++++++ arch/powerpc/dts/gdsys/gazerbeam-uboot.dtsi | 2 +- arch/sandbox/dts/test.dts | 8 ++--- arch/x86/cpu/apollolake/acpi.c | 25 +++++++++++--- arch/x86/cpu/apollolake/cpu.c | 88 +++++++++++++++++++++++++++++++++++++++++++++-- arch/x86/cpu/apollolake/cpu_common.c | 25 ++++++++++++++ arch/x86/cpu/apollolake/cpu_spl.c | 20 ----------- arch/x86/cpu/apollolake/fsp_s.c | 8 ++--- arch/x86/cpu/apollolake/hostbridge.c | 2 +- arch/x86/cpu/apollolake/lpc.c | 2 +- arch/x86/cpu/apollolake/pch.c | 4 +-- arch/x86/cpu/apollolake/pmc.c | 2 +- arch/x86/cpu/apollolake/punit.c | 4 +-- arch/x86/cpu/apollolake/uart.c | 2 +- arch/x86/cpu/cpu.c | 9 ++++- arch/x86/cpu/i386/interrupt.c | 14 ++++---- arch/x86/cpu/intel_common/acpi.c | 1 - arch/x86/cpu/intel_common/cpu.c | 19 +++++++++++ arch/x86/cpu/intel_common/intel_opregion.c | 2 +- arch/x86/cpu/intel_common/itss.c | 10 +++--- arch/x86/cpu/intel_common/p2sb.c | 2 +- arch/x86/dts/bayleybay.dts | 2 ++ arch/x86/dts/baytrail_som-db5800-som-6867.dts | 2 ++ arch/x86/dts/cherryhill.dts | 2 ++ arch/x86/dts/chromebook_coral.dts | 12 +++++-- arch/x86/dts/chromebook_link.dts | 2 ++ arch/x86/dts/chromebook_samus.dts | 4 ++- arch/x86/dts/chromebox_panther.dts | 2 ++ arch/x86/dts/conga-qeval20-qa3-e3845.dts | 2 ++ arch/x86/dts/cougarcanyon2.dts | 2 ++ arch/x86/dts/crownbay.dts | 2 ++ arch/x86/dts/dfi-bt700.dtsi | 2 ++ arch/x86/dts/edison.dts | 2 ++ arch/x86/dts/galileo.dts | 28 +++++++++++++++ arch/x86/dts/minnowmax.dts | 2 ++ arch/x86/dts/qemu-x86_i440fx.dts | 2 ++ arch/x86/dts/qemu-x86_q35.dts | 2 ++ arch/x86/dts/smbios.dtsi | 32 ++++++++++++++++++ arch/x86/dts/u-boot.dtsi | 4 +++ arch/x86/include/asm/acpi/vbnv_layout.h | 38 +++++++++++++++++++++ arch/x86/include/asm/arch-apollolake/cpu.h | 14 ++++++++ arch/x86/include/asm/cpu_common.h | 9 +++++ arch/x86/include/asm/intel_gnvs.h | 54 ++++++++++++++++++++++++++--- arch/x86/include/asm/interrupt.h | 17 ++++++++++ arch/x86/include/asm/msr-index.h | 20 ++++++++++- arch/x86/include/asm/tables.h | 4 ++- arch/x86/lib/acpi_nhlt.c | 19 ++++++++--- arch/x86/lib/acpi_table.c | 78 ++++++++++++++++++++++++++++-------------- arch/x86/lib/fsp/fsp_dram.c | 35 ++++++++++++------- arch/x86/lib/fsp/fsp_graphics.c | 2 +- arch/x86/lib/fsp2/fsp_dram.c | 8 +++-- arch/x86/lib/interrupts.c | 3 ++ arch/x86/lib/tables.c | 88 +++++++++++++++++++++++++++++++++++------------ arch/x86/lib/tpl.c | 2 +- arch/x86/lib/zimage.c | 26 +++++++++++--- board/coreboot/coreboot/coreboot.c | 45 +++++++++++++++++++++++++ board/gdsys/common/cmd_ioloop.c | 12 ++++--- board/gdsys/mpc8308/gazerbeam.c | 47 ++++++++++++++------------ board/google/chromebook_coral/coral.c | 2 +- board/intel/galileo/Kconfig | 11 ------ common/Kconfig.boot | 17 ++++++++++ common/log.c | 1 + common/spl/spl_fit.c | 15 +++++---- configs/chromebook_coral_defconfig | 13 ++++--- configs/clearfog_gt_8k_defconfig | 2 -- configs/coreboot_defconfig | 1 + configs/gazerbeam_defconfig | 4 +-- configs/lion-rk3368_defconfig | 4 +-- configs/mt7622_rfb_defconfig | 1 - configs/mvebu_db_armada8k_defconfig | 2 -- configs/myir_mys_6ulx_defconfig | 3 +- configs/odroid-c2_defconfig | 4 +-- configs/r8a774a1_beacon_defconfig | 2 -- configs/r8a77970_eagle_defconfig | 2 -- configs/r8a77980_condor_defconfig | 2 -- configs/r8a77990_ebisu_defconfig | 2 -- configs/r8a77995_draak_defconfig | 2 -- configs/rcar3_salvator-x_defconfig | 2 -- configs/rcar3_ulcb_defconfig | 2 -- configs/roc-cc-rk3328_defconfig | 4 +-- configs/rock-pi-e-rk3328_defconfig | 4 +-- configs/rock64-rk3328_defconfig | 4 +-- configs/sandbox64_defconfig | 4 +-- configs/sandbox_defconfig | 4 +-- configs/sandbox_flattree_defconfig | 4 +-- configs/sandbox_spl_defconfig | 4 +-- configs/uDPU_defconfig | 3 +- doc/arch/x86.rst | 8 +++++ doc/device-tree-bindings/{board/gdsys,board_gazerbeam.txt => sysinfo/gdsys,sysinfo_gazerbeam.txt} | 8 ++--- doc/device-tree-bindings/sysinfo/smbios.txt | 77 ++++++++++++++++++++++++++++++++++++++++++ doc/device-tree-bindings/sysinfo/sysinfo.txt | 19 +++++++++++ drivers/Kconfig | 4 +-- drivers/Makefile | 2 +- drivers/board/Kconfig | 25 -------------- drivers/board/Makefile | 7 ---- drivers/board/board-uclass.c | 71 -------------------------------------- drivers/core/acpi.c | 10 +++--- drivers/gpio/intel_gpio.c | 4 +-- drivers/misc/cros_ec_i2c.c | 4 +-- drivers/misc/cros_ec_lpc.c | 4 +-- drivers/misc/cros_ec_spi.c | 4 +-- drivers/pinctrl/intel/pinctrl.c | 2 +- drivers/pinctrl/intel/pinctrl_apl.c | 2 +- drivers/rtc/mc146818.c | 4 +-- drivers/sound/da7219.c | 4 +-- drivers/sound/max98357a.c | 2 +- drivers/sysinfo/Kconfig | 33 ++++++++++++++++++ drivers/sysinfo/Makefile | 8 +++++ drivers/{board => sysinfo}/gazerbeam.c | 74 ++++++++++++++++++++-------------------- drivers/{board => sysinfo}/gazerbeam.h | 0 drivers/{board => sysinfo}/sandbox.c | 50 +++++++++++++-------------- drivers/{board => sysinfo}/sandbox.h | 0 drivers/sysinfo/smbios.c | 24 +++++++++++++ drivers/sysinfo/sysinfo-uclass.c | 71 ++++++++++++++++++++++++++++++++++++++ drivers/sysreset/sysreset_x86.c | 4 +-- drivers/timer/mpc83xx_timer.c | 10 +++--- drivers/timer/tsc_timer.c | 4 +-- include/acpi/acpi_table.h | 10 ++++++ include/asm-generic/global_data.h | 13 +++++++ include/bloblist.h | 2 ++ include/configs/chromebook_coral.h | 9 ++++- include/dm/acpi.h | 9 +++++ include/dm/uclass-id.h | 2 +- include/linux/bitops.h | 4 +-- include/log.h | 1 + include/smbios.h | 32 +++++++++++++++++- include/{board.h => sysinfo.h} | 80 +++++++++++++++++++++---------------------- lib/Kconfig | 31 ++++++++--------- lib/Makefile | 1 + lib/acpi/acpi_device.c | 2 +- lib/acpi/acpi_table.c | 4 +-- lib/smbios-parser.c | 96 ++++++++++++++++++++++++++++++++++++++++++++++++++++ lib/smbios.c | 120 +++++++++++++++++++++++++++++++++++++++++++++++------------------ test/dm/Makefile | 2 +- test/dm/acpi.c | 4 +++ test/dm/board.c | 59 -------------------------------- test/dm/sysinfo.c | 59 ++++++++++++++++++++++++++++++++ 144 files changed, 1645 insertions(+), 590 deletions(-) create mode 100644 arch/arm/dts/imx6ull-myir-mys-6ulx-eval-u-boot.dts create mode 100644 arch/x86/dts/smbios.dtsi create mode 100644 arch/x86/include/asm/acpi/vbnv_layout.h rename doc/device-tree-bindings/{board/gdsys,board_gazerbeam.txt => sysinfo/gdsys,sysinfo_gazerbeam.txt} (90%) create mode 100644 doc/device-tree-bindings/sysinfo/smbios.txt create mode 100644 doc/device-tree-bindings/sysinfo/sysinfo.txt delete mode 100644 drivers/board/Kconfig delete mode 100644 drivers/board/Makefile delete mode 100644 drivers/board/board-uclass.c create mode 100644 drivers/sysinfo/Kconfig create mode 100644 drivers/sysinfo/Makefile rename drivers/{board => sysinfo}/gazerbeam.c (69%) rename drivers/{board => sysinfo}/gazerbeam.h (100%) rename drivers/{board => sysinfo}/sandbox.c (50%) rename drivers/{board => sysinfo}/sandbox.h (100%) create mode 100644 drivers/sysinfo/smbios.c create mode 100644 drivers/sysinfo/sysinfo-uclass.c rename include/{board.h => sysinfo.h} (65%) create mode 100644 lib/smbios-parser.c delete mode 100644 test/dm/board.c create mode 100644 test/dm/sysinfo.c Regards, Bin

2 1

[PATCH] Makefile: Fix calling make with V=1
by Pali Rohár 06 Nov '20

06 Nov '20

Calling 'make V=1 all' on Ubuntu 18.04 with gcc version 9.2.1 and GNU Make version 4.1 fails on error: scripts/Kbuild.include:220: *** Recursive variable 'echo-cmd' references itself (eventually). Stop. As a workaround expand 'echo-cmd' variable via 'call' construction instead of expanding it directly. Signed-off-by: Pali Rohár <pali(a)kernel.org> Reported-by: Patrick DELAUNAY <patrick.delaunay(a)st.com> --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 94feb7d9a5..b90fe8b865 100644 --- a/Makefile +++ b/Makefile @@ -1309,7 +1309,7 @@ init_sp_bss_offset_check: u-boot.dtb FORCE fi endif -shell_cmd = { $(echo-cmd) $(cmd_$(1)); } +shell_cmd = { $(call echo-cmd,$(1)) $(cmd_$(1)); } quiet_cmd_objcopy_uboot = OBJCOPY $@ cmd_objcopy_uboot = $(cmd_objcopy) && $(call shell_cmd,static_rela,$<,$@,$(CONFIG_SYS_TEXT_BASE)) || { rm -f $@; false; } -- 2.20.1

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[GIT PULL] Pull request: u-boot-imx u-boot-imx-20201105
by Stefano Babic 06 Nov '20

06 Nov '20

Hi Tom, please pull from u-boot-imx, thanks ! The following changes since commit 2c31d7e746766f47a007f39c030706e493a9cc77: Merge tag 'u-boot-rockchip-20201031' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip (2020-10-30 23:13:13 -0400) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git tags/u-boot-imx-20201105 for you to fetch changes up to b431970e7f0ce5b83fae1502eddc3568115207ad: board: ge: b1x5v2: Add MAINTAINERS (2020-11-04 19:47:30 +0100) ---------------------------------------------------------------- u-boot-imx for 2021.1 --------------------- - new boards : GE (new B1x5v2), phytec phyCORE-i.MX8MM - converted doc to reST - fixes for verdin-imx8mm (Toradex) - fixes for i.MX thermal driver - mx7ulp: Align the PLL_USB frequency - mx53: primary/secondary bmode Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/741465284 ---------------------------------------------------------------- Fabio Estevam (2): mx7ulp: clock: Remove unuseful information mx7ulp: clock: Align the PLL_USB frequency Igor Opaniuk (1): verdin-imx8mm: enable fdt overlays and env importing Jorge Ramirez-Ortiz (1): mx6: peripheral clock from oscillator Lukasz Majewski (3): arm: Implement show_boot_progress() for imx53's HSC and DDC devices dts: Provide LED DTS description for HSC and DDC imx53 devices defconfig: Enable CONFIG_SHOW_BOOT_PROGRESS for imx53's HSC and DDC devices Marek Vasut (1): ARM: imx: Add support for the primary/secondary bmode to MX53 Michael Walle (1): watchdog: Hide WATCHDOG_RESET_DISABLE Peng Fan (12): board: imx: address dd usage in README doc: board: Convert i.MX8MP EVK README to reST doc: board: Convert i.MX8MN EVK README to reST doc: board: Convert i.MX8MM EVK README to reST doc: board: Convert i.MX8MQ EVK README to reST doc: board: Convert i.MX8QXP MEK README to reST doc: board: Convert i.MXRT1020 EVK README to reST doc: board: Convert i.MXRT1050 EVK README to reST doc: board: Convert i.MX6 Sabreauto README to reST doc: board: Convert i.MX6 Sabresd README to reST doc: board: Convert i.MX6UL 14x14 EVK README to reST doc: board: Convert i.MX6ULL EVK README to reST Sebastian Reichel (12): bootcount: add a DM SPI flash backing store for bootcount rtc: m41t62: reset SQW in m41t62_rtc_reset rtc: m41t62: add oscillator fail bit reset support imx6: allow usage of disable_ldb_di_clock_sources for CONFIG_MX6QDL sysreset: Add poweroff-gpio driver board: ge: common: rename ge_common.c to ge_rtc.c board: ge: common: add config option for RTC and VPD feature board: ge: common: vpd: separate I2C specific code board: ge: b1x5v2: Add GE B1x5v2 and B1x5Pv2 board: ge: bx50v3: Update MAINTAINERS board: ge: ppd: Update MAINTAINERS board: ge: b1x5v2: Add MAINTAINERS Teresa Remmet (1): board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM support Tim Harvey (2): imx: cpu: terminate line with CR if invalid temp sensor thermal: imx_tmu: fix missing include arch/arm/dts/Makefile | 2 + arch/arm/dts/imx53-kp.dts | 4 + arch/arm/dts/imx6dl-b1x5v2.dts | 654 +++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/phycore-imx8mm-u-boot.dtsi | 100 ++++++++ arch/arm/dts/phycore-imx8mm.dts | 259 +++++++++++++++++++ arch/arm/mach-imx/cpu.c | 3 +- arch/arm/mach-imx/imx8m/Kconfig | 6 + arch/arm/mach-imx/mx5/soc.c | 21 +- arch/arm/mach-imx/mx6/Kconfig | 9 + arch/arm/mach-imx/mx6/clock.c | 2 +- arch/arm/mach-imx/mx6/soc.c | 5 +- arch/arm/mach-imx/mx7ulp/clock.c | 6 +- board/freescale/imx8mm_evk/README | 37 --- board/freescale/imx8mn_evk/README | 37 --- board/freescale/imx8mp_evk/README | 41 --- board/freescale/imx8mq_evk/README | 37 --- board/freescale/imx8qxp_mek/README | 50 ---- board/freescale/imxrt1020-evk/README | 31 --- board/freescale/imxrt1050-evk/README | 31 --- board/freescale/mx6sabreauto/README | 82 ------ board/freescale/mx6sabresd/README | 114 --------- board/ge/b1x5v2/Kconfig | 14 + board/ge/b1x5v2/MAINTAINERS | 9 + board/ge/b1x5v2/Makefile | 6 + board/ge/b1x5v2/b1x5v2.c | 698 ++++++++++++++++++++++++++++++++++++++++++++++++++ board/ge/b1x5v2/spl.c | 587 ++++++++++++++++++++++++++++++++++++++++++ board/ge/bx50v3/Kconfig | 2 + board/ge/bx50v3/MAINTAINERS | 11 +- board/ge/bx50v3/bx50v3.c | 4 +- board/ge/common/Kconfig | 7 + board/ge/common/Makefile | 3 +- board/ge/common/{ge_common.c => ge_rtc.c} | 0 board/ge/common/{ge_common.h => ge_rtc.h} | 0 board/ge/common/vpd_reader.c | 12 +- board/ge/common/vpd_reader.h | 23 +- board/ge/mx53ppd/Kconfig | 2 + board/ge/mx53ppd/MAINTAINERS | 10 +- board/ge/mx53ppd/mx53ppd.c | 4 +- board/k+p/kp_imx53/kp_imx53.c | 51 ++++ board/phytec/phycore_imx8mm/Kconfig | 12 + board/phytec/phycore_imx8mm/MAINTAINERS | 9 + board/phytec/phycore_imx8mm/Makefile | 11 + board/phytec/phycore_imx8mm/lpddr4_timing.c | 1846 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ board/phytec/phycore_imx8mm/phycore-imx8mm.c | 53 ++++ board/phytec/phycore_imx8mm/spl.c | 128 ++++++++++ configs/ge_b1x5v2_defconfig | 137 ++++++++++ configs/kp_imx53_defconfig | 1 + configs/phycore-imx8mm_defconfig | 103 ++++++++ configs/verdin-imx8mm_defconfig | 2 +- doc/board/freescale/imx8mm_evk.rst | 56 ++++ doc/board/freescale/imx8mn_evk.rst | 57 +++++ doc/board/freescale/imx8mp_evk.rst | 61 +++++ doc/board/freescale/imx8mq_evk.rst | 56 ++++ doc/board/freescale/imx8qxp_mek.rst | 66 +++++ doc/board/freescale/imxrt1020-evk.rst | 41 +++ doc/board/freescale/imxrt1050-evk.rst | 41 +++ doc/board/freescale/index.rst | 11 + doc/board/freescale/mx6sabreauto.rst | 100 ++++++++ doc/board/freescale/mx6sabresd.rst | 132 ++++++++++ board/freescale/mx6ul_14x14_evk/README => doc/board/freescale/mx6ul_14x14_evk.rst | 62 +++-- board/freescale/mx6ullevk/README => doc/board/freescale/mx6ullevk.rst | 29 ++- drivers/bootcount/Kconfig | 10 + drivers/bootcount/Makefile | 1 + drivers/bootcount/spi-flash.c | 125 +++++++++ drivers/rtc/m41t62.c | 139 +++++++++- drivers/sysreset/Kconfig | 7 + drivers/sysreset/Makefile | 1 + drivers/sysreset/poweroff_gpio.c | 92 +++++++ drivers/thermal/imx_tmu.c | 1 + drivers/watchdog/Kconfig | 13 +- include/configs/ge_b1x5v2.h | 127 +++++++++ include/configs/phycore_imx8mm.h | 130 ++++++++++ 72 files changed, 6099 insertions(+), 535 deletions(-) create mode 100644 arch/arm/dts/imx6dl-b1x5v2.dts create mode 100644 arch/arm/dts/phycore-imx8mm-u-boot.dtsi create mode 100644 arch/arm/dts/phycore-imx8mm.dts delete mode 100644 board/freescale/imx8mm_evk/README delete mode 100644 board/freescale/imx8mn_evk/README delete mode 100644 board/freescale/imx8mp_evk/README delete mode 100644 board/freescale/imx8mq_evk/README delete mode 100644 board/freescale/imx8qxp_mek/README delete mode 100644 board/freescale/imxrt1020-evk/README delete mode 100644 board/freescale/imxrt1050-evk/README delete mode 100644 board/freescale/mx6sabreauto/README delete mode 100644 board/freescale/mx6sabresd/README create mode 100644 board/ge/b1x5v2/Kconfig create mode 100644 board/ge/b1x5v2/MAINTAINERS create mode 100644 board/ge/b1x5v2/Makefile create mode 100644 board/ge/b1x5v2/b1x5v2.c create mode 100644 board/ge/b1x5v2/spl.c create mode 100644 board/ge/common/Kconfig rename board/ge/common/{ge_common.c => ge_rtc.c} (100%) rename board/ge/common/{ge_common.h => ge_rtc.h} (100%) create mode 100644 board/phytec/phycore_imx8mm/Kconfig create mode 100644 board/phytec/phycore_imx8mm/MAINTAINERS create mode 100644 board/phytec/phycore_imx8mm/Makefile create mode 100644 board/phytec/phycore_imx8mm/lpddr4_timing.c create mode 100644 board/phytec/phycore_imx8mm/phycore-imx8mm.c create mode 100644 board/phytec/phycore_imx8mm/spl.c create mode 100644 configs/ge_b1x5v2_defconfig create mode 100644 configs/phycore-imx8mm_defconfig create mode 100644 doc/board/freescale/imx8mm_evk.rst create mode 100644 doc/board/freescale/imx8mn_evk.rst create mode 100644 doc/board/freescale/imx8mp_evk.rst create mode 100644 doc/board/freescale/imx8mq_evk.rst create mode 100644 doc/board/freescale/imx8qxp_mek.rst create mode 100644 doc/board/freescale/imxrt1020-evk.rst create mode 100644 doc/board/freescale/imxrt1050-evk.rst create mode 100644 doc/board/freescale/mx6sabreauto.rst create mode 100644 doc/board/freescale/mx6sabresd.rst rename board/freescale/mx6ul_14x14_evk/README => doc/board/freescale/mx6ul_14x14_evk.rst (65%) rename board/freescale/mx6ullevk/README => doc/board/freescale/mx6ullevk.rst (66%) create mode 100644 drivers/bootcount/spi-flash.c create mode 100644 drivers/sysreset/poweroff_gpio.c create mode 100644 include/configs/ge_b1x5v2.h create mode 100644 include/configs/phycore_imx8mm.h Best regards, Stefano -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic(a)denx.de =====================================================================

2 1

[PATCH v2 0/2] arm64: meson: add libretech cc v2 support
by Jerome Brunet 06 Nov '20

06 Nov '20

This patchset adds support for the Amlogic based libretech cc v2. Like the v1, this revised platform used the s905x SoC. Changes since v1: - Move Makefile change to patch #1 - Amend documentation for libretech cc v2 Jerome Brunet (2): arm64: dts: import libretech-cc-v2 from linux v5.10-rc1 arm64: meson: add support for libretech-cc v2 arch/arm/dts/Makefile | 1 + ...eson-gxl-s905x-libretech-cc-v2-u-boot.dtsi | 7 + .../dts/meson-gxl-s905x-libretech-cc-v2.dts | 318 ++++++++++++++++++ configs/libretech-cc_v2_defconfig | 82 +++++ 4 files changed, 408 insertions(+) create mode 100644 arch/arm/dts/meson-gxl-s905x-libretech-cc-v2-u-boot.dtsi create mode 100644 arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts create mode 100644 configs/libretech-cc_v2_defconfig -- 2.28.0

2 4

[PATCH 0/2] Fix the potential warning without DM_REGULATOR
by Jaehoon Chung 06 Nov '20

06 Nov '20

When CONFIG_DM_REGULATOR is disabled, there are some warnings. This patch-set is fixed them. drivers/phy/meson-g12a-usb2.c: In function 'phy_meson_g12a_usb2_power_on': drivers/phy/meson-g12a-usb2.c:70:35: warning: unused variable 'priv' [-Wunused-variable] 70 | struct phy_meson_g12a_usb2_priv *priv = dev_get_priv(dev); | ^~~~ drivers/phy/meson-g12a-usb2.c: In function 'phy_meson_g12a_usb2_power_off': drivers/phy/meson-g12a-usb2.c:86:35: warning: unused variable 'priv' [-Wunused-variable] 86 | struct phy_meson_g12a_usb2_priv *priv = dev_get_priv(dev); | ^~~~ LD drivers/phy/built-in.o CC drivers/video/simple_panel.o CC drivers/video/meson/meson_dw_hdmi.o drivers/video/meson/meson_dw_hdmi.c: In function 'meson_dw_hdmi_probe': drivers/video/meson/meson_dw_hdmi.c:382:18: warning: unused variable 'supply' [-Wunused-variable] 382 | struct udevice *supply; | ^~~~~~ Jaehoon Chung (2): phy: meson-g12a-usb2: fix the potential build warning video: meson: meson_dw_hdmi: fix the potential build warning drivers/phy/meson-g12a-usb2.c | 4 ++-- drivers/video/meson/meson_dw_hdmi.c | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) -- 2.29.0

2 3

[PATCH v4] imx: support for conga-QMX8 board
by Oliver Graute 06 Nov '20

06 Nov '20

Add i.MX8QM qmx8 congatec board support U-Boot 2021.01-rc1-00246-g63fe655de6 (Nov 06 2020 - 10:09:02 +0100) CPU: NXP i.MX8QM RevB A53 at 1200 MHz Model: Congatec QMX8 Qseven series Board: conga-QMX8 Build: SCFW 494c97f3, SECO-FW d7523fe8, ATF 09c5cc9 Boot: SD2 DRAM: 6 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... *** Warning - bad CRC, using default environment In: serial@5a060000 Out: serial@5a060000 Err: serial@5a060000 switch to partitions #0, OK mmc2 is current device Net: Error: ethernet@5b040000 address not set. No ethernet found. Hit any key to stop autoboot: 0 Signed-off-by: Oliver Graute <oliver.graute(a)kococonnector.com> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Ye Li <ye.li(a)nxp.com> Cc: uboot-imx <uboot-imx(a)nxp.com> --- These changes are based on this vendor tree: git.congatec.com/imx8_early_access/imx8_uboot_internal.git Changes for v4: - fixed missing DTS file in MAINTAINERS - replaced bd_t with struct bd_info - replaced README with imx8qm-dmsse20-a1.rst - move CMD_FUSE to Kconfig - replaced power_domain_lookup_name with imx8_power_domain_lookup_name Changes for v3: - include log.h - include delay.h - improved README - set phy register to six - Remove 'fdt_high' and 'initrd_high' environment variables - set CONFIG_SYS_BOOTMAPSZ to 256MB - increased CONFIG_SYS_FSL_USDHC_NUM to 3 Changes for v2: - added USDHC3_BASE_ADDR - replaced CONFIG_FSL_ESDHC with CONFIG_FSL_ESDHC_IMX - set CONFIG_FEC_MXC_PHYADDR to -1 - moved CONFIG_ENV_SIZE and CONFIG_ENV_OFFSET to defconfig arch/arm/dts/Makefile | 1 + arch/arm/dts/imx8qm-cgtqmx8.dts | 411 ++++++++++++++++++++++++ arch/arm/mach-imx/imx8/Kconfig | 7 + board/congatec/cgtqmx8/Kconfig | 14 + board/congatec/cgtqmx8/MAINTAINERS | 7 + board/congatec/cgtqmx8/Makefile | 11 + board/congatec/cgtqmx8/cgtqmx8.c | 469 ++++++++++++++++++++++++++++ board/congatec/cgtqmx8/imximage.cfg | 21 ++ board/congatec/cgtqmx8/spl.c | 77 +++++ board/congatec/common/Kconfig | 48 +++ board/congatec/common/Makefile | 23 ++ board/congatec/common/mmc.c | 52 +++ configs/cgtqmx8_defconfig | 86 +++++ doc/board/congatec/cgtqmx8.rst | 70 +++++ doc/board/congatec/index.rst | 9 + include/configs/cgtqmx8.h | 186 +++++++++++ 16 files changed, 1492 insertions(+) create mode 100644 arch/arm/dts/imx8qm-cgtqmx8.dts create mode 100644 board/congatec/cgtqmx8/Kconfig create mode 100644 board/congatec/cgtqmx8/MAINTAINERS create mode 100644 board/congatec/cgtqmx8/Makefile create mode 100644 board/congatec/cgtqmx8/cgtqmx8.c create mode 100644 board/congatec/cgtqmx8/imximage.cfg create mode 100644 board/congatec/cgtqmx8/spl.c create mode 100644 board/congatec/common/Kconfig create mode 100644 board/congatec/common/Makefile create mode 100644 board/congatec/common/mmc.c create mode 100644 configs/cgtqmx8_defconfig create mode 100644 doc/board/congatec/cgtqmx8.rst create mode 100644 doc/board/congatec/index.rst create mode 100644 include/configs/cgtqmx8.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9900b44274..6eb6399468 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -735,6 +735,7 @@ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \ dtb-$(CONFIG_ARCH_IMX8) += \ fsl-imx8qm-apalis.dtb \ fsl-imx8qm-mek.dtb \ + imx8qm-cgtqmx8.dtb \ imx8qm-rom7720-a1.dtb \ fsl-imx8qxp-ai_ml.dtb \ fsl-imx8qxp-colibri.dtb \ diff --git a/arch/arm/dts/imx8qm-cgtqmx8.dts b/arch/arm/dts/imx8qm-cgtqmx8.dts new file mode 100644 index 0000000000..43334147bb --- /dev/null +++ b/arch/arm/dts/imx8qm-cgtqmx8.dts @@ -0,0 +1,411 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * Copyright 2017 congatec AG + * Copyright (C) 2019 Oliver Graute <oliver.graute(a)kococonnector.com> + */ + +/dts-v1/; + +/* First 128KB is for PSCI ATF. */ +/memreserve/ 0x80000000 0x00020000; + +#include "fsl-imx8qm.dtsi" + +/ { + model = "Congatec QMX8 Qseven series"; + compatible = "fsl,imx8qm-qmx8", "fsl,imx8qm"; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + stdout-path = &lpuart0; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "sw-3p3-sd1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <3000>; + }; + + reg_usdhc3_vmmc: usdhc3_vmmc { + compatible = "regulator-fixed"; + regulator-name = "sw-3p3-sd2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <3000>; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii"; + phy-handle = <&ethphy0>; + fsl,magic-packet; + fsl,rgmii_txc_dly; + fsl,rgmii_rxc_dly; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@6 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <6>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + }; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + rtc_ext: m41t62@68 { + compatible = "st,m41t62"; + reg = <0x68>; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + wm8904: wm8904@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + + clocks = <&clk IMX8QM_AUD_MCLKOUT0>; + clock-names = "mclk"; + wlf,shared-lrclk; + /* power-domains = <&pd_mclk_out0>; */ + + assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QM_AUD_MCLKOUT0>; + + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx8qm-qmx8 { + + pinctrl_hog: hoggrp{ + fsl,pins = < + SC_P_M40_GPIO0_01_LSIO_GPIO0_IO09 0x00000021 + SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x00000021 + SC_P_M40_GPIO0_00_LSIO_GPIO0_IO08 0x00000021 + SC_P_ESAI1_SCKT_LSIO_GPIO2_IO07 0x00000021 + SC_P_SPDIF0_TX_LSIO_GPIO2_IO15 0x00000021 + SC_P_FLEXCAN1_RX_LSIO_GPIO3_IO31 0x00000021 + SC_P_ESAI1_TX0_LSIO_GPIO2_IO08 0x00000021 + SC_P_FLEXCAN1_TX_LSIO_GPIO4_IO00 0x00000021 + SC_P_ESAI1_TX1_LSIO_GPIO2_IO09 0x00000021 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 + >; + }; + + pinctrl_lpi2c0: lpi2c0grp { + fsl,pins = < + SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0xc600004c + SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + SC_P_GPT0_CLK_DMA_I2C1_SCL 0xc600004c + SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_DMA_UART0_RX 0x06000020 + SC_P_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + SC_P_UART1_RX_DMA_UART1_RX 0x06000020 + SC_P_UART1_TX_DMA_UART1_TX 0x06000020 + SC_P_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 + SC_P_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 + >; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + SC_P_M41_GPIO0_00_DMA_UART3_RX 0x06000020 + SC_P_M41_GPIO0_01_DMA_UART3_TX 0x06000020 + >; + }; + + pinctrl_mlb: mlbgrp { + fsl,pins = < + SC_P_MLB_SIG_CONN_MLB_SIG 0x21 + SC_P_MLB_CLK_CONN_MLB_CLK 0x21 + SC_P_MLB_DATA_CONN_MLB_DATA 0x21 + >; + }; + + pinctrl_isl29023: isl29023grp { + fsl,pins = < + SC_P_ADC_IN2_LSIO_GPIO3_IO20 0x00000021 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 + SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc3_gpio: usdhc3grpgpio { + fsl,pins = < + SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x00000021 + SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020 + >; + }; +/* + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; +*/ + }; +}; + +&lpuart0 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { /* Q7 connector */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + status = "okay"; +}; + +&pd_dma_lpuart0 { + debug_console; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <&reg_usdhc2_vmmc>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>; + bus-width = <4>; + cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <&reg_usdhc3_vmmc>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "okay"; +}; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 9d1f73dfc7..5cbcaa7b9e 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -80,6 +80,12 @@ config TARGET_IMX8QM_MEK select BOARD_LATE_INIT select IMX8QM +config TARGET_CONGA_QMX8 + bool "Support congatec conga-QMX8 board" + select BOARD_LATE_INIT + select SUPPORT_SPL + select IMX8QM + config TARGET_IMX8QM_ROM7720_A1 bool "Support i.MX8QM ROM-7720-A1" select BOARD_LATE_INIT @@ -95,6 +101,7 @@ endchoice source "board/freescale/imx8qm_mek/Kconfig" source "board/freescale/imx8qxp_mek/Kconfig" +source "board/congatec/cgtqmx8/Kconfig" source "board/advantech/imx8qm_rom7720_a1/Kconfig" source "board/toradex/apalis-imx8/Kconfig" source "board/toradex/colibri-imx8x/Kconfig" diff --git a/board/congatec/cgtqmx8/Kconfig b/board/congatec/cgtqmx8/Kconfig new file mode 100644 index 0000000000..7273039261 --- /dev/null +++ b/board/congatec/cgtqmx8/Kconfig @@ -0,0 +1,14 @@ +if TARGET_CONGA_QMX8 + +config SYS_BOARD + default "cgtqmx8" + +config SYS_VENDOR + default "congatec" + +config SYS_CONFIG_NAME + default "cgtqmx8" + +source "board/congatec/common/Kconfig" + +endif diff --git a/board/congatec/cgtqmx8/MAINTAINERS b/board/congatec/cgtqmx8/MAINTAINERS new file mode 100644 index 0000000000..53bc0f93b7 --- /dev/null +++ b/board/congatec/cgtqmx8/MAINTAINERS @@ -0,0 +1,7 @@ +i.MX8QM CGTQMX8 BOARD +M: Oliver Graute <oliver.graute(a)kococonnector.com> +S: Maintained +F: board/congatec/cgtqmx8/ +F: arch/arm/dts/imx8qm-cgtqmx8.dts +F: include/configs/cgtqmx8.h +F: configs/cgtqmx8_defconfig diff --git a/board/congatec/cgtqmx8/Makefile b/board/congatec/cgtqmx8/Makefile new file mode 100644 index 0000000000..4b59dbb6bc --- /dev/null +++ b/board/congatec/cgtqmx8/Makefile @@ -0,0 +1,11 @@ +# +# Copyright 2017 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cgtqmx8.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif diff --git a/board/congatec/cgtqmx8/cgtqmx8.c b/board/congatec/cgtqmx8/cgtqmx8.c new file mode 100644 index 0000000000..0e531e5b1c --- /dev/null +++ b/board/congatec/cgtqmx8/cgtqmx8.c @@ -0,0 +1,469 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 congatec AG + * Copyright (C) 2019 Oliver Graute <oliver.graute(a)kococonnector.com> + */ +#include <common.h> +#include <errno.h> +#include <linux/libfdt.h> +#include <fsl_esdhc.h> +#include <init.h> + +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/clock.h> +#include <asm/arch/sci/sci.h> +#include <asm/arch/imx8-pins.h> +#include <usb.h> +#include <asm/arch/iomux.h> +#include <asm/arch/sys_proto.h> +#include <linux/delay.h> +#include <power-domain.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define ESDHC_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ESDHC_CLK_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define FSPI_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define I2C_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +static iomux_cfg_t uart0_pads[] = { + SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads)); +} + +int board_early_init_f(void) +{ + /* sc_ipc_t ipcHndl = 0; */ + sc_err_t sciErr = 0; + + /* When start u-boot in XEN VM, directly return */ + /* if (IS_ENABLED(CONFIG_XEN)) */ + /* return 0; */ + + /* ipcHndl = gd->arch.ipc_channel_handle; */ + + /* Power up UART0, this is very early while power domain is not working */ + sciErr = sc_pm_set_resource_power_mode(-1, SC_R_UART_0, SC_PM_PW_MODE_ON); + if (sciErr != SC_ERR_NONE) + return 0; + + /* Set UART0 clock root to 80 MHz */ + sc_pm_clock_rate_t rate = 80000000; + sciErr = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, &rate); + if (sciErr != SC_ERR_NONE) + return 0; + + /* Enable UART0 clock root */ + sciErr = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false); + if (sciErr != SC_ERR_NONE) + return 0; + + setup_iomux_uart(); + + return 0; +} + +#ifdef CONFIG_FSL_ESDHC_IMX + +#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 22) +#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 12) + +static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { + {USDHC1_BASE_ADDR, 0, 8}, + {USDHC2_BASE_ADDR, 0, 4}, + {USDHC3_BASE_ADDR, 0, 4}, +}; + +static iomux_cfg_t emmc0[] = { + SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), + SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL), +}; + +static iomux_cfg_t usdhc1_sd[] = { + SC_P_USDHC1_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), + SC_P_USDHC1_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA6 | MUX_MODE_ALT(2) | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA7 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_VSELECT | MUX_PAD_CTRL(ESDHC_PAD_CTRL), +}; + +static iomux_cfg_t usdhc2_sd[] = { + SC_P_USDHC2_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), + SC_P_USDHC2_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_VSELECT | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_WP | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL), +}; + +int board_mmc_init(struct bd_info *bis) +{ + int i, ret; + struct power_domain pd; + + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 (onboard eMMC) USDHC1 + * mmc1 (external SD card) USDHC2 + * mmc2 (onboard µSD) USDHC3 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + /* onboard eMMC */ + if (!imx8_power_domain_lookup_name("conn_sdhc0", &pd)) + power_domain_on(&pd); + + imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0)); + init_clk_usdhc(0); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + /* external SD card */ + if (!imx8_power_domain_lookup_name("conn_sdhc1", &pd)) + power_domain_on(&pd); + + imx8_iomux_setup_multiple_pads(usdhc1_sd, ARRAY_SIZE(usdhc1_sd)); + init_clk_usdhc(1); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gpio_request(USDHC1_CD_GPIO, "sd1_cd"); + gpio_direction_input(USDHC1_CD_GPIO); + break; + case 2: + /* onboard µSD */ + if (!imx8_power_domain_lookup_name("conn_sdhc2", &pd)) + power_domain_on(&pd); + + imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd)); + init_clk_usdhc(2); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + gpio_request(USDHC2_CD_GPIO, "sd2_cd"); + gpio_direction_input(USDHC2_CD_GPIO); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return 0; + } + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = 1; + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + } + + return ret; +} + +#endif /* CONFIG_FSL_ESDHC_IMX */ + +#ifdef CONFIG_FEC_MXC +#include <miiphy.h> + +static iomux_cfg_t pad_enet0[] = { + SC_P_ENET0_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + imx8_iomux_setup_multiple_pads(pad_enet0, ARRAY_SIZE(pad_enet0)); +} + +static void enet_device_phy_reset(void) +{ + gpio_set_value(FEC0_RESET, 0); + udelay(50); + gpio_set_value(FEC0_RESET, 1); + + /* The board has a long delay for this reset to become stable */ + mdelay(200); +} + +int board_eth_init(struct bd_info *bis) +{ + setup_iomux_fec(); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +static int setup_fec(void) +{ + /* Reset ENET PHY */ + enet_device_phy_reset(); + + return 0; +} +#endif + +#ifdef CONFIG_MXC_GPIO + +#define LVDS_ENABLE IMX_GPIO_NR(1, 6) +#define BKL_ENABLE IMX_GPIO_NR(1, 7) + +static iomux_cfg_t board_gpios[] = { + SC_P_LVDS0_I2C0_SCL | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), + SC_P_LVDS0_I2C0_SDA | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), + SC_P_ESAI1_FST | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), +}; + +static void board_gpio_init(void) +{ + imx8_iomux_setup_multiple_pads(board_gpios, ARRAY_SIZE(board_gpios)); + + /* enable LVDS */ + gpio_request(LVDS_ENABLE, "lvds_enable"); + gpio_direction_output(LVDS_ENABLE, 1); + + /* enable backlight */ + gpio_request(BKL_ENABLE, "bkl_enable"); + gpio_direction_output(BKL_ENABLE, 1); + + /* ethernet reset */ + gpio_request(FEC0_RESET, "enet0_reset"); + gpio_direction_output(FEC0_RESET, 1); +} +#endif + +int checkboard(void) +{ + puts("Board: conga-QMX8\n"); + + build_info(); + print_bootinfo(); + + /* Note: After reloc, ipcHndl will no longer be valid. If handle + * returned by sc_ipc_open matches SC_IPC_CH, use this + * macro (valid after reloc) for subsequent SCI calls. + */ + /* + if (gd->arch.ipc_channel_handle != SC_IPC_CH) { + printf("\nSCI error! Invalid handle\n"); + } + */ + + return 0; +} + +int board_init(void) +{ + if (IS_ENABLED(CONFIG_XEN)) + return 0; + +#ifdef CONFIG_MXC_GPIO + board_gpio_init(); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + + return 0; +} + +void detail_board_ddr_info(void) +{ + puts("\nDDR "); +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ +/* + puts("SCI reboot request"); + sc_pm_reboot(SC_IPC_CH, SC_PM_RESET_TYPE_COLD); + while (1) + putc('.'); +*/ + /* TODO */ +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return 0; +} +#endif + +int board_mmc_get_env_dev(int devno) +{ + /* Use EMMC */ + if (IS_ENABLED(CONFIG_XEN)) + return 0; + + return devno; +} + +int mmc_map_to_kernel_blk(int dev_no) +{ + /* Use EMMC */ + if (IS_ENABLED(CONFIG_XEN)) + return 0; + + return dev_no; +} + +extern uint32_t _end_ofs; +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "QMX8"); + env_set("board_rev", "iMX8QM"); +#endif + + env_set("sec_boot", "no"); +#ifdef CONFIG_AHAB_BOOT + env_set("sec_boot", "yes"); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + +#ifdef IMX_LOAD_HDMI_FIMRWARE + char *end_of_uboot; + char command[256]; + + end_of_uboot = (char *)(ulong)(CONFIG_SYS_TEXT_BASE + _end_ofs + fdt_totalsize(gd->fdt_blob)); + end_of_uboot += 9; + + /* load hdmitxfw.bin and hdmirxfw.bin*/ + memcpy(IMX_HDMI_FIRMWARE_LOAD_ADDR, end_of_uboot, + IMX_HDMITX_FIRMWARE_SIZE + IMX_HDMIRX_FIRMWARE_SIZE); + + sprintf(command, "hdp load 0x%x", IMX_HDMI_FIRMWARE_LOAD_ADDR); + run_command(command, 0); + + sprintf(command, "hdprx load 0x%x", + IMX_HDMI_FIRMWARE_LOAD_ADDR + IMX_HDMITX_FIRMWARE_SIZE); + run_command(command, 0); +#endif + + return 0; +} + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) +{ + return 0; /*TODO*/ +} +#endif /*CONFIG_ANDROID_RECOVERY*/ +#endif /*CONFIG_FSL_FASTBOOT*/ + +/* Only Enable USB3 resources currently */ +int board_usb_init(int index, enum usb_init_type init) +{ + return 0; +} diff --git a/board/congatec/cgtqmx8/imximage.cfg b/board/congatec/cgtqmx8/imximage.cfg new file mode 100644 index 0000000000..e324c7ca37 --- /dev/null +++ b/board/congatec/cgtqmx8/imximage.cfg @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#define __ASSEMBLY__ + +/* Boot from SD, sector size 0x400 */ +BOOT_FROM SD 0x400 +/* SoC type IMX8QM */ +SOC_TYPE IMX8QM +/* Append seco container image */ +APPEND mx8qm-ahab-container.img +/* Create the 2nd container */ +CONTAINER +/* Add scfw image with exec attribute */ +IMAGE SCU mx8qm-val-scfw-tcm.bin +/* Add ATF image with exec attribute */ +IMAGE A35 bl31.bin 0x80000000 +/* Add U-Boot image with load attribute */ +DATA A35 u-boot-dtb.bin 0x80020000 diff --git a/board/congatec/cgtqmx8/spl.c b/board/congatec/cgtqmx8/spl.c new file mode 100644 index 0000000000..bdf9fee541 --- /dev/null +++ b/board/congatec/cgtqmx8/spl.c @@ -0,0 +1,77 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <init.h> +#include <log.h> +#include <spl.h> +#include <dm/uclass.h> +#include <dm/device.h> +#include <dm/uclass-internal.h> +#include <dm/device-internal.h> +#include <dm/lists.h> + +DECLARE_GLOBAL_DATA_PTR; + +void spl_board_init(void) +{ + struct udevice *dev; + int offset; + + uclass_find_first_device(UCLASS_MISC, &dev); + + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } + + offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "nxp,imx8-pd"); + while (offset != -FDT_ERR_NOTFOUND) { + lists_bind_fdt(gd->dm_root, offset_to_ofnode(offset), + NULL, true); + offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset, + "nxp,imx8-pd"); + } + + uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev); + + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } + + arch_cpu_init(); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + puts("Normal Boot\n"); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); +} diff --git a/board/congatec/common/Kconfig b/board/congatec/common/Kconfig new file mode 100644 index 0000000000..5c205bd830 --- /dev/null +++ b/board/congatec/common/Kconfig @@ -0,0 +1,48 @@ +if !ARCH_IMX8M && !ARCH_IMX8 + +config CHAIN_OF_TRUST + depends on !FIT_SIGNATURE && SECURE_BOOT + imply CMD_BLOB + imply CMD_HASH if ARM + select FSL_CAAM + select SPL_BOARD_INIT if (ARM && SPL) + select SHA_HW_ACCEL + select SHA_PROG_HW_ACCEL + select ENV_IS_NOWHERE + select CMD_EXT4 if ARM + select CMD_EXT4_WRITE if ARM + bool + default y + +config CMD_ESBC_VALIDATE + bool "Enable the 'esbc_validate' and 'esbc_halt' commands" + default y if CHAIN_OF_TRUST + help + This option enables two commands used for secure booting: + + esbc_validate - validate signature using RSA verification + esbc_halt - put the core in spin loop (Secure Boot Only) + +endif + +config VOL_MONITOR_LTC3882_READ + depends on VID + bool "Enable the LTC3882 voltage monitor read" + default n + help + This option enables LTC3882 voltage monitor read + functionality. It is used by common VID driver. + +config VOL_MONITOR_LTC3882_SET + depends on VID + bool "Enable the LTC3882 voltage monitor set" + default n + help + This option enables LTC3882 voltage monitor set + functionality. It is used by common VID driver. + +config USB_TCPC + bool "USB Typec port controller simple driver" + default n + help + Enable USB type-c port controller (TCPC) driver diff --git a/board/congatec/common/Makefile b/board/congatec/common/Makefile new file mode 100644 index 0000000000..d4ddfbf971 --- /dev/null +++ b/board/congatec/common/Makefile @@ -0,0 +1,23 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +MINIMAL= + +ifdef CONFIG_SPL_BUILD +ifdef CONFIG_SPL_INIT_MINIMAL +MINIMAL=y +endif +endif + +ifdef MINIMAL +# necessary to create built-in.o +obj- := __dummy__.o +else + +obj-y += mmc.o + +endif diff --git a/board/congatec/common/mmc.c b/board/congatec/common/mmc.c new file mode 100644 index 0000000000..6a61d0c19a --- /dev/null +++ b/board/congatec/common/mmc.c @@ -0,0 +1,52 @@ + /* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2018 NXP + * + */ +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <linux/errno.h> +#include <asm/io.h> +#include <env.h> +#include <command.h> +#include <stdbool.h> +#include <mmc.h> + +static int check_mmc_autodetect(void) +{ + char *autodetect_str = env_get("mmcautodetect"); + + if ((autodetect_str != NULL) && + (strcmp(autodetect_str, "yes") == 0)) { + return 1; + } + + return 0; +} + +/* This should be defined for each board */ +__weak int mmc_map_to_kernel_blk(int dev_no) +{ + return dev_no; +} + +void board_late_mmc_env_init(void) +{ + char cmd[32]; + char mmcblk[32]; + u32 dev_no = mmc_get_env_dev(); + + if (!check_mmc_autodetect()) + return; + + env_set_ulong("mmcdev", dev_no); + + /* Set mmcblk env */ + sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", + mmc_map_to_kernel_blk(dev_no)); + env_set("mmcroot", mmcblk); + + sprintf(cmd, "mmc dev %d", dev_no); + run_command(cmd, 0); +} diff --git a/configs/cgtqmx8_defconfig b/configs/cgtqmx8_defconfig new file mode 100644 index 0000000000..21c788cb98 --- /dev/null +++ b/configs/cgtqmx8_defconfig @@ -0,0 +1,86 @@ +CONFIG_ARM=y +CONFIG_SPL_SYS_ICACHE_OFF=y +CONFIG_SPL_SYS_DCACHE_OFF=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_CONGA_QMX8=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_SPL=y +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/congatec/cgtqmx8/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_IMX_BOOTAUX=y +CONFIG_LOG=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_HUSH_PARSER=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FUSE=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx8qm-cgtqmx8" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_DM_GPIO=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set +CONFIG_SYS_MMCSD_FS_BOOT_PARTITION=0 +CONFIG_SYS_MMC_ENV_PART=0 +CONFIG_SYS_MMC_ENV_DEV=1 diff --git a/doc/board/congatec/cgtqmx8.rst b/doc/board/congatec/cgtqmx8.rst new file mode 100644 index 0000000000..bccdef2f16 --- /dev/null +++ b/doc/board/congatec/cgtqmx8.rst @@ -0,0 +1,70 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for the Congatec conga-QMX8 board +======================================== + +Quick Start +----------- + +- Build the ARM Trusted firmware binary +- Get scfw_tcm.bin and ahab-container.img +- Get imx-mkimage +- Build U-Boot +- Build imx-mkimage +- Flash the binary into the SD card +- Boot + +Get and Build the ARM Trusted firmware +-------------------------------------- + +.. code-block:: bash + + $ git clone https://source.codeaurora.org/external/imx/imx-atf + $ cd imx-atf/ + $ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga + $ make PLAT=imx8qm bl31 + +Get scfw_tcm.bin and ahab-container.img +--------------------------------------- + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.1.bin + $ chmod +x imx-sc-firmware-1.1.bin + $ ./imx-sc-firmware-1.1.bin + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin + $ chmod +x firmware-imx-8.0.bin + $ ./firmware-imx-8.0.bin + +Or use this to avoid running random scripts from the internet, +but note that you must agree to the license the script displays: + +.. code-block:: bash + + $ dd if=imx-sc-firmware-1.1.bin of=imx-sc-firmware-1.1.tar.bz2 bs=37185 skip=1 + $ tar -xf imx-sc-firmware-1.1.tar.bz2 + $ cp imx-sc-firmware-1.1/mx8qx-val-scfw-tcm.bin $(builddir) + + $ dd if=firmware-imx-8.0.bin of=firmware-imx-8.0.tar.bz2 bs=37180 skip=1 + $ tar -xf firmware-imx-8.0.tar.bz2 + $ cp firmware-imx-8.0/firmware/seco/mx8qm-ahab-container.img $(builddir) + +Build U-Boot +------------ + +.. code-block:: bash + + $ export ATF_LOAD_ADDR=0x80000000 + $ export BL33_LOAD_ADDR=0x80020000 + $ make cgtqmx8_defconfig + $ make u-boot.bin + $ make flash.bin + +Flash the binary into the SD card +--------------------------------- + +Burn the flash.bin binary to SD card offset 32KB: + +.. code-block:: bash + + $ sudo dd if=flash.bin of=/dev/sd[x] bs=1k seek=32 conv=fsync diff --git a/doc/board/congatec/index.rst b/doc/board/congatec/index.rst new file mode 100644 index 0000000000..cc57b36b2e --- /dev/null +++ b/doc/board/congatec/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Congatec +======== + +.. toctree:: + :maxdepth: 2 + + cgtqmx8.rst diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h new file mode 100644 index 0000000000..0abafdbb51 --- /dev/null +++ b/include/configs/cgtqmx8.h @@ -0,0 +1,186 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017-2018 NXP + * Copyright 2018 congatec AG + * + */ + +#ifndef __CGTQMX8_H +#define __CGTQMX8_H + +#include <linux/sizes.h> +#include <asm/arch/imx-regs.h> + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_TEXT_BASE 0x0 +#define CONFIG_SPL_MAX_SIZE (124 * 1024) +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800 + +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x013E000 +#define CONFIG_SPL_BSS_START_ADDR 0x00128000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x00120000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */ +#define CONFIG_SERIAL_LPUART_BASE 0x5a060000 +#define CONFIG_MALLOC_F_ADDR 0x00120000 + +#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#define CONFIG_OF_EMBED +#endif + +#define CONFIG_REMAKE_ELF + +#define CONFIG_BOARD_EARLY_INIT_F + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_BOARD_SETUP + +#undef CONFIG_CMD_EXPORTENV +#undef CONFIG_CMD_IMPORTENV +#undef CONFIG_CMD_IMLS + +#undef CONFIG_CMD_CRC32 +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5B010000 +#define USDHC2_BASE_ADDR 0x5B020000 +#define USDHC3_BASE_ADDR 0x5B030000 +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +/* Boot M4 */ +#define M4_BOOT_ENV \ + "m4_0_image=m4_0.bin\0" \ + "m4_1_image=m4_1.bin\0" \ + "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \ + "loadm4image_1=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \ + "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ + "m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" \ + +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) " +#else +#define MFG_NAND_PARTITION "" +#endif +#define FEC0_RESET IMX_GPIO_NR(2, 5) +#define FEC0_PDOMAIN "conn_enet0" + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + MFG_NAND_PARTITION \ + "clk_ignore_unused "\ + "\0" \ + "initrd_addr=0x83800000\0" \ + "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + M4_BOOT_ENV \ + "script=boot.scr\0" \ + "image=Image\0" \ + "panel=NULL\0" \ + "console=ttyLP0\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "fdt_file=imx8qm-cgt-qmx8.dtb\0" \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} earlycon\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp rw earlycon\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x80280000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ +#define CONFIG_SYS_FSL_USDHC_NUM 3 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ +#define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */ + +/* Serial */ +#define CONFIG_BAUDRATE 115200 + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +/* Networking */ +#define CONFIG_FEC_MXC_PHYADDR -1 +#define CONFIG_FEC_XCV_TYPE RGMII +#define FEC_QUIRK_ENET_MAC + +#endif /* __CGTQMX8_H */ -- 2.17.1

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[PATCH] arm: mvebu: a38x: Configurable USB2 high-speed impedance threshold
by Joshua Scott 06 Nov '20

06 Nov '20

Hardware testing of a board using the Armada 385 has shown that an impedance threshold setting of 0x7 performs better in an eye-diagram test than with Marvell's recommended value 0x6. As other boards may still perform better with Marvell's reccomended value, a configuration option is added with a default value of 0x6. Signed-off-by: Joshua Scott <joshua.scott(a)alliedtelesis.co.nz> Cc: Stefan Roese <sr(a)denx.de.in> --- arch/arm/mach-mvebu/Kconfig | 5 +++++ arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c | 6 +++--- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 0d8e0922a2..bec011e584 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -30,6 +30,11 @@ config ARMADA_38X select ARMADA_32BIT select HAVE_MVEBU_EFUSE +config ARMADA_38X_HS_IMPEDANCE_THRESH + hex "Armada 38x USB 2.0 High-Speed Impedance Threshold (0x0 - 0x7)" + depends on ARMADA_38X + default 0x6 + config ARMADA_XP bool select ARMADA_32BIT diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c index 2454730e6d..ae2a361104 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c +++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c @@ -677,9 +677,9 @@ struct op_params usb2_power_up_params[] = { {0xc200c, 0x0 /*NA*/, 0xf000, {0x1000}, 0, 0}, {0xc400c, 0x0 /*NA*/, 0xf000, {0x1000}, 0, 0}, /* Change the High speed impedance threshold */ - {0xc0008, 0x0 /*NA*/, 0x700, {0x600}, 0, 0}, - {0xc2008, 0x0 /*NA*/, 0x700, {0x600}, 0, 0}, - {0xc4008, 0x0 /*NA*/, 0x700, {0x600}, 0, 0}, + {0xc0008, 0x0 /*NA*/, 0x700, {CONFIG_ARMADA_38X_HS_IMPEDANCE_THRESH << 8}, 0, 0}, + {0xc2008, 0x0 /*NA*/, 0x700, {CONFIG_ARMADA_38X_HS_IMPEDANCE_THRESH << 8}, 0, 0}, + {0xc4008, 0x0 /*NA*/, 0x700, {CONFIG_ARMADA_38X_HS_IMPEDANCE_THRESH << 8}, 0, 0}, /* Change the squelch level of the receiver to meet the receiver electrical measurements (squelch and receiver sensitivity tests) */ {0xc0014, 0x0 /*NA*/, 0xf, {0x8}, 0, 0}, {0xc2014, 0x0 /*NA*/, 0xf, {0x8}, 0, 0}, -- 2.29.2

2 1