November 2020 - U-Boot

[PATCH] fixup: x86: Add missing global_data declaration in tables
by Simon Glass 06 Nov '20

06 Nov '20

This file needs to use the global data pointer. Add the required declaration. This is a fixup patch for the following: 09218442ca7 x86: Allow putting some tables in the bloblist Signed-off-by: Simon Glass <sjg(a)chromium.org> --- arch/x86/lib/tables.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c index 8dc07868c1f..c4007fa4866 100644 --- a/arch/x86/lib/tables.c +++ b/arch/x86/lib/tables.c @@ -14,6 +14,8 @@ #include <asm/tables.h> #include <asm/coreboot_tables.h> +DECLARE_GLOBAL_DATA_PTR; + /** * Function prototype to write a specific configuration table * -- 2.29.1.341.ge80a0c044ae-goog

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[PATCH 1/2] doc: board: amlogic: Update support matrix
by Neil Armstrong 05 Nov '20

05 Nov '20

Update the matrix table with new supported features and new SoC features to support. Signed-off-by: Neil Armstrong <narmstrong(a)baylibre.com> --- doc/board/amlogic/index.rst | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/doc/board/amlogic/index.rst b/doc/board/amlogic/index.rst index 0e2f8c9aad..9e780ba47c 100644 --- a/doc/board/amlogic/index.rst +++ b/doc/board/amlogic/index.rst @@ -26,7 +26,7 @@ This matrix concerns the actual source code version. +-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ | Clock Control | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | +-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ -| PWM | No | No | No | No | No | No | No | +| PWM | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | +-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ | Reset Control | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | +-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ @@ -44,9 +44,9 @@ This matrix concerns the actual source code version. +-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ | I2C | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | +-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ -| USB | **Yes** | **Yes** | **Yes** | No | **Yes** | **Yes** | **Yes** | +| USB | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | +-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ -| USB OTG | No | **Yes** | **Yes** | No | **Yes** | **Yes** | **Yes** | +| USB OTG | No | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | +-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ | eMMC | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | +-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ @@ -66,6 +66,8 @@ This matrix concerns the actual source code version. +-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ | LCD/LVDS Output | No | *N/A* | No | No | No | No | No | +-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ +| MIPI DSI Output | *N/A* | *N/A* | *N/A* | No | No | No | No | ++-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ | SoC (version) information | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | +-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+ -- 2.25.1

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[PATCH] rockchip: Rock960: fix up USB support
by Peter Robinson 05 Nov '20

05 Nov '20

Fix up USB config options so keyboards and other USB devices work. --- configs/rock960-rk3399_defconfig | 9 ++++++--- include/configs/rock960_rk3399.h | 2 ++ 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 1d997847c2..a5a50785c5 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -3,12 +3,12 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_ROCKCHIP_RK3399=y -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 CONFIG_TARGET_ROCK960_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock960" CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" CONFIG_MISC_INIT_R=y CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -41,6 +41,8 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_DM_ETH=y CONFIG_NVME=y CONFIG_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y @@ -54,10 +56,11 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC3=y -CONFIG_ROCKCHIP_USB2_PHY=y +CONFIG_DM_KEYBOARD=y CONFIG_USB_KEYBOARD=y -CONFIG_USB_GADGET=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y diff --git a/include/configs/rock960_rk3399.h b/include/configs/rock960_rk3399.h index c6f9122154..2edad71028 100644 --- a/include/configs/rock960_rk3399.h +++ b/include/configs/rock960_rk3399.h @@ -15,4 +15,6 @@ #define SDRAM_BANK_SIZE (2UL << 30) +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #endif -- 2.26.2

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[PATCH 0/2] arm64: meson: add libretech cc v2 support
by Jerome Brunet 05 Nov '20

05 Nov '20

This patchset adds support for the Amlogic based libretech cc v2. Like the v1, this revised platform used the s905x SoC. Jerome Brunet (2): arm64: dts: import libretech-cc-v2 from linux v5.10-rc1 arm64: meson: add support for libretech-cc v2 arch/arm/dts/Makefile | 1 + ...eson-gxl-s905x-libretech-cc-v2-u-boot.dtsi | 7 + .../dts/meson-gxl-s905x-libretech-cc-v2.dts | 318 ++++++++++++++++++ configs/libretech-cc_v2_defconfig | 82 +++++ 4 files changed, 408 insertions(+) create mode 100644 arch/arm/dts/meson-gxl-s905x-libretech-cc-v2-u-boot.dtsi create mode 100644 arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts create mode 100644 configs/libretech-cc_v2_defconfig -- 2.28.0

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[PATCH v3 00/30] x86: Allow Coral to boot into Chrome OS
by Simon Glass 05 Nov '20

05 Nov '20

This series adds various minor features and tweaks to allow Coral to boot into Chrome OS from U-Boot. It relies on three other series which have been recently sent: - smbios (u-boot-dm/smbios-working) - bootm (u-boot-dm/bootm-working) - misca (u-boot-dm/misca-working) This should provide a solid base for using ACPI on other Intel Apollo Lake (APL) devices. Changes in v3: - Add a macro to read gd->acpi_ctx to allow use of IS_ENABLED() - Move the bloblist types into this patch - Avoid build error when gd->acpi_ctx is not available - Correct printf specifier for debug lines Changes in v2: - Rename update_fixed_mtrss() to update_fixed_mtrrs() - Add comments to enable_pm_timer_emulation() and cpu_mca_configure() - Convert spaces to tabs for consistency - Use log_err() to report error - Rename struct chromeos_acpi to struct chromeos_acpi_gnvs - Fix comment style - Define CONFIG_CHROMEOS_VBOOT in the Kconfig too - Correct a bisect build error - Drop patch "Store the FADT so we can avoid searching for it" - Drop patch "Move ROM_TABLE_ADDR into the C file" Simon Glass (30): Add an assembly guard around linux/bitops.h x86: apl: Add core init for the SoC x86: Add a layout for Chrome OS verified boot x86: Add support for private files x86: Allow writing tables to fail x86: acpi: Store the ACPI context in global_data x86: Don't bother clearing global NVS x86: coral: Drop the duplicate PCIe settings x86: Add SMBIOS info for Coral x86: coral: Correct max98357 file x86: Use if instead of #ifdef in write_tables() x86: Allow putting some tables in the bloblist x86: nhlt: Correct output of bytes and 16-bit data x86: nhlt: Fix a few bugs in the table generation x86: Show the interrupt pointer with 'irqinfo' x86: sound: Correct error handling acpi: Correct reset handling in acpi_device_add_power_res() x86: acpi: Allow the SSDT to be empty x86: acpi: Put the generated code first in DSDT acpi: Don't reset the tables with every new generation x86: Define the Chrome OS GNVS region x86: Use CONFIG_CHROMEOS_VBOOT for verified boot x86: Set up Chrome OS to boot into developer mode x86: Boot coral into Chrome OS by default x86: fsp: Convert fsp_dram to use log_debug() x86: Silence some logging statements x86: acpi: Include the TPMv1 table only if needed x86: acpi: Don't show the UART address by default x86: pinctrl: Silence the warning when a pin is not found x86: fsp: Adjust calculations for MTRR range and DRAM top arch/x86/cpu/apollolake/acpi.c | 25 ++++- arch/x86/cpu/apollolake/cpu.c | 84 +++++++++++++++++ arch/x86/cpu/apollolake/cpu_common.c | 25 +++++ arch/x86/cpu/apollolake/cpu_spl.c | 20 ---- arch/x86/cpu/apollolake/fsp_s.c | 8 +- arch/x86/cpu/cpu.c | 9 +- arch/x86/cpu/i386/interrupt.c | 14 +-- arch/x86/cpu/intel_common/acpi.c | 1 - arch/x86/cpu/intel_common/cpu.c | 19 ++++ arch/x86/cpu/intel_common/intel_opregion.c | 2 +- arch/x86/cpu/intel_common/itss.c | 8 +- arch/x86/dts/chromebook_coral.dts | 12 ++- arch/x86/dts/chromebook_samus.dts | 2 +- arch/x86/dts/u-boot.dtsi | 4 + arch/x86/include/asm/acpi/vbnv_layout.h | 38 ++++++++ arch/x86/include/asm/arch-apollolake/cpu.h | 14 +++ arch/x86/include/asm/cpu_common.h | 9 ++ arch/x86/include/asm/intel_gnvs.h | 54 ++++++++++- arch/x86/include/asm/interrupt.h | 17 ++++ arch/x86/include/asm/msr-index.h | 20 +++- arch/x86/include/asm/tables.h | 4 +- arch/x86/lib/acpi_nhlt.c | 19 +++- arch/x86/lib/acpi_table.c | 78 ++++++++++------ arch/x86/lib/fsp/fsp_dram.c | 35 ++++--- arch/x86/lib/fsp/fsp_graphics.c | 2 +- arch/x86/lib/fsp2/fsp_dram.c | 8 +- arch/x86/lib/interrupts.c | 3 + arch/x86/lib/tables.c | 86 +++++++++++++----- arch/x86/lib/tpl.c | 2 +- .../max98357-render-2ch-48khz-24b.dat | Bin 0 -> 116 bytes common/Kconfig.boot | 17 ++++ configs/chromebook_coral_defconfig | 11 ++- drivers/core/acpi.c | 10 +- drivers/pinctrl/intel/pinctrl.c | 2 +- drivers/sound/da7219.c | 4 +- drivers/sound/max98357a.c | 2 +- include/acpi/acpi_table.h | 10 ++ include/asm-generic/global_data.h | 13 +++ include/bloblist.h | 2 + include/configs/chromebook_coral.h | 9 +- include/dm/acpi.h | 9 ++ include/linux/bitops.h | 4 +- lib/Kconfig | 9 ++ lib/acpi/acpi_device.c | 2 +- lib/acpi/acpi_table.c | 4 +- test/dm/acpi.c | 4 + 46 files changed, 595 insertions(+), 139 deletions(-) create mode 100644 arch/x86/include/asm/acpi/vbnv_layout.h -- 2.29.1.341.ge80a0c044ae-goog

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[PATCH v5 00/13] x86: Updates to SMBIOS
by Simon Glass 05 Nov '20

05 Nov '20

At present there are a few Kconfig options which allow SMBIOS fields to be specified at build time. Not all fields are supported. Also, defining these at build-time is limiting since a factory system cannot insert values for particular boards or models without rebuilding U-Boot. This series adds a way to set SMBIOS properties using the devicetree. With this approach, more fields are supported and it is easy to update values in the devicetree in the factory. It also updates existing boards to use devicetree and drops the CONFIG options, using a new default sysinfo driver. Changes in v5: - Fix "sysinfo_gazerbeam" compatible string to use a hyphen - Add a note as to why the patch does not just rename some files - Fix up the example for the binding - Fix "manufactuer" typo - Fix "Informaiton" typo - Update commit message to explain why family does not have a default - Fix 'manuafacture' typo in commit message - Move the Kconfig comment into the devicetree - Rename smbios_add_prop_default() to smbios_add_prop() Changes in v4: - Fix build error with vexpress_ca9x4 Changes in v3: - Use a different binding with subnodes for each table type - Add onto the sysinfo binding Changes in v2: - Move dm.h header file to avoid build error on qemu-arm - Deal with boards that don't use of-control Simon Glass (13): board: Rename uclass to sysinfo doc: Add a binding for sysinfo x86: Pass an ofnode into each SMBIOS function smbios: Allow properties to come from the device tree smbios: Add more properties smbios: Add documentation and devicetree binding sysinfo: Provide a default driver to set SMBIOS values rockchip: Use devicetree for SMBIOS settings imx: Use devicetree for SMBIOS settings on MYiR MYS-6ULX odroid-c2: Use devicetree for SMBIOS settings arm64: mvebu: Use devicetree for SMBIOS settings on uDPU x86: galileo: Use devicetree for SMBIOS settings smbios: Drop the unused Kconfig options arch/arm/dts/armada-3720-uDPU-u-boot.dtsi | 20 +++ .../dts/imx6ull-myir-mys-6ulx-eval-u-boot.dts | 25 ++++ arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi | 23 ++++ arch/arm/dts/rk3328-roc-cc-u-boot.dtsi | 21 +++ arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi | 23 ++++ arch/arm/dts/rk3328-rock64-u-boot.dtsi | 21 +++ arch/arm/dts/rk3368-lion-u-boot.dtsi | 20 +++ arch/powerpc/dts/gdsys/gazerbeam-uboot.dtsi | 2 +- arch/sandbox/dts/test.dts | 8 +- arch/x86/dts/galileo.dts | 28 ++++ board/gdsys/common/cmd_ioloop.c | 12 +- board/gdsys/mpc8308/gazerbeam.c | 47 +++---- board/google/chromebook_coral/coral.c | 2 +- board/intel/galileo/Kconfig | 11 -- common/spl/spl_fit.c | 15 ++- configs/chromebook_coral_defconfig | 2 +- configs/clearfog_gt_8k_defconfig | 2 - configs/gazerbeam_defconfig | 4 +- configs/lion-rk3368_defconfig | 4 +- configs/mt7622_rfb_defconfig | 1 - configs/mvebu_db_armada8k_defconfig | 2 - configs/myir_mys_6ulx_defconfig | 3 +- configs/odroid-c2_defconfig | 4 +- configs/r8a774a1_beacon_defconfig | 2 - configs/r8a77970_eagle_defconfig | 2 - configs/r8a77980_condor_defconfig | 2 - configs/r8a77990_ebisu_defconfig | 2 - configs/r8a77995_draak_defconfig | 2 - configs/rcar3_salvator-x_defconfig | 2 - configs/rcar3_ulcb_defconfig | 2 - configs/roc-cc-rk3328_defconfig | 4 +- configs/rock-pi-e-rk3328_defconfig | 4 +- configs/rock64-rk3328_defconfig | 4 +- configs/sandbox64_defconfig | 4 +- configs/sandbox_defconfig | 4 +- configs/sandbox_flattree_defconfig | 4 +- configs/sandbox_spl_defconfig | 4 +- configs/uDPU_defconfig | 3 +- doc/arch/x86.rst | 8 ++ .../gdsys,sysinfo_gazerbeam.txt} | 8 +- doc/device-tree-bindings/sysinfo/smbios.txt | 77 +++++++++++ doc/device-tree-bindings/sysinfo/sysinfo.txt | 19 +++ drivers/Kconfig | 4 +- drivers/Makefile | 2 +- drivers/board/Kconfig | 25 ---- drivers/board/Makefile | 7 - drivers/board/board-uclass.c | 71 ----------- drivers/sysinfo/Kconfig | 33 +++++ drivers/sysinfo/Makefile | 8 ++ drivers/{board => sysinfo}/gazerbeam.c | 74 +++++------ drivers/{board => sysinfo}/gazerbeam.h | 0 drivers/{board => sysinfo}/sandbox.c | 50 ++++---- drivers/{board => sysinfo}/sandbox.h | 0 drivers/sysinfo/smbios.c | 24 ++++ drivers/sysinfo/sysinfo-uclass.c | 71 +++++++++++ drivers/timer/mpc83xx_timer.c | 10 +- include/dm/uclass-id.h | 2 +- include/smbios.h | 5 +- include/{board.h => sysinfo.h} | 80 ++++++------ lib/Kconfig | 17 +-- lib/smbios.c | 120 +++++++++++++----- test/dm/Makefile | 2 +- test/dm/board.c | 59 --------- test/dm/sysinfo.c | 59 +++++++++ 64 files changed, 761 insertions(+), 419 deletions(-) create mode 100644 arch/arm/dts/imx6ull-myir-mys-6ulx-eval-u-boot.dts rename doc/device-tree-bindings/{board/gdsys,board_gazerbeam.txt => sysinfo/gdsys,sysinfo_gazerbeam.txt} (90%) create mode 100644 doc/device-tree-bindings/sysinfo/smbios.txt create mode 100644 doc/device-tree-bindings/sysinfo/sysinfo.txt delete mode 100644 drivers/board/Kconfig delete mode 100644 drivers/board/Makefile delete mode 100644 drivers/board/board-uclass.c create mode 100644 drivers/sysinfo/Kconfig create mode 100644 drivers/sysinfo/Makefile rename drivers/{board => sysinfo}/gazerbeam.c (69%) rename drivers/{board => sysinfo}/gazerbeam.h (100%) rename drivers/{board => sysinfo}/sandbox.c (50%) rename drivers/{board => sysinfo}/sandbox.h (100%) create mode 100644 drivers/sysinfo/smbios.c create mode 100644 drivers/sysinfo/sysinfo-uclass.c rename include/{board.h => sysinfo.h} (65%) delete mode 100644 test/dm/board.c create mode 100644 test/dm/sysinfo.c -- 2.29.1.341.ge80a0c044ae-goog

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[RESEND,PATCH v2 0/1] RISC-V tracing support
by Pragnesh Patel 05 Nov '20

05 Nov '20

This series add a support of tracing for RISC-V arch. This series is also available here [1] for testing. [1] https://github.com/pragnesh26992/u-boot/tree/trace How to test this patch: 1) Enable tracing in "configs/sifive_fu540_defconfig" CONFIG_TRACE=y CONFIG_TRACE_BUFFER_SIZE=0x01000000 CONFIG_TRACE_CALL_DEPTH_LIMIT=15 CONFIG_CMD_TRACE=y 2) make FTRACE=1 sifive_fu540_defconfig 3) make FTRACE=1 Following are the boot messages on FU540 five cores SMP platform: U-Boot SPL 2021.01-rc1-00244-gc0ac5b69ea-dirty (Nov 05 2020 - 15:21:06 +0530) Trying to boot from MMC1 U-Boot 2021.01-rc1-00244-gc0ac5b69ea-dirty (Nov 05 2020 - 15:21:06 +0530) CPU: rv64imafdc Model: SiFive HiFive Unleashed A00 DRAM: 8 GiB trace: enabled MMC: spi@10050000:mmc@0: 0 *** Warning - bad CRC, using default environment In: serial@10010000 Out: serial@10010000 Err: serial@10010000 Board serial number should not be 0 !! Net: Error: ethernet@10090000 address not set. No ethernet found. Hit any key to stop autoboot: 0 => trace stats 178,556 function sites 9,378,800 function calls 1 untracked function calls 1,279,056 traced function calls (8070507 dropped due to overflow) 19 maximum observed call depth 15 call depth limit 9,568,845 calls not traced due to depth => trace calls 0x83000000 0xf00000 Call list dumped to 83000000, size 0xea33d0 => Pragnesh Patel (1): riscv: Add timer_get_us() for tracing drivers/timer/andes_plmt_timer.c | 16 +++++++++++++++- drivers/timer/riscv_timer.c | 14 +++++++++++++- drivers/timer/sifive_clint_timer.c | 16 +++++++++++++++- 3 files changed, 43 insertions(+), 3 deletions(-) -- 2.17.1

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[PATCH v2 0/1] RISC-V tracing support
by Pragnesh Patel 05 Nov '20

05 Nov '20

This series add a support of tracing for RISC-V arch. This series is also available here [1] for testing. [1] https://github.com/pragnesh26992/u-boot/tree/trace How to test this patch: 1) Enable tracing in "configs/sifive_fu540_defconfig" CONFIG_TRACE=y CONFIG_TRACE_BUFFER_SIZE=0x01000000 CONFIG_TRACE_CALL_DEPTH_LIMIT=15 CONFIG_CMD_TRACE=y 2) make FTRACE=1 sifive_fu540_defconfig 3) make FTRACE=1 Following are the boot messages on FU540 five cores SMP platform: U-Boot SPL 2021.01-rc1-00244-gc0ac5b69ea-dirty (Nov 05 2020 - 15:21:06 +0530) Trying to boot from MMC1 U-Boot 2021.01-rc1-00244-gc0ac5b69ea-dirty (Nov 05 2020 - 15:21:06 +0530) CPU: rv64imafdc Model: SiFive HiFive Unleashed A00 DRAM: 8 GiB trace: enabled MMC: spi@10050000:mmc@0: 0 *** Warning - bad CRC, using default environment In: serial@10010000 Out: serial@10010000 Err: serial@10010000 Board serial number should not be 0 !! Net: Error: ethernet@10090000 address not set. No ethernet found. Hit any key to stop autoboot: 0 => trace stats 178,556 function sites 9,378,800 function calls 1 untracked function calls 1,279,056 traced function calls (8070507 dropped due to overflow) 19 maximum observed call depth 15 call depth limit 9,568,845 calls not traced due to depth => trace calls 0x83000000 0xf00000 Call list dumped to 83000000, size 0xea33d0 => Pragnesh Patel (1): riscv: Add timer_get_us() for tracing drivers/timer/andes_plmt_timer.c | 14 ++++++++++++++ drivers/timer/riscv_timer.c | 14 +++++++++++++- drivers/timer/sifive_clint_timer.c | 16 +++++++++++++++- 3 files changed, 42 insertions(+), 2 deletions(-) -- 2.17.1

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[RESEND PATCH 0/3] pinctrl: renesas: trivial fixes and enhancements
by Lad Prabhakar 05 Nov '20

05 Nov '20

Hi All, This patch series includes trivial fixes and enhancements to renesas pfc driver. This is exactly the same series posted earlier [1]. [1] https://patchwork.ozlabs.org/project/uboot/list/?series=203651 Cheers, Prabhakar Lad Prabhakar (3): pinctrl: renesas: Drop unused members from struct sh_pfc_pinctrl pinctrl: renesas: Make sure the pin type is updated after setting the MUX pinctrl: renesas: Implement get_pin_muxing() callback drivers/pinctrl/renesas/pfc.c | 54 ++++++++++++++++++++++++++++++----- 1 file changed, 47 insertions(+), 7 deletions(-) -- 2.17.1

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[RFC] serial: pl01x: add sbsa-uart favor
by AKASHI Takahiro 05 Nov '20

05 Nov '20

sbsa-uart is a virtual UART device with a sub-set of PL011 functionality which is described in SBSA (Server Base System Architecture)[1]. It mainly targets for server use, but sbsa-uart itself is useful in any para-virtualized use cases, including Xen. At present, this patch is submitted as RFC because: * for some reason, data cache must be turned off (in initr_dcache()) * there is a prerequisite patch for Xen[2] The patch with xenguest_arm64_defconfig was tested on upstream Xen and qemu-arm64. (To work with xenguest_arm64_defconfig, minor and non-essential tweaks are needed.) The output looks like: U-Boot 2021.01-rc1-00005-g3b8e3cde5345 (Nov 04 2020 - 13:54:44 +0900) xenguest Xen virtual CPU Model: XENVM-4.15 DRAM: 128 MiB PVBLOCK: Failed to read device/vbd directory: ENOENT In: sbsa-pl011 Out: sbsa-pl011 Err: sbsa-pl011 xenguest# dm tree Class Index Probed Driver Name ----------------------------------------------------------- root 0 [ + ] root_driver root_driver firmware 0 [ ] psci |-- psci serial 0 [ + ] serial_pl01x |-- sbsa-pl011 pvblock 0 [ ] pvblock `-- pvblock [1] https://developer.arm.com/architectures/platform-design/server-systems [2] https://lists.xenproject.org/archives/html/xen-devel/2020-10/msg02122.html Signed-off-by: AKASHI Takahiro <takahiro.akashi(a)linaro.org> --- drivers/serial/Kconfig | 13 +++++++++++-- drivers/serial/serial_pl01x.c | 16 +++++++++++++--- include/dm/platform_data/serial_pl01x.h | 1 + 3 files changed, 25 insertions(+), 5 deletions(-) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index b4805a2e4ea4..fb570174c577 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -332,6 +332,15 @@ config DEBUG_UART_PL011 work. The driver will be available until the real driver model serial is running. +config DEBUG_UART_SBSA + bool "sbsa-uart" + depends on PL01X_SERIAL + help + Select this to enable a debug UART using the pl01x driver with the + SBSA_UART type. You will need to provide parameters to make this + work. The driver will be available until the real driver model + serial is running. + config DEBUG_UART_PIC32 bool "Microchip PIC32" depends on PIC32_SERIAL @@ -415,7 +424,7 @@ config DEBUG_UART_BASE config DEBUG_UART_CLOCK int "UART input clock" - depends on DEBUG_UART + depends on DEBUG_UART && !DEBUG_UART_SBSA default 0 if DEBUG_UART_SANDBOX help The UART input clock determines the speed of the internal UART @@ -427,7 +436,7 @@ config DEBUG_UART_CLOCK config DEBUG_UART_SHIFT int "UART register shift" - depends on DEBUG_UART + depends on DEBUG_UART && !DEBUG_UART_SBSA default 0 if DEBUG_UART help Some UARTs (notably ns16550) support different register layouts diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index 2772c25f1d2d..5ef4ae0c6a65 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -84,6 +84,8 @@ static int pl01x_generic_serial_init(struct pl01x_regs *regs, /* disable everything */ writel(0, &regs->pl011_cr); break; + case TYPE_SBSA_UART: + break; default: return -EINVAL; } @@ -146,7 +148,8 @@ static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type, writel(UART_PL010_CR_UARTEN, &regs->pl010_cr); break; } - case TYPE_PL011: { + case TYPE_PL011: + case TYPE_SBSA_UART: { unsigned int temp; unsigned int divider; unsigned int remainder; @@ -171,6 +174,9 @@ static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type, writel(fraction, &regs->pl011_fbrd); } + if (type == TYPE_SBSA_UART) + break; + pl011_set_line_control(regs); /* Finally, enable the UART */ writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | @@ -340,6 +346,7 @@ static const struct dm_serial_ops pl01x_serial_ops = { static const struct udevice_id pl01x_serial_id[] ={ {.compatible = "arm,pl011", .data = TYPE_PL011}, {.compatible = "arm,pl010", .data = TYPE_PL010}, + {.compatible = "arm,sbsa-uart", .data = TYPE_SBSA_UART}, {} }; @@ -386,7 +393,8 @@ U_BOOT_DRIVER(serial_pl01x) = { #endif -#if defined(CONFIG_DEBUG_UART_PL010) || defined(CONFIG_DEBUG_UART_PL011) +#if defined(CONFIG_DEBUG_UART_PL010) || defined(CONFIG_DEBUG_UART_PL011) || \ + defined(CONFIG_DEBUG_UART_SBSA) #include <debug_uart.h> @@ -395,7 +403,9 @@ static void _debug_uart_init(void) #ifndef CONFIG_DEBUG_UART_SKIP_INIT struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE; enum pl01x_type type = CONFIG_IS_ENABLED(DEBUG_UART_PL011) ? - TYPE_PL011 : TYPE_PL010; + TYPE_PL011 : + (CONFIG_IS_ENABLED(DEBUG_UART_PL010) ? + TYPE_PL010 : TYPE_SBSA_UART); pl01x_generic_serial_init(regs, type); pl01x_generic_setbrg(regs, type, diff --git a/include/dm/platform_data/serial_pl01x.h b/include/dm/platform_data/serial_pl01x.h index 77d96c49f03a..4bacbd512400 100644 --- a/include/dm/platform_data/serial_pl01x.h +++ b/include/dm/platform_data/serial_pl01x.h @@ -9,6 +9,7 @@ enum pl01x_type { TYPE_PL010, TYPE_PL011, + TYPE_SBSA_UART, }; /* -- 2.28.0

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