January 2020 - U-Boot

Pull request for UEFI sub-system for efi-2020-04-rc1
by Heinrich Schuchardt 09 Jan '20

09 Jan '20

The following changes since commit 5a8fa095cb848c60c630a83edf30d4fc46101e90: Merge branch 'next' (2020-01-06 17:07:49 -0500) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-efi.git tags/efi-2020-04-rc1 for you to fetch changes up to 7d6f16fbde9a03adc7d85b8809cb16dbc5e311f9: efi_selftest: unit test for EFI_RNG_PROTOCOL (2020-01-07 18:08:22 +0100) ---------------------------------------------------------------- Pull request for UEFI sub-system for efi-2020-04-rc1 This pull request provides: * support for FIT images for UEFI binaries * drivers for hardware random number generators * an implementation of the EFI_RNG_PROTOCOL * a sub-command for efidebug to display configuration tables ---------------------------------------------------------------- AKASHI Takahiro (1): include: pe.h: add signature-related definitions Cristian Ciocaltea (6): test/py: Fix broken 'notbuildconfigspec' marker image: Add IH_OS_EFI for EFI chain-load boot bootm: Add a bootm command for type IH_OS_EFI doc: Add sample uefi.its image description file doc: uefi.rst: Document launching UEFI binaries from FIT images test/py: Create a test for launching UEFI binaries from FIT images Heinrich Schuchardt (19): configs: qemu: enable FIT images on qemu_arm(64)_defconfig efi_loader: imply USB_KEYBOARD_FN_KEYS efi_loader: adjust file system info efi_loader: pass address to efi_install_fdt() efi_loader: use hardware device tree by default efi_loader: carve out efi_run_image() efi_loader: export efi_install_fdt() efi_loader: git ignore helloworld_efi.S test/py: describe env__efi_loader_helloworld_file efi_loader: clear screen should move cursor to home part: efi: comment for GPT_HEADER_SIGNATURE_UBOOT efi_loader: __cyg_profile_func_enter/_exit efi_loader: free load options after execution efi_loader: define all known warning status codes cmd: efidebug: simplify get_guid_text() cmd: efidebug: new sub-command tables cmd: efidebug: capitalize UEFI cmd: add rng command efi_selftest: unit test for EFI_RNG_PROTOCOL Sughosh Ganu (12): efi_selftest: Update .gitignore efi_loader: Add guidcpy function dm: rng: Add random number generator(rng) uclass clk: stm32mp1: Add a clock entry for RNG1 device stm32mp1: rng: Add a driver for random number generator(rng) device configs: stm32mp15: Enable random number generator(rng) device sandbox: rng: Add a random number generator(rng) driver configs: sandbox: Enable random number generator(rng) device test: rng: Add basic test for random number generator(rng) uclass virtio: rng: Add a random number generator(rng) driver efi: qemu: arm64: Add efi_rng_protocol implementation for the platform efi_rng_protocol: Install the efi_rng_protocol on the root node arch/sandbox/dts/test.dts | 4 + board/emulation/qemu-arm/qemu-arm.c | 42 ++++ cmd/Kconfig | 14 ++ cmd/Makefile | 1 + cmd/bootefi.c | 135 ++++++----- cmd/efidebug.c | 78 ++++-- cmd/rng.c | 56 +++++ common/bootm_os.c | 56 +++++ common/image-fit.c | 3 +- common/image.c | 1 + configs/qemu_arm64_defconfig | 5 + configs/qemu_arm_defconfig | 5 + configs/sandbox64_defconfig | 2 + configs/sandbox_defconfig | 2 + configs/stm32mp15_basic_defconfig | 2 + configs/stm32mp15_optee_defconfig | 2 + configs/stm32mp15_trusted_defconfig | 2 + doc/uImage.FIT/uefi.its | 67 ++++++ doc/uefi/uefi.rst | 34 +++ drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/clk/clk_stm32mp1.c | 1 + drivers/rng/Kconfig | 22 ++ drivers/rng/Makefile | 8 + drivers/rng/rng-uclass.c | 23 ++ drivers/rng/sandbox_rng.c | 56 +++++ drivers/rng/stm32mp1_rng.c | 160 +++++++++++++ drivers/virtio/Kconfig | 6 + drivers/virtio/Makefile | 1 + drivers/virtio/virtio-uclass.c | 1 + drivers/virtio/virtio_rng.c | 88 +++++++ include/dm/uclass-id.h | 1 + include/efi.h | 8 +- include/efi_loader.h | 16 ++ include/efi_rng.h | 32 +++ include/image.h | 1 + include/part_efi.h | 2 +- include/pe.h | 18 ++ include/rng.h | 33 +++ include/virtio.h | 4 +- lib/efi_loader/.gitignore | 1 + lib/efi_loader/Kconfig | 9 + lib/efi_loader/Makefile | 1 + lib/efi_loader/efi_boottime.c | 4 +- lib/efi_loader/efi_console.c | 16 +- lib/efi_loader/efi_file.c | 11 +- lib/efi_loader/efi_freestanding.c | 32 +++ lib/efi_loader/efi_rng.c | 114 +++++++++ lib/efi_loader/efi_root_node.c | 4 + lib/efi_selftest/.gitignore | 3 +- lib/efi_selftest/Makefile | 1 + lib/efi_selftest/efi_selftest_rng.c | 117 +++++++++ test/dm/Makefile | 1 + test/dm/rng.c | 26 ++ test/py/conftest.py | 2 +- test/py/tests/test_efi_fit.py | 458 ++++++++++++++++++++++++++++++++++++ test/py/tests/test_efi_loader.py | 7 +- 57 files changed, 1719 insertions(+), 83 deletions(-) create mode 100644 cmd/rng.c create mode 100644 doc/uImage.FIT/uefi.its create mode 100644 drivers/rng/Kconfig create mode 100644 drivers/rng/Makefile create mode 100644 drivers/rng/rng-uclass.c create mode 100644 drivers/rng/sandbox_rng.c create mode 100644 drivers/rng/stm32mp1_rng.c create mode 100644 drivers/virtio/virtio_rng.c create mode 100644 include/efi_rng.h create mode 100644 include/rng.h create mode 100644 lib/efi_loader/efi_rng.c create mode 100644 lib/efi_selftest/efi_selftest_rng.c create mode 100644 test/dm/rng.c create mode 100644 test/py/tests/test_efi_fit.py

2 1

[U-Boot] [PATCH v2 1/4] dm: spi: Return 0 if driver does not implement ops->cs_info
by Bin Meng 09 Jan '20

09 Jan '20

If an SPI controller driver does not implement ops->cs_info, that probably means any chip select number could be valid, hence let's return 0 for spi_cs_info(). Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> Reviewed-by: Jagan Teki <jagan(a)amarulasolutions.com> --- Changes in v2: - update spi-howto.rst to reflect the code changes doc/driver-model/spi-howto.rst | 4 ++-- drivers/spi/spi-uclass.c | 7 +++---- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/doc/driver-model/spi-howto.rst b/doc/driver-model/spi-howto.rst index a538fdc..7e64fae 100644 --- a/doc/driver-model/spi-howto.rst +++ b/doc/driver-model/spi-howto.rst @@ -634,8 +634,8 @@ method for cs_info() to deal with this. If you don't provide it, then the device tree will be used to determine what chip selects are valid. Return -ENODEV if the supplied chip select is invalid, or 0 if it is valid. -If you don't provide the cs_info() method, -ENODEV is assumed for all -chip selects that do not appear in the device tree. +If you don't provide the cs_info() method, 0 is assumed for all chip selects +that do not appear in the device tree. Test it diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index 88cb2a1..24de0b5 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -237,11 +237,10 @@ int spi_cs_info(struct udevice *bus, uint cs, struct spi_cs_info *info) return ops->cs_info(bus, cs, info); /* - * We could assume there is at least one valid chip select, but best - * to be sure and return an error in this case. The driver didn't - * care enough to tell us. + * We could assume there is at least one valid chip select. + * The driver didn't care enough to tell us. */ - return -ENODEV; + return 0; } int spi_find_bus_and_cs(int busnum, int cs, struct udevice **busp, -- 2.7.4

2 15

[PATCH] imx: dts: tbs2910: add u-boot dtsi to shrink image size
by Anatolij Gustschin 09 Jan '20

09 Jan '20

Use U-Boot specific board dtsi to remove some not used nodes and properties. With this change applied considerable size reduction has been observed: $ ./tools/buildman/buildman -b tbs2910 -f tbs2910 || \ ./tools/buildman/buildman -b tbs2910 -sS tbs2910 ... Summary of 2 commits for 1 boards (1 thread, 12 jobs per thread) 01: Merge branch '2019-12-05-master-imports' arm: w+ tbs2910 02: imx: dts: tbs2910: add u-boot dtsi to shrink image size arm: (for 1/1 boards) all -24448.0 text -24448.0 Signed-off-by: Anatolij Gustschin <agust(a)denx.de> --- This patch was only build-tested, maybe this removes to much and needs some tweaking. I'd appreciate if someone could test it on actual hardware and finish the work, so we hopefully can solve frequent CI build breakage caused by this target. arch/arm/dts/imx6q-tbs2910-u-boot.dtsi | 219 +++++++++++++++++++++++++ 1 file changed, 219 insertions(+) create mode 100644 arch/arm/dts/imx6q-tbs2910-u-boot.dtsi diff --git a/arch/arm/dts/imx6q-tbs2910-u-boot.dtsi b/arch/arm/dts/imx6q-tbs2910-u-boot.dtsi new file mode 100644 index 0000000000..3e9307f17f --- /dev/null +++ b/arch/arm/dts/imx6q-tbs2910-u-boot.dtsi @@ -0,0 +1,219 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot specific modifications for original tbs2910 DTS. + * This drops not used nodes/properties to reduce the image size. + */ + +/ { + /delete-property/ model; + /delete-property/ compatible; + + aliases { + /delete-property/ can0; + /delete-property/ can1; + /delete-property/ gpio3; + /delete-property/ gpio4; + /delete-property/ gpio5; + /delete-property/ ipu1; + /delete-property/ mmc3; + /delete-property/ spi0; + /delete-property/ spi1; + /delete-property/ spi2; + /delete-property/ spi3; + /delete-property/ spi4; + /delete-property/ serial2; + /delete-property/ serial3; + /delete-property/ serial4; + /delete-property/ video1; + }; + + /delete-node/ cpus; + /delete-node/ capture-subsystem; + /delete-node/ chosen; + /delete-node/ display-subsystem; + /delete-node/ fan; + /delete-node/ ir_recv; + /delete-node/ leds; + /delete-node/ memory; + /delete-node/ sound-sgtl5000; + /delete-node/ sound-spdif; + + soc { + u-boot,dm-pre-reloc; + /delete-property/ ranges; + /delete-node/ timer@a00600; + + aips-bus@2000000 { + /delete-property/ ranges; + /delete-node/ aipstz@207c000; + spba-bus@2000000 { + /delete-property/ ranges; + /delete-node/ spba@203c000; + }; + }; + + aips-bus@2100000 { + /delete-property/ ranges; + /delete-node/ aipstz@217c000; + /delete-node/ mlb@218c000; + /delete-node/ romcp@21ac000; + /delete-node/ tzasc@21d0000; + /delete-node/ tzasc@21d4000; + /delete-node/ vdoa@21e4000; + }; + }; +}; + +&anatop { + /delete-node/ regulator-1p1; + /delete-node/ regulator-2p5; + /delete-node/ regulator-3p0; + /delete-node/ regulator-vddcore; + /delete-node/ regulator-vddpu; + /delete-node/ regulator-vddsoc; +}; + +&sata { + /delete-property/ clocks; + /delete-property/ clock-names; + /delete-property/ interrupts; + /delete-property/ interrupts; + /delete-property/ fsl,transmit-level-mV; + /delete-property/ fsl,transmit-boost-mdB; + /delete-property/ fsl,transmit-atten-16ths; + /delete-property/ fsl,receive-eq-mdB; +}; + +&pcie { + /delete-property/ reg-names; + /delete-property/ device_type; + /delete-property/ bus-range; + /delete-property/ ranges; + /delete-property/ num-lanes; + /delete-property/ interrupts; + /delete-property/ interrupt-names; + /delete-property/ #interrupt-cells; + /delete-property/ interrupt-map-mask; + /delete-property/ interrupt-map; + /delete-property/ clocks; + /delete-property/ clock-names; +}; + +&uart1 { + /delete-property/ interrupts; + /delete-property/ clocks; + /delete-property/ clock-names; + /delete-property/ dmas; + /delete-property/ dma-names; +}; + +&uart2 { + /delete-property/ interrupts; + /delete-property/ clocks; + /delete-property/ clock-names; + /delete-property/ dmas; + /delete-property/ dma-names; +}; + +/delete-node/ &L2; +/delete-node/ &asrc; +/delete-node/ &audmux; +/delete-node/ &can1; +/delete-node/ &can2; +/delete-node/ &crypto; +/delete-node/ &dcic1; +/delete-node/ &dcic2; +/delete-node/ &dma_apbh; +/delete-node/ &ecspi1; +/delete-node/ &ecspi2; +/delete-node/ &ecspi3; +/delete-node/ &ecspi4; +/delete-node/ &ecspi5; +/delete-node/ &epit1; +/delete-node/ &epit2; +/delete-node/ &esai; +/delete-node/ &gpt; +/delete-node/ &gpio4; +/delete-node/ &gpio5; +/delete-node/ &gpio6; +/delete-node/ &gpu_3d; +/delete-node/ &gpu_2d; +/delete-node/ &gpu_vg; +/delete-node/ &gpmi; +/delete-node/ &ipu2; +/delete-node/ &kpp; +/delete-node/ &ldb; +/delete-node/ &mipi_csi; +/delete-node/ &mmdc0; +/delete-node/ &mmdc1; +/delete-node/ &ocotp; +/delete-node/ &ocram; +/delete-node/ &pinctrl_gpio_fan; +/delete-node/ &pinctrl_ir; +/delete-node/ &pinctrl_gpio_leds; +/delete-node/ &pinctrl_sgtl5000; +/delete-node/ &pinctrl_spdif; +/delete-node/ &pmu; +/delete-node/ &pwm1; +/delete-node/ &pwm2; +/delete-node/ &pwm3; +/delete-node/ &pwm4; +/delete-node/ &sdma; +/delete-node/ &reg_2p5v; +/delete-node/ &sgtl5000; +/delete-node/ &snvs; +/delete-node/ &spdif; +/delete-node/ &src; +/delete-node/ &ssi1; +/delete-node/ &ssi2; +/delete-node/ &ssi3; +/delete-node/ &tempmon; +/delete-node/ &uart3; +/delete-node/ &uart4; +/delete-node/ &uart5; +/delete-node/ &usbh2; +/delete-node/ &usbh3; +/delete-node/ &usdhc1; +/delete-node/ &vpu; +/delete-node/ &wdog2; +/delete-node/ &weim; + +&gpr { + /delete-node/ ipu1_csi0_mux; + /delete-node/ ipu2_csi1_mux; +}; + +&gpc { + /delete-node/ pgc; +}; + +&hdmi { + /delete-node/ port@2; + /delete-node/ port@3; +}; + +&mipi_dsi { + ports { + /delete-node/ port@2; + /delete-node/ port@3; + }; +}; + +&ipu1 { + u-boot,dm-pre-reloc; + /delete-property/ interrupts; + /delete-property/ clocks; + /delete-property/ clock-names; + /delete-property/ resets; + /delete-node/ port@0; + /delete-node/ port@1; + + port@2 { + /delete-node/ endpoint@3; + /delete-node/ endpoint@4; + }; + port@3 { + /delete-node/ endpoint@3; + /delete-node/ endpoint@4; + }; +}; -- 2.17.1

4 6

[PATCH v2] mtd: rawnand: denali_dt: make the core clock optional
by Masahiro Yamada 09 Jan '20

09 Jan '20

From: Masahiro Yamada Masahiro Yamada <yamada.masahiro(a)socionext.com> The "nand_x" and "ecc" clocks are currently optional. Make the core clock optional in the same way. This will allow platforms with no clock driver support to use this driver. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- V2: - Fix sof line drivers/mtd/nand/raw/denali_dt.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/raw/denali_dt.c b/drivers/mtd/nand/raw/denali_dt.c index 0ce81324b90e..b1e14982c443 100644 --- a/drivers/mtd/nand/raw/denali_dt.c +++ b/drivers/mtd/nand/raw/denali_dt.c @@ -91,7 +91,7 @@ static int denali_dt_probe(struct udevice *dev) if (ret) ret = clk_get_by_index(dev, 0, &clk); if (ret) - return ret; + clk.dev = NULL; ret = clk_get_by_name(dev, "nand_x", &clk_x); if (ret) @@ -101,9 +101,11 @@ static int denali_dt_probe(struct udevice *dev) if (ret) clk_ecc.dev = NULL; - ret = clk_enable(&clk); - if (ret) - return ret; + if (clk.dev) { + ret = clk_enable(&clk); + if (ret) + return ret; + } if (clk_x.dev) { ret = clk_enable(&clk_x); -- 2.17.1

1 0

[PATCH] mtd: rawnand: denali_dt: make the core clock optional
by Masahiro Yamada 09 Jan '20

09 Jan '20

From: Masahiro Yamada Masahiro Yamada <yamada.masahiro(a)socionext.com> The "nand_x" and "ecc" clocks are currently optional. Make the core clock optional in the same way. This will allow platforms with no clock driver support to use this driver. Signed-off-by: Masahiro Yamada Masahiro Yamada <yamada.masahiro(a)socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- drivers/mtd/nand/raw/denali_dt.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/raw/denali_dt.c b/drivers/mtd/nand/raw/denali_dt.c index 0ce81324b90e..b1e14982c443 100644 --- a/drivers/mtd/nand/raw/denali_dt.c +++ b/drivers/mtd/nand/raw/denali_dt.c @@ -91,7 +91,7 @@ static int denali_dt_probe(struct udevice *dev) if (ret) ret = clk_get_by_index(dev, 0, &clk); if (ret) - return ret; + clk.dev = NULL; ret = clk_get_by_name(dev, "nand_x", &clk_x); if (ret) @@ -101,9 +101,11 @@ static int denali_dt_probe(struct udevice *dev) if (ret) clk_ecc.dev = NULL; - ret = clk_enable(&clk); - if (ret) - return ret; + if (clk.dev) { + ret = clk_enable(&clk); + if (ret) + return ret; + } if (clk_x.dev) { ret = clk_enable(&clk_x); -- 2.17.1

1 0

[PATCH] ARM: socfpga: Drop last use of socfpga_reset_manager
by Marek Vasut 09 Jan '20

09 Jan '20

This particular chunk of code was not updated, likely due to the order in which the patches were posted and applied. Fix this missing part. Fixes: bb25aca13433 ("arm: socfpga: Convert reset manager from struct to defines") Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Chin Liang See <chin.liang.see(a)intel.com> Cc: Dalon Westergreen <dwesterg(a)gmail.com> Cc: Dinh Nguyen <dinguyen(a)kernel.org> Cc: Ley Foon Tan <ley.foon.tan(a)intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> Cc: Tien Fong Chee <tien.fong.chee(a)intel.com> --- arch/arm/mach-socfpga/spl_gen5.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index e19f55aa9b..3f513c3c48 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -137,10 +137,7 @@ void board_init_f(ulong dummy) debug("Reset init failed: %d\n", ret); #ifdef CONFIG_SPL_NAND_DENALI - struct socfpga_reset_manager *reset_manager_base = - (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS; - - clrbits_le32(&reset_manager_base->per_mod_reset, BIT(4)); + clrbits_le32(SOCFPGA_RSTMGR_ADDRESS + RSTMGR_GEN5_PERMODRST, BIT(4)); #endif /* enable console uart printing */ -- 2.24.1

2 1

[PATCH] cmd: tpm: add a subcommand device
by Philippe Reynes 09 Jan '20

09 Jan '20

The command tpm (and tpm2) search the tpm and use it. On sandbox, there are two tpm (tpm 1.x and tpm 2.0). So the command tpm and tpm2 are always executed with the first tpm (tpm 1.x), and the command tpm2 always fails. This add a subcommand device to command tpm and command tpm2. Then the command tpm and tpm2 use the device selected with the subcommand device. To be compatible with previous behaviour, if the subcommand device is not used before a tpm (or tpm2) command, the device 0 is selected. Signed-off-by: Philippe Reynes <philippe.reynes(a)softathome.com> --- cmd/tpm-common.c | 75 +++++++++++++++++++++++++++++++++++++++++++++++++--- cmd/tpm-user-utils.h | 1 + cmd/tpm-v1.c | 3 +++ cmd/tpm-v2.c | 3 +++ 4 files changed, 78 insertions(+), 4 deletions(-) diff --git a/cmd/tpm-common.c b/cmd/tpm-common.c index 38900fb..a99d438 100644 --- a/cmd/tpm-common.c +++ b/cmd/tpm-common.c @@ -12,6 +12,8 @@ #include <tpm-common.h> #include "tpm-user-utils.h" +static struct udevice *tpm_dev; + /** * Print a byte string in hexdecimal format, 16-bytes per line. * @@ -231,19 +233,84 @@ int type_string_write_vars(const char *type_str, u8 *data, return 0; } +static int tpm_show_device(void) +{ + struct udevice *dev; + char buf[80]; + int n = 0, rc; + + uclass_first_device(UCLASS_TPM, &dev); + while (dev) { + rc = tpm_get_desc(dev, buf, sizeof(buf)); + if (rc < 0) + printf("device %d: can't get info\n", n); + else + printf("device %d: %s\n", n, buf); + + uclass_next_device(&dev); + n++; + }; + + return 0; +} + +static int tpm_set_device(unsigned long num) +{ + struct udevice *dev; + unsigned long n = 0; + int rc = CMD_RET_FAILURE; + + uclass_first_device(UCLASS_TPM, &dev); + while (dev) { + if (n == num) { + tpm_dev = dev; + rc = 0; + break; + } + + uclass_next_device(&dev); + n++; + }; + + return rc; +} + int get_tpm(struct udevice **devp) { int rc; - rc = uclass_first_device_err(UCLASS_TPM, devp); - if (rc) { - printf("Could not find TPM (ret=%d)\n", rc); - return CMD_RET_FAILURE; + if (!tpm_dev) { + rc = tpm_set_device(0); + if (rc < 0) { + printf("Couldn't set TPM 0 (%d)\n", rc); + return CMD_RET_FAILURE; + } } + if (devp) + *devp = tpm_dev; + return 0; } +int do_tpm_device(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + unsigned long num; + int rc; + + if (argc == 2) { + num = simple_strtoul(argv[1], NULL, 10); + + rc = tpm_set_device(num); + if (rc < 0) + printf("Couldn't set TPM %lu (%d)\n", num, rc); + } else { + rc = tpm_show_device(); + } + + return rc; +} + int do_tpm_info(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { struct udevice *dev; diff --git a/cmd/tpm-user-utils.h b/cmd/tpm-user-utils.h index 8ce9861..a851d9c 100644 --- a/cmd/tpm-user-utils.h +++ b/cmd/tpm-user-utils.h @@ -17,6 +17,7 @@ int type_string_pack(const char *type_str, char * const values[], u8 *data); int type_string_write_vars(const char *type_str, u8 *data, char * const vars[]); int get_tpm(struct udevice **devp); +int do_tpm_device(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]); int do_tpm_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]); int do_tpm_info(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]); int do_tpm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); diff --git a/cmd/tpm-v1.c b/cmd/tpm-v1.c index 2807331..bc34e06 100644 --- a/cmd/tpm-v1.c +++ b/cmd/tpm-v1.c @@ -645,6 +645,7 @@ TPM_COMMAND_NO_ARG(tpm_physical_enable) TPM_COMMAND_NO_ARG(tpm_physical_disable) static cmd_tbl_t tpm1_commands[] = { + U_BOOT_CMD_MKENT(device, 0, 1, do_tpm_device, "", ""), U_BOOT_CMD_MKENT(info, 0, 1, do_tpm_info, "", ""), U_BOOT_CMD_MKENT(init, 0, 1, do_tpm_init, "", ""), U_BOOT_CMD_MKENT(startup, 0, 1, @@ -721,6 +722,8 @@ U_BOOT_CMD(tpm, CONFIG_SYS_MAXARGS, 1, do_tpm, "cmd args...\n" " - Issue TPM command <cmd> with arguments <args...>.\n" "Admin Startup and State Commands:\n" +" device [num device]\n" +" - Show all devices or set the specified device\n" " info - Show information about the TPM\n" " init\n" " - Put TPM into a state where it waits for 'startup' command.\n" diff --git a/cmd/tpm-v2.c b/cmd/tpm-v2.c index 459a955..0cd3982 100644 --- a/cmd/tpm-v2.c +++ b/cmd/tpm-v2.c @@ -354,6 +354,7 @@ static int do_tpm_pcr_setauthvalue(cmd_tbl_t *cmdtp, int flag, } static cmd_tbl_t tpm2_commands[] = { + U_BOOT_CMD_MKENT(device, 0, 1, do_tpm_device, "", ""), U_BOOT_CMD_MKENT(info, 0, 1, do_tpm_info, "", ""), U_BOOT_CMD_MKENT(init, 0, 1, do_tpm_init, "", ""), U_BOOT_CMD_MKENT(startup, 0, 1, do_tpm2_startup, "", ""), @@ -381,6 +382,8 @@ cmd_tbl_t *get_tpm2_commands(unsigned int *size) U_BOOT_CMD(tpm2, CONFIG_SYS_MAXARGS, 1, do_tpm, "Issue a TPMv2.x command", "<command> [<arguments>]\n" "\n" +"device [num device]\n" +" Show all devices or set the specified device\n" "info\n" " Show information about the TPM.\n" "init\n" -- 2.7.4

2 1

[PATCH] arm64: zynqmp: Add support for zcu1285 revA board
by Michal Simek 09 Jan '20

09 Jan '20

zcu1285 is the same as zcu1275 but it is using Avnet FMC http://www.ultrazed.org/product/network-fmc-module Unfortunately not everything is connected now that's why this is only describing system which Xilinx is using. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/zynqmp-zcu1285-revA.dts | 245 +++++++++++++++++++++++++++ configs/xilinx_zynqmp_virt_defconfig | 2 +- 3 files changed, 247 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/zynqmp-zcu1285-revA.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a82ba0da9abe..e30186de493b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -281,6 +281,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-zcu111-revA.dtb \ zynqmp-zcu1275-revA.dtb \ zynqmp-zcu1275-revB.dtb \ + zynqmp-zcu1285-revA.dtb \ zynqmp-zcu208-revA.dtb \ zynqmp-zcu216-revA.dtb \ zynqmp-zc1232-revA.dtb \ diff --git a/arch/arm/dts/zynqmp-zcu1285-revA.dts b/arch/arm/dts/zynqmp-zcu1285-revA.dts new file mode 100644 index 000000000000..9c1801313889 --- /dev/null +++ b/arch/arm/dts/zynqmp-zcu1285-revA.dts @@ -0,0 +1,245 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP ZCU1285 RevA + * + * (C) Copyright 2018 - 2019, Xilinx, Inc. + * + * Michal Simek <michal.simek(a)xilinx.com> + * Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" + +/ { + model = "ZynqMP ZCU1285 RevA"; + compatible = "xlnx,zynqmp-zcu1285-revA", "xlnx,zynqmp-zcu1285", + "xlnx,zynqmp"; + + aliases { + serial0 = &uart0; + serial1 = &dcc; + spi0 = &qspi; + mmc0 = &sdhci1; + i2c = &i2c0; /* EMIO */ + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + ina226-u60 { + compatible = "iio-hwmon"; + io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>; + }; + ina226-u61 { + compatible = "iio-hwmon"; + io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>; + }; + ina226-u63 { + compatible = "iio-hwmon"; + io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>; + }; + ina226-u65 { + compatible = "iio-hwmon"; + io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; + }; + ina226-u64 { + compatible = "iio-hwmon"; + io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>; + }; +}; + +&dcc { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + i2c-mux@75 { + compatible = "nxp,pca9548"; /* u22 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* PMBUS */ + max20751@74 { /* u23 */ + compatible = "maxim,max20751"; + reg = <0x74>; + }; + max20751@70 { /* u89 */ + compatible = "maxim,max20751"; + reg = <0x70>; + }; + max15301@a { /* u28 */ + compatible = "maxim,max15301"; + reg = <0xa>; + }; + max15303@b { /* u48 */ + compatible = "maxim,max15303"; + reg = <0xb>; + }; + max15303@d { /* u27 */ + compatible = "maxim,max15303"; + reg = <0xd>; + }; + max15303@e { /* u11 */ + compatible = "maxim,max15303"; + reg = <0xe>; + }; + max15303@f { /* u96 */ + compatible = "maxim,max15303"; + reg = <0xf>; + }; + max15303@11 { /* u47 */ + compatible = "maxim,max15303"; + reg = <0x11>; + }; + max15303@12 { /* u24 */ + compatible = "maxim,max15303"; + reg = <0x12>; + }; + max15301@13 { /* u29 */ + compatible = "maxim,max15301"; + reg = <0x13>; + }; + max15303@14 { /* u51 */ + compatible = "maxim,max15303"; + reg = <0x14>; + }; + max15303@15 { /* u30 */ + compatible = "maxim,max15303"; + reg = <0x15>; + }; + max15303@16 { /* u102 */ + compatible = "maxim,max15303"; + reg = <0x16>; + }; + max15301@17 { /* u50 */ + compatible = "maxim,max15301"; + reg = <0x17>; + }; + max15301@18 { /* u31 */ + compatible = "maxim,max15301"; + reg = <0x18>; + }; + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* CM_I2C */ + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* SYS_EEPROM */ + eeprom: eeprom@54 { /* u101 */ + compatible = "atmel,24c32"; /* 24LC32A */ + reg = <0x54>; + }; + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* FMC1 */ + }; + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + /* FMC2 */ + }; + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + /* ANALOG_PMBUS */ + u60: ina226@40 { /* u60 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u60"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + u61: ina226@41 { /* u61 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u61"; + reg = <0x41>; + shunt-resistor = <1000>; + }; + u63: ina226@42 { /* u63 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u63"; + reg = <0x42>; + shunt-resistor = <1000>; + }; + u65: ina226@43 { /* u65 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u65"; + reg = <0x43>; + shunt-resistor = <1000>; + }; + u64: ina226@44 { /* u64 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u64"; + reg = <0x44>; + shunt-resistor = <1000>; + }; + }; + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* ANALOG_CM_I2C */ + }; + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + /* FMC3 */ + }; + }; +}; + +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + }; +}; + +&uart0 { + status = "okay"; +}; + +&sdhci1 { + status = "okay"; + xlnx,mio_bank = <1>; +}; diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 7e0fcf15c4f5..2327eeee4acf 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -46,7 +46,7 @@ CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu100-revC" -CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu208-revA zynqmp-zcu216-revA" +CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y -- 2.24.0

1 0

[PATCH] armv8: ls1028a_serdes: add 7777, 9999, 899b to the list of serdes protocols
by Alex Marginean 09 Jan '20

09 Jan '20

These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c index 313f3f1e8a..e2aaa23f69 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c @@ -35,6 +35,9 @@ static struct serdes_config serdes1_cfg_tbl[] = { {0xEB58, {SGMII_T1, QSGMII_B, PCIE2, SATA1} }, {0xEB8B, {PCIE1, SGMII_T1, PCIE2, SATA1} }, {0xE8CC, {PCIE1, PCIE1, SGMII_T1, SATA1} }, + {0x7777, {SGMII1, SGMII2, SGMII3, SGMII4} }, + {0x9999, {SGMII1, SGMII2, SGMII3, SGMII4} }, + {0xb998, {SGMII_T1, SGMII2, SGMII3, PCIE1} }, {} }; -- 2.17.1

1 0

[PATCH v2 1/2] Add GigaDevice gd25q128 128Mbit chip to spi-nor id table.
by Mauro Condarelli 09 Jan '20

09 Jan '20

From: MCon <mc5686(a)mclink.it> Tested on VoCore2 Signed-off-by: MCon <mc5686(a)mclink.it> Signed-off-by: Mauro Condarelli <mc5686(a)mclink.it> --- Changes in v2: None drivers/mtd/spi/spi-nor-ids.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index d3b84574ac..973b6f86c9 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -107,6 +107,11 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { + INFO("gd25q128", 0xc84018, 0, 64 * 1024, 256, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, { INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | -- 2.24.1

4 9