January 2020 - U-Boot

[PATCH v2 00/10] ARM: clearfog: add run-time board detect
by Baruch Siach 21 Jan '20

21 Jan '20

Newer revisions of SolidRun Clearfog Base/Pro carriers and Armada 388 SOM add EEPROM storage for board detection. This patch series adds support for reading EEPROM stored board information, and using it to set RAM training parameters, serdes configuration, and kernel DT selection. The information is stored in EEPROM in TLV format defined for the ONIE project. https://opencomputeproject.github.io/onie/design-spec/hw_requirements.html This series add the sys_eeprom command from ONIE carried U-Boot patch, with a number for changes as described in the patch log. The TLV format is unchanged. This series also adds support for the newly introduced single board, Aramda 385 based Clearfog GTR system. RAM configuration on that system requires both Armada 38x DDR clocks to be enabled. The first patch in this series adds the necessary code to allow per-board selection of DDR clock. Changes in v2: * Fix checkpatch issues in TLV EEPROM code * Make TLV EEPROM API independent of static storage for compatibility with pre-relocation code * Rename sys_eeprom to less generic tlv_eeprom throughout the code * Drop typedefs * Move board level TLV parse code to the common/ sub-directory for easier reuse in other SolidRun platforms * Integrate fixes from Joel Johnson: add missing u-boot/crc.h include; select SPL_DRIVERS_MISC_SUPPORT; fix build with CMD_TLV_EEPROM unset * Add review tags from Stefan Roese Baruch Siach (10): ddr: marvell: a38x: allow board specific clock out setup arm: mvebu: clearfog: enable both DDR clocks cmd: add tlv_eeprom command ARM: mvebu: clearfog: add EEPROM devices ARM: mvebu: clearfog: add support for EEPROM TLV info ARM: mvebu: clearfog: read basic TLV data ARM: mvebu: clearfog: print TLV stored product name ARM: mvebu: clearfog: run-time selection of DT file ARM: mvebu: clearfog: add Clearfog GTR support ARM: mvebu: clearfog: add Clearfog Base serdes configuration arch/arm/dts/armada-388-clearfog-u-boot.dtsi | 12 + arch/arm/dts/armada-388-clearfog.dts | 6 + .../arm/dts/armada-38x-solidrun-microsom.dtsi | 8 + arch/arm/mach-mvebu/Kconfig | 1 + board/solidrun/clearfog/clearfog.c | 72 +- board/solidrun/common/Makefile | 5 + board/solidrun/common/tlv_data.c | 102 ++ board/solidrun/common/tlv_data.h | 18 + cmd/Kconfig | 14 + cmd/Makefile | 2 + cmd/tlv_eeprom.c | 1105 +++++++++++++++++ configs/clearfog_defconfig | 4 + drivers/ddr/marvell/a38x/ddr3_training.c | 10 +- drivers/ddr/marvell/a38x/ddr_topology_def.h | 3 + include/tlv_eeprom.h | 164 +++ 15 files changed, 1522 insertions(+), 4 deletions(-) create mode 100644 board/solidrun/common/Makefile create mode 100644 board/solidrun/common/tlv_data.c create mode 100644 board/solidrun/common/tlv_data.h create mode 100644 cmd/tlv_eeprom.c create mode 100644 include/tlv_eeprom.h -- 2.24.1

2 14

[PATCH RESEND] ARM: imx: mx6ull: Add iMX6ULL VisionSOM SoM and EVK
by Marek Vasut 21 Jan '20

21 Jan '20

From: Arkadiusz Karas <arkadiusz.karas(a)somlabs.com> Add iMX6ULL VisionSOM SoM and VisionCB-RT-STD evaluation board support. The SoM has an iMX6ULL, 512 MiB of DRAM and microSD slot. The carrier board has Ethernet, USB host port, USB OTG port. Signed-off-by: Arkadiusz Karas <arkadiusz.karas(a)somlabs.com> Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Stefano Babic <sbabic(a)denx.de> --- NOTE: There are other variants and options of the VisionSOM available: - iMX6UL instead of iMX6ULL - NAND can be populated (optional, easy to add support for) - eMMC can be populated (optional, easy to add support for) --- arch/arm/dts/Makefile | 1 + arch/arm/dts/imx6ull-somlabs-visionsom.dts | 276 ++++++++++++++++++ arch/arm/mach-imx/mx6/Kconfig | 13 + board/somlabs/visionsom-6ull/Kconfig | 12 + board/somlabs/visionsom-6ull/MAINTAINERS | 6 + board/somlabs/visionsom-6ull/Makefile | 4 + board/somlabs/visionsom-6ull/imximage.cfg | 107 +++++++ board/somlabs/visionsom-6ull/visionsom-6ull.c | 146 +++++++++ configs/somlabs_visionsom_6ull_defconfig | 49 ++++ include/configs/somlabs_visionsom_6ull.h | 116 ++++++++ 10 files changed, 730 insertions(+) create mode 100644 arch/arm/dts/imx6ull-somlabs-visionsom.dts create mode 100644 board/somlabs/visionsom-6ull/Kconfig create mode 100644 board/somlabs/visionsom-6ull/MAINTAINERS create mode 100644 board/somlabs/visionsom-6ull/Makefile create mode 100644 board/somlabs/visionsom-6ull/imximage.cfg create mode 100644 board/somlabs/visionsom-6ull/visionsom-6ull.c create mode 100644 configs/somlabs_visionsom_6ull_defconfig create mode 100644 include/configs/somlabs_visionsom_6ull.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 04a8cccda5..b2f127d398 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -676,6 +676,7 @@ dtb-$(CONFIG_MX6ULL) += \ imx6ull-colibri.dtb \ imx6ull-phytec-segin-ff-rdk-emmc.dtb \ imx6ull-dart-6ul.dtb \ + imx6ull-somlabs-visionsom.dtb \ imx6ulz-14x14-evk.dtb dtb-$(CONFIG_ARCH_MX6) += \ diff --git a/arch/arm/dts/imx6ull-somlabs-visionsom.dts b/arch/arm/dts/imx6ull-somlabs-visionsom.dts new file mode 100644 index 0000000000..868f3f8440 --- /dev/null +++ b/arch/arm/dts/imx6ull-somlabs-visionsom.dts @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017-2019 SoMLabs + * Copyright (C) 2016 Freescale Semiconductor, Inc. + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include "imx6ull.dtsi" + +/ { + model = "SoMLabs VisionSOM-6ULL"; + compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull"; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x20000000>; + }; + + leds { + compatible = "gpio-leds"; + + usr0 { + label = "usr0"; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + usr1 { + label = "usr1"; + gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + }; + + usr2 { + label = "usr2"; + gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + }; + + usr3 { + label = "usr3"; + gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg2>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio2 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + }; +}; + +&cpu0 { + arm-supply = <&reg_arm>; + soc-supply = <&reg_soc>; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <&ethphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; + +}; + +&gpc { + fsl,cpu_pupscr_sw2iso = <0x1>; + fsl,cpu_pupscr_sw = <0x0>; + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; + fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */ +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + +}; + +&i2c2 { + clock_frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + /* 32kHz low power reference clock for WiFi */ + MX6UL_PAD_JTAG_TCK__OSC32K_32K_OUT 0x17099 + /* LED 0..3 */ + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x17099 + MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x17099 + MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x17099 + MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x17099 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1F829 + + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x400010a9 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY 0x30b0 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x10b0 + >; + }; + + pinctrl_usb_otg2: usbotg2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x10b0 + >; + }; +}; + +&tsc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc>; + xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + measure-delay-time = <0xffff>; + pre-charge-time = <0xfff>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <&reg_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <&reg_usb_otg2_vbus>; + dr_mode = "host"; + status = "okay"; +}; + +&usbphy1 { + tx-d-cal = <0x5>; +}; + +&usbphy2 { + tx-d-cal = <0x5>; +}; + +&usdhc2 { + non-removable; + disable-wp; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,wdog_b; +}; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index f1a1021f10..9d91f9ab44 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -540,6 +540,18 @@ config TARGET_SKSIMX6 bool "sks-imx6" select SUPPORT_SPL +config TARGET_SOMLABS_VISIONSOM_6ULL + bool "visionsom-6ull" + select MX6ULL + select BOARD_LATE_INIT + select DM + select DM_ETH + select DM_GPIO + select DM_MMC + select DM_SERIAL + select DM_THERMAL + imply CMD_DM + config TARGET_TBS2910 bool "TBS2910 Matrix ARM mini PC" @@ -694,6 +706,7 @@ source "board/logicpd/imx6/Kconfig" source "board/seco/Kconfig" source "board/sks-kinkel/sksimx6/Kconfig" source "board/solidrun/mx6cuboxi/Kconfig" +source "board/somlabs/visionsom-6ull/Kconfig" source "board/technexion/pico-imx6/Kconfig" source "board/technexion/pico-imx6ul/Kconfig" source "board/tbs/tbs2910/Kconfig" diff --git a/board/somlabs/visionsom-6ull/Kconfig b/board/somlabs/visionsom-6ull/Kconfig new file mode 100644 index 0000000000..37408aa798 --- /dev/null +++ b/board/somlabs/visionsom-6ull/Kconfig @@ -0,0 +1,12 @@ +if TARGET_SOMLABS_VISIONSOM_6ULL + +config SYS_BOARD + default "visionsom-6ull" + +config SYS_VENDOR + default "somlabs" + +config SYS_CONFIG_NAME + default "somlabs_visionsom_6ull" + +endif diff --git a/board/somlabs/visionsom-6ull/MAINTAINERS b/board/somlabs/visionsom-6ull/MAINTAINERS new file mode 100644 index 0000000000..905c000bc4 --- /dev/null +++ b/board/somlabs/visionsom-6ull/MAINTAINERS @@ -0,0 +1,6 @@ +VISIONSOM-6ULL BOARD +M: Arkadiusz Karas <arkadiusz.karas(a)somlabs.com> +S: Maintained +F: board/somlabs/visionsom-6ull/ +F: include/configs/somlabs_visionsom_6ull.h +F: configs/somlabs_visionsom_6ull_defconfig diff --git a/board/somlabs/visionsom-6ull/Makefile b/board/somlabs/visionsom-6ull/Makefile new file mode 100644 index 0000000000..9c3768aa45 --- /dev/null +++ b/board/somlabs/visionsom-6ull/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ +# (C) Copyright 2019 Arkadiusz Karas <arkadiusz.karas(a)somlabs.com> + +obj-y := visionsom-6ull.o diff --git a/board/somlabs/visionsom-6ull/imximage.cfg b/board/somlabs/visionsom-6ull/imximage.cfg new file mode 100644 index 0000000000..b49a2df6dd --- /dev/null +++ b/board/somlabs/visionsom-6ull/imximage.cfg @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 A. Karas + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include <config.h> + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : sd + */ + +BOOT_FROM sd + +/* + * Secure boot support + */ +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Micron MT41K256M16TW-107 */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +DATA 4 0x020E04B4 0x000C0000 +DATA 4 0x020E04AC 0x00000000 +DATA 4 0x020E027C 0x00000030 +DATA 4 0x020E0250 0x00000030 +DATA 4 0x020E024C 0x00000030 +DATA 4 0x020E0490 0x00000030 +DATA 4 0x020E0288 0x00000030 +DATA 4 0x020E0270 0x00000000 +DATA 4 0x020E0260 0x00000030 +DATA 4 0x020E0264 0x00000030 +DATA 4 0x020E04A0 0x00000030 +DATA 4 0x020E0494 0x00020000 +DATA 4 0x020E0280 0x00000030 +DATA 4 0x020E0284 0x00000030 +DATA 4 0x020E04B0 0x00020000 +DATA 4 0x020E0498 0x00000030 +DATA 4 0x020E04A4 0x00000030 +DATA 4 0x020E0244 0x00000030 +DATA 4 0x020E0248 0x00000030 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B080C 0x00000000 +DATA 4 0x021B083C 0x41570155 +DATA 4 0x021B0848 0x4040474A +DATA 4 0x021B0850 0x40405550 +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B08C0 0x00921012 +DATA 4 0x021B08b8 0x00000800 +DATA 4 0x021B0004 0x0002002D +DATA 4 0x021B0008 0x1B333030 +DATA 4 0x021B000C 0x676B52F3 +DATA 4 0x021B0010 0xB66D0B63 +DATA 4 0x021B0014 0x01FF00DB +DATA 4 0x021B0018 0x00201740 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B002C 0x000026D2 +DATA 4 0x021B0030 0x006B1023 +DATA 4 0x021B0040 0x0000004F +DATA 4 0x021B0000 0x84180000 +DATA 4 0x021B0890 0x23400A38 +DATA 4 0x021B001C 0x02008032 +DATA 4 0x021B001C 0x00008033 +DATA 4 0x021B001C 0x00048031 +DATA 4 0x021B001C 0x15208030 +DATA 4 0x021B001C 0x04008040 +DATA 4 0x021B0020 0x00000800 +DATA 4 0x021B0818 0x00000227 +DATA 4 0x021B0004 0x0002552D +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 diff --git a/board/somlabs/visionsom-6ull/visionsom-6ull.c b/board/somlabs/visionsom-6ull/visionsom-6ull.c new file mode 100644 index 0000000000..bc7257be40 --- /dev/null +++ b/board/somlabs/visionsom-6ull/visionsom-6ull.c @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017-2019 A. Karas, SomLabs + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + */ + +#include <init.h> +#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <asm/io.h> +#include <common.h> +#include <env.h> +#include <fsl_esdhc_imx.h> +#include <i2c.h> +#include <miiphy.h> +#include <linux/sizes.h> +#include <mmc.h> +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +#ifdef CONFIG_FEC_MXC +static int setup_fec(void) +{ + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + int ret; + + /* + * Use 50M anatop loopback REF_CLK1 for ENET1, + * clear gpr1[13], set gpr1[17]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + + ret = enable_fec_anatop_clock(0, ENET_50MHZ); + if (ret) + return ret; + + enable_enet_clk(1); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int mmc_map_to_kernel_blk(int devno) +{ + return devno; +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_SYS_I2C + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + + if (is_cpu_type(MXC_CPU_MX6ULL)) + env_set("board", "visionsom-6ull"); + else + env_set("board", "visionsom-6ul"); + + return 0; +} + +int checkboard(void) +{ + printf("Board: SoMLabs VisionSOM-6UL%s\n", + is_cpu_type(MXC_CPU_MX6ULL) ? "L" : ""); + + return 0; +} diff --git a/configs/somlabs_visionsom_6ull_defconfig b/configs/somlabs_visionsom_6ull_defconfig new file mode 100644 index 0000000000..e39c03573a --- /dev/null +++ b/configs/somlabs_visionsom_6ull_defconfig @@ -0,0 +1,49 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_TARGET_SOMLABS_VISIONSOM_6ULL=y +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xC0000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/somlabs/visionsom-6ull/imximage.cfg" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +# CONFIG_CMD_MDIO is not set +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-somlabs-visionsom" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_LZO=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h new file mode 100644 index 0000000000..6759f24c08 --- /dev/null +++ b/include/configs/somlabs_visionsom_6ull.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017-2019 A. Karas, SomLabs + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * Configuration settings for the SoMlabs VisionSOM 6ULL board. + */ +#ifndef __SOMLABS_VISIONSOM_6ULL_H +#define __SOMLABS_VISIONSOM_6ULL_H + +#include <asm/arch/imx-regs.h> +#include <linux/sizes.h> +#include "mx6_common.h" +#include <asm/mach-imx/gpio.h> + +/* SPL options */ +#include "imx6_spl.h" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* MMC Configs */ +#ifdef CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR + +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#endif /* CONFIG_FSL_USDHC */ + +#define CONFIG_CMD_READ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "console=ttymxc0\0" \ + "initrd_addr=0x86800000\0" \ + "fdt_addr=0x83000000\0" \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "splashimage=0x80000000\0" \ + "splashfile=/boot/splash.bmp\0" \ + "mmcdev=1\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk1p1 rootwait rw\0" \ + "setrootmmc=setenv rootspec root=${mmcroot}\0" \ + "setbootscriptmmc=setenv loadbootscript " \ + "load mmc ${mmcdev}:${mmcpart} " \ + "${loadaddr} /boot/${script};\0" \ + "setloadmmc=setenv loadimage load mmc ${mmcdev}:${mmcpart} " \ + "${loadaddr} /boot/${image}; " \ + "setenv loadfdt load mmc ${mmcdev}:${mmcpart} " \ + "${fdt_addr} /boot/${fdt_file};\0" \ + "setbootargs=setenv bootargs console=${console},${baudrate} " \ + "${rootspec}\0" \ + "execbootscript=echo Running bootscript...; source\0" \ + "setfdtfile=setenv fdt_file somlabs-visionsom-6ull.dtb\0" \ + "checkbootdev=run setbootscriptmmc; " \ + "run setrootmmc; " \ + "run setloadmmc; " \ + +#define CONFIG_BOOTCOMMAND \ + "run setfdtfile; " \ + "run checkbootdev; " \ + "run loadfdt;" \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run setbootargs; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "fi; " \ + "fi" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* environment organization */ +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + +#ifdef CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "eth0" +#endif + +#define CONFIG_IMX_THERMAL + +#endif -- 2.24.1

2 2

[U-Boot] [PATCH V3 1/2] power: domain: add dev_power_domain_on
by Peng Fan 21 Jan '20

21 Jan '20

Add this new API to power on multiple domains attached to a device. Signed-off-by: Peng Fan <peng.fan(a)nxp.com> Reviewed-by: Lokesh Vutla <lokeshvutla(a)ti.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- V3: Fix build break Add R-b tag V2: create dev_power_domain_on drivers/power/domain/power-domain-uclass.c | 22 ++++++++++++++++++++++ include/power-domain.h | 17 +++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/drivers/power/domain/power-domain-uclass.c b/drivers/power/domain/power-domain-uclass.c index 2ea0ff24c7..6eb4267de3 100644 --- a/drivers/power/domain/power-domain-uclass.c +++ b/drivers/power/domain/power-domain-uclass.c @@ -107,6 +107,28 @@ int power_domain_off(struct power_domain *power_domain) return ops->off(power_domain); } + +#if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) +int dev_power_domain_on(struct udevice *dev) +{ + struct power_domain pd; + int i, count, ret; + + count = dev_count_phandle_with_args(dev, "power-domains", + "#power-domain-cells"); + for (i = 0; i < count; i++) { + ret = power_domain_get_by_index(dev, &pd, i); + if (ret) + return ret; + ret = power_domain_on(&pd); + if (ret) + return ret; + } + + return 0; +} +#endif + UCLASS_DRIVER(power_domain) = { .id = UCLASS_POWER_DOMAIN, .name = "power_domain", diff --git a/include/power-domain.h b/include/power-domain.h index ef15dc9f60..490fedbb12 100644 --- a/include/power-domain.h +++ b/include/power-domain.h @@ -155,4 +155,21 @@ static inline int power_domain_off(struct power_domain *power_domain) } #endif +/** + * dev_power_domain_on - Enable power domains for a device . + * + * @dev: The client device. + * + * @return 0 if OK, or a negative error code. + */ +#if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) && \ + CONFIG_IS_ENABLED(POWER_DOMAIN) +int dev_power_domain_on(struct udevice *dev); +#else +static inline int dev_power_domain_on(struct udevice *dev) +{ + return 0; +} +#endif + #endif -- 2.16.4

4 16

[PATCH] mmc: sdhci-cadence: send tune request twice to work around errata
by Masahiro Yamada 21 Jan '20

21 Jan '20

Cadence sent out an errata report to their customers of this IP. This errata is not so severe, but the tune request should be sent twice to avoid the potential issue. Quote from the report: Problem Summary --------------- The IP6116 SD/eMMC PHY design has a timing issue on receive data path. This issue may lead to an incorrect values of read/write pointers of the synchronization FIFO. Such a situation can happen at the SDR104 and HS200 tuning procedure when the PHY is requested to change a phase of sampling clock when moving to the next tuning iteration. Workarounds ----------- The following are valid workarounds to resolve the issue: 1. In eMMC mode, software sends tune request twice instead of once at each iteration. This means that the clock phase is not changed on the second request so there is no potential for clock instability. 2. In SD mode, software must not use the hardware tuning and instead perform an almost identical procedure to eMMC, using the HRS34 Tune Force register. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- drivers/mmc/sdhci-cadence.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/sdhci-cadence.c b/drivers/mmc/sdhci-cadence.c index 4736263bf2a6..eb53653435df 100644 --- a/drivers/mmc/sdhci-cadence.c +++ b/drivers/mmc/sdhci-cadence.c @@ -170,6 +170,7 @@ static int sdhci_cdns_set_tune_val(struct sdhci_cdns_plat *plat, { void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS06; u32 tmp; + int i, ret; if (WARN_ON(!FIELD_FIT(SDHCI_CDNS_HRS06_TUNE, val))) return -EINVAL; @@ -177,11 +178,23 @@ static int sdhci_cdns_set_tune_val(struct sdhci_cdns_plat *plat, tmp = readl(reg); tmp &= ~SDHCI_CDNS_HRS06_TUNE; tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_TUNE, val); - tmp |= SDHCI_CDNS_HRS06_TUNE_UP; - writel(tmp, reg); - return readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS06_TUNE_UP), - 1); + /* + * Workaround for IP errata: + * The IP6116 SD/eMMC PHY design has a timing issue on receive data + * path. Send tune request twice. + */ + for (i = 0; i < 2; i++) { + tmp |= SDHCI_CDNS_HRS06_TUNE_UP; + writel(tmp, reg); + + ret = readl_poll_timeout(reg, tmp, + !(tmp & SDHCI_CDNS_HRS06_TUNE_UP), 1); + if (ret) + return ret; + } + + return 0; } static int __maybe_unused sdhci_cdns_execute_tuning(struct udevice *dev, -- 2.17.1

1 0

[PATCH v3 20/20] mips: mtmips: add support for mt7628-rfb
by Weijie Gao 21 Jan '20

21 Jan '20

This patch adds support for mt7628 reference board. SPL_DM and DT are not enabled for SPL to save about 17KiB for u-boot-spl.bin. Signed-off-by: Weijie Gao <weijie.gao(a)mediatek.com> --- Changes since v2: none --- arch/mips/dts/Makefile | 1 + arch/mips/dts/mediatek,mt7628-rfb.dts | 67 +++++++++++++++++++++++++++ arch/mips/mach-mtmips/Kconfig | 9 ++++ board/mediatek/mt7628/Kconfig | 12 +++++ board/mediatek/mt7628/MAINTAINERS | 7 +++ board/mediatek/mt7628/Makefile | 3 ++ board/mediatek/mt7628/board.c | 8 ++++ configs/mt7628_rfb_defconfig | 46 ++++++++++++++++++ include/configs/mt7628.h | 55 ++++++++++++++++++++++ 9 files changed, 208 insertions(+) create mode 100644 arch/mips/dts/mediatek,mt7628-rfb.dts create mode 100644 board/mediatek/mt7628/Kconfig create mode 100644 board/mediatek/mt7628/MAINTAINERS create mode 100644 board/mediatek/mt7628/Makefile create mode 100644 board/mediatek/mt7628/board.c create mode 100644 configs/mt7628_rfb_defconfig create mode 100644 include/configs/mt7628.h diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index c9d75596f2..cbd0c8bc8b 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -17,6 +17,7 @@ dtb-$(CONFIG_BOARD_COMTREND_CT5361) += comtrend,ct-5361.dtb dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) += comtrend,wap-5813n.dtb dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb +dtb-$(CONFIG_BOARD_MT7628_RFB) += mediatek,mt7628-rfb.dtb dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f(a)st1704.dtb diff --git a/arch/mips/dts/mediatek,mt7628-rfb.dts b/arch/mips/dts/mediatek,mt7628-rfb.dts new file mode 100644 index 0000000000..6ff36daa6e --- /dev/null +++ b/arch/mips/dts/mediatek,mt7628-rfb.dts @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao(a)mediatek.com> + */ + +/dts-v1/; + +#include "mt7628a.dtsi" + +/ { + compatible = "mediatek,mt7628-rfb", "ralink,mt7628a-soc"; + model = "MediaTek MT7628 RFB"; + + aliases { + serial0 = &uart0; + spi0 = &spi0; + }; + + chosen { + stdout-path = &uart0; + }; +}; + +&pinctrl { + state_default: pin_state { + pleds { + groups = "p0led", "p1led", "p2led", "p3led", "p4led"; + function = "led"; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + num-cs = <2>; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <25000000>; + reg = <0>; + }; +}; + +&eth { + mediatek,wan-port = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&ephy_router_mode>; +}; + +&mmc { + bus-width = <4>; + cap-sd-highspeed; + + pinctrl-names = "default"; + pinctrl-0 = <&sd_router_mode>; + + status = "okay"; +}; diff --git a/arch/mips/mach-mtmips/Kconfig b/arch/mips/mach-mtmips/Kconfig index 2b8a848d18..bcd635f438 100644 --- a/arch/mips/mach-mtmips/Kconfig +++ b/arch/mips/mach-mtmips/Kconfig @@ -75,6 +75,14 @@ config BOARD_LINKIT_SMART_7688 ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs, and a MT7688 (PCIe). +config BOARD_MT7628_RFB + bool "MediaTek MT7628 RFB" + depends on SOC_MT7628 + help + The reference design of MT7628. The board has 128 MiB DDR2, 8 MiB + SPI-NOR flash, 1 built-in switch with 5 ports, 1 UART, 1 USB host, + 1 SDXC, 1 PCIe socket and JTAG pins. + endchoice config SPL_UART2_SPIS_PINMUX @@ -86,6 +94,7 @@ config SPL_UART2_SPIS_PINMUX (shared with SPIS) rather than the usual GPIO 20/21. source "board/gardena/smart-gateway-mt7688/Kconfig" +source "board/mediatek/mt7628/Kconfig" source "board/seeed/linkit-smart-7688/Kconfig" endmenu diff --git a/board/mediatek/mt7628/Kconfig b/board/mediatek/mt7628/Kconfig new file mode 100644 index 0000000000..d6b6f9d632 --- /dev/null +++ b/board/mediatek/mt7628/Kconfig @@ -0,0 +1,12 @@ +if BOARD_MT7628_RFB + +config SYS_BOARD + default "mt7628" + +config SYS_VENDOR + default "mediatek" + +config SYS_CONFIG_NAME + default "mt7628" + +endif diff --git a/board/mediatek/mt7628/MAINTAINERS b/board/mediatek/mt7628/MAINTAINERS new file mode 100644 index 0000000000..032fd0e2f7 --- /dev/null +++ b/board/mediatek/mt7628/MAINTAINERS @@ -0,0 +1,7 @@ +MT7628_RFB BOARD +M: Weijie Gao <weijie.gao(a)mediatek.com> +S: Maintained +F: board/mediatek/mt7628 +F: include/configs/mt7628.h +F: configs/mt7628_rfb_defconfig +F: arch/mips/dts/mediatek,mt7628-rfb.dts diff --git a/board/mediatek/mt7628/Makefile b/board/mediatek/mt7628/Makefile new file mode 100644 index 0000000000..db129c5aba --- /dev/null +++ b/board/mediatek/mt7628/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += board.o diff --git a/board/mediatek/mt7628/board.c b/board/mediatek/mt7628/board.c new file mode 100644 index 0000000000..f837a06fbb --- /dev/null +++ b/board/mediatek/mt7628/board.c @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. + * + * Author: Weijie Gao <weijie.gao(a)mediatek.com> + */ + +#include <common.h> diff --git a/configs/mt7628_rfb_defconfig b/configs/mt7628_rfb_defconfig new file mode 100644 index 0000000000..eb73dbb490 --- /dev/null +++ b/configs/mt7628_rfb_defconfig @@ -0,0 +1,46 @@ +CONFIG_MIPS=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x30000 +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SYS_MALLOC_F_LEN=0x20000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL=y +CONFIG_ARCH_MTMIPS=y +CONFIG_BOARD_MT7628_RFB=y +CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y +CONFIG_MIPS_BOOT_FDT=y +CONFIG_FIT=y +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_NOR_SUPPORT=y +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_DM is not set +CONFIG_CMD_GPIO=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_SPI=y +# CONFIG_CMD_NFS is not set +# CONFIG_PARTITIONS is not set +CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7628-rfb" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +# CONFIG_INPUT is not set +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_MT7628_ETH=y +# CONFIG_SPECIFY_CONSOLE_INDEX is not set +CONFIG_SPI=y +CONFIG_MT7621_SPI=y +CONFIG_LZMA=y diff --git a/include/configs/mt7628.h b/include/configs/mt7628.h new file mode 100644 index 0000000000..e97d23ad97 --- /dev/null +++ b/include/configs/mt7628.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao(a)mediatek.com> + */ + +#ifndef __CONFIG_MT7628_H +#define __CONFIG_MT7628_H + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000 + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_MALLOC_LEN 0x100000 +#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_LOAD_ADDR 0x80010000 + +#define CONFIG_SYS_INIT_SP_OFFSET 0x80000 + +#define CONFIG_SYS_BOOTM_LEN 0x1000000 + +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_CBSIZE 1024 + +/* Serial SPL */ +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT) +#define CONFIG_SYS_NS16550_MEM32 +#define CONFIG_SYS_NS16550_CLK 40000000 +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_COM1 0xb0000c00 +#define CONFIG_CONS_INDEX 1 +#endif + +/* Serial common */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ + 230400, 460800, 921600 } + +/* SPL */ +#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SPL_BSS_START_ADDR 0x80010000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x10000 +#define CONFIG_SPL_MAX_SIZE 0x10000 + +/* Dummy value */ +#define CONFIG_SYS_UBOOT_BASE 0 + +#endif /* __CONFIG_MT7628_H */ -- 2.17.1

2 1

[PATCH v3 18/20] mips: mtmips: add SPL support
by Weijie Gao 21 Jan '20

21 Jan '20

This patch adds SPL support for mtmips platform. The lowlevel architecture is split into SPL and the rest parts are built into a memory loadable u-boot image. Optional SPL_DM and OF_CONTROL are also supported. The increment of size is very small (< 10 KiB) if SPL_DM and OF_CONTROL are not enabled and the memory bootable u-boot (u-boot.img) is generated automatically so there is not need to add a separate config for it. A lzma compressed payload (u-boot-lzma.img) is also generated and it will be combined with u-boot-spl.bin to form the unified ROM bootable binary u-boot-mtmips.bin. A spl loader is added to support uncompress the payload. Signed-off-by: Weijie Gao <weijie.gao(a)mediatek.com> --- Changes since v2: * Remove spl_load.c and move its feature to common spl_nor.c * Add u-boot,dm-pre-reloc to u-boot-mt7628.dtsi --- Makefile | 9 ++++ arch/mips/Kconfig | 3 ++ arch/mips/dts/mt7628-u-boot.dtsi | 56 +++++++++++++++++++++ arch/mips/dts/mt7628a.dtsi | 2 +- arch/mips/mach-mtmips/Kconfig | 23 +++++++++ arch/mips/mach-mtmips/Makefile | 1 + arch/mips/mach-mtmips/include/mach/serial.h | 13 +++++ arch/mips/mach-mtmips/mt7628/Makefile | 1 + arch/mips/mach-mtmips/mt7628/serial.c | 34 +++++++++++++ arch/mips/mach-mtmips/spl.c | 44 ++++++++++++++++ 10 files changed, 185 insertions(+), 1 deletion(-) create mode 100644 arch/mips/dts/mt7628-u-boot.dtsi create mode 100644 arch/mips/mach-mtmips/include/mach/serial.h create mode 100644 arch/mips/mach-mtmips/mt7628/serial.c create mode 100644 arch/mips/mach-mtmips/spl.c diff --git a/Makefile b/Makefile index 8013cbd9f9..1e18a37913 100644 --- a/Makefile +++ b/Makefile @@ -895,6 +895,7 @@ ALL-$(CONFIG_OF_SEPARATE) += u-boot-dtb-tegra.bin endif ALL-$(CONFIG_ARCH_MEDIATEK) += u-boot-mtk.bin +ALL-$(CONFIG_ARCH_MTMIPS) += u-boot-mtmips.bin # Add optional build target if defined in board/cpu/soc headers ifneq ($(CONFIG_BUILD_TARGET),) @@ -1664,6 +1665,14 @@ u-boot-mtk.bin: u-boot.bin FORCE $(call if_changed,mkimage) endif +ifeq ($(CONFIG_SPL),y) +u-boot-mtmips.bin: u-boot.dtb u-boot-lzma.img spl/u-boot-spl.bin FORCE + $(call if_changed,binman) +else +u-boot-mtmips.bin: u-boot.bin FORCE + $(call if_changed,copy) +endif + ARCH_POSTLINK := $(wildcard $(srctree)/arch/$(ARCH)/Makefile.postlink) # Rule to link u-boot diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 7b9d0072eb..4c1eea1ccc 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -98,6 +98,9 @@ config ARCH_MTMIPS select SUPPORTS_CPU_MIPS32_R2 select SUPPORTS_LITTLE_ENDIAN select SYSRESET + select SUPPORT_SPL + select SPL_LZMA + select BINMAN config ARCH_JZ47XX bool "Support Ingenic JZ47xx" diff --git a/arch/mips/dts/mt7628-u-boot.dtsi b/arch/mips/dts/mt7628-u-boot.dtsi new file mode 100644 index 0000000000..e3901d843c --- /dev/null +++ b/arch/mips/dts/mt7628-u-boot.dtsi @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao(a)mediatek.com> + */ + +/ { + binman { + filename = "u-boot-mtmips.bin"; + pad-byte = <0xff>; + +#ifdef CONFIG_SPL + u-boot-spl { + }; + + u-boot-lzma-img { + }; +#else + u-boot { + }; +#endif + }; +}; + +&palmbus { + u-boot,dm-pre-reloc; +}; + +&reboot { + u-boot,dm-pre-reloc; +}; + +&clkctrl { + u-boot,dm-pre-reloc; +}; + +&rstctrl { + u-boot,dm-pre-reloc; +}; + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&uart0 { + u-boot,dm-pre-reloc; +}; + +&uart1 { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi index 2200135a77..6baa63add3 100644 --- a/arch/mips/dts/mt7628a.dtsi +++ b/arch/mips/dts/mt7628a.dtsi @@ -33,7 +33,7 @@ #clock-cells = <0>; }; - palmbus@10000000 { + palmbus: palmbus@10000000 { compatible = "palmbus", "simple-bus"; reg = <0x10000000 0x200000>; ranges = <0x0 0x10000000 0x1FFFFF>; diff --git a/arch/mips/mach-mtmips/Kconfig b/arch/mips/mach-mtmips/Kconfig index 3f25de8b85..493fe0b21d 100644 --- a/arch/mips/mach-mtmips/Kconfig +++ b/arch/mips/mach-mtmips/Kconfig @@ -20,8 +20,15 @@ config SYS_ICACHE_LINE_SIZE default 32 config SYS_TEXT_BASE + default 0x9c000000 if !SPL + default 0x80200000 if SPL + +config SPL_TEXT_BASE default 0x9c000000 +config SPL_LOADER_SUPPORT + default y + choice prompt "MediaTek MIPS SoC select" @@ -34,6 +41,14 @@ config SOC_MT7628 select PINCTRL_MT7628 select MTK_SERIAL select SYSRESET_RESETCTL + select SPL_SEPARATE_BSS if SPL + select SPL_INIT_STACK_WITHOUT_MALLOC_F if SPL + select SPL_OF_CONTROL if SPL_DM + select SPL_SIMPLE_BUS if SPL_DM + select SPL_DM_SERIAL if SPL_DM + select SPL_CLK if SPL_DM && SPL_SERIAL_SUPPORT + select SPL_SYSRESET if SPL_DM + select SPL_OF_LIBFDT if SPL_OF_CONTROL help This supports MediaTek MT7628/MT7688. @@ -88,6 +103,14 @@ endchoice config SUPPORTS_BOOT_RAM bool +config SPL_UART2_SPIS_PINMUX + bool "Use alternative pinmux for UART2 in SPL stage" + depends on SPL_SERIAL_SUPPORT + default n + help + Select this if the UART2 of your board is connected to GPIO 16/17 + (shared with SPIS) rather than the usual GPIO 20/21. + source "board/gardena/smart-gateway-mt7688/Kconfig" source "board/seeed/linkit-smart-7688/Kconfig" diff --git a/arch/mips/mach-mtmips/Makefile b/arch/mips/mach-mtmips/Makefile index 72f0369030..a7e6a66304 100644 --- a/arch/mips/mach-mtmips/Makefile +++ b/arch/mips/mach-mtmips/Makefile @@ -3,5 +3,6 @@ obj-y += cpu.o obj-y += ddr_init.o obj-y += ddr_cal.o +obj-$(CONFIG_SPL_BUILD) += spl.o obj-$(CONFIG_SOC_MT7628) += mt7628/ diff --git a/arch/mips/mach-mtmips/include/mach/serial.h b/arch/mips/mach-mtmips/include/mach/serial.h new file mode 100644 index 0000000000..bfa246b428 --- /dev/null +++ b/arch/mips/mach-mtmips/include/mach/serial.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao(a)mediatek.com> + */ + +#ifndef _MTMIPS_SERIAL_H_ +#define _MTMIPS_SERIAL_H_ + +void mtmips_spl_serial_init(void); + +#endif /* _MTMIPS_SERIAL_H_ */ diff --git a/arch/mips/mach-mtmips/mt7628/Makefile b/arch/mips/mach-mtmips/mt7628/Makefile index db62e90d77..7e139d5adf 100644 --- a/arch/mips/mach-mtmips/mt7628/Makefile +++ b/arch/mips/mach-mtmips/mt7628/Makefile @@ -3,3 +3,4 @@ obj-y += lowlevel_init.o obj-y += init.o obj-y += ddr.o +obj-$(CONFIG_SPL_BUILD) += serial.o diff --git a/arch/mips/mach-mtmips/mt7628/serial.c b/arch/mips/mach-mtmips/mt7628/serial.c new file mode 100644 index 0000000000..a7d324792d --- /dev/null +++ b/arch/mips/mach-mtmips/mt7628/serial.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao(a)mediatek.com> + */ + +#include <common.h> +#include <asm/io.h> +#include "mt7628.h" + +void mtmips_spl_serial_init(void) +{ +#ifdef CONFIG_SPL_SERIAL_SUPPORT + void __iomem *base = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); + +#if CONFIG_CONS_INDEX == 1 + clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART0_MODE_M); +#elif CONFIG_CONS_INDEX == 2 + clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART1_MODE_M); +#elif CONFIG_CONS_INDEX == 3 + setbits_32(base + SYSCTL_AGPIO_CFG_REG, EPHY_GPIO_AIO_EN_M); +#ifdef CONFIG_SPL_UART2_SPIS_PINMUX + setbits_32(base + SYSCTL_GPIO_MODE1_REG, SPIS_MODE_M); + clrsetbits_32(base + SYSCTL_GPIO_MODE1_REG, UART2_MODE_M, + 1 << UART2_MODE_S); +#else + clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART2_MODE_M); + clrsetbits_32(base + SYSCTL_GPIO_MODE1_REG, SPIS_MODE_M, + 1 << SPIS_MODE_S); +#endif /* CONFIG_SPL_UART2_SPIS_PINMUX */ +#endif /* CONFIG_CONS_INDEX */ +#endif /* CONFIG_SPL_SERIAL_SUPPORT */ +} diff --git a/arch/mips/mach-mtmips/spl.c b/arch/mips/mach-mtmips/spl.c new file mode 100644 index 0000000000..2a24af70c3 --- /dev/null +++ b/arch/mips/mach-mtmips/spl.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. + * + * Author: Weijie Gao <weijie.gao(a)mediatek.com> + */ + +#include <common.h> +#include <fdt.h> +#include <spl.h> +#include <asm/sections.h> +#include <linux/sizes.h> +#include <mach/serial.h> + +void __noreturn board_init_f(ulong dummy) +{ + spl_init(); + +#ifdef CONFIG_SPL_SERIAL_SUPPORT + /* + * mtmips_spl_serial_init() is useful if debug uart is enabled, + * or DM based serial is not enabled. + */ + mtmips_spl_serial_init(); + preloader_console_init(); +#endif + + board_init_r(NULL, 0); +} + +void board_boot_order(u32 *spl_boot_list) +{ + spl_boot_list[0] = BOOT_DEVICE_NOR; +} + +unsigned long spl_nor_get_uboot_base(void) +{ + void *uboot_base = __image_copy_end; + + if (fdt_magic(uboot_base) == FDT_MAGIC) + return (unsigned long)uboot_base + fdt_totalsize(uboot_base); + + return (unsigned long)uboot_base; +} -- 2.17.1

2 1

[PATCH v3 19/20] mips: mtmips: enable SPL for all boards
by Weijie Gao 21 Jan '20

21 Jan '20

This patch enables SPL for all mtmips boards. And also remove defconfig files which are intend to build ram bootable u-boot files. SPL_DM and OF_CONTROL are enabled for both boards. Signed-off-by: Weijie Gao <weijie.gao(a)mediatek.com> --- Changes since v2: * Move spi related files to previous patch --- arch/mips/mach-mtmips/Kconfig | 26 ------- board/gardena/smart-gateway-mt7688/board.c | 2 + ...gardena-smart-gateway-mt7688-ram_defconfig | 74 ------------------- .../gardena-smart-gateway-mt7688_defconfig | 12 ++- configs/linkit-smart-7688-ram_defconfig | 65 ---------------- configs/linkit-smart-7688_defconfig | 12 ++- .../configs/gardena-smart-gateway-mt7688.h | 20 ++++- include/configs/linkit-smart-7688.h | 21 +++++- 8 files changed, 59 insertions(+), 173 deletions(-) delete mode 100644 configs/gardena-smart-gateway-mt7688-ram_defconfig delete mode 100644 configs/linkit-smart-7688-ram_defconfig diff --git a/arch/mips/mach-mtmips/Kconfig b/arch/mips/mach-mtmips/Kconfig index 493fe0b21d..2b8a848d18 100644 --- a/arch/mips/mach-mtmips/Kconfig +++ b/arch/mips/mach-mtmips/Kconfig @@ -61,7 +61,6 @@ config BOARD_GARDENA_SMART_GATEWAY_MT7688 bool "GARDENA smart Gateway" depends on SOC_MT7628 select BOARD_LATE_INIT - select SUPPORTS_BOOT_RAM help GARDENA smart Gateway boards have a MT7688 SoC with 128 MiB of RAM and 8 MiB of flash (SPI NOR) and additional SPI NAND storage. @@ -69,7 +68,6 @@ config BOARD_GARDENA_SMART_GATEWAY_MT7688 config BOARD_LINKIT_SMART_7688 bool "LinkIt Smart 7688" depends on SOC_MT7628 - select SUPPORTS_BOOT_RAM help Seeed LinkIt Smart 7688 boards have a MT7688 SoC with 128 MiB of RAM and 32 MiB of flash (SPI). @@ -79,30 +77,6 @@ config BOARD_LINKIT_SMART_7688 endchoice -choice - prompt "Boot mode" - -config BOOT_RAM - bool "RAM boot" - depends on SUPPORTS_BOOT_RAM - help - This builds an image that is linked to a RAM address. It can be used - for booting from CFE via TFTP using an ELF image, but it can also be - booted from RAM by other bootloaders using a BIN image. - -config BOOT_ROM - bool "ROM boot" - depends on SUPPORTS_BOOT_RAM - help - This builds an image that is linked to a ROM address. It can be - used as main bootloader image which is programmed onto the onboard - flash storage (SPI NOR). - -endchoice - -config SUPPORTS_BOOT_RAM - bool - config SPL_UART2_SPIS_PINMUX bool "Use alternative pinmux for UART2 in SPL stage" depends on SPL_SERIAL_SUPPORT diff --git a/board/gardena/smart-gateway-mt7688/board.c b/board/gardena/smart-gateway-mt7688/board.c index ae03f0a434..80f9f1ae65 100644 --- a/board/gardena/smart-gateway-mt7688/board.c +++ b/board/gardena/smart-gateway-mt7688/board.c @@ -294,8 +294,10 @@ err_free: return ret; } +#ifndef CONFIG_SPL_BUILD U_BOOT_CMD( fd_write, 1, 0, do_fd_write, "Write test factory-data values to SPI NOR", "\n" ); +#endif diff --git a/configs/gardena-smart-gateway-mt7688-ram_defconfig b/configs/gardena-smart-gateway-mt7688-ram_defconfig deleted file mode 100644 index 38c9272723..0000000000 --- a/configs/gardena-smart-gateway-mt7688-ram_defconfig +++ /dev/null @@ -1,74 +0,0 @@ -CONFIG_MIPS=y -CONFIG_SYS_TEXT_BASE=0x80010000 -CONFIG_ENV_SIZE=0x10000 -CONFIG_ENV_OFFSET=0xA0000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y -CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_ARCH_MTMIPS=y -CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y -# CONFIG_MIPS_BOOT_ENV_LEGACY is not set -CONFIG_MIPS_BOOT_FDT=y -CONFIG_ENV_VARS_UBOOT_CONFIG=y -CONFIG_FIT=y -CONFIG_FIT_SIGNATURE=y -CONFIG_LEGACY_IMAGE_FORMAT=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="cp.b 83000000 84000000 10000 && dhcp uEnv.txt && env import -t ${fileaddr} ${filesize} && run do_u_boot_init; reset" -CONFIG_USE_PREBOOT=y -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_VERSION_VARIABLE=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_LICENSE=y -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_XIMG is not set -CONFIG_CMD_MEMINFO=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_MTD=y -CONFIG_CMD_SPI=y -CONFIG_CMD_WDT=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BOOTCOUNT=y -CONFIG_CMD_TIME=y -CONFIG_CMD_UUID=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="spi-nand0=spi0.1,nor0=spi0.0" -CONFIG_MTDPARTS_DEFAULT="spi0.0:640k(uboot),64k(uboot_env0),64k(uboot_env1),64k(factory),-(unused);spi0.1:-(nand)" -CONFIG_CMD_UBI=y -CONFIG_DEFAULT_DEVICE_TREE="gardena-smart-gateway-mt7688" -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_OFFSET_REDUND=0xB0000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -# CONFIG_DM_DEVICE_REMOVE is not set -CONFIG_HAVE_BLOCK_DEVICE=y -CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_LED=y -CONFIG_LED_BLINK=y -CONFIG_LED_GPIO=y -CONFIG_MTD=y -CONFIG_DM_MTD=y -CONFIG_MTD_SPI_NAND=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -CONFIG_SPI_FLASH_XMC=y -CONFIG_SPI_FLASH_MTD=y -CONFIG_MTD_UBI_BEB_LIMIT=22 -CONFIG_MT7628_ETH=y -CONFIG_PHY=y -CONFIG_SPI=y -CONFIG_MT7621_SPI=y -CONFIG_WDT=y -CONFIG_WDT_MT7621=y -CONFIG_LZMA=y diff --git a/configs/gardena-smart-gateway-mt7688_defconfig b/configs/gardena-smart-gateway-mt7688_defconfig index 0fd3c81ee8..4bce62b5ed 100644 --- a/configs/gardena-smart-gateway-mt7688_defconfig +++ b/configs/gardena-smart-gateway-mt7688_defconfig @@ -1,13 +1,16 @@ CONFIG_MIPS=y -CONFIG_SYS_TEXT_BASE=0x9c000000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_ENV_OFFSET=0xA0000 +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SYS_MALLOC_F_LEN=0x20000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL=y CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c -CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_ARCH_MTMIPS=y -CONFIG_BOOT_ROM=y CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y @@ -22,6 +25,8 @@ CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_NOR_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_LICENSE=y # CONFIG_CMD_ELF is not set @@ -49,6 +54,7 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_OFFSET_REDUND=0xB0000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_HAVE_BLOCK_DEVICE=y CONFIG_BOOTCOUNT_LIMIT=y diff --git a/configs/linkit-smart-7688-ram_defconfig b/configs/linkit-smart-7688-ram_defconfig deleted file mode 100644 index 6d8969aacb..0000000000 --- a/configs/linkit-smart-7688-ram_defconfig +++ /dev/null @@ -1,65 +0,0 @@ -CONFIG_MIPS=y -CONFIG_SYS_TEXT_BASE=0x80010000 -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_OFFSET=0x80000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_ARCH_MTMIPS=y -CONFIG_BOARD_LINKIT_SMART_7688=y -CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y -# CONFIG_MIPS_BOOT_ENV_LEGACY is not set -CONFIG_MIPS_BOOT_FDT=y -CONFIG_FIT=y -CONFIG_FIT_SIGNATURE=y -CONFIG_LEGACY_IMAGE_FORMAT=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_LICENSE=y -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_XIMG is not set -CONFIG_CMD_MEMINFO=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_MTD=y -CONFIG_CMD_PART=y -CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_TIME=y -CONFIG_CMD_FS_GENERIC=y -# CONFIG_DOS_PARTITION is not set -CONFIG_DEFAULT_DEVICE_TREE="linkit-smart-7688" -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -# CONFIG_DM_DEVICE_REMOVE is not set -CONFIG_BLK=y -CONFIG_LED=y -CONFIG_LED_BLINK=y -CONFIG_LED_GPIO=y -CONFIG_MTD=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -CONFIG_SPI_FLASH_MTD=y -CONFIG_MT7628_ETH=y -CONFIG_PHY=y -CONFIG_MT76X8_USB_PHY=y -CONFIG_SPI=y -CONFIG_MT7621_SPI=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_GENERIC=y -CONFIG_USB_STORAGE=y -CONFIG_FS_EXT4=y -CONFIG_FS_FAT=y -CONFIG_LZMA=y -CONFIG_LZO=y diff --git a/configs/linkit-smart-7688_defconfig b/configs/linkit-smart-7688_defconfig index 9ddee9a861..642755ec65 100644 --- a/configs/linkit-smart-7688_defconfig +++ b/configs/linkit-smart-7688_defconfig @@ -1,12 +1,15 @@ CONFIG_MIPS=y -CONFIG_SYS_TEXT_BASE=0x9c000000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_ENV_OFFSET=0x80000 +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SYS_MALLOC_F_LEN=0x20000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SPL=y CONFIG_ARCH_MTMIPS=y CONFIG_BOARD_LINKIT_SMART_7688=y -CONFIG_BOOT_ROM=y CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y @@ -16,6 +19,8 @@ CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_NOR_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_LICENSE=y # CONFIG_CMD_ELF is not set @@ -39,6 +44,7 @@ CONFIG_DEFAULT_DEVICE_TREE="linkit-smart-7688" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_BLK=y CONFIG_LED=y diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h index 59c60743d2..9a087a0fba 100644 --- a/include/configs/gardena-smart-gateway-mt7688.h +++ b/include/configs/gardena-smart-gateway-mt7688.h @@ -16,10 +16,28 @@ #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 -#ifdef CONFIG_BOOT_RAM +/* SPL */ +#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) #define CONFIG_SKIP_LOWLEVEL_INIT #endif +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SPL_BSS_START_ADDR 0x80010000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x10000 +#define CONFIG_SPL_MAX_SIZE 0x10000 + +/* Dummy value */ +#define CONFIG_SYS_UBOOT_BASE 0 + +/* Serial SPL */ +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT) +#define CONFIG_SYS_NS16550_MEM32 +#define CONFIG_SYS_NS16550_CLK 40000000 +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_COM1 0xb0000c00 +#define CONFIG_CONS_INDEX 1 +#endif + /* UART */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 921600 } diff --git a/include/configs/linkit-smart-7688.h b/include/configs/linkit-smart-7688.h index ca5b693e4c..494c0e34bd 100644 --- a/include/configs/linkit-smart-7688.h +++ b/include/configs/linkit-smart-7688.h @@ -16,10 +16,29 @@ #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 -#ifdef CONFIG_BOOT_RAM +/* SPL */ +#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) #define CONFIG_SKIP_LOWLEVEL_INIT #endif +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SPL_BSS_START_ADDR 0x80010000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x10000 +#define CONFIG_SPL_MAX_SIZE 0x10000 + +/* Dummy value */ +#define CONFIG_SYS_UBOOT_BASE 0 + +/* Serial SPL */ +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT) +#define CONFIG_SYS_NS16550_MEM32 +#define CONFIG_SYS_NS16550_CLK 40000000 +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_COM3 0xb0000e00 +#define CONFIG_CONS_INDEX 3 + +#endif + /* UART */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 921600 } -- 2.17.1

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[PATCH v3 17/20] spl: nor: add lzma decompression support for legacy image
by Weijie Gao 21 Jan '20

21 Jan '20

This patch adds support for decompressing LZMA compressed u-boot payload in legacy uImage format. Using this patch together with u-boot-lzma.img is useful for NOR flashes as they can reduce the size and load time of u-boot payload. Signed-off-by: Weijie Gao <weijie.gao(a)mediatek.com> --- Changes since v2: new --- common/spl/spl_nor.c | 59 ++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 54 insertions(+), 5 deletions(-) diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c index b1e79b9ded..7c81fb28f6 100644 --- a/common/spl/spl_nor.c +++ b/common/spl/spl_nor.c @@ -4,8 +4,19 @@ */ #include <common.h> +#include <cpu_func.h> #include <spl.h> +#if IS_ENABLED(CONFIG_SPL_LZMA) +#include <lzma/LzmaTypes.h> +#include <lzma/LzmaDec.h> +#include <lzma/LzmaTools.h> +#endif + +#ifndef CONFIG_SYS_BOOTM_LEN +#define CONFIG_SYS_BOOTM_LEN (8 << 20) +#endif + static ulong spl_nor_load_read(struct spl_load_info *load, ulong sector, ulong count, void *buf) { @@ -27,6 +38,9 @@ static int spl_nor_load_image(struct spl_image_info *spl_image, int ret; __maybe_unused const struct image_header *header; __maybe_unused struct spl_load_info load; + __maybe_unused SizeT lzma_len; + struct image_header hdr; + uintptr_t dataptr; /* * Loading of the payload to SDRAM is done with skipping of @@ -107,14 +121,49 @@ static int spl_nor_load_image(struct spl_image_info *spl_image, spl_nor_get_uboot_base()); } - ret = spl_parse_image_header(spl_image, - (const struct image_header *)spl_nor_get_uboot_base()); + /* Payload image may not be aligned, so copy it for safety. */ + memcpy(&hdr, (void *)spl_nor_get_uboot_base(), sizeof(hdr)); + ret = spl_parse_image_header(spl_image, &hdr); if (ret) return ret; - memcpy((void *)(unsigned long)spl_image->load_addr, - (void *)(spl_nor_get_uboot_base() + sizeof(struct image_header)), - spl_image->size); + dataptr = spl_nor_get_uboot_base() + sizeof(struct image_header); + + switch (image_get_comp(&hdr)) { + case IH_COMP_NONE: + memmove((void *)(unsigned long)spl_image->load_addr, + (void *)dataptr, spl_image->size); + break; +#if IS_ENABLED(CONFIG_SPL_LZMA) + case IH_COMP_LZMA: + lzma_len = CONFIG_SYS_BOOTM_LEN; + + ret = lzmaBuffToBuffDecompress((void *)spl_image->load_addr, + &lzma_len, (void *)dataptr, + spl_image->size); + + if (ret) { + printf("LZMA decompression error: %d\n", ret); + return ret; + } + + spl_image->size = lzma_len; + break; +#endif + default: + debug("Compression method %s is not supported\n", + genimg_get_comp_short_name(image_get_comp(&hdr))); + return -EINVAL; + } + + flush_cache((unsigned long)spl_image->load_addr, spl_image->size); + + /* + * If the image did not provide an entry point, assume the entry point + * is the same as its load address. + */ + if (!spl_image->entry_point) + spl_image->entry_point = spl_image->load_addr; return 0; } -- 2.17.1

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[PATCH v3 15/20] Makefile: add support to generate LZMA compressed u-boot image
by Weijie Gao 21 Jan '20

21 Jan '20

This patch adds support for generating LZMA compressed u-boot image. The compressed image can be used for SPL to reduce the size of the u-boot binary. Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck(a)gmail.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> Signed-off-by: Weijie Gao <weijie.gao(a)mediatek.com> --- Changes since v2: none --- Makefile | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Makefile b/Makefile index 3f332e6885..8013cbd9f9 100644 --- a/Makefile +++ b/Makefile @@ -952,6 +952,9 @@ append = cat $(filter-out $< $(PHONY), $^) >> $@ quiet_cmd_pad_cat = CAT $@ cmd_pad_cat = $(cmd_objcopy) && $(append) || rm -f $@ +quiet_cmd_lzma = LZMA $@ +cmd_lzma = lzma -c -z -k -9 $< > $@ + cfg: u-boot.cfg quiet_cmd_cfgcheck = CFGCHK $2 @@ -1334,6 +1337,16 @@ else UBOOT_BIN := u-boot.bin endif +MKIMAGEFLAGS_u-boot-lzma.img = -A $(ARCH) -T standalone -C lzma -O u-boot \ + -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ + -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" + +u-boot.bin.lzma: u-boot.bin FORCE + $(call if_changed,lzma) + +u-boot-lzma.img: u-boot.bin.lzma FORCE + $(call if_changed,mkimage) + u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl u-boot-ivt.img: \ $(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin \ $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_OF_HOSTFILE),dts/dt.dtb) \ -- 2.17.1

2 1

[PATCH v3 14/20] lib: enable lzma decompression support for SPL build
by Weijie Gao 21 Jan '20

21 Jan '20

This patch enables LZMA decompression support for SPL build Reviewed-by: Tom Rini <trini(a)konsulko.com> Signed-off-by: Weijie Gao <weijie.gao(a)mediatek.com> --- Changes since v2: none --- lib/Kconfig | 5 +++++ lib/Makefile | 1 + 2 files changed, 6 insertions(+) diff --git a/lib/Kconfig b/lib/Kconfig index d040a87d26..6e491c3552 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -428,6 +428,11 @@ config SPL_LZ4 fast compression and decompression speed. It belongs to the LZ77 family of byte-oriented compression schemes. +config SPL_LZMA + bool "Enable LZMA decompression support for SPL build" + help + This enables support for LZMA compression altorithm for SPL boot. + config SPL_LZO bool "Enable LZO decompression support in SPL" help diff --git a/lib/Makefile b/lib/Makefile index 6b7b9ce85c..889f505800 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -65,6 +65,7 @@ obj-$(CONFIG_$(SPL_)ZLIB) += zlib/ obj-$(CONFIG_$(SPL_)ZSTD) += zstd/ obj-$(CONFIG_$(SPL_)GZIP) += gunzip.o obj-$(CONFIG_$(SPL_)LZO) += lzo/ +obj-$(CONFIG_$(SPL_)LZMA) += lzma/ obj-$(CONFIG_$(SPL_)LZ4) += lz4_wrapper.o obj-$(CONFIG_LIBAVB) += libavb/ -- 2.17.1

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