September 2019 - U-Boot

[U-Boot] [PATCH] board: atmel: sama5d27_wlsom1_ek: fix SPL OFFS on SPI
by Eugen.Hristev＠microchip.com 16 Sep '19

16 Sep '19

From: Eugen Hristev <eugen.hristev(a)microchip.com> Fixes redefinition of CONFIG_SYS_SPI_U_BOOT_OFFS This is now a Kconfig Fixes: 3e541a6e8fba ("board: atmel: sama5d2_wlsom1_ek: add qspi support and qspi boot config") Signed-off-by: Eugen Hristev <eugen.hristev(a)microchip.com> --- >From the initial submission of the board add patch until it was accepted, SPI_U_BOOT_OFFS was converted to Kconfig. Fixed with this patch. configs/sama5d27_wlsom1_ek_qspiflash_defconfig | 3 ++- include/configs/sama5d27_wlsom1_ek.h | 4 ---- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig index ec05af1..82568e2 100644 --- a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig +++ b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig @@ -16,6 +16,7 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEBUG_UART=y +CONFIG_SPL_TEXT_BASE=0x200000 CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2" @@ -26,12 +27,12 @@ CONFIG_USE_BOOTARGS=y CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_TEXT_BASE=0x200000 CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DISPLAY_PRINT=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_AT91_MCK_BYPASS=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set diff --git a/include/configs/sama5d27_wlsom1_ek.h b/include/configs/sama5d27_wlsom1_ek.h index 250eb73..6bcbc06 100644 --- a/include/configs/sama5d27_wlsom1_ek.h +++ b/include/configs/sama5d27_wlsom1_ek.h @@ -43,8 +43,4 @@ #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #endif -#ifdef CONFIG_QSPI_BOOT -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 -#endif - #endif -- 2.7.4

1 1

[U-Boot] [PATCH] configs: sama5d27_wlsom1_ek: add CONFIG_SPL_AT91_MCK_BYPASS
by Eugen.Hristev＠microchip.com 16 Sep '19

16 Sep '19

From: Eugen Hristev <eugen.hristev(a)microchip.com> This board has an external oscillator as MCK that does not need driving. Bypass the driving for the main oscillator in SPL. Signed-off-by: Eugen Hristev <eugen.hristev(a)microchip.com> --- configs/sama5d27_wlsom1_ek_mmc_defconfig | 1 + configs/sama5d27_wlsom1_ek_qspiflash_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/sama5d27_wlsom1_ek_mmc_defconfig b/configs/sama5d27_wlsom1_ek_mmc_defconfig index 5584c9c..50a8a8e 100644 --- a/configs/sama5d27_wlsom1_ek_mmc_defconfig +++ b/configs/sama5d27_wlsom1_ek_mmc_defconfig @@ -30,6 +30,7 @@ CONFIG_SPL_TEXT_BASE=0x200000 CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DISPLAY_PRINT=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +CONFIG_SPL_AT91_MCK_BYPASS=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set diff --git a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig index 56cca3e..ec05af1 100644 --- a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig +++ b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig @@ -31,6 +31,7 @@ CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DISPLAY_PRINT=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_AT91_MCK_BYPASS=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set -- 2.7.4

1 1

Re: [U-Boot] [PATCH] imx: fix missing MAINTAINERS pico boards
by Peng Fan 16 Sep '19

16 Sep '19

Hi Stefano, +u-boot mail list. > Subject: [PATCH] imx: fix missing MAINTAINERS pico boards > > Add missing files pico-nymph-imx7d_defconfig and > c>onfigs/pico-dwarf-imx7d_defconfig > > Signed-off-by: Stefano Babic <sbabic(a)denx.de> > CC: Fabio Estevam <festevam(a)gmail.com> > CC: Otavio Salvador <otavio(a)ossystems.com.br> > --- > board/technexion/pico-imx7d/MAINTAINERS | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/board/technexion/pico-imx7d/MAINTAINERS > b/board/technexion/pico-imx7d/MAINTAINERS > index 6e7316be9f..325e1735c3 100644 > --- a/board/technexion/pico-imx7d/MAINTAINERS > +++ b/board/technexion/pico-imx7d/MAINTAINERS > @@ -8,3 +8,5 @@ F: configs/pico-imx7d_defconfig > F: configs/pico-imx7d_bl33_defconfig > F: configs/pico-hobbit-imx7d_defconfig > F: configs/pico-pi-imx7d_defconfig > +F: configs/pico-nymph-imx7d_defconfig > +F: configs/pico-dwarf-imx7d_defconfig Reviewed-by: Peng Fan <peng.fan(a)nxp.com> > -- > 2.17.1

1 0

[U-Boot] [PATCH v2 1/8] mmc: fsl_esdhc: Add peripheral clock support
by Yinbo Zhu 16 Sep '19

16 Sep '19

This patch is to add peripheral clock support Signed-off-by: Yinbo Zhu <yinbo.zhu(a)nxp.com> --- .../armv8/fsl-layerscape/fsl_lsch2_speed.c | 49 ++++++++++++------- .../armv8/fsl-layerscape/fsl_lsch3_speed.c | 45 ++++++++++++++++- .../asm/arch-fsl-layerscape/immap_lsch2.h | 2 +- .../asm/arch-fsl-layerscape/immap_lsch3.h | 1 + 4 files changed, 78 insertions(+), 19 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 9ece4b90e6..23391398ed 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -22,10 +22,12 @@ DECLARE_GLOBAL_DATA_PTR; void get_sys_info(struct sys_info *sys_info) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); -#if (defined(CONFIG_FSL_ESDHC) &&\ - defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)) ||\ - defined(CONFIG_SYS_DPAA_FMAN) - +/* rcw_tmp is needed to get FMan clock, or to get cluster group A + * mux 2 clock for LS1043A/LS1046A. + */ +#if defined(CONFIG_SYS_DPAA_FMAN) || \ + defined(CONFIG_TARGET_LS1046ARDB) || \ + defined(CONFIG_TARGET_LS1043ARDB) u32 rcw_tmp; #endif struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR); @@ -122,32 +124,32 @@ void get_sys_info(struct sys_info *sys_info) } #endif +#ifdef CONFIG_FSL_ESDHC #define HWA_CGA_M2_CLK_SEL 0x00000007 #define HWA_CGA_M2_CLK_SHIFT 0 -#ifdef CONFIG_FSL_ESDHC -#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK +#if defined(CONFIG_TARGET_LS1046ARDB) || defined(CONFIG_TARGET_LS1043ARDB) rcw_tmp = in_be32(&gur->rcwsr[15]); switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) { case 1: - sys_info->freq_sdhc = freq_c_pll[1]; + sys_info->freq_cga_m2 = freq_c_pll[1]; break; +#if defined(CONFIG_TARGET_LS1046ARDB) case 2: - sys_info->freq_sdhc = freq_c_pll[1] / 2; + sys_info->freq_cga_m2 = freq_c_pll[1] / 2; break; +#endif case 3: - sys_info->freq_sdhc = freq_c_pll[1] / 3; + sys_info->freq_cga_m2 = freq_c_pll[1] / 3; break; +#if defined(CONFIG_TARGET_LS1046ARDB) case 6: - sys_info->freq_sdhc = freq_c_pll[0] / 2; + sys_info->freq_cga_m2 = freq_c_pll[0] / 2; break; +#endif default: - printf("Error: Unknown ESDHC clock select!\n"); + printf("Error: Unknown peripheral clock select!\n"); break; } -#else - sys_info->freq_sdhc = (sys_info->freq_systembus / - CONFIG_SYS_FSL_PCLK_DIV) / - CONFIG_SYS_FSL_SDHC_CLK_DIV; #endif #endif @@ -183,9 +185,22 @@ int get_clocks(void) gd->mem_clk = sys_info.freq_ddrbus; #ifdef CONFIG_FSL_ESDHC - gd->arch.sdhc_clk = sys_info.freq_sdhc; +#if defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK) +#if defined(CONFIG_TARGET_LS1046ARDB) + gd->arch.sdhc_clk = sys_info.freq_cga_m2 / 2; +#endif +#if defined(CONFIG_TARGET_LS1043ARDB) + gd->arch.sdhc_clk = sys_info.freq_cga_m2; +#endif +#if defined(CONFIG_TARGET_LS1012ARDB) + gd->arch.sdhc_clk = sys_info.freq_systembus; +#endif +#else + gd->arch.sdhc_clk = (sys_info.freq_systembus / + CONFIG_SYS_FSL_PCLK_DIV) / + CONFIG_SYS_FSL_SDHC_CLK_DIV; +#endif #endif - if (gd->cpu_clk != 0) return 0; else diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index 0985778ff9..c2b11039af 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -63,6 +63,9 @@ void get_sys_info(struct sys_info *sys_info) }; uint i, cluster; +#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LS1088ARDB) + uint rcw_tmp; +#endif uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; unsigned long sysclk = CONFIG_SYS_CLK_FREQ; @@ -126,8 +129,39 @@ void get_sys_info(struct sys_info *sys_info) sys_info->freq_localbus = sys_info->freq_systembus / CONFIG_SYS_FSL_IFC_CLK_DIV; #endif -} +#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LS1088ARDB) +#define HWA_CGA_M2_CLK_SEL 0x00380000 +#define HWA_CGA_M2_CLK_SHIFT 19 + rcw_tmp = in_le32(&gur->rcwsr[5]); + switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) { + case 1: + sys_info->freq_cga_m2 = freq_c_pll[1]; + break; + case 2: + sys_info->freq_cga_m2 = freq_c_pll[1] / 2; + break; + case 3: + sys_info->freq_cga_m2 = freq_c_pll[1] / 3; + break; + case 4: + sys_info->freq_cga_m2 = freq_c_pll[1] / 4; + break; + case 6: + sys_info->freq_cga_m2 = freq_c_pll[0] / 2; + break; + case 7: + sys_info->freq_cga_m2 = freq_c_pll[0] / 3; + break; + default: + printf("Error: Unknown peripheral clock select!\n"); + break; + } +#endif +#if defined(CONFIG_TARGET_LX2160ARDB) || defined(CONFIG_TARGET_LS2080ARDB) + sys_info->freq_cga_m2 = sys_info->freq_systembus; +#endif +} int get_clocks(void) { @@ -140,7 +174,16 @@ int get_clocks(void) gd->arch.mem2_clk = sys_info.freq_ddrbus2; #endif #if defined(CONFIG_FSL_ESDHC) +#if defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK) +#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LX2160ARDB) + gd->arch.sdhc_clk = sys_info.freq_cga_m2 / 2; +#endif +#if defined(CONFIG_TARGET_LS2080ARDB) || defined(CONFIG_TARGET_LS1088ARDB) + gd->arch.sdhc_clk = sys_info.freq_cga_m2; +#endif +#else gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV; +#endif #endif /* defined(CONFIG_FSL_ESDHC) */ if (gd->cpu_clk != 0) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index b4b7c3492e..3a59abb10e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -180,7 +180,7 @@ struct sys_info { unsigned long freq_systembus; unsigned long freq_ddrbus; unsigned long freq_localbus; - unsigned long freq_sdhc; + unsigned long freq_cga_m2; #ifdef CONFIG_SYS_DPAA_FMAN unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 551bc648c9..5d095319b0 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -264,6 +264,7 @@ struct sys_info { /* frequency of platform PLL */ unsigned long freq_systembus; unsigned long freq_ddrbus; + unsigned long freq_cga_m2; #ifdef CONFIG_SYS_FSL_HAS_DP_DDR unsigned long freq_ddrbus2; #endif -- 2.17.1

2 9

Re: [U-Boot] [PATCH v6] board/fsl/lx2160a: Fix MC firmware loading during SD boot
by Priyanka Jain 16 Sep '19

16 Sep '19

>From: Pankaj Bansal >Sent: Wednesday, July 17, 2019 4:04 PM >To: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com>; Meenakshi >Aggarwal <meenakshi.aggarwal(a)nxp.com> >Cc: Varun Sethi <V.Sethi(a)nxp.com>; u-boot(a)lists.denx.de >Subject: [PATCH v6] board/fsl/lx2160a: Fix MC firmware loading during SD boot > >during SD boot, following error comes: > MMC read: dev # 0, block # 20480, count 2048 ... 2048 blocks read: OK > > MMC read: dev # 0, block # 28672, count 2048 ... 2048 blocks read: OK > fsl-mc: ERR: Bad firmware image (bad FIT header) > Hit any key to stop autoboot: 0 > >it's occurring MC firmware and DPC are copied from SD card to DDR. >Size reserved between MC and DPC firmware on DDR is 1MB. >if the size of MC firmware(load address 0x80000000) is more than 1 MB then >part of MC firmware will be overwritten by DPC firmware (load address >0x80100000). > >so, Update the MC/DPL/DPC firmware's DDR address as per their respective >addresses in SD card. > >Signed-off-by: Pankaj Bansal <pankaj.bansal(a)nxp.com> Slight updates in subject and description Applied to fsl-qoriq master, awaiting upstream. Thanks priyankajain

1 0

Re: [U-Boot] [PATCH] arm: dts: ls1028a-qds: define the MDIO MUX
by Priyanka Jain 16 Sep '19

16 Sep '19

>-----Original Message----- >From: Alex Marginean <alexandru.marginean(a)nxp.com> >Sent: Wednesday, August 7, 2019 10:00 PM >To: u-boot(a)lists.denx.de >Cc: Joe Hershberger <joe.hershberger(a)ni.com>; Prabhakar Kushwaha ><prabhakar.kushwaha(a)nxp.com> >Subject: [PATCH] arm: dts: ls1028a-qds: define the MDIO MUX > >QDS board has an on-board RGMII PHY and 4 slots for extension cards. >All these can be accessed over MDIO through a MDIO MUX controlled over I2C. >This patch adds the DT structure describing the MUX in board dts. > >Signed-off-by: Alex Marginean <alexm.osslist(a)gmail.com> >--- Applied to fsl-qoriq master, awaiting upstream. Thanks priyankajain

1 0

Re: [U-Boot] [PATCH v2] armv8: fsl-layerscape: Correct I2C clock divider for some of the plarforms
by Priyanka Jain 16 Sep '19

16 Sep '19

>-----Original Message----- >From: Chuanhua Han <chuanhua.han(a)nxp.com> >Sent: Thursday, August 8, 2019 2:35 PM >To: albert.u.boot(a)aribaud.ne; Prabhakar Kushwaha ><prabhakar.kushwaha(a)nxp.com> >Cc: u-boot(a)lists.denx.de; Chuanhua Han <chuanhua.han(a)nxp.com> >Subject: [PATCH v2] armv8: fsl-layerscape: Correct I2C clock divider for some of >the plarforms > >By default, i2c input clock is platform clk / 2, but this is not correct for all the >platforms, so correct I2C clock divider's default values for LS1012A, LS1028A, >LX2160A and LS1088A. > >Signed-off-by: Chuanhua Han <chuanhua.han(a)nxp.com> Slight update in subject and description Applied to fsl-qoriq master, awaiting upstream. Thanks priyankajain

1 0

[U-Boot] [PATCH v4 0/4] Make some changes to SDP
by Sherry Sun 16 Sep '19

16 Sep '19

Changes in v4: - Add SDP_USB_REQUEST_BUFLEN instead of magic number (65) in patch3/4. - Remove the unnecessary blank lines in patch3/4. Changes in v3: - Add reviewed-by tag for patch2/4 and patch4/4 since this two have been reviewed in v1. Changes in v2: - Update the commit log in patch 1/4. This patchset adds: 1. Add usb_gadget_initialize() and usb_gadget_release() to initialize and release UDC during sdp download. 2. Add high speed endpoint descriptor for sdp. 3. Add a macro definition--CONFIG_SDP_LOADADDR as default sdp load address while SDP_WRITE and SDP_JUMP command addr is zero. The current patches have been validated on both i.MX8 and i.MX8M platform. Sherry Sun (4): imx: spl: Change USB boot device type for imx8/8m SDP: use CONFIG_SDP_LOADADDR as default load address SDP: fix wrong usb request size and add high speed endpoint descriptor SDP: Call usb_gadget_initialize and usb_gadget_release to support UDC arch/arm/mach-imx/spl.c | 2 +- common/spl/spl_sdp.c | 4 ++++ drivers/usb/gadget/Kconfig | 4 ++++ drivers/usb/gadget/f_sdp.c | 43 +++++++++++++++++++++++++++++++++----- 4 files changed, 47 insertions(+), 6 deletions(-) -- 2.17.1

1 5

Re: [U-Boot] [PATCH v3] board: fsl: lx2160a: implement board_fix_fdt
by Priyanka Jain 16 Sep '19

16 Sep '19

>From: Pankaj Bansal >Sent: Saturday, August 17, 2019 6:38 AM >To: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com>; Meenakshi >Aggarwal <meenakshi.aggarwal(a)nxp.com> >Cc: Varun Sethi <V.Sethi(a)nxp.com>; u-boot(a)lists.denx.de >Subject: [PATCH v3] board: fsl: lx2160a: implement board_fix_fdt > >In lx2160a rev2 the pcie controller has been changed. >Therefore, we need to change the device tree nodes of pcie controllers so that >new controller can be probed. >It involves changing the "compatible" field as well as registers names'. >we are keeping same device tree for lx2160a rev1 and rev2, therefore we >change the device tree nodes as part of fdt fixups. >These changes would only be applied if the soc revision is not rev1. > >Signed-off-by: Pankaj Bansal <pankaj.bansal(a)nxp.com> Description updated Applied to fsl-qoriq master, awaiting upstream. Thanks priyankajain

1 0

Re: [U-Boot] [PATCH] board: fsl: lx2160aqds: fix 'compatible' property
by Priyanka Jain 16 Sep '19

16 Sep '19

>-----Original Message----- >From: U-Boot <u-boot-bounces(a)lists.denx.de> On Behalf Of Florin Chiculita >Sent: Monday, August 19, 2019 9:27 PM >To: u-boot(a)lists.denx.de >Subject: [U-Boot] [PATCH] board: fsl: lx2160aqds: fix 'compatible' property > >The code that generates the compatible property concatenates the ethernet phy >id and clause-compatible information without separating them with a comma, >therefore no ethernet phy driver will be loaded by Linux kernel. > >Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita(a)nxp.com> >--- Slight update in subject and description Applied to fsl-qoriq master, awaiting upstream. Thanks priyankajain

1 0