September 2019 - U-Boot

[U-Boot] [PATCH v1 01/20] arch: powerpc: add eSDHC node to p1020 dts
by Yinbo Zhu 17 Sep '19

17 Sep '19

This patch is to add eSDHC node to p1020 dts Signed-off-by: Yinbo Zhu <yinbo.zhu(a)nxp.com> --- arch/powerpc/dts/p1020-post.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi index 1e5e67804b..fb3b203a24 100644 --- a/arch/powerpc/dts/p1020-post.dtsi +++ b/arch/powerpc/dts/p1020-post.dtsi @@ -24,6 +24,13 @@ single-cpu-affinity; last-interrupt-source = <255>; }; + + esdhc: esdhc@2e000 { + compatible = "fsl,esdhc"; + reg = <0x2e000 0x1000>; + /* Filled in by U-Boot */ + clock-frequency = <0>; + }; }; /* PCIe controller base address 0x9000 */ -- 2.17.1

2 20

[U-Boot] imx6dl_mamoj broken
by Stefano Babic 17 Sep '19

17 Sep '19

Hi Raffaele, hi Simone, your imx6dl_mamoj is broken on u-boot-imx. Reason is that SPL overrruns and it is bigger as the OCRAM on the DL SOC. arm: + imx6dl_mamoj +spl/u-boot-spl.bin exceeds file size limit: + limit: 53248 bytes + actual: 58597 bytes + excess: 5349 bytes +make[1]: *** [spl/u-boot-spl.bin] Error 1 +make[1]: *** Deleting file `spl/u-boot-spl.bin' +make: *** [sub-make] Error 2 Can you check it and fix it, please ? You see the error here: https://travis-ci.org/sbabic/u-boot-imx/jobs/584953098 Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic(a)denx.de =====================================================================

5 10

[U-Boot] [PATCH v2 1/7] imx8: Add lpcg driver for iMX8QM/QXP
by Ye Li 17 Sep '19

17 Sep '19

Each module may have one or more lpcg registers for SW/HW enabling its clocks. Add lpcg register address and its driver for accessing lpcg. Signed-off-by: Ye Li <ye.li(a)nxp.com> --- Changes in v2: - Fix license and blank line arch/arm/include/asm/arch-imx8/imx8qm_lpcg.h | 198 ++++++++++++++++++++++++++ arch/arm/include/asm/arch-imx8/imx8qxp_lpcg.h | 192 +++++++++++++++++++++++++ arch/arm/include/asm/arch-imx8/lpcg.h | 25 ++++ arch/arm/mach-imx/imx8/Makefile | 2 +- arch/arm/mach-imx/imx8/lpcg.c | 114 +++++++++++++++ 5 files changed, 530 insertions(+), 1 deletion(-) create mode 100644 arch/arm/include/asm/arch-imx8/imx8qm_lpcg.h create mode 100644 arch/arm/include/asm/arch-imx8/imx8qxp_lpcg.h create mode 100644 arch/arm/include/asm/arch-imx8/lpcg.h create mode 100644 arch/arm/mach-imx/imx8/lpcg.c diff --git a/arch/arm/include/asm/arch-imx8/imx8qm_lpcg.h b/arch/arm/include/asm/arch-imx8/imx8qm_lpcg.h new file mode 100644 index 0000000..718dac4 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/imx8qm_lpcg.h @@ -0,0 +1,198 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#ifndef _SC_LPCG_H +#define _SC_LPCG_H + +/*LSIO SS */ +#define PWM_0_LPCG 0x5D400000 +#define PWM_1_LPCG 0x5D410000 +#define PWM_2_LPCG 0x5D420000 +#define PWM_3_LPCG 0x5D430000 +#define PWM_4_LPCG 0x5D440000 +#define PWM_5_LPCG 0x5D450000 +#define PWM_6_LPCG 0x5D460000 +#define PWM_7_LPCG 0x5D470000 +#define GPIO_0_LPCG 0x5D480000 +#define GPIO_1_LPCG 0x5D490000 +#define GPIO_2_LPCG 0x5D4A0000 +#define GPIO_3_LPCG 0x5D4B0000 +#define GPIO_4_LPCG 0x5D4C0000 +#define GPIO_5_LPCG 0x5D4D0000 +#define GPIO_6_LPCG 0x5D4E0000 +#define GPIO_7_LPCG 0x5D4F0000 +#define FSPI_0_LPCG 0x5D520000 +#define FSPI_1_LPCG 0x5D530000 +#define GPT_0_LPCG 0x5D540000 +#define GPT_1_LPCG 0x5D550000 +#define GPT_2_LPCG 0x5D560000 +#define GPT_3_LPCG 0x5D570000 +#define GPT_4_LPCG 0x5D580000 +#define OCRAM_LPCG 0x5D590000 +#define KPP_LPCG 0x5D5A0000 +#define MU_5A_LPCG 0x5D600000 +#define MU_6A_LPCG 0x5D610000 +#define MU_7A_LPCG 0x5D620000 +#define MU_8A_LPCG 0x5D630000 +#define MU_9A_LPCG 0x5D640000 +#define MU_10A_LPCG 0x5D650000 +#define MU_11A_LPCG 0x5D660000 +#define MU_12A_LPCG 0x5D670000 +#define MU_13A_LPCG 0x5D680000 + +/* HSIO SS */ +#define CRR_5_LPCG 0x5F0F0000 +#define CRR_4_LPCG 0x5F0E0000 +#define CRR_3_LPCG 0x5F0D0000 +#define CRR_2_LPCG 0x5F0C0000 +#define CRR_1_LPCG 0x5F0B0000 +#define CRR_0_LPCG 0x5F0A0000 +#define PHY_1_LPCG 0x5F090000 +#define PHY_2_LPCG 0x5F080000 +#define SATA_0_LPCG 0x5F070000 +#define PCIE_B_LPCG 0x5F060000 +#define PCIE_A_LPCG 0x5F050000 + +/* DMA SS */ +#define FLEX_CAN_2_LPCG 0x5ACF0000 +#define FLEX_CAN_1_LPCG 0x5ACE0000 +#define FLEX_CAN_0_LPCG 0x5ACD0000 +#define FTM_1_LPCG 0x5ACB0000 +#define FTM_0_LPCG 0x5ACA0000 +#define ADC_1_LPCG 0x5AC90000 +#define ADC_0_LPCG 0x5AC80000 +#define LPI2C_4_LPCG 0x5AC40000 +#define LPI2C_3_LPCG 0x5AC30000 +#define LPI2C_2_LPCG 0x5AC20000 +#define LPI2C_1_LPCG 0x5AC10000 +#define LPI2C_0_LPCG 0x5AC00000 +#define EMVSIM_1_LPCG 0x5A4E0000 +#define EMVSIM_0_LPCG 0x5A4D0000 +#define LPUART_4_LPCG 0x5A4A0000 +#define LPUART_3_LPCG 0x5A490000 +#define LPUART_2_LPCG 0x5A480000 +#define LPUART_1_LPCG 0x5A470000 +#define LPUART_0_LPCG 0x5A460000 +#define LPSPI_3_LPCG 0x5A430000 +#define LPSPI_2_LPCG 0x5A420000 +#define LPSPI_1_LPCG 0x5A410000 +#define LPSPI_0_LPCG 0x5A400000 + +/* Display SS */ +#define DC_0_LPCG 0x56010000 +#define DC_1_LPCG 0x57010000 + +/* LVDS */ +#define DI_LVDS_0_LPCG 0x56243000 +#define DI_LVDS_1_LPCG 0x57243000 + +/* DI HDMI */ +#define DI_HDMI_LPCG 0x56263000 + +/* RX-HDMI */ +#define RX_HDMI_LPCG 0x58263000 + +/* MIPI CSI SS */ +#define MIPI_CSI_0_LPCG 0x58223000 +#define MIPI_CSI_1_LPCG 0x58243000 + +/* MIPI DSI SS */ +#define MIPI_DSI_0_LPCG 0x56223000 +#define MIPI_DSI_1_LPCG 0x57223000 + +/* Imaging SS */ +#define IMG_JPEG_ENC_LPCG 0x585F0000 +#define IMG_JPEG_DEC_LPCG 0x585D0000 +#define IMG_PXL_LINK_DC1_LPCG 0x585C0000 +#define IMG_PXL_LINK_DC0_LPCG 0x585B0000 +#define IMG_PXL_LINK_HDMI_LPCG 0x585A0000 +#define IMG_PXL_LINK_CSI1_LPCG 0x58590000 +#define IMG_PXL_LINK_CSI0_LPCG 0x58580000 +#define IMG_PDMA_7_LPCG 0x58570000 +#define IMG_PDMA_6_LPCG 0x58560000 +#define IMG_PDMA_5_LPCG 0x58550000 +#define IMG_PDMA_4_LPCG 0x58540000 +#define IMG_PDMA_3_LPCG 0x58530000 +#define IMG_PDMA_2_LPCG 0x58520000 +#define IMG_PDMA_1_LPCG 0x58510000 +#define IMG_PDMA_0_LPCG 0x58500000 + +/* HSIO SS */ +#define HSIO_GPIO_LPCG 0x5F100000 +#define HSIO_MISC_LPCG 0x5F0F0000 +#define HSIO_SATA_CRR4_LPCG 0x5F0E0000 +#define HSIO_PCIE_X1_CRR3_LPCG 0x5F0D0000 +#define HSIO_PCIE_X2_CRR2_LPCG 0x5F0C0000 +#define HSIO_PHY_X1_CRR1_LPCG 0x5F0B0000 +#define HSIO_PHY_X2_CRR0_LPCG 0x5F0A0000 +#define HSIO_PHY_X1_LPCG 0x5F090000 +#define HSIO_PHY_X2_LPCG 0x5F080000 +#define HSIO_SATA_LPCG 0x5F070000 +#define HSIO_PCIE_X1_LPCG 0x5F060000 +#define HSIO_PCIE_X2_LPCG 0x5F050000 + +/* M4 SS */ +#define M4_0_I2C_LPCG 0x37630000 +#define M4_0_LPUART_LPCG 0x37620000 +#define M4_0_LPIT_LPCG 0x37610000 +#define M4_1_I2C_LPCG 0x3B630000 +#define M4_1_LPUART_LPCG 0x3B620000 +#define M4_1_LPIT_LPCG 0x3B610000 + +/* Audio SS */ +#define AUD_ASRC_0_LPCG 0x59400000 +#define AUD_ESAI_0_LPCG 0x59410000 +#define AUD_SPDIF_0_LPCG 0x59420000 +#define AUD_SPDIF_1_LPCG 0x59430000 +#define AUD_SAI_0_LPCG 0x59440000 +#define AUD_SAI_1_LPCG 0x59450000 +#define AUD_SAI_2_LPCG 0x59460000 +#define AUD_SAI_3_LPCG 0x59470000 +#define AUD_HDMI_RX_SAI_0_LPCG 0x59480000 +#define AUD_HDMI_TX_SAI_0_LPCG 0x59490000 +#define AUD_GPT_5_LPCG 0x594B0000 +#define AUD_GPT_6_LPCG 0x594C0000 +#define AUD_GPT_7_LPCG 0x594D0000 +#define AUD_GPT_8_LPCG 0x594E0000 +#define AUD_GPT_9_LPCG 0x594F0000 +#define AUD_GPT_10_LPCG 0x59500000 +#define AUD_DSP_LPCG 0x59580000 +#define AUD_OCRAM_LPCG 0x59590000 +#define AUD_EDMA_0_LPCG 0x595f0000 +#define AUD_ASRC_1_LPCG 0x59c00000 +#define AUD_ESAI_1_LPCG 0x59c10000 +#define AUD_SAI_6_LPCG 0x59c20000 +#define AUD_SAI_7_LPCG 0x59c30000 +#define AUD_AMIX_LPCG 0x59c40000 +#define AUD_MQS_LPCG 0x59c50000 +#define AUD_ACM_LPCG 0x59c60000 +#define AUD_REC_CLK0_LPCG 0x59d00000 +#define AUD_REC_CLK1_LPCG 0x59d10000 +#define AUD_PLL_CLK0_LPCG 0x59d20000 +#define AUD_PLL_CLK1_LPCG 0x59d30000 +#define AUD_MCLKOUT0_LPCG 0x59d50000 +#define AUD_MCLKOUT1_LPCG 0x59d60000 +#define AUD_EDMA_1_LPCG 0x59df0000 + +/* Connectivity SS */ +#define USDHC_0_LPCG 0x5B200000 +#define USDHC_1_LPCG 0x5B210000 +#define USDHC_2_LPCG 0x5B220000 +#define ENET_0_LPCG 0x5B230000 +#define ENET_1_LPCG 0x5B240000 +#define DTCP_LPCG 0x5B250000 +#define MLB_LPCG 0x5B260000 +#define USB_2_LPCG 0x5B270000 +#define USB_3_LPCG 0x5B280000 +#define NAND_LPCG 0x5B290000 +#define EDMA_LPCG 0x5B2A0000 + +/* CM40 SS */ +#define CM40_I2C_LPCG 0x37630000 + +/* CM41 SS */ +#define CM41_I2C_LPCG 0x3B630000 + +#endif diff --git a/arch/arm/include/asm/arch-imx8/imx8qxp_lpcg.h b/arch/arm/include/asm/arch-imx8/imx8qxp_lpcg.h new file mode 100644 index 0000000..074b208 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/imx8qxp_lpcg.h @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#ifndef _SC_LPCG_H +#define _SC_LPCG_H + +/*LSIO SS */ +#define PWM_0_LPCG 0x5D400000 +#define PWM_1_LPCG 0x5D410000 +#define PWM_2_LPCG 0x5D420000 +#define PWM_3_LPCG 0x5D430000 +#define PWM_4_LPCG 0x5D440000 +#define PWM_5_LPCG 0x5D450000 +#define PWM_6_LPCG 0x5D460000 +#define PWM_7_LPCG 0x5D470000 +#define GPIO_0_LPCG 0x5D480000 +#define GPIO_1_LPCG 0x5D490000 +#define GPIO_2_LPCG 0x5D4A0000 +#define GPIO_3_LPCG 0x5D4B0000 +#define GPIO_4_LPCG 0x5D4C0000 +#define GPIO_5_LPCG 0x5D4D0000 +#define GPIO_6_LPCG 0x5D4E0000 +#define GPIO_7_LPCG 0x5D4F0000 +#define FSPI_0_LPCG 0x5D520000 +#define FSPI_1_LPCG 0x5D530000 +#define GPT_0_LPCG 0x5D540000 +#define GPT_1_LPCG 0x5D550000 +#define GPT_2_LPCG 0x5D560000 +#define GPT_3_LPCG 0x5D570000 +#define GPT_4_LPCG 0x5D580000 +#define OCRAM_LPCG 0x5D590000 +#define KPP_LPCG 0x5D5A0000 +#define ROMCP_LPCG 0x5D500000 +#define MU_5A_LPCG 0x5D600000 +#define MU_6A_LPCG 0x5D610000 +#define MU_7A_LPCG 0x5D620000 +#define MU_8A_LPCG 0x5D630000 +#define MU_9A_LPCG 0x5D640000 +#define MU_10A_LPCG 0x5D650000 +#define MU_11A_LPCG 0x5D660000 +#define MU_12A_LPCG 0x5D670000 +#define MU_13A_LPCG 0x5D680000 + +/* HSIO SS */ +#define CRR_5_LPCG 0x5F0F0000 +#define CRR_4_LPCG 0x5F0E0000 +#define CRR_3_LPCG 0x5F0D0000 +#define CRR_2_LPCG 0x5F0C0000 +#define CRR_1_LPCG 0x5F0B0000 +#define CRR_0_LPCG 0x5F0A0000 +#define PHY_1_LPCG 0x5F090000 +#define PHY_2_LPCG 0x5F080000 +#define SATA_0_LPCG 0x5F070000 +#define PCIE_B_LPCG 0x5F060000 +#define PCIE_A_LPCG 0x5F050000 + +/* DMA SS */ +#define FLEX_CAN_2_LPCG 0x5ACF0000 +#define FLEX_CAN_1_LPCG 0x5ACE0000 +#define FLEX_CAN_0_LPCG 0x5ACD0000 +#define FTM_1_LPCG 0x5ACB0000 +#define FTM_0_LPCG 0x5ACA0000 +#define ADC_0_LPCG 0x5AC80000 +#define LPI2C_3_LPCG 0x5AC30000 +#define LPI2C_2_LPCG 0x5AC20000 +#define LPI2C_1_LPCG 0x5AC10000 +#define LPI2C_0_LPCG 0x5AC00000 +#define PWM_LPCG 0x5A590000 +#define LCD_LPCG 0x5A580000 +#define LPUART_3_LPCG 0x5A490000 +#define LPUART_2_LPCG 0x5A480000 +#define LPUART_1_LPCG 0x5A470000 +#define LPUART_0_LPCG 0x5A460000 +#define LPSPI_3_LPCG 0x5A430000 +#define LPSPI_2_LPCG 0x5A420000 +#define LPSPI_1_LPCG 0x5A410000 +#define LPSPI_0_LPCG 0x5A400000 + +/* Display SS */ +#define DC_0_LPCG 0x56010000 +#define DC_1_LPCG 0x57010000 + +/* LVDS */ +#define DI_LVDS_0_LPCG 0x56243000 +#define DI_LVDS_1_LPCG 0x57243000 + +/* DI HDMI */ +#define DI_HDMI_LPCG 0x56263000 + +/* RX-HDMI */ +#define RX_HDMI_LPCG 0x58263000 + +/* MIPI CSI SS */ +#define MIPI_CSI_0_LPCG 0x58223000 +#define MIPI_CSI_1_LPCG 0x58243000 + +/* PARALLEL CSI SS */ +#define PARALLEL_CSI_LPCG 0x58263000 + +/* Display MIPI SS */ +#define DI_MIPI0_LPCG 0x56223000 +#define DI_MIPI1_LPCG 0x56243000 + +/* Imaging SS */ +#define IMG_JPEG_ENC_LPCG 0x585F0000 +#define IMG_JPEG_DEC_LPCG 0x585D0000 +#define IMG_PXL_LINK_DC1_LPCG 0x585C0000 +#define IMG_PXL_LINK_DC0_LPCG 0x585B0000 +#define IMG_PXL_LINK_HDMI_LPCG 0x585A0000 +#define IMG_PXL_LINK_CSI1_LPCG 0x58590000 +#define IMG_PXL_LINK_CSI0_LPCG 0x58580000 +#define IMG_PDMA_7_LPCG 0x58570000 +#define IMG_PDMA_6_LPCG 0x58560000 +#define IMG_PDMA_5_LPCG 0x58550000 +#define IMG_PDMA_4_LPCG 0x58540000 +#define IMG_PDMA_3_LPCG 0x58530000 +#define IMG_PDMA_2_LPCG 0x58520000 +#define IMG_PDMA_1_LPCG 0x58510000 +#define IMG_PDMA_0_LPCG 0x58500000 + +/* HSIO SS */ +#define HSIO_GPIO_LPCG 0x5F100000 +#define HSIO_MISC_LPCG 0x5F0F0000 +#define HSIO_SATA_CRR4_LPCG 0x5F0E0000 +#define HSIO_PCIE_X1_CRR3_LPCG 0x5F0D0000 +#define HSIO_PCIE_X2_CRR2_LPCG 0x5F0C0000 +#define HSIO_PHY_X1_CRR1_LPCG 0x5F0B0000 +#define HSIO_PHY_X2_CRR0_LPCG 0x5F0A0000 +#define HSIO_PHY_X1_LPCG 0x5F090000 +#define HSIO_PHY_X2_LPCG 0x5F080000 +#define HSIO_SATA_LPCG 0x5F070000 +#define HSIO_PCIE_X1_LPCG 0x5F060000 +#define HSIO_PCIE_X2_LPCG 0x5F050000 + +/* M4 SS */ +#define M4_0_I2C_LPCG 0x37630000 +#define M4_0_LPUART_LPCG 0x37620000 +#define M4_0_LPIT_LPCG 0x37610000 +#define M4_1_I2C_LPCG 0x3B630000 +#define M4_1_LPUART_LPCG 0x3B620000 +#define M4_1_LPIT_LPCG 0x3B610000 + +/* Audio SS */ +#define AUD_ASRC_0_LPCG 0x59400000 +#define AUD_ESAI_0_LPCG 0x59410000 +#define AUD_SPDIF_0_LPCG 0x59420000 +#define AUD_SAI_0_LPCG 0x59440000 +#define AUD_SAI_1_LPCG 0x59450000 +#define AUD_SAI_2_LPCG 0x59460000 +#define AUD_SAI_3_LPCG 0x59470000 +#define AUD_GPT_5_LPCG 0x594B0000 +#define AUD_GPT_6_LPCG 0x594C0000 +#define AUD_GPT_7_LPCG 0x594D0000 +#define AUD_GPT_8_LPCG 0x594E0000 +#define AUD_GPT_9_LPCG 0x594F0000 +#define AUD_GPT_10_LPCG 0x59500000 +#define AUD_DSP_LPCG 0x59580000 +#define AUD_OCRAM_LPCG 0x59590000 +#define AUD_EDMA_0_LPCG 0x595f0000 +#define AUD_ASRC_1_LPCG 0x59c00000 +#define AUD_SAI_4_LPCG 0x59c20000 +#define AUD_SAI_5_LPCG 0x59c30000 +#define AUD_AMIX_LPCG 0x59c40000 +#define AUD_MQS_LPCG 0x59c50000 +#define AUD_ACM_LPCG 0x59c60000 +#define AUD_REC_CLK0_LPCG 0x59d00000 +#define AUD_REC_CLK1_LPCG 0x59d10000 +#define AUD_PLL_CLK0_LPCG 0x59d20000 +#define AUD_PLL_CLK1_LPCG 0x59d30000 +#define AUD_MCLKOUT0_LPCG 0x59d50000 +#define AUD_MCLKOUT1_LPCG 0x59d60000 +#define AUD_EDMA_1_LPCG 0x59df0000 + +/* Connectivity SS */ +#define USDHC_0_LPCG 0x5B200000 +#define USDHC_1_LPCG 0x5B210000 +#define USDHC_2_LPCG 0x5B220000 +#define ENET_0_LPCG 0x5B230000 +#define ENET_1_LPCG 0x5B240000 +#define DTCP_LPCG 0x5B250000 +#define MLB_LPCG 0x5B260000 +#define USB_2_LPCG 0x5B270000 +#define USB_3_LPCG 0x5B280000 +#define NAND_LPCG 0x5B290000 +#define EDMA_LPCG 0x5B2A0000 + +/* CM40 SS */ +#define CM40_I2C_LPCG 0x37630000 + +#endif diff --git a/arch/arm/include/asm/arch-imx8/lpcg.h b/arch/arm/include/asm/arch-imx8/lpcg.h new file mode 100644 index 0000000..9ba4bb4 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/lpcg.h @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#ifndef __ASM_ARCH_IMX8_LPCG_H__ +#define __ASM_ARCH_IMX8_LPCG_H__ + +#if defined(CONFIG_IMX8QM) +#include "imx8qm_lpcg.h" +#elif defined(CONFIG_IMX8QXP) +#include "imx8qxp_lpcg.h" +#else +#error "No lpcg header" +#endif + +void lpcg_clock_off(u32 lpcg_addr, u8 clk); +void lpcg_clock_on(u32 lpcg_addr, u8 clk); +void lpcg_clock_autogate(u32 lpcg_addr, u8 clk); +bool lpcg_is_clock_on(u32 lpcg_addr, u8 clk); +void lpcg_all_clock_off(u32 lpcg_addr); +void lpcg_all_clock_on(u32 lpcg_addr); +void lpcg_all_clock_autogate(u32 lpcg_addr); + +#endif /* __ASM_ARCH_IMX8_LPCG_H__ */ diff --git a/arch/arm/mach-imx/imx8/Makefile b/arch/arm/mach-imx/imx8/Makefile index 31ad169..e23f84f 100644 --- a/arch/arm/mach-imx/imx8/Makefile +++ b/arch/arm/mach-imx/imx8/Makefile @@ -4,4 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += cpu.o iomux.o +obj-y += cpu.o iomux.o lpcg.o diff --git a/arch/arm/mach-imx/imx8/lpcg.c b/arch/arm/mach-imx/imx8/lpcg.c new file mode 100644 index 0000000..621b871 --- /dev/null +++ b/arch/arm/mach-imx/imx8/lpcg.c @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <common.h> +#include <asm/io.h> +#include <linux/errno.h> +#include <asm/arch/lpcg.h> + +#define LPCG_CLOCK_MASK 0x3U +#define LPCG_CLOCK_OFF 0x0U +#define LPCG_CLOCK_ON 0x2U +#define LPCG_CLOCK_AUTO 0x3U +#define LPCG_CLOCK_STOP 0x8U + +#define LPCG_ALL_CLOCK_OFF 0x00000000U +#define LPCG_ALL_CLOCK_ON 0x22222222U +#define LPCG_ALL_CLOCK_AUTO 0x33333333U +#define LPCG_ALL_CLOCK_STOP 0x88888888U + +static inline void lpcg_write(u32 lpcgVal, ulong lpcg_addr) +{ + /* + * Write twice with 4x DSC clock cycles (40x IPS clock cycles) interval + * to work around LPCG issue + */ + writel(lpcgVal, lpcg_addr); + udelay(10); /* 10us is enough. Worst case is 40x IPS cycle (200Mhz) */ + writel(lpcgVal, lpcg_addr); + udelay(10); +} + +void lpcg_clock_off(u32 lpcg_addr, u8 clk) +{ + u32 lpcgVal; + + /* Read from LPCG */ + lpcgVal = readl((ulong)lpcg_addr); + + /* Modify */ + lpcgVal &= ~((u32)(LPCG_CLOCK_MASK) << (clk * 4U)); + lpcgVal |= ((u32)(LPCG_CLOCK_OFF) << (clk * 4U)); + + /* Write to LPCG */ + lpcg_write(lpcgVal, (ulong)lpcg_addr); +} + +void lpcg_clock_on(u32 lpcg_addr, u8 clk) +{ + u32 lpcgVal; + + /* Read from LPCG */ + lpcgVal = readl((ulong)lpcg_addr); + + /* Modify */ + lpcgVal &= ~((u32)(LPCG_CLOCK_MASK) << (clk * 4U)); + lpcgVal |= ((u32)(LPCG_CLOCK_ON) << (clk * 4U)); + + /* Write to LPCG */ + lpcg_write(lpcgVal, (ulong)lpcg_addr); +} + +bool lpcg_is_clock_on(u32 lpcg_addr, u8 clk) +{ + u32 lpcgVal; + + /* Read from LPCG */ + lpcgVal = readl((ulong)lpcg_addr); + lpcgVal = (lpcgVal >> (clk * 4U)) & (u32)(LPCG_CLOCK_MASK); + + if (lpcgVal == LPCG_CLOCK_ON) + return true; + + return false; +} + +void lpcg_clock_autogate(u32 lpcg_addr, u8 clk) +{ + u32 lpcgVal; + + /* Read from LPCG */ + lpcgVal = readl((ulong)lpcg_addr); + + /* Modify */ + lpcgVal &= ~((u32)(LPCG_CLOCK_MASK) << (clk * 4U)); + lpcgVal |= ((u32)(LPCG_CLOCK_AUTO) << (clk * 4U)); + + /* Write to LPCG */ + lpcg_write(lpcgVal, (ulong)lpcg_addr); +} + +void lpcg_all_clock_off(u32 lpcg_addr) +{ + /* Write to LPCG */ + lpcg_write(LPCG_ALL_CLOCK_OFF, (ulong)lpcg_addr); +} + +void lpcg_all_clock_on(u32 lpcg_addr) +{ + /* Write to LPCG */ + lpcg_write(LPCG_ALL_CLOCK_ON, (ulong)lpcg_addr); + + /* Wait for clocks to start */ + while ((readl((ulong)lpcg_addr) & LPCG_ALL_CLOCK_STOP) != 0U) + { + } +} + +void lpcg_all_clock_autogate(u32 lpcg_addr) +{ + /* Write to LPCG */ + lpcg_write(LPCG_ALL_CLOCK_AUTO, (ulong)lpcg_addr); +} -- 2.7.4

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[U-Boot] [PATCH] armv7: ls102xa: Correct entry of SCFG_QSPI_CLKSEL
by Kuldeep Singh 17 Sep '19

17 Sep '19

Previous value "0xC" was reserved. Hence correcting it to new value "0x5" which is ClusterPLL/16. Signed-off-by: Ashish Kumar <Ashish.Kumar(a)nxp.com> Signed-off-by: Kuldeep Singh <kuldeep.singh(a)nxp.com> --- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 137cd61804..f2ba182346 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -155,7 +155,7 @@ struct ccsr_gur { #define SCFG_ETSECCMCR_GE0_CLK125 0x00000000 #define SCFG_ETSECCMCR_GE1_CLK125 0x08000000 #define SCFG_PIXCLKCR_PXCKEN 0x80000000 -#define SCFG_QSPI_CLKSEL 0xc0100000 +#define SCFG_QSPI_CLKSEL 0x50100000 #define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000 #define SCFG_SNPCNFGCR_DCU_RD_WR 0x03000000 #define SCFG_SNPCNFGCR_SATA_RD_WR 0x00c00000 -- 2.17.1

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[U-Boot] [PATCH] core: device: support multiple power domains for one device
by Peng Fan 17 Sep '19

17 Sep '19

When device has multiple power domains, power_domain_get could not able to support that. So let's iterate each power domain and enable it. Signed-off-by: Peng Fan <peng.fan(a)nxp.com> --- drivers/core/device.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/core/device.c b/drivers/core/device.c index 474c1642ee..67fcff87fa 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -311,7 +311,7 @@ int device_probe(struct udevice *dev) const struct driver *drv; int size = 0; int ret; - int seq; + int seq, i, count; if (!dev) return -EINVAL; @@ -390,8 +390,16 @@ int device_probe(struct udevice *dev) if (CONFIG_IS_ENABLED(POWER_DOMAIN) && dev->parent && device_get_uclass_id(dev) != UCLASS_POWER_DOMAIN) { - if (!power_domain_get(dev, &pd)) - power_domain_on(&pd); + count = dev_count_phandle_with_args(dev, "power-domains", + "#power-domain-cells"); + for (i = 0; i < count; i++) { + ret = power_domain_get_by_index(dev, &pd, i); + if (ret) + goto fail; + ret = power_domain_on(&pd); + if (ret) + goto fail; + } } ret = uclass_pre_probe_device(dev); -- 2.16.4

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Re: [U-Boot] [PATCH] rpi3: Enable verified boot from FIT image
by Jun Nie 17 Sep '19

17 Sep '19

Matthias Brugger <mbrugger(a)suse.com> 于2019年7月31日周三下午4:05写道： > > > > On 11/07/2019 05:55, Jun Nie wrote: > > Enable verified boot from FIT image with select configs > > and specify boot script image node in FIT image, the FIT > > image is verified before it is run. > > > > Code that reusing dtb in firmware is disabled, so that > > the dtb with pubic key packed in u-boot.bin can be used > > to verify the signature of next stage FIT image. > > > > Signed-off-by: Jun Nie <jun.nie(a)linaro.org> > > --- > > board/raspberrypi/rpi/rpi.c | 6 ++++++ > > include/configs/rpi.h | 15 ++++++++++++++- > > 2 files changed, 20 insertions(+), 1 deletion(-) > > > > diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c > > index 617c892..950ee84 100644 > > --- a/board/raspberrypi/rpi/rpi.c > > +++ b/board/raspberrypi/rpi/rpi.c > > @@ -297,6 +297,7 @@ static void set_fdtfile(void) > > env_set("fdtfile", fdtfile); > > } > > > > +#ifndef CONFIG_FIT_SIGNATURE > > /* > > * If the firmware provided a valid FDT at boot time, let's expose it in > > * ${fdt_addr} so it may be passed unmodified to the kernel. > > @@ -311,6 +312,7 @@ static void set_fdt_addr(void) > > > > env_set_hex("fdt_addr", fw_dtb_pointer); > > } > > +#endif > > > > /* > > * Prevent relocation from stomping on a firmware provided FDT blob. > > @@ -393,7 +395,9 @@ static void set_serial_number(void) > > > > int misc_init_r(void) > > { > > +#ifndef CONFIG_FIT_SIGNATURE > > set_fdt_addr(); > > +#endif > > set_fdtfile(); > > set_usbethaddr(); > > #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG > > @@ -470,6 +474,7 @@ int board_init(void) > > return bcm2835_power_on_module(BCM2835_MBOX_POWER_DEVID_USB_HCD); > > } > > > > +#ifndef CONFIG_FIT_SIGNATURE > > /* > > * If the firmware passed a device tree use it for U-Boot. > > */ > > @@ -479,6 +484,7 @@ void *board_fdt_blob_setup(void) > > return NULL; > > return (void *)fw_dtb_pointer; > > } > > +#endif > > Just to get this clear we need this because we want to pass the device tree via > OF_SEPARATE, correct? You are right. U-boot need to read he signature from dtb. > > > > > int ft_board_setup(void *blob, bd_t *bd) > > { > > diff --git a/include/configs/rpi.h b/include/configs/rpi.h > > index f76c7d1..ba91205 100644 > > --- a/include/configs/rpi.h > > +++ b/include/configs/rpi.h > > @@ -180,11 +180,24 @@ > > > > #include <config_distro_bootcmd.h> > > > > +#ifdef CONFIG_FIT_SIGNATURE > > +#define FIT_BOOT_CMD \ > > + "boot_a_script=" \ > > + "load ${devtype} ${devnum}:${distro_bootpart} " \ > > + "${scriptaddr} ${prefix}${script}; " \ > > + "iminfo ${scriptaddr};" \ > > + "if test $? -eq 1; then reset; fi;" \ > > + "source ${scriptaddr}:bootscr\0" > > +#else > > +#define FIT_BOOT_CMD "" > > +#endif > > + > > Doesn't this overwrite the boot_a_script in distro_bootcmd? > > Would it make sense to add FIT booting to the distro boot command? > > Regards, > Matthias Yes, it overwrite the boot_a_script in distro_bootcmd. It is make sense to add this to the distro boot command. I can send another patch to move these lines to common code later. > > > #define CONFIG_EXTRA_ENV_SETTINGS \ > > "dhcpuboot=usb start; dhcp u-boot.uimg; bootm\0" \ > > ENV_DEVICE_SETTINGS \ > > ENV_MEM_LAYOUT_SETTINGS \ > > - BOOTENV > > + BOOTENV \ > > + FIT_BOOT_CMD > > > > > > #endif > >

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[U-Boot] [PATCH v1 0/8] power: pmic: support more PMIC
by Elaine Zhang 17 Sep '19

17 Sep '19

Support more PMIC and improve compatibility between pmics. Elaine Zhang (2): power: pmic: rk816: support rk816 pmic power: pmic: rk805: support rk805 pmic Joseph Chen (6): dm: regulator: support regulator more state power: pmic: rk8xx: bind more function dm: pmic: add pmic_shutdown() interface power: pmic: rk8xx: add pmic_shutdown() implement pmic: add RK817 support pmic: add rk809 support drivers/power/pmic/pmic-uclass.c | 11 + drivers/power/pmic/rk8xx.c | 173 +++++- drivers/power/regulator/regulator-uclass.c | 67 ++ drivers/power/regulator/rk8xx.c | 940 ++++++++++++++++++++++++++--- include/power/pmic.h | 9 + include/power/regulator.h | 42 ++ include/power/rk8xx_pmic.h | 42 ++ 7 files changed, 1196 insertions(+), 88 deletions(-) -- 1.9.1

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[U-Boot] [PATCH] core: of_addr: Correct the size type of of_get_address to fdt_size_t
by Keerthy 17 Sep '19

17 Sep '19

Currently the size parameter is defined as u64 type. Correct the size type of of_get_address to fdt_size_t so that both 64 bit and 32 bit architectures are taken care of. The initial bug report: https://patchwork.ozlabs.org/patch/1090094/#2212555 Fixes: e679d03b08fb ("core: ofnode: Add ofnode_get_addr_size_index") Reported-by: Eugeniu Rosca <rosca.eugeniu(a)gmail.com> Tested-by: Eugeniu Rosca <rosca.eugeniu(a)gmail.com> Signed-off-by: Keerthy <j-keerthy(a)ti.com> --- Changes from RFT: * Fixed a typo in the commit log. * Added Reported-by: Eugeniu Rosca <rosca.eugeniu(a)gmail.com> Tested-by: Eugeniu Rosca <rosca.eugeniu(a)gmail.com> drivers/core/of_addr.c | 4 ++-- drivers/core/ofnode.c | 2 +- include/dm/of_addr.h | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/core/of_addr.c b/drivers/core/of_addr.c index 4e256d9926..812a400b19 100644 --- a/drivers/core/of_addr.c +++ b/drivers/core/of_addr.c @@ -122,7 +122,7 @@ static void dev_count_cells(const struct device_node *np, int *nap, int *nsp) } const __be32 *of_get_address(const struct device_node *dev, int index, - u64 *size, unsigned int *flags) + fdt_size_t *size, unsigned int *flags) { const __be32 *prop; int psize; @@ -347,7 +347,7 @@ int of_address_to_resource(const struct device_node *dev, int index, struct resource *r) { const __be32 *addrp; - u64 size; + fdt_size_t size; unsigned int flags; const char *name = NULL; diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index 2ac73af934..b21b5183a3 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -260,7 +260,7 @@ fdt_addr_t ofnode_get_addr_size_index(ofnode node, int index, fdt_size_t *size) uint flags; prop_val = of_get_address(ofnode_to_np(node), index, - (u64 *)size, &flags); + size, &flags); if (!prop_val) return FDT_ADDR_T_NONE; diff --git a/include/dm/of_addr.h b/include/dm/of_addr.h index 3fa1ffce81..52443ef296 100644 --- a/include/dm/of_addr.h +++ b/include/dm/of_addr.h @@ -58,7 +58,7 @@ u64 of_translate_dma_address(const struct device_node *no, const __be32 *in_addr * @return pointer to address which can be read */ const __be32 *of_get_address(const struct device_node *no, int index, - u64 *size, unsigned int *flags); + fdt_size_t *size, unsigned int *flags); struct resource; -- 2.17.1

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[U-Boot] [PATCH] rockchip: Move config SYS_MALLOC_LEN to Kconfig
by Kever Yang 17 Sep '19

17 Sep '19

Use Kconfig for option SYS_MALLOC_LEN and default to 0x2000000. Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- Kconfig | 3 ++- include/configs/rk3036_common.h | 1 - include/configs/rk3128_common.h | 1 - include/configs/rk3188_common.h | 1 - include/configs/rk322x_common.h | 1 - include/configs/rk3288_common.h | 1 - include/configs/rk3328_common.h | 1 - include/configs/rk3368_common.h | 1 - include/configs/rk3399_common.h | 1 - include/configs/rv1108_common.h | 1 - 10 files changed, 2 insertions(+), 10 deletions(-) diff --git a/Kconfig b/Kconfig index d2eb744e70..d5538dd3f4 100644 --- a/Kconfig +++ b/Kconfig @@ -156,7 +156,8 @@ config SYS_MALLOC_F_LEN config SYS_MALLOC_LEN hex "Define memory for Dynamic allocation" - depends on ARCH_ZYNQ || ARCH_VERSAL || ARCH_STM32MP + depends on ARCH_ZYNQ || ARCH_VERSAL || ARCH_STM32MP || ARCH_ROCKCHIP + default 0x2000000 if ARCH_ROCKCHIP help This defines memory to be allocated for Dynamic allocation TODO: Use for other architectures diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index 66331a1376..7f148eff87 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -8,7 +8,6 @@ #include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" -#define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h index d12696d6b3..be55fb73ed 100644 --- a/include/configs/rk3128_common.h +++ b/include/configs/rk3128_common.h @@ -10,7 +10,6 @@ #define CONFIG_SYS_MAXARGS 16 #define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index 44e8d0ccd2..3bcc04808a 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -12,7 +12,6 @@ #include "rockchip-common.h" #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY -#define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index f2fb7e07b9..7e0c831174 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -9,7 +9,6 @@ #include "rockchip-common.h" #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 84b474ac7b..4a62da3ef7 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -12,7 +12,6 @@ #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* 16MB */ #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY -#define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_ROCKCHIP_STIMER_BASE 0xff810020 diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 6ed7525304..f8b56bae4f 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -12,7 +12,6 @@ #define CONFIG_ROCKCHIP_STIMER_BASE 0xff1d0020 -#define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index 340413dbba..e4b2114a0d 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -16,7 +16,6 @@ #define CONFIG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 #define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 12ad60d443..a5e69b26ad 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -8,7 +8,6 @@ #include "rockchip-common.h" -#define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h index 691aa51e98..758e85e89d 100644 --- a/include/configs/rv1108_common.h +++ b/include/configs/rv1108_common.h @@ -10,7 +10,6 @@ #define CONFIG_IRAM_BASE 0x10080000 -#define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT -- 2.17.1

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[U-Boot] [PATCH 0/3] Raspberry Pi4: add support for DFU over USB
by Marek Szyprowski 17 Sep '19

17 Sep '19

Hi All This patchset enables support for DFU over USB protocol on Raspberry Pi4 board. The board has DWC2 UDC controller connected to the USB-C power connector. Enabling DFU on it, make the u-boot development much more convenient, as one no longer needs to swap SD-card between RPi4 board and host machine to update the u-boot binary. Patches are based on current 'master' u-boot branch. They were tested on the 2019-07-10-raspbian-buster-lite.img sd-card image with the following lines added to config.txt: dtoverlay=dwc2,dr_mode=peripheral dtparam=i2c_arm=on dtparam=spi=on enable_uart=1 uart_2ndstage=1 kernel=u-boot.bin To enable DFU, one has to enter follwing command: # dfu 0 mmc 0 During the development of this feature I've encountered a serious bug in FAT write code. Over-writing discontiguous files always caused serious filesystem corruption. This was especially anoying, because the system environment is kept on FAT volume in uboot.env file, so 'saveenv' basically corrupted the boot partiting on the second call. I hope that my fix for FAT code will be helpful for non-RPi users too. Best regards Marek Szyprowski Samsung R&D Institute Poland Patch summary: Marek Szyprowski (3): fat: write: fix broken write to fragmented files usb: dwc2_udc_otg: add bcm2835 SoC (Raspberry Pi4) support config: enable DFU over USB on Raspberry Pi4 boards configs/rpi_4_32b_defconfig | 11 +++++++++++ drivers/usb/gadget/dwc2_udc_otg.c | 2 ++ drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c | 12 ++++++------ fs/fat/fat_write.c | 6 +++--- include/configs/rpi.h | 10 ++++++++++ 5 files changed, 32 insertions(+), 9 deletions(-) -- 2.17.1

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