September 2019 - U-Boot

[U-Boot] [PATCH v4 00/17] Add Intel Agilex SoC support
by Ley Foon Tan 04 Oct '19

04 Oct '19

This is 4th version of patchset to add Intel Agilex SoC[1] support. Most of changes are related to _SOC64 prefix change and use base address from DT for managers access. Detail changelog can find in commit message. This patchset needs to apply after patchset in [2] for manager driver struct to defines conversion. Patch status: No change: Patch 1, 4, 6, 7, 10, 11, 14, 17 Have changes: Patch 2, 3, 5, 8, 9, 12, 13, 15, 16 Detail change log is in patch commit message. Intel Agilex SoC is with a 64-bit quad core ARM Cortex-A53 MPCore hard processor system (HPS). New IPs in Agilex are CCU, clock manager and SDRAM, other IPs have minor changes compared to Stratix 10. Intel Agilex HPS TRM: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb… v3->v4: ------- - Rename _S10 to _SOC64 perfix for S10 and Agilex common defines. - Use base address from DT for managers access. - Add u-boot,dm-pre-reloc to sysmgr node in dts History: --------- [v1]: https://patchwork.ozlabs.org/cover/1097830/ [v2]: https://patchwork.ozlabs.org/cover/1127440/ [v3]: https://patchwork.ozlabs.org/cover/1149863/ [1]: https://www.intel.com/content/www/us/en/products/programmable/fpga/agilex.h… [2]: https://patchwork.ozlabs.org/cover/1160079/ Ley Foon Tan (17): arm: socfpga: agilex: Add base address for Intel Agilex SoC arm: socfpga: Move firewall code to firewall file arm: socfpga: Move Stratix10 and Agilex reset manager common code arm: socfpga: agilex: Add reset manager support arm: socfpga: Move Stratix10 and Agilex system manager common code arm: socfpga: agilex: Add system manager support arm: socfpga: Move Stratix10 and Agilex clock manager common code clk: agilex: Add clock driver for Agilex arm: socfpga: agilex: Add clock wrapper functions arm: socfpga: agilex: Add CCU support for Agilex arm: agilex: Add clock handoff offset for Agilex ddr: altera: Restructure Stratix 10 SDRAM driver ddr: altera: agilex: Add SDRAM driver for Agilex board: intel: agilex: Add socdk board support for Intel Agilex SoC arm: socfpga: agilex: Add SPL for Agilex SoC arm: dts: agilex: Add base dtsi and devkit dts arm: socfpga: agilex: Enable Agilex SoC build arch/arm/Kconfig | 4 +- arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_agilex.dtsi | 495 +++++++++++++++ arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 75 +++ arch/arm/dts/socfpga_agilex_socdk.dts | 136 ++++ arch/arm/mach-socfpga/Kconfig | 15 + arch/arm/mach-socfpga/Makefile | 18 + arch/arm/mach-socfpga/ccu_agilex.c | 99 +++ arch/arm/mach-socfpga/clock_manager_agilex.c | 84 +++ arch/arm/mach-socfpga/clock_manager_s10.c | 2 +- .../mach-socfpga/{spl_s10.c => firewall.c} | 122 +--- .../mach-socfpga/include/mach/base_addr_s10.h | 4 + .../mach-socfpga/include/mach/ccu_agilex.h | 67 ++ .../mach-socfpga/include/mach/clock_manager.h | 2 + .../include/mach/clock_manager_agilex.h | 14 + .../include/mach/clock_manager_s10.h | 16 +- .../include/mach/clock_manager_soc64.h | 23 + .../mach/{firewall_s10.h => firewall.h} | 10 +- .../mach-socfpga/include/mach/handoff_s10.h | 9 +- .../mach-socfpga/include/mach/reset_manager.h | 2 + .../include/mach/reset_manager_agilex.h | 11 + .../include/mach/reset_manager_s10.h | 87 +-- .../include/mach/reset_manager_soc64.h | 38 ++ .../include/mach/system_manager.h | 2 + .../include/mach/system_manager_agilex.h | 11 + .../include/mach/system_manager_s10.h | 116 +--- .../include/mach/system_manager_soc64.h | 123 ++++ arch/arm/mach-socfpga/mailbox_s10.c | 2 +- arch/arm/mach-socfpga/misc.c | 4 + arch/arm/mach-socfpga/misc_s10.c | 4 +- arch/arm/mach-socfpga/reset_manager_s10.c | 34 +- arch/arm/mach-socfpga/spl_agilex.c | 95 +++ arch/arm/mach-socfpga/spl_s10.c | 95 +-- arch/arm/mach-socfpga/system_manager_s10.c | 26 +- arch/arm/mach-socfpga/wrap_pll_config_s10.c | 13 +- board/intel/agilex-socdk/MAINTAINERS | 7 + board/intel/agilex-socdk/Makefile | 7 + board/intel/agilex-socdk/socfpga.c | 7 + configs/socfpga_agilex_defconfig | 59 ++ drivers/clk/altera/Makefile | 1 + drivers/clk/altera/clk-agilex.c | 579 ++++++++++++++++++ drivers/clk/altera/clk-agilex.h | 237 +++++++ drivers/ddr/altera/Kconfig | 6 +- drivers/ddr/altera/Makefile | 3 +- drivers/ddr/altera/sdram_agilex.c | 168 +++++ drivers/ddr/altera/sdram_s10.c | 298 +-------- drivers/ddr/altera/sdram_s10.h | 148 +---- drivers/ddr/altera/sdram_soc64.c | 304 +++++++++ .../ddr/altera/{sdram_s10.h => sdram_soc64.h} | 71 ++- include/configs/socfpga_agilex_socdk.h | 207 +++++++ .../dt-bindings/clock/socfpga-soc64-clock.h | 84 +++ 51 files changed, 3105 insertions(+), 940 deletions(-) create mode 100644 arch/arm/dts/socfpga_agilex.dtsi create mode 100644 arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_agilex_socdk.dts create mode 100644 arch/arm/mach-socfpga/ccu_agilex.c create mode 100644 arch/arm/mach-socfpga/clock_manager_agilex.c copy arch/arm/mach-socfpga/{spl_s10.c => firewall.c} (54%) create mode 100644 arch/arm/mach-socfpga/include/mach/ccu_agilex.h create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h rename arch/arm/mach-socfpga/include/mach/{firewall_s10.h => firewall.h} (94%) create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_agilex.h create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_agilex.h create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_soc64.h create mode 100644 arch/arm/mach-socfpga/spl_agilex.c create mode 100644 board/intel/agilex-socdk/MAINTAINERS create mode 100644 board/intel/agilex-socdk/Makefile create mode 100644 board/intel/agilex-socdk/socfpga.c create mode 100644 configs/socfpga_agilex_defconfig create mode 100644 drivers/clk/altera/clk-agilex.c create mode 100644 drivers/clk/altera/clk-agilex.h create mode 100644 drivers/ddr/altera/sdram_agilex.c create mode 100644 drivers/ddr/altera/sdram_soc64.c copy drivers/ddr/altera/{sdram_s10.h => sdram_soc64.h} (79%) create mode 100644 include/configs/socfpga_agilex_socdk.h create mode 100644 include/dt-bindings/clock/socfpga-soc64-clock.h -- 2.19.0

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[U-Boot] [PATCH v2 0/3] efi_loader: disk: install FILE_SYSTEM_PROTOCOL to whole disk
by AKASHI Takahiro 04 Oct '19

04 Oct '19

Changes in v2 (Sept 12, 2019) * add patch#1 and #2 * install the protocol only if a file system does exist AKASHI Takahiro (3): fs: export fs_close() efi_loader: disk: install FILE_SYSTEM_PROTOCOL only if available efi_loader: disk: install file system protocol to a whole disk fs/fs.c | 2 +- include/fs.h | 7 +++++++ lib/efi_loader/efi_disk.c | 19 ++++++++++++++++++- 3 files changed, 26 insertions(+), 2 deletions(-) -- 2.21.0

2 12

[U-Boot] [PATCH v2 0/2] efi_loader: device_path: support Sandbox's host device
by AKASHI Takahiro 04 Oct '19

04 Oct '19

Changes in v2 (Sept 12, 2019) * use "vendor device path" with dedicate guid instead of LUN * add patch#2 for pretty printing AKASHI Takahiro (2): efi_loader: device_path: support Sandbox's "host" devices efi_loader: device_path: show a host device in understandable form include/efi_loader.h | 8 ++++++ lib/efi_loader/efi_device_path.c | 33 ++++++++++++++++++++++++ lib/efi_loader/efi_device_path_to_text.c | 5 ++++ 3 files changed, 46 insertions(+) -- 2.21.0

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[U-Boot] [PATCH] imx: add support for i.MX8MQ power domain controller
by Patrick Wildt 03 Oct '19

03 Oct '19

Add support for the power domain controller that's used on the i.MX8MQ. This will be needed to be able to power on the PCIe controller. Bindings taken from Linux, driver implementation taken from the i.MX8 power domain controller and adjusted for the i.MX8M SoC. Signed-off-by: Patrick Wildt <patrick(a)blueri.se> diff --git a/arch/arm/dts/fsl-imx8mq.dtsi b/arch/arm/dts/fsl-imx8mq.dtsi index 814a1b7df4..fbf5009886 100644 --- a/arch/arm/dts/fsl-imx8mq.dtsi +++ b/arch/arm/dts/fsl-imx8mq.dtsi @@ -19,6 +19,7 @@ #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/pinctrl/pins-imx8mq.h> +#include <dt-bindings/power/imx8mq-power.h> #include <dt-bindings/thermal/thermal.h> / { @@ -71,12 +72,6 @@ interrupt-parent = <&gic>; }; - power: power-controller { - compatible = "fsl,imx8mq-pm-domain"; - num-domains = <11>; - #power-domain-cells = <1>; - }; - pwm2: pwm@30670000 { compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; reg = <0x0 0x30670000 0x0 0x10000>; @@ -276,6 +271,37 @@ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <3>; interrupt-parent = <&gic>; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + /* + * As per comment in ATF source code: + * + * PCIE1 and PCIE2 share the + * same reset signal, if we + * power down PCIE2, PCIE1 + * will be held in reset too. + * + * So instead of creating two + * separate power domains for + * PCIE1 and PCIE2 we create a + * link between both and use + * it as a shared PCIE power + * domain. + */ + pgc_pcie: power-domain@1 { + #power-domain-cells = <0>; + reg = <IMX8M_POWER_DOMAIN_PCIE1>; + power-domains = <&pgc_pcie2>; + }; + + pgc_pcie2: power-domain@a { + #power-domain-cells = <0>; + reg = <IMX8M_POWER_DOMAIN_PCIE2>; + }; + }; }; usdhc1: usdhc@30b40000 { diff --git a/arch/arm/include/asm/arch-imx8m/power-domain.h b/arch/arm/include/asm/arch-imx8m/power-domain.h new file mode 100644 index 0000000000..0f94945894 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8m/power-domain.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2017 NXP + */ + +#ifndef _ASM_ARCH_IMX8M_POWER_DOMAIN_H +#define _ASM_ARCH_IMX8M_POWER_DOMAIN_H + +struct imx8m_power_domain_platdata { + int resource_id; + int has_pd; + struct power_domain pd; +}; + +#endif diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig index e45731edda..6c87a8a1ef 100644 --- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig @@ -35,6 +35,8 @@ CONFIG_FSL_USDHC=y CONFIG_DM_ETH=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX8M=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig index 06bba6220b..7e2d6a90bf 100644 --- a/drivers/power/domain/Kconfig +++ b/drivers/power/domain/Kconfig @@ -23,6 +23,13 @@ config IMX8_POWER_DOMAIN Enable support for manipulating NXP i.MX8 on-SoC power domains via IPC requests to the SCU. +config IMX8M_POWER_DOMAIN + bool "Enable i.MX8M power domain driver" + depends on POWER_DOMAIN && ARCH_IMX8M + help + Enable support for manipulating NXP i.MX8M on-SoC power domains via + requests to the ATF. + config MTK_POWER_DOMAIN bool "Enable the MediaTek power domain driver" depends on POWER_DOMAIN && ARCH_MEDIATEK diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile index 695aafe17d..4d87d7c7f9 100644 --- a/drivers/power/domain/Makefile +++ b/drivers/power/domain/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_$(SPL_)POWER_DOMAIN) += power-domain-uclass.o obj-$(CONFIG_BCM6328_POWER_DOMAIN) += bcm6328-power-domain.o obj-$(CONFIG_IMX8_POWER_DOMAIN) += imx8-power-domain.o +obj-$(CONFIG_IMX8M_POWER_DOMAIN) += imx8m-power-domain.o obj-$(CONFIG_MTK_POWER_DOMAIN) += mtk-power-domain.o obj-$(CONFIG_MESON_GX_VPU_POWER_DOMAIN) += meson-gx-pwrc-vpu.o obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o diff --git a/drivers/power/domain/imx8m-power-domain.c b/drivers/power/domain/imx8m-power-domain.c new file mode 100644 index 0000000000..164fb3d31d --- /dev/null +++ b/drivers/power/domain/imx8m-power-domain.c @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2017 NXP + */ + +#include <common.h> +#include <dm.h> +#include <power-domain-uclass.h> +#include <asm/io.h> +#include <asm/arch/power-domain.h> +#include <asm/mach-imx/sys_proto.h> +#include <dm/device-internal.h> +#include <dm/device.h> +#include <imx_sip.h> + +DECLARE_GLOBAL_DATA_PTR; + +static int imx8m_power_domain_request(struct power_domain *power_domain) +{ + return 0; +} + +static int imx8m_power_domain_free(struct power_domain *power_domain) +{ + return 0; +} + +static int imx8m_power_domain_on(struct power_domain *power_domain) +{ + struct udevice *dev = power_domain->dev; + struct imx8m_power_domain_platdata *pdata; + pdata = dev_get_platdata(dev); + + if (pdata->resource_id < 0) + return -EINVAL; + + if (pdata->has_pd) + power_domain_on(&pdata->pd); + + call_imx_sip(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN, pdata->resource_id, 1); + + return 0; +} + +static int imx8m_power_domain_off(struct power_domain *power_domain) +{ + struct udevice *dev = power_domain->dev; + struct imx8m_power_domain_platdata *pdata; + pdata = dev_get_platdata(dev); + + if (pdata->resource_id < 0) + return -EINVAL; + + call_imx_sip(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN, pdata->resource_id, 0); + + if (pdata->has_pd) + power_domain_off(&pdata->pd); + + return 0; +} + +static int imx8m_power_domain_of_xlate(struct power_domain *power_domain, + struct ofnode_phandle_args *args) +{ + return 0; +} + +static int imx8m_power_domain_bind(struct udevice *dev) +{ + int offset; + const char *name; + int ret = 0; + + offset = dev_of_offset(dev); + for (offset = fdt_first_subnode(gd->fdt_blob, offset); offset > 0; + offset = fdt_next_subnode(gd->fdt_blob, offset)) { + /* Bind the subnode to this driver */ + name = fdt_get_name(gd->fdt_blob, offset, NULL); + + ret = device_bind_with_driver_data(dev, dev->driver, name, + dev->driver_data, + offset_to_ofnode(offset), + NULL); + + if (ret == -ENODEV) + printf("Driver '%s' refuses to bind\n", + dev->driver->name); + + if (ret) + printf("Error binding driver '%s': %d\n", + dev->driver->name, ret); + } + + return 0; +} + +static int imx8m_power_domain_probe(struct udevice *dev) +{ + return 0; +} + +static int imx8m_power_domain_ofdata_to_platdata(struct udevice *dev) +{ + struct imx8m_power_domain_platdata *pdata = dev_get_platdata(dev); + + pdata->resource_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), + "reg", -1); + + if (!power_domain_get(dev, &pdata->pd)) + pdata->has_pd = 1; + + return 0; +} + +static const struct udevice_id imx8m_power_domain_ids[] = { + { .compatible = "fsl,imx8mq-gpc" }, + { } +}; + +struct power_domain_ops imx8m_power_domain_ops = { + .request = imx8m_power_domain_request, + .free = imx8m_power_domain_free, + .on = imx8m_power_domain_on, + .off = imx8m_power_domain_off, + .of_xlate = imx8m_power_domain_of_xlate, +}; + +U_BOOT_DRIVER(imx8m_power_domain) = { + .name = "imx8m_power_domain", + .id = UCLASS_POWER_DOMAIN, + .of_match = imx8m_power_domain_ids, + .bind = imx8m_power_domain_bind, + .probe = imx8m_power_domain_probe, + .ofdata_to_platdata = imx8m_power_domain_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct imx8m_power_domain_platdata), + .ops = &imx8m_power_domain_ops, +}; diff --git a/include/dt-bindings/power/imx8mq-power.h b/include/dt-bindings/power/imx8mq-power.h new file mode 100755 index 0000000000..8a513bd916 --- /dev/null +++ b/include/dt-bindings/power/imx8mq-power.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (C) 2018 Pengutronix, Lucas Stach <kernel(a)pengutronix.de> + */ + +#ifndef __DT_BINDINGS_IMX8MQ_POWER_H__ +#define __DT_BINDINGS_IMX8MQ_POWER_H__ + +#define IMX8M_POWER_DOMAIN_MIPI 0 +#define IMX8M_POWER_DOMAIN_PCIE1 1 +#define IMX8M_POWER_DOMAIN_USB_OTG1 2 +#define IMX8M_POWER_DOMAIN_USB_OTG2 3 +#define IMX8M_POWER_DOMAIN_DDR1 4 +#define IMX8M_POWER_DOMAIN_GPU 5 +#define IMX8M_POWER_DOMAIN_VPU 6 +#define IMX8M_POWER_DOMAIN_DISP 7 +#define IMX8M_POWER_DOMAIN_MIPI_CSI1 8 +#define IMX8M_POWER_DOMAIN_MIPI_CSI2 9 +#define IMX8M_POWER_DOMAIN_PCIE2 10 + +#endif diff --git a/include/imx_sip.h b/include/imx_sip.h index fbb6c5ecdc..139ff61b8a 100644 --- a/include/imx_sip.h +++ b/include/imx_sip.h @@ -6,6 +6,9 @@ #ifndef _IMX_SIP_H__ #define _IMX_SIP_H_ +#define IMX_SIP_GPC 0xC2000000 +#define IMX_SIP_GPC_PM_DOMAIN 0x03 + #define IMX_SIP_SRC 0xC2000005 #define IMX_SIP_SRC_M4_START 0x00 #define IMX_SIP_SRC_M4_STARTED 0x01

1 1

[U-Boot] [PATCH] imx: update i.MX8MQ clocks
by Patrick Wildt 03 Oct '19

03 Oct '19

imx: update i.MX8MQ clocks I would like to add support for additional drivers, and for that it makes sense to update the clock headers first, before adding a node to the device tree. Since no drivers use them so far it's easy to just update the header and adjust the device tree. Signed-off-by: Patrick Wildt <patrick(a)blueri.se> diff --git a/arch/arm/dts/fsl-imx8mq.dtsi b/arch/arm/dts/fsl-imx8mq.dtsi index 814a1b7df4..c35c23e293 100644 --- a/arch/arm/dts/fsl-imx8mq.dtsi +++ b/arch/arm/dts/fsl-imx8mq.dtsi @@ -228,11 +228,11 @@ lcdif: lcdif@30320000 { compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif"; reg = <0x0 0x30320000 0x0 0x10000>; - clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_DIV>, + clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>, <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; clock-names = "pix", "axi", "disp_axi"; - assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_SRC>; + assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>; assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>; assigned-clock-rate = <594000000>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; @@ -283,10 +283,10 @@ reg = <0x0 0x30b40000 0x0 0x10000>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_DUMMY>, - <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>, + <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, <&clk IMX8MQ_CLK_USDHC1_ROOT>; clock-names = "ipg", "ahb", "per"; - assigned-clocks = <&clk IMX8MQ_CLK_USDHC1_DIV>; + assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; assigned-clock-rates = <400000000>; fsl,tuning-start-tap = <20>; fsl,tuning-step= <2>; @@ -299,7 +299,7 @@ reg = <0x0 0x30b50000 0x0 0x10000>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_DUMMY>, - <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>, + <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, <&clk IMX8MQ_CLK_USDHC2_ROOT>; clock-names = "ipg", "ahb", "per"; fsl,tuning-start-tap = <20>; @@ -316,19 +316,18 @@ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>, <&clk IMX8MQ_CLK_ENET1_ROOT>, - <&clk IMX8MQ_CLK_ENET_TIMER_DIV>, - <&clk IMX8MQ_CLK_ENET_REF_DIV>, - <&clk IMX8MQ_CLK_ENET_PHY_REF_DIV>; + <&clk IMX8MQ_CLK_ENET_TIMER>, + <&clk IMX8MQ_CLK_ENET_REF>, + <&clk IMX8MQ_CLK_ENET_PHY_REF>; clock-names = "ipg", "ahb", "ptp", "enet_clk_ref", "enet_out"; - assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI_SRC>, - <&clk IMX8MQ_CLK_ENET_TIMER_SRC>, - <&clk IMX8MQ_CLK_ENET_REF_SRC>, - <&clk IMX8MQ_CLK_ENET_TIMER_DIV>; + assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI>, + <&clk IMX8MQ_CLK_ENET_TIMER>, + <&clk IMX8MQ_CLK_ENET_REF>; assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, <&clk IMX8MQ_SYS2_PLL_100M>, <&clk IMX8MQ_SYS2_PLL_125M>; - assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; + assigned-clock-rates = <0>, <100000000>, <125000000>; stop-mode = <&gpr 0x10 3>; fsl,num-tx-queues=<3>; fsl,num-rx-queues=<3>; diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h index 11dcafcfde..65463673d2 100644 --- a/include/dt-bindings/clock/imx8mq-clock.h +++ b/include/dt-bindings/clock/imx8mq-clock.h @@ -1,10 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright 2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H @@ -148,465 +145,263 @@ /* BUS TYPE */ /* MAIN AXI */ -#define IMX8MQ_CLK_MAIN_AXI_SRC 103 -#define IMX8MQ_CLK_MAIN_AXI_CG 104 -#define IMX8MQ_CLK_MAIN_AXI_PRE_DIV 105 -#define IMX8MQ_CLK_MAIN_AXI_DIV 106 +#define IMX8MQ_CLK_MAIN_AXI 103 /* ENET AXI */ -#define IMX8MQ_CLK_ENET_AXI_SRC 107 -#define IMX8MQ_CLK_ENET_AXI_CG 108 -#define IMX8MQ_CLK_ENET_AXI_PRE_DIV 109 -#define IMX8MQ_CLK_ENET_AXI_DIV 110 +#define IMX8MQ_CLK_ENET_AXI 104 /* NAND_USDHC_BUS */ -#define IMX8MQ_CLK_NAND_USDHC_BUS_SRC 111 -#define IMX8MQ_CLK_NAND_USDHC_BUS_CG 112 -#define IMX8MQ_CLK_NAND_USDHC_BUS_PRE_DIV 113 -#define IMX8MQ_CLK_NAND_USDHC_BUS_DIV 114 +#define IMX8MQ_CLK_NAND_USDHC_BUS 105 /* VPU BUS */ -#define IMX8MQ_CLK_VPU_BUS_SRC 115 -#define IMX8MQ_CLK_VPU_BUS_CG 116 -#define IMX8MQ_CLK_VPU_BUS_PRE_DIV 117 -#define IMX8MQ_CLK_VPU_BUS_DIV 118 +#define IMX8MQ_CLK_VPU_BUS 106 /* DISP_AXI */ -#define IMX8MQ_CLK_DISP_AXI_SRC 119 -#define IMX8MQ_CLK_DISP_AXI_CG 120 -#define IMX8MQ_CLK_DISP_AXI_PRE_DIV 121 -#define IMX8MQ_CLK_DISP_AXI_DIV 122 +#define IMX8MQ_CLK_DISP_AXI 107 /* DISP APB */ -#define IMX8MQ_CLK_DISP_APB_SRC 123 -#define IMX8MQ_CLK_DISP_APB_CG 124 -#define IMX8MQ_CLK_DISP_APB_PRE_DIV 125 -#define IMX8MQ_CLK_DISP_APB_DIV 126 +#define IMX8MQ_CLK_DISP_APB 108 /* DISP RTRM */ -#define IMX8MQ_CLK_DISP_RTRM_SRC 127 -#define IMX8MQ_CLK_DISP_RTRM_CG 128 -#define IMX8MQ_CLK_DISP_RTRM_PRE_DIV 129 -#define IMX8MQ_CLK_DISP_RTRM_DIV 130 +#define IMX8MQ_CLK_DISP_RTRM 109 /* USB_BUS */ -#define IMX8MQ_CLK_USB_BUS_SRC 131 -#define IMX8MQ_CLK_USB_BUS_CG 132 -#define IMX8MQ_CLK_USB_BUS_PRE_DIV 133 -#define IMX8MQ_CLK_USB_BUS_DIV 134 +#define IMX8MQ_CLK_USB_BUS 110 /* GPU_AXI */ -#define IMX8MQ_CLK_GPU_AXI_SRC 135 -#define IMX8MQ_CLK_GPU_AXI_CG 136 -#define IMX8MQ_CLK_GPU_AXI_PRE_DIV 137 -#define IMX8MQ_CLK_GPU_AXI_DIV 138 +#define IMX8MQ_CLK_GPU_AXI 111 /* GPU_AHB */ -#define IMX8MQ_CLK_GPU_AHB_SRC 139 -#define IMX8MQ_CLK_GPU_AHB_CG 140 -#define IMX8MQ_CLK_GPU_AHB_PRE_DIV 141 -#define IMX8MQ_CLK_GPU_AHB_DIV 142 +#define IMX8MQ_CLK_GPU_AHB 112 /* NOC */ -#define IMX8MQ_CLK_NOC_SRC 143 -#define IMX8MQ_CLK_NOC_CG 144 -#define IMX8MQ_CLK_NOC_PRE_DIV 145 -#define IMX8MQ_CLK_NOC_DIV 146 +#define IMX8MQ_CLK_NOC 113 /* NOC_APB */ -#define IMX8MQ_CLK_NOC_APB_SRC 147 -#define IMX8MQ_CLK_NOC_APB_CG 148 -#define IMX8MQ_CLK_NOC_APB_PRE_DIV 149 -#define IMX8MQ_CLK_NOC_APB_DIV 150 +#define IMX8MQ_CLK_NOC_APB 115 /* AHB */ -#define IMX8MQ_CLK_AHB_SRC 151 -#define IMX8MQ_CLK_AHB_CG 152 -#define IMX8MQ_CLK_AHB_PRE_DIV 153 -#define IMX8MQ_CLK_AHB_DIV 154 +#define IMX8MQ_CLK_AHB 116 /* AUDIO AHB */ -#define IMX8MQ_CLK_AUDIO_AHB_SRC 155 -#define IMX8MQ_CLK_AUDIO_AHB_CG 156 -#define IMX8MQ_CLK_AUDIO_AHB_PRE_DIV 157 -#define IMX8MQ_CLK_AUDIO_AHB_DIV 158 +#define IMX8MQ_CLK_AUDIO_AHB 117 /* DRAM_ALT */ -#define IMX8MQ_CLK_DRAM_ALT_SRC 159 -#define IMX8MQ_CLK_DRAM_ALT_CG 160 -#define IMX8MQ_CLK_DRAM_ALT_PRE_DIV 161 -#define IMX8MQ_CLK_DRAM_ALT_DIV 162 +#define IMX8MQ_CLK_DRAM_ALT 118 /* DRAM APB */ -#define IMX8MQ_CLK_DRAM_APB_SRC 163 -#define IMX8MQ_CLK_DRAM_APB_CG 164 -#define IMX8MQ_CLK_DRAM_APB_PRE_DIV 165 -#define IMX8MQ_CLK_DRAM_APB_DIV 166 +#define IMX8MQ_CLK_DRAM_APB 119 /* VPU_G1 */ -#define IMX8MQ_CLK_VPU_G1_SRC 167 -#define IMX8MQ_CLK_VPU_G1_CG 168 -#define IMX8MQ_CLK_VPU_G1_PRE_DIV 169 -#define IMX8MQ_CLK_VPU_G1_DIV 170 +#define IMX8MQ_CLK_VPU_G1 120 /* VPU_G2 */ -#define IMX8MQ_CLK_VPU_G2_SRC 171 -#define IMX8MQ_CLK_VPU_G2_CG 172 -#define IMX8MQ_CLK_VPU_G2_PRE_DIV 173 -#define IMX8MQ_CLK_VPU_G2_DIV 174 +#define IMX8MQ_CLK_VPU_G2 121 /* DISP_DTRC */ -#define IMX8MQ_CLK_DISP_DTRC_SRC 175 -#define IMX8MQ_CLK_DISP_DTRC_CG 176 -#define IMX8MQ_CLK_DISP_DTRC_PRE_DIV 177 -#define IMX8MQ_CLK_DISP_DTRC_DIV 178 +#define IMX8MQ_CLK_DISP_DTRC 122 /* DISP_DC8000 */ -#define IMX8MQ_CLK_DISP_DC8000_SRC 179 -#define IMX8MQ_CLK_DISP_DC8000_CG 180 -#define IMX8MQ_CLK_DISP_DC8000_PRE_DIV 181 -#define IMX8MQ_CLK_DISP_DC8000_DIV 182 +#define IMX8MQ_CLK_DISP_DC8000 123 /* PCIE_CTRL */ -#define IMX8MQ_CLK_PCIE1_CTRL_SRC 183 -#define IMX8MQ_CLK_PCIE1_CTRL_CG 184 -#define IMX8MQ_CLK_PCIE1_CTRL_PRE_DIV 185 -#define IMX8MQ_CLK_PCIE1_CTRL_DIV 186 +#define IMX8MQ_CLK_PCIE1_CTRL 124 /* PCIE_PHY */ -#define IMX8MQ_CLK_PCIE1_PHY_SRC 187 -#define IMX8MQ_CLK_PCIE1_PHY_CG 188 -#define IMX8MQ_CLK_PCIE1_PHY_PRE_DIV 189 -#define IMX8MQ_CLK_PCIE1_PHY_DIV 190 +#define IMX8MQ_CLK_PCIE1_PHY 125 /* PCIE_AUX */ -#define IMX8MQ_CLK_PCIE1_AUX_SRC 191 -#define IMX8MQ_CLK_PCIE1_AUX_CG 192 -#define IMX8MQ_CLK_PCIE1_AUX_PRE_DIV 193 -#define IMX8MQ_CLK_PCIE1_AUX_DIV 194 +#define IMX8MQ_CLK_PCIE1_AUX 126 /* DC_PIXEL */ -#define IMX8MQ_CLK_DC_PIXEL_SRC 195 -#define IMX8MQ_CLK_DC_PIXEL_CG 196 -#define IMX8MQ_CLK_DC_PIXEL_PRE_DIV 197 -#define IMX8MQ_CLK_DC_PIXEL_DIV 198 +#define IMX8MQ_CLK_DC_PIXEL 127 /* LCDIF_PIXEL */ -#define IMX8MQ_CLK_LCDIF_PIXEL_SRC 199 -#define IMX8MQ_CLK_LCDIF_PIXEL_CG 200 -#define IMX8MQ_CLK_LCDIF_PIXEL_PRE_DIV 201 -#define IMX8MQ_CLK_LCDIF_PIXEL_DIV 202 +#define IMX8MQ_CLK_LCDIF_PIXEL 128 /* SAI1~6 */ -#define IMX8MQ_CLK_SAI1_SRC 203 -#define IMX8MQ_CLK_SAI1_CG 204 -#define IMX8MQ_CLK_SAI1_PRE_DIV 205 -#define IMX8MQ_CLK_SAI1_DIV 206 - -#define IMX8MQ_CLK_SAI2_SRC 207 -#define IMX8MQ_CLK_SAI2_CG 208 -#define IMX8MQ_CLK_SAI2_PRE_DIV 209 -#define IMX8MQ_CLK_SAI2_DIV 210 - -#define IMX8MQ_CLK_SAI3_SRC 211 -#define IMX8MQ_CLK_SAI3_CG 212 -#define IMX8MQ_CLK_SAI3_PRE_DIV 213 -#define IMX8MQ_CLK_SAI3_DIV 214 - -#define IMX8MQ_CLK_SAI4_SRC 215 -#define IMX8MQ_CLK_SAI4_CG 216 -#define IMX8MQ_CLK_SAI4_PRE_DIV 217 -#define IMX8MQ_CLK_SAI4_DIV 218 - -#define IMX8MQ_CLK_SAI5_SRC 219 -#define IMX8MQ_CLK_SAI5_CG 220 -#define IMX8MQ_CLK_SAI5_PRE_DIV 221 -#define IMX8MQ_CLK_SAI5_DIV 222 - -#define IMX8MQ_CLK_SAI6_SRC 223 -#define IMX8MQ_CLK_SAI6_CG 224 -#define IMX8MQ_CLK_SAI6_PRE_DIV 225 -#define IMX8MQ_CLK_SAI6_DIV 226 +#define IMX8MQ_CLK_SAI1 129 + +#define IMX8MQ_CLK_SAI2 130 + +#define IMX8MQ_CLK_SAI3 131 + +#define IMX8MQ_CLK_SAI4 132 + +#define IMX8MQ_CLK_SAI5 133 + +#define IMX8MQ_CLK_SAI6 134 /* SPDIF1 */ -#define IMX8MQ_CLK_SPDIF1_SRC 227 -#define IMX8MQ_CLK_SPDIF1_CG 228 -#define IMX8MQ_CLK_SPDIF1_PRE_DIV 229 -#define IMX8MQ_CLK_SPDIF1_DIV 230 +#define IMX8MQ_CLK_SPDIF1 135 /* SPDIF2 */ -#define IMX8MQ_CLK_SPDIF2_SRC 231 -#define IMX8MQ_CLK_SPDIF2_CG 232 -#define IMX8MQ_CLK_SPDIF2_PRE_DIV 233 -#define IMX8MQ_CLK_SPDIF2_DIV 234 +#define IMX8MQ_CLK_SPDIF2 136 /* ENET_REF */ -#define IMX8MQ_CLK_ENET_REF_SRC 235 -#define IMX8MQ_CLK_ENET_REF_CG 236 -#define IMX8MQ_CLK_ENET_REF_PRE_DIV 237 -#define IMX8MQ_CLK_ENET_REF_DIV 238 +#define IMX8MQ_CLK_ENET_REF 137 /* ENET_TIMER */ -#define IMX8MQ_CLK_ENET_TIMER_SRC 239 -#define IMX8MQ_CLK_ENET_TIMER_CG 240 -#define IMX8MQ_CLK_ENET_TIMER_PRE_DIV 241 -#define IMX8MQ_CLK_ENET_TIMER_DIV 242 +#define IMX8MQ_CLK_ENET_TIMER 138 /* ENET_PHY */ -#define IMX8MQ_CLK_ENET_PHY_REF_SRC 243 -#define IMX8MQ_CLK_ENET_PHY_REF_CG 244 -#define IMX8MQ_CLK_ENET_PHY_REF_PRE_DIV 245 -#define IMX8MQ_CLK_ENET_PHY_REF_DIV 246 +#define IMX8MQ_CLK_ENET_PHY_REF 139 /* NAND */ -#define IMX8MQ_CLK_NAND_SRC 247 -#define IMX8MQ_CLK_NAND_CG 248 -#define IMX8MQ_CLK_NAND_PRE_DIV 249 -#define IMX8MQ_CLK_NAND_DIV 250 +#define IMX8MQ_CLK_NAND 140 /* QSPI */ -#define IMX8MQ_CLK_QSPI_SRC 251 -#define IMX8MQ_CLK_QSPI_CG 252 -#define IMX8MQ_CLK_QSPI_PRE_DIV 253 -#define IMX8MQ_CLK_QSPI_DIV 254 +#define IMX8MQ_CLK_QSPI 141 /* USDHC1 */ -#define IMX8MQ_CLK_USDHC1_SRC 255 -#define IMX8MQ_CLK_USDHC1_CG 256 -#define IMX8MQ_CLK_USDHC1_PRE_DIV 257 -#define IMX8MQ_CLK_USDHC1_DIV 258 +#define IMX8MQ_CLK_USDHC1 142 /* USDHC2 */ -#define IMX8MQ_CLK_USDHC2_SRC 259 -#define IMX8MQ_CLK_USDHC2_CG 260 -#define IMX8MQ_CLK_USDHC2_PRE_DIV 261 -#define IMX8MQ_CLK_USDHC2_DIV 262 +#define IMX8MQ_CLK_USDHC2 143 /* I2C1 */ -#define IMX8MQ_CLK_I2C1_SRC 263 -#define IMX8MQ_CLK_I2C1_CG 264 -#define IMX8MQ_CLK_I2C1_PRE_DIV 265 -#define IMX8MQ_CLK_I2C1_DIV 266 +#define IMX8MQ_CLK_I2C1 144 /* I2C2 */ -#define IMX8MQ_CLK_I2C2_SRC 267 -#define IMX8MQ_CLK_I2C2_CG 268 -#define IMX8MQ_CLK_I2C2_PRE_DIV 269 -#define IMX8MQ_CLK_I2C2_DIV 270 +#define IMX8MQ_CLK_I2C2 145 /* I2C3 */ -#define IMX8MQ_CLK_I2C3_SRC 271 -#define IMX8MQ_CLK_I2C3_CG 272 -#define IMX8MQ_CLK_I2C3_PRE_DIV 273 -#define IMX8MQ_CLK_I2C3_DIV 274 +#define IMX8MQ_CLK_I2C3 146 /* I2C4 */ -#define IMX8MQ_CLK_I2C4_SRC 275 -#define IMX8MQ_CLK_I2C4_CG 276 -#define IMX8MQ_CLK_I2C4_PRE_DIV 277 -#define IMX8MQ_CLK_I2C4_DIV 278 +#define IMX8MQ_CLK_I2C4 147 /* UART1 */ -#define IMX8MQ_CLK_UART1_SRC 279 -#define IMX8MQ_CLK_UART1_CG 280 -#define IMX8MQ_CLK_UART1_PRE_DIV 281 -#define IMX8MQ_CLK_UART1_DIV 282 +#define IMX8MQ_CLK_UART1 148 /* UART2 */ -#define IMX8MQ_CLK_UART2_SRC 283 -#define IMX8MQ_CLK_UART2_CG 284 -#define IMX8MQ_CLK_UART2_PRE_DIV 285 -#define IMX8MQ_CLK_UART2_DIV 286 +#define IMX8MQ_CLK_UART2 149 /* UART3 */ -#define IMX8MQ_CLK_UART3_SRC 287 -#define IMX8MQ_CLK_UART3_CG 288 -#define IMX8MQ_CLK_UART3_PRE_DIV 289 -#define IMX8MQ_CLK_UART3_DIV 290 +#define IMX8MQ_CLK_UART3 150 /* UART4 */ -#define IMX8MQ_CLK_UART4_SRC 291 -#define IMX8MQ_CLK_UART4_CG 292 -#define IMX8MQ_CLK_UART4_PRE_DIV 293 -#define IMX8MQ_CLK_UART4_DIV 294 +#define IMX8MQ_CLK_UART4 151 /* USB_CORE_REF */ -#define IMX8MQ_CLK_USB_CORE_REF_SRC 295 -#define IMX8MQ_CLK_USB_CORE_REF_CG 296 -#define IMX8MQ_CLK_USB_CORE_REF_PRE_DIV 297 -#define IMX8MQ_CLK_USB_CORE_REF_DIV 298 +#define IMX8MQ_CLK_USB_CORE_REF 152 /* USB_PHY_REF */ -#define IMX8MQ_CLK_USB_PHY_REF_SRC 299 -#define IMX8MQ_CLK_USB_PHY_REF_CG 300 -#define IMX8MQ_CLK_USB_PHY_REF_PRE_DIV 301 -#define IMX8MQ_CLK_USB_PHY_REF_DIV 302 +#define IMX8MQ_CLK_USB_PHY_REF 153 /* ECSPI1 */ -#define IMX8MQ_CLK_ECSPI1_SRC 303 -#define IMX8MQ_CLK_ECSPI1_CG 304 -#define IMX8MQ_CLK_ECSPI1_PRE_DIV 305 -#define IMX8MQ_CLK_ECSPI1_DIV 306 +#define IMX8MQ_CLK_ECSPI1 154 /* ECSPI2 */ -#define IMX8MQ_CLK_ECSPI2_SRC 307 -#define IMX8MQ_CLK_ECSPI2_CG 308 -#define IMX8MQ_CLK_ECSPI2_PRE_DIV 309 -#define IMX8MQ_CLK_ECSPI2_DIV 310 +#define IMX8MQ_CLK_ECSPI2 155 /* PWM1 */ -#define IMX8MQ_CLK_PWM1_SRC 311 -#define IMX8MQ_CLK_PWM1_CG 312 -#define IMX8MQ_CLK_PWM1_PRE_DIV 313 -#define IMX8MQ_CLK_PWM1_DIV 314 +#define IMX8MQ_CLK_PWM1 156 /* PWM2 */ -#define IMX8MQ_CLK_PWM2_SRC 315 -#define IMX8MQ_CLK_PWM2_CG 316 -#define IMX8MQ_CLK_PWM2_PRE_DIV 317 -#define IMX8MQ_CLK_PWM2_DIV 318 +#define IMX8MQ_CLK_PWM2 157 /* PWM3 */ -#define IMX8MQ_CLK_PWM3_SRC 319 -#define IMX8MQ_CLK_PWM3_CG 320 -#define IMX8MQ_CLK_PWM3_PRE_DIV 321 -#define IMX8MQ_CLK_PWM3_DIV 322 +#define IMX8MQ_CLK_PWM3 158 /* PWM4 */ -#define IMX8MQ_CLK_PWM4_SRC 323 -#define IMX8MQ_CLK_PWM4_CG 324 -#define IMX8MQ_CLK_PWM4_PRE_DIV 325 -#define IMX8MQ_CLK_PWM4_DIV 326 +#define IMX8MQ_CLK_PWM4 159 /* GPT1 */ -#define IMX8MQ_CLK_GPT1_SRC 327 -#define IMX8MQ_CLK_GPT1_CG 328 -#define IMX8MQ_CLK_GPT1_PRE_DIV 329 -#define IMX8MQ_CLK_GPT1_DIV 330 +#define IMX8MQ_CLK_GPT1 160 /* WDOG */ -#define IMX8MQ_CLK_WDOG_SRC 331 -#define IMX8MQ_CLK_WDOG_CG 332 -#define IMX8MQ_CLK_WDOG_PRE_DIV 333 -#define IMX8MQ_CLK_WDOG_DIV 334 +#define IMX8MQ_CLK_WDOG 161 /* WRCLK */ -#define IMX8MQ_CLK_WRCLK_SRC 335 -#define IMX8MQ_CLK_WRCLK_CG 336 -#define IMX8MQ_CLK_WRCLK_PRE_DIV 337 -#define IMX8MQ_CLK_WRCLK_DIV 338 +#define IMX8MQ_CLK_WRCLK 162 /* DSI_CORE */ -#define IMX8MQ_CLK_DSI_CORE_SRC 339 -#define IMX8MQ_CLK_DSI_CORE_CG 340 -#define IMX8MQ_CLK_DSI_CORE_PRE_DIV 341 -#define IMX8MQ_CLK_DSI_CORE_DIV 342 +#define IMX8MQ_CLK_DSI_CORE 163 /* DSI_PHY */ -#define IMX8MQ_CLK_DSI_PHY_REF_SRC 343 -#define IMX8MQ_CLK_DSI_PHY_REF_CG 344 -#define IMX8MQ_CLK_DSI_PHY_REF_PRE_DIV 345 -#define IMX8MQ_CLK_DSI_PHY_REF_DIV 346 +#define IMX8MQ_CLK_DSI_PHY_REF 164 /* DSI_DBI */ -#define IMX8MQ_CLK_DSI_DBI_SRC 347 -#define IMX8MQ_CLK_DSI_DBI_CG 348 -#define IMX8MQ_CLK_DSI_DBI_PRE_DIV 349 -#define IMX8MQ_CLK_DSI_DBI_DIV 350 +#define IMX8MQ_CLK_DSI_DBI 165 /*DSI_ESC */ -#define IMX8MQ_CLK_DSI_ESC_SRC 351 -#define IMX8MQ_CLK_DSI_ESC_CG 352 -#define IMX8MQ_CLK_DSI_ESC_PRE_DIV 353 -#define IMX8MQ_CLK_DSI_ESC_DIV 354 +#define IMX8MQ_CLK_DSI_ESC 166 /* CSI1_CORE */ -#define IMX8MQ_CLK_CSI1_CORE_SRC 355 -#define IMX8MQ_CLK_CSI1_CORE_CG 356 -#define IMX8MQ_CLK_CSI1_CORE_PRE_DIV 357 -#define IMX8MQ_CLK_CSI1_CORE_DIV 358 +#define IMX8MQ_CLK_CSI1_CORE 167 /* CSI1_PHY */ -#define IMX8MQ_CLK_CSI1_PHY_REF_SRC 359 -#define IMX8MQ_CLK_CSI1_PHY_REF_CG 360 -#define IMX8MQ_CLK_CSI1_PHY_REF_PRE_DIV 361 -#define IMX8MQ_CLK_CSI1_PHY_REF_DIV 362 +#define IMX8MQ_CLK_CSI1_PHY_REF 168 /* CSI_ESC */ -#define IMX8MQ_CLK_CSI1_ESC_SRC 363 -#define IMX8MQ_CLK_CSI1_ESC_CG 364 -#define IMX8MQ_CLK_CSI1_ESC_PRE_DIV 365 -#define IMX8MQ_CLK_CSI1_ESC_DIV 366 +#define IMX8MQ_CLK_CSI1_ESC 169 /* CSI2_CORE */ -#define IMX8MQ_CLK_CSI2_CORE_SRC 367 -#define IMX8MQ_CLK_CSI2_CORE_CG 368 -#define IMX8MQ_CLK_CSI2_CORE_PRE_DIV 369 -#define IMX8MQ_CLK_CSI2_CORE_DIV 370 +#define IMX8MQ_CLK_CSI2_CORE 170 /* CSI2_PHY */ -#define IMX8MQ_CLK_CSI2_PHY_REF_SRC 371 -#define IMX8MQ_CLK_CSI2_PHY_REF_CG 372 -#define IMX8MQ_CLK_CSI2_PHY_REF_PRE_DIV 373 -#define IMX8MQ_CLK_CSI2_PHY_REF_DIV 374 +#define IMX8MQ_CLK_CSI2_PHY_REF 171 /* CSI2_ESC */ -#define IMX8MQ_CLK_CSI2_ESC_SRC 375 -#define IMX8MQ_CLK_CSI2_ESC_CG 376 -#define IMX8MQ_CLK_CSI2_ESC_PRE_DIV 377 -#define IMX8MQ_CLK_CSI2_ESC_DIV 378 +#define IMX8MQ_CLK_CSI2_ESC 172 /* PCIE2_CTRL */ -#define IMX8MQ_CLK_PCIE2_CTRL_SRC 379 -#define IMX8MQ_CLK_PCIE2_CTRL_CG 380 -#define IMX8MQ_CLK_PCIE2_CTRL_PRE_DIV 381 -#define IMX8MQ_CLK_PCIE2_CTRL_DIV 382 +#define IMX8MQ_CLK_PCIE2_CTRL 173 /* PCIE2_PHY */ -#define IMX8MQ_CLK_PCIE2_PHY_SRC 383 -#define IMX8MQ_CLK_PCIE2_PHY_CG 384 -#define IMX8MQ_CLK_PCIE2_PHY_PRE_DIV 385 -#define IMX8MQ_CLK_PCIE2_PHY_DIV 386 +#define IMX8MQ_CLK_PCIE2_PHY 174 /* PCIE2_AUX */ -#define IMX8MQ_CLK_PCIE2_AUX_SRC 387 -#define IMX8MQ_CLK_PCIE2_AUX_CG 388 -#define IMX8MQ_CLK_PCIE2_AUX_PRE_DIV 389 -#define IMX8MQ_CLK_PCIE2_AUX_DIV 390 +#define IMX8MQ_CLK_PCIE2_AUX 175 /* ECSPI3 */ -#define IMX8MQ_CLK_ECSPI3_SRC 391 -#define IMX8MQ_CLK_ECSPI3_CG 392 -#define IMX8MQ_CLK_ECSPI3_PRE_DIV 393 -#define IMX8MQ_CLK_ECSPI3_DIV 394 +#define IMX8MQ_CLK_ECSPI3 176 /* CCGR clocks */ -#define IMX8MQ_CLK_A53_ROOT 395 -#define IMX8MQ_CLK_DRAM_ROOT 396 -#define IMX8MQ_CLK_ECSPI1_ROOT 397 -#define IMX8MQ_CLK_ECSPI2_ROOT 398 -#define IMX8MQ_CLK_ECSPI3_ROOT 399 -#define IMX8MQ_CLK_ENET1_ROOT 400 -#define IMX8MQ_CLK_GPT1_ROOT 401 -#define IMX8MQ_CLK_I2C1_ROOT 402 -#define IMX8MQ_CLK_I2C2_ROOT 403 -#define IMX8MQ_CLK_I2C3_ROOT 404 -#define IMX8MQ_CLK_I2C4_ROOT 405 -#define IMX8MQ_CLK_M4_ROOT 406 -#define IMX8MQ_CLK_PCIE1_ROOT 407 -#define IMX8MQ_CLK_PCIE2_ROOT 408 -#define IMX8MQ_CLK_PWM1_ROOT 409 -#define IMX8MQ_CLK_PWM2_ROOT 410 -#define IMX8MQ_CLK_PWM3_ROOT 411 -#define IMX8MQ_CLK_PWM4_ROOT 412 -#define IMX8MQ_CLK_QSPI_ROOT 413 -#define IMX8MQ_CLK_SAI1_ROOT 414 -#define IMX8MQ_CLK_SAI2_ROOT 415 -#define IMX8MQ_CLK_SAI3_ROOT 416 -#define IMX8MQ_CLK_SAI4_ROOT 417 -#define IMX8MQ_CLK_SAI5_ROOT 418 -#define IMX8MQ_CLK_SAI6_ROOT 419 -#define IMX8MQ_CLK_UART1_ROOT 420 -#define IMX8MQ_CLK_UART2_ROOT 421 -#define IMX8MQ_CLK_UART3_ROOT 422 -#define IMX8MQ_CLK_UART4_ROOT 423 -#define IMX8MQ_CLK_USB1_CTRL_ROOT 424 -#define IMX8MQ_CLK_USB2_CTRL_ROOT 425 -#define IMX8MQ_CLK_USB1_PHY_ROOT 426 -#define IMX8MQ_CLK_USB2_PHY_ROOT 427 -#define IMX8MQ_CLK_USDHC1_ROOT 428 -#define IMX8MQ_CLK_USDHC2_ROOT 429 -#define IMX8MQ_CLK_WDOG1_ROOT 430 -#define IMX8MQ_CLK_WDOG2_ROOT 431 -#define IMX8MQ_CLK_WDOG3_ROOT 432 -#define IMX8MQ_CLK_GPU_ROOT 433 -#define IMX8MQ_CLK_HEVC_ROOT 434 -#define IMX8MQ_CLK_AVC_ROOT 435 -#define IMX8MQ_CLK_VP9_ROOT 436 -#define IMX8MQ_CLK_HEVC_INTER_ROOT 437 -#define IMX8MQ_CLK_DISP_ROOT 438 -#define IMX8MQ_CLK_HDMI_ROOT 439 -#define IMX8MQ_CLK_HDMI_PHY_ROOT 440 -#define IMX8MQ_CLK_VPU_DEC_ROOT 441 -#define IMX8MQ_CLK_CSI1_ROOT 442 -#define IMX8MQ_CLK_CSI2_ROOT 443 -#define IMX8MQ_CLK_RAWNAND_ROOT 444 -#define IMX8MQ_CLK_SDMA1_ROOT 445 -#define IMX8MQ_CLK_SDMA2_ROOT 446 -#define IMX8MQ_CLK_VPU_G1_ROOT 447 -#define IMX8MQ_CLK_VPU_G2_ROOT 448 +#define IMX8MQ_CLK_A53_ROOT 177 +#define IMX8MQ_CLK_DRAM_ROOT 178 +#define IMX8MQ_CLK_ECSPI1_ROOT 179 +#define IMX8MQ_CLK_ECSPI2_ROOT 180 +#define IMX8MQ_CLK_ECSPI3_ROOT 181 +#define IMX8MQ_CLK_ENET1_ROOT 182 +#define IMX8MQ_CLK_GPT1_ROOT 183 +#define IMX8MQ_CLK_I2C1_ROOT 184 +#define IMX8MQ_CLK_I2C2_ROOT 185 +#define IMX8MQ_CLK_I2C3_ROOT 186 +#define IMX8MQ_CLK_I2C4_ROOT 187 +#define IMX8MQ_CLK_M4_ROOT 188 +#define IMX8MQ_CLK_PCIE1_ROOT 189 +#define IMX8MQ_CLK_PCIE2_ROOT 190 +#define IMX8MQ_CLK_PWM1_ROOT 191 +#define IMX8MQ_CLK_PWM2_ROOT 192 +#define IMX8MQ_CLK_PWM3_ROOT 193 +#define IMX8MQ_CLK_PWM4_ROOT 194 +#define IMX8MQ_CLK_QSPI_ROOT 195 +#define IMX8MQ_CLK_SAI1_ROOT 196 +#define IMX8MQ_CLK_SAI2_ROOT 197 +#define IMX8MQ_CLK_SAI3_ROOT 198 +#define IMX8MQ_CLK_SAI4_ROOT 199 +#define IMX8MQ_CLK_SAI5_ROOT 200 +#define IMX8MQ_CLK_SAI6_ROOT 201 +#define IMX8MQ_CLK_UART1_ROOT 202 +#define IMX8MQ_CLK_UART2_ROOT 203 +#define IMX8MQ_CLK_UART3_ROOT 204 +#define IMX8MQ_CLK_UART4_ROOT 205 +#define IMX8MQ_CLK_USB1_CTRL_ROOT 206 +#define IMX8MQ_CLK_USB2_CTRL_ROOT 207 +#define IMX8MQ_CLK_USB1_PHY_ROOT 208 +#define IMX8MQ_CLK_USB2_PHY_ROOT 209 +#define IMX8MQ_CLK_USDHC1_ROOT 210 +#define IMX8MQ_CLK_USDHC2_ROOT 211 +#define IMX8MQ_CLK_WDOG1_ROOT 212 +#define IMX8MQ_CLK_WDOG2_ROOT 213 +#define IMX8MQ_CLK_WDOG3_ROOT 214 +#define IMX8MQ_CLK_GPU_ROOT 215 +#define IMX8MQ_CLK_HEVC_ROOT 216 +#define IMX8MQ_CLK_AVC_ROOT 217 +#define IMX8MQ_CLK_VP9_ROOT 218 +#define IMX8MQ_CLK_HEVC_INTER_ROOT 219 +#define IMX8MQ_CLK_DISP_ROOT 220 +#define IMX8MQ_CLK_HDMI_ROOT 221 +#define IMX8MQ_CLK_HDMI_PHY_ROOT 222 +#define IMX8MQ_CLK_VPU_DEC_ROOT 223 +#define IMX8MQ_CLK_CSI1_ROOT 224 +#define IMX8MQ_CLK_CSI2_ROOT 225 +#define IMX8MQ_CLK_RAWNAND_ROOT 226 +#define IMX8MQ_CLK_SDMA1_ROOT 227 +#define IMX8MQ_CLK_SDMA2_ROOT 228 +#define IMX8MQ_CLK_VPU_G1_ROOT 229 +#define IMX8MQ_CLK_VPU_G2_ROOT 230 /* SCCG PLL GATE */ -#define IMX8MQ_SYS1_PLL_OUT 449 -#define IMX8MQ_SYS2_PLL_OUT 450 -#define IMX8MQ_SYS3_PLL_OUT 451 -#define IMX8MQ_DRAM_PLL_OUT 452 - -#define IMX8MQ_GPT_3M_CLK 453 - -#define IMX8MQ_CLK_IPG_ROOT 454 -#define IMX8MQ_CLK_IPG_AUDIO_ROOT 455 -#define IMX8MQ_CLK_SAI1_IPG 456 -#define IMX8MQ_CLK_SAI2_IPG 457 -#define IMX8MQ_CLK_SAI3_IPG 458 -#define IMX8MQ_CLK_SAI4_IPG 459 -#define IMX8MQ_CLK_SAI5_IPG 460 -#define IMX8MQ_CLK_SAI6_IPG 461 +#define IMX8MQ_SYS1_PLL_OUT 231 +#define IMX8MQ_SYS2_PLL_OUT 232 +#define IMX8MQ_SYS3_PLL_OUT 233 +#define IMX8MQ_DRAM_PLL_OUT 234 + +#define IMX8MQ_GPT_3M_CLK 235 + +#define IMX8MQ_CLK_IPG_ROOT 236 +#define IMX8MQ_CLK_IPG_AUDIO_ROOT 237 +#define IMX8MQ_CLK_SAI1_IPG 238 +#define IMX8MQ_CLK_SAI2_IPG 239 +#define IMX8MQ_CLK_SAI3_IPG 240 +#define IMX8MQ_CLK_SAI4_IPG 241 +#define IMX8MQ_CLK_SAI5_IPG 242 +#define IMX8MQ_CLK_SAI6_IPG 243 /* DSI AHB/IPG clocks */ /* rxesc clock */ -#define IMX8MQ_CLK_DSI_AHB_SRC 462 -#define IMX8MQ_CLK_DSI_AHB_CG 463 -#define IMX8MQ_CLK_DSI_AHB_PRE_DIV 464 -#define IMX8MQ_CLK_DSI_AHB_DIV 465 +#define IMX8MQ_CLK_DSI_AHB 244 /* txesc clock */ -#define IMX8MQ_CLK_DSI_IPG_DIV 466 - -/* VIDEO2 PLL */ -#define IMX8MQ_VIDEO2_PLL1_REF_SEL 467 -#define IMX8MQ_VIDEO2_PLL1_REF_DIV 468 -#define IMX8MQ_VIDEO2_PLL1 469 -#define IMX8MQ_VIDEO2_PLL1_OUT 470 -#define IMX8MQ_VIDEO2_PLL1_OUT_DIV 471 -#define IMX8MQ_VIDEO2_PLL2 472 -#define IMX8MQ_VIDEO2_PLL2_DIV 473 -#define IMX8MQ_VIDEO2_PLL2_OUT 474 -#define IMX8MQ_CLK_TMU_ROOT 475 - -#define IMX8MQ_CLK_END 476 +#define IMX8MQ_CLK_DSI_IPG_DIV 245 + +#define IMX8MQ_CLK_TMU_ROOT 246 + +/* Display root clocks */ +#define IMX8MQ_CLK_DISP_AXI_ROOT 247 +#define IMX8MQ_CLK_DISP_APB_ROOT 248 +#define IMX8MQ_CLK_DISP_RTRM_ROOT 249 + +#define IMX8MQ_CLK_OCOTP_ROOT 250 + +#define IMX8MQ_CLK_DRAM_ALT_ROOT 251 +#define IMX8MQ_CLK_DRAM_CORE 252 + +#define IMX8MQ_CLK_MU_ROOT 253 +#define IMX8MQ_VIDEO2_PLL_OUT 254 + +#define IMX8MQ_CLK_CLKO2 255 + +#define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK 256 + +#define IMX8MQ_CLK_CLKO1 257 +#define IMX8MQ_CLK_ARM 258 + +#define IMX8MQ_CLK_GPIO1_ROOT 259 +#define IMX8MQ_CLK_GPIO2_ROOT 260 +#define IMX8MQ_CLK_GPIO3_ROOT 261 +#define IMX8MQ_CLK_GPIO4_ROOT 262 +#define IMX8MQ_CLK_GPIO5_ROOT 263 + +#define IMX8MQ_CLK_SNVS_ROOT 264 +#define IMX8MQ_CLK_GIC 265 + +#define IMX8MQ_CLK_END 266 #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */

1 1

[U-Boot] [RFC 0/9] import x509/pkcs7 parsers from linux
by AKASHI Takahiro 03 Oct '19

03 Oct '19

Asn1 parsers of x509 certificates and pkcs7 messages are required to implement image authentication and variable authentication as part of UEFI secure boot feature. As we discussed before in the thread[1], most people insisted that we should re-use corresponding source code from Linux repository for this purpose. Here is my attempt to import all the necessary files from Linux; Those will eventually be part of UEFI secure boot implementation, but I'd like to get early feedback from other peoples before submitting the whole patchset so that they will be better formatted for merging. My approach here is * files from Linux 5.0 (will be updated to the latest when I will submit them as finalized patches.) * modify files as little as possible * mark/protect unavoidable changes with "#if(n)def __UBOOT__" so that future fixes/differences in Linux repository will easily be applied to U-Boot. Please note that checkpatch.pl will complain with a bunch of warnings/errors but I intentionally left them unchanged for the sake of better maintainability I said above. Any comments will be appreciated. -Takahiro Akashi [1] https://lists.denx.de/pipermail/u-boot/2019-April/366423.html AKASHI Takahiro (9): cmd: add asn1_compiler Makefile: add build script for asn1 parsers lib: add asn1 decoder lib: add oid registry utility lib: crypto: add public key utility lib: crypto: add public_key_verify_signature() lib: crypto: add x509 parser lib: crypto: add pkcs7 message parser lib: crypto: add rsa public key parser cmd/Kconfig | 3 + include/crypto/internal/rsa.h | 62 ++ include/crypto/pkcs7.h | 51 + include/crypto/public_key.h | 89 ++ include/keys/asymmetric-type.h | 92 ++ include/linux/asn1.h | 69 ++ include/linux/asn1_ber_bytecode.h | 93 ++ include/linux/asn1_decoder.h | 24 + include/linux/oid_registry.h | 103 ++ lib/Kconfig | 12 + lib/Makefile | 18 + lib/asn1_decoder.c | 520 ++++++++++ lib/build_OID_registry | 207 ++++ lib/crypto/Kconfig | 38 + lib/crypto/Makefile | 46 + lib/crypto/asymmetric_type.c | 655 ++++++++++++ lib/crypto/pkcs7.asn1 | 135 +++ lib/crypto/pkcs7_parser.c | 690 ++++++++++++ lib/crypto/pkcs7_parser.h | 69 ++ lib/crypto/public_key.c | 344 ++++++ lib/crypto/public_key_local.c | 69 ++ lib/crypto/rsa_helper.c | 81 ++ lib/crypto/rsapubkey.asn1 | 4 + lib/crypto/x509.asn1 | 60 ++ lib/crypto/x509_akid.asn1 | 35 + lib/crypto/x509_cert_parser.c | 644 ++++++++++++ lib/crypto/x509_parser.h | 61 ++ lib/crypto/x509_public_key.c | 284 +++++ lib/oid_registry.c | 178 ++++ scripts/Makefile | 3 + scripts/Makefile.build | 2 +- scripts/asn1_compiler.c | 1615 +++++++++++++++++++++++++++++ 32 files changed, 6355 insertions(+), 1 deletion(-) create mode 100644 include/crypto/internal/rsa.h create mode 100644 include/crypto/pkcs7.h create mode 100644 include/crypto/public_key.h create mode 100644 include/keys/asymmetric-type.h create mode 100644 include/linux/asn1.h create mode 100644 include/linux/asn1_ber_bytecode.h create mode 100644 include/linux/asn1_decoder.h create mode 100644 include/linux/oid_registry.h create mode 100644 lib/asn1_decoder.c create mode 100755 lib/build_OID_registry create mode 100644 lib/crypto/Kconfig create mode 100644 lib/crypto/Makefile create mode 100644 lib/crypto/asymmetric_type.c create mode 100644 lib/crypto/pkcs7.asn1 create mode 100644 lib/crypto/pkcs7_parser.c create mode 100644 lib/crypto/pkcs7_parser.h create mode 100644 lib/crypto/public_key.c create mode 100644 lib/crypto/public_key_local.c create mode 100644 lib/crypto/rsa_helper.c create mode 100644 lib/crypto/rsapubkey.asn1 create mode 100644 lib/crypto/x509.asn1 create mode 100644 lib/crypto/x509_akid.asn1 create mode 100644 lib/crypto/x509_cert_parser.c create mode 100644 lib/crypto/x509_parser.h create mode 100644 lib/crypto/x509_public_key.c create mode 100644 lib/oid_registry.c create mode 100644 scripts/asn1_compiler.c -- 2.21.0

1 10

[U-Boot] [PATCH 00/38] x86: Various modifications to prepare for FSP2
by Simon Glass 02 Oct '19

02 Oct '19

Quite a bit of minor refactoring is needed to prepare for using FSP2 in U-Boot. This series consists of a number of small changes to this end. It is the last series before apollolake support is added. Changes include: - Allowing drivers to be used in TPL/SPL - Moving common FSP code into a common directory - Support for memory-mapped flash on newer Intel chips - Passing the HOB list from SPL to U-Boot proper This series is available at u-boot-dm/x86-working Simon Glass (38): binman: Pass the toolpath to binman from the main Makefile binman: Allow selection of logging verbosity dm: gpio: Allow control of GPIO uclass in SPL mtd: spi: Add 'struct spi_flash {' to the code serial: ns16550: Allow serial to enabled/disabled in SPL spl: Correct priority selection for image loaders spl: Avoid checking for Ctrl-C in SPL with print_buffer() spl: handoff: Correct Kconfig condition for SPL and TPL spl: Add an arch-specific hook for writing to SPL handoff spl: Set up the bloblist in board_init_r() spl: Add a function to determine the U-Boot phase x86: spi: Add a driver for the Intel Fast SPI interface spi: sandbox: Add a test driver for sandbox SPI flash spi: Add support for memory-mapped flash x86: sysreset: Allow reset driver to be included in SPL/TPL x86: Rename some FSP functions to have an fsp_ prefix x86: fsp: Create a common fsp_support.h header x86: fsp: Use if() instead of #ifdef x86: fsp: Tidy up comment style a little x86: fsp: Move common dram functions into a common file x86: Move common fsp functions into a common file x86: fsp: Move common support functions into a common file efi: Move inline functions to unconditional part of header x86: fsp: Add a few more definitions for FSP2 x86: fsp: Add access to variable MRC data x86: Move common Intel CPU info code into a function x86: Add binman symbols to the image x86: pci: Add a function to clear and set PCI config regs x86: spl: Use hang() instead of a while() loop x86: spl: Reduce priority of the basic SPL image loader x86: spl: Move broadwell-specific code out of generic x86 spl x86: fsp: Save usable RAM and hob_list in the handoff area x86: fsp: Allow the HOBs to be used after relocation x86: Change condition for using CAR x86: Add more comments to the start-up code x86: Add support for booting from Fast SPI x86: Add various MTRR indexes and values x86: Rename turbo ratio MSR to MSR_TURBO_RATIO_LIMIT Makefile | 4 +- arch/sandbox/cpu/spl.c | 7 + arch/sandbox/dts/test.dts | 4 + arch/x86/Kconfig | 8 + arch/x86/cpu/baytrail/fsp_configs.c | 2 +- arch/x86/cpu/braswell/fsp_configs.c | 2 +- arch/x86/cpu/broadwell/cpu.c | 5 + arch/x86/cpu/broadwell/cpu_full.c | 18 +- arch/x86/cpu/cpu.c | 6 + arch/x86/cpu/intel_common/Makefile | 1 + arch/x86/cpu/intel_common/cpu.c | 13 + arch/x86/cpu/intel_common/cpu_from_spl.c | 6 + arch/x86/cpu/intel_common/fast_spi.c | 48 ++++ arch/x86/cpu/ivybridge/fsp_configs.c | 2 +- arch/x86/cpu/ivybridge/model_206ax.c | 8 +- arch/x86/cpu/pci.c | 19 ++ arch/x86/cpu/queensbay/fsp_configs.c | 2 +- arch/x86/cpu/start.S | 16 +- arch/x86/cpu/start_from_spl.S | 5 +- arch/x86/cpu/start_from_tpl.S | 3 +- arch/x86/cpu/u-boot-spl.lds | 6 + arch/x86/include/asm/cpu_common.h | 11 + arch/x86/include/asm/fsp/fsp_hob.h | 4 + arch/x86/include/asm/fsp/fsp_infoheader.h | 15 +- arch/x86/include/asm/fsp/fsp_support.h | 174 +++++++++++++ arch/x86/include/asm/fsp1/fsp_support.h | 147 ++--------- arch/x86/include/asm/handoff.h | 8 + arch/x86/include/asm/hob.h | 26 +- arch/x86/include/asm/msr-index.h | 24 +- arch/x86/include/asm/mtrr.h | 1 + arch/x86/include/asm/pci.h | 40 +++ arch/x86/include/asm/spl.h | 4 +- arch/x86/lib/Makefile | 1 + arch/x86/lib/fsp/Makefile | 7 + arch/x86/lib/fsp/fsp_common.c | 104 ++++++++ arch/x86/lib/fsp/fsp_dram.c | 100 ++++++++ arch/x86/lib/fsp/fsp_support.c | 199 +++++++++++++++ arch/x86/lib/fsp1/fsp_car.S | 10 +- arch/x86/lib/fsp1/fsp_common.c | 96 +------ arch/x86/lib/fsp1/fsp_dram.c | 88 +------ arch/x86/lib/fsp1/fsp_support.c | 181 +------------ arch/x86/lib/hob.c | 19 +- arch/x86/lib/spl.c | 13 +- arch/x86/lib/tpl.c | 7 +- cmd/x86/fsp.c | 2 +- common/spl/Kconfig | 4 +- common/spl/spl.c | 47 ++-- configs/slimbootloader_defconfig | 1 + drivers/gpio/Kconfig | 22 ++ drivers/gpio/Makefile | 2 +- drivers/mtd/spi/Kconfig | 9 + drivers/mtd/spi/Makefile | 3 +- drivers/mtd/spi/intel_fast_spi.c | 294 ++++++++++++++++++++++ drivers/mtd/spi/sandbox_direct.c | 110 ++++++++ drivers/mtd/spi/sf-uclass.c | 11 + drivers/pci/pci-uclass.c | 2 +- drivers/serial/ns16550.c | 6 +- drivers/sysreset/Kconfig | 12 + drivers/sysreset/Makefile | 2 +- include/efi_loader.h | 42 ++-- include/handoff.h | 13 + include/linux/mtd/spi-nor.h | 8 +- include/spi_flash.h | 27 ++ include/spl.h | 64 ++++- lib/display_options.c | 2 + test/dm/sf.c | 51 ++++ tools/binman/README | 6 + 67 files changed, 1612 insertions(+), 592 deletions(-) create mode 100644 arch/x86/cpu/intel_common/fast_spi.c create mode 100644 arch/x86/include/asm/fsp/fsp_support.h create mode 100644 arch/x86/lib/fsp/Makefile create mode 100644 arch/x86/lib/fsp/fsp_common.c create mode 100644 arch/x86/lib/fsp/fsp_dram.c create mode 100644 arch/x86/lib/fsp/fsp_support.c create mode 100644 drivers/mtd/spi/intel_fast_spi.c create mode 100644 drivers/mtd/spi/sandbox_direct.c -- 2.23.0.187.g17f5b7556c-goog

2 39

[U-Boot] [PATCH v3 00/10] x86: Prepare for adding FSP2 code
by Simon Glass 02 Oct '19

02 Oct '19

At present the x86 FSP (Firmware Support Package) code assumes that FSP version 1 is used. Since this code was added to U-Boot a new version (FSP2) has been produced by Intel. In preparation for adding support for FSP2, move the existing code into a directory that indicates it is used for FSP1. Changes in v3: - Drop struct efi_guid and add a comment about forward declarations Changes in v2: - Correct Intel FSP web link - Rewrite to make azalia a common file for FSP1 and FSP2 Simon Glass (10): x86: Rename existing FSP code to fsp1 x86: Move fsp_azalia.h to the generic fsp directory x86: Create a new fsp_arch.h header x86: Move fsp_api.h inclusion out of fsp_support.h x86: Move fsp_types.h to the generic fsp directory x86: Move fsp_fv.h to the generic fsp directory x86: Move fsp_hob.h to the generic fsp directory x86: Move fsp_infoheader.h to the generic fsp directory x86: Move fsp_bootmode.h to the generic fsp directory x86: Move fsp_ffs.h include to fsp_arch.h arch/x86/Kconfig | 25 ++++++++++++++++++- arch/x86/cpu/baytrail/acpi.c | 2 +- arch/x86/cpu/baytrail/fsp_configs.c | 2 +- arch/x86/cpu/braswell/fsp_configs.c | 2 +- arch/x86/cpu/ivybridge/fsp_configs.c | 2 +- arch/x86/cpu/queensbay/fsp_configs.c | 2 +- arch/x86/cpu/queensbay/tnc.c | 2 +- arch/x86/include/asm/{fsp => fsp1}/fsp_api.h | 0 arch/x86/include/asm/{fsp => fsp1}/fsp_ffs.h | 0 .../include/asm/{fsp => fsp1}/fsp_support.h | 19 +++++++------- arch/x86/include/asm/fsp_arch.h | 22 ++++++++++++++++ arch/x86/include/asm/u-boot-x86.h | 2 +- arch/x86/lib/Makefile | 3 ++- arch/x86/lib/{fsp => fsp1}/Makefile | 0 arch/x86/lib/{fsp => fsp1}/fsp_car.S | 0 arch/x86/lib/{fsp => fsp1}/fsp_common.c | 2 +- arch/x86/lib/{fsp => fsp1}/fsp_dram.c | 2 +- arch/x86/lib/{fsp => fsp1}/fsp_graphics.c | 2 +- arch/x86/lib/{fsp => fsp1}/fsp_support.c | 2 +- .../som-db5800-som-6867/som-db5800-som-6867.c | 2 +- board/intel/cherryhill/cherryhill.c | 2 +- cmd/x86/fsp.c | 2 +- drivers/pci/pci-uclass.c | 2 +- 23 files changed, 73 insertions(+), 26 deletions(-) rename arch/x86/include/asm/{fsp => fsp1}/fsp_api.h (100%) rename arch/x86/include/asm/{fsp => fsp1}/fsp_ffs.h (100%) rename arch/x86/include/asm/{fsp => fsp1}/fsp_support.h (94%) create mode 100644 arch/x86/include/asm/fsp_arch.h rename arch/x86/lib/{fsp => fsp1}/Makefile (100%) rename arch/x86/lib/{fsp => fsp1}/fsp_car.S (100%) rename arch/x86/lib/{fsp => fsp1}/fsp_common.c (99%) rename arch/x86/lib/{fsp => fsp1}/fsp_dram.c (98%) rename arch/x86/lib/{fsp => fsp1}/fsp_graphics.c (98%) rename arch/x86/lib/{fsp => fsp1}/fsp_support.c (99%) -- 2.23.0.444.g18eeb5a265-goog

2 25

[U-Boot] [PATCH 00/13] arm64: zynqmp: Clean communication with PMUFW
by Michal Simek 02 Oct '19

02 Oct '19

Hi, This patch series using ZynqMP firmware driver to provide a interface to communicate with the PMU Firmware. As part of the series a mailbox driver is also implemented to handle communication through ipi interface. There are two new wiring: 1. Reading PMUFW version via firmware driver - mailbox driver in case of SPL - SMC in case of full U-Boot 2. Using the same patch for loading PMUFW configuration object The whole series is based on several patches I have sent already that's why I am providing a branch which also contains this series. https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze/tree/next Thanks, Michal Ibai Erkiaga (10): mailbox: check ops prior calling mailbox: allow subnode for mbox regs mailbox: zynqmp: ipi mailbox driver firmware: zynqmp: Add zynqmp-power support arm64: zynqmp: add firmware and mailbox node to DT firmware: zynqmp: get fw version with mailbox driver firmware: zynqmp: create firmware header arm64: zynqmp: use firmware driver to get version arm64: zynqmp: remove old fw version function arm64: zynqmp: probe firmware driver Michal Simek (3): arm64: zynqmp: Cleanup PM SMC macro composition firmware: zynqmp: Separate function for sending message via mailbox arm64: zynqmp: Use mailbox driver for PMUFW config loading MAINTAINERS | 2 + arch/arm/Kconfig | 3 + arch/arm/dts/zynqmp.dtsi | 44 +++++- arch/arm/mach-zynqmp/Makefile | 4 - arch/arm/mach-zynqmp/cpu.c | 24 +--- arch/arm/mach-zynqmp/include/mach/sys_proto.h | 24 +--- arch/arm/mach-zynqmp/pmu_ipc.c | 112 --------------- board/xilinx/zynqmp/cmds.c | 1 + board/xilinx/zynqmp/zynqmp.c | 19 +-- drivers/firmware/Kconfig | 2 + drivers/firmware/firmware-zynqmp.c | 131 +++++++++++++++++ drivers/fpga/zynqmppl.c | 5 +- drivers/mailbox/Kconfig | 6 + drivers/mailbox/Makefile | 1 + drivers/mailbox/mailbox-uclass.c | 19 ++- drivers/mailbox/zynqmp-ipi.c | 134 ++++++++++++++++++ include/zynqmp_firmware.h | 37 +++++ 17 files changed, 388 insertions(+), 180 deletions(-) delete mode 100644 arch/arm/mach-zynqmp/pmu_ipc.c create mode 100644 drivers/mailbox/zynqmp-ipi.c create mode 100644 include/zynqmp_firmware.h -- 2.17.1

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[U-Boot] [RFC] Minimum Python 3 version?
by Tom Rini 01 Oct '19

01 Oct '19

Hey all, I'm currently kicking test.py to use Python 3 instead of Python 2.7 and seeing places where it would (seemingly) be nice to be able to say that we have Python 3.6 as our minimum version. To do this however we'll have to tell people using older LTS distributions that they need to figure out the best way for them to install a newer Python is, if they want to run tests at least. This will also mean moving GitLab to "bionic" rather than "xenial", but that's not too bad and I've done so for trying to get all of the fs tests to run (they don't, but I think that's down to needing to kick gitlab-runner harder) and also moving Travis-CI to bionic but that too is now just a few-line change to .travis.yml So, does anyone object to saying that for everything that uses Python to work, Python 3.6 or newer is needed, and for more common tools we'll make best-effort to support older? -- Tom

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