September 2019 - U-Boot

[U-Boot] [PATCH v2 0/4] Fix default values for address and size cells
by matthias.bgg＠kernel.org 22 Oct '19

22 Oct '19

From: Matthias Brugger <mbrugger(a)suse.com> The libftd implementation of U-Boot is outdated with the upstream project. Especially the default number of size-cells was wrong. This series fixes this by backporting the corresponding patches from the upstream project. Changes since v1: - fix spelling of U-Boot (patch 1 + 2 /4) - add Reviewed-by tag (patch 1/4) - fix the case of size-cells == 0 (patch 3/4) - fix default address cells for livetree (patch 4/4) v1 can be found here: https://patchwork.ozlabs.org/patch/1137331/ https://patchwork.ozlabs.org/patch/1137330/ Matthias Brugger (4): libfdt: fdt_address_cells() and fdt_size_cells() libfdt: return correct value if #size-cells property is not present libfdt: Allow #size-cells of 0 dm: Fix default address cells return value include/dm/of.h | 2 +- scripts/dtc/libfdt/fdt_addresses.c | 45 ++++++++++++++++-------------- scripts/dtc/libfdt/libfdt.h | 2 +- 3 files changed, 26 insertions(+), 23 deletions(-) -- 2.22.0

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[U-Boot] [v3, 1/2] armv7: ls102xa: add errata ID A-008646 for workaround
by Biwen Li 22 Oct '19

22 Oct '19

The patch adds an errata ID A-008646 for workaround to provide more information by ID. Signed-off-by: Biwen Li <biwen.li(a)nxp.com> --- Change in v3: - adjust code style Change in v2: - update subject and description arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c index bb169aaaf4..afa4fd7a48 100644 --- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c +++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c @@ -68,9 +68,10 @@ static void __secure ls1_deepsleep_irq_cfg(void) ippdexpcr0 = in_be32(&rcpm->ippdexpcr0); /* - * Workaround: There is bug of register ippdexpcr1, when read it always - * returns zero, so its value is saved to a scrachpad register to be - * read, that is why we don't read it from register ippdexpcr1 itself. + * Workaround of errata A-008646: There is bug of register ippdexpcr1, + * when read it always returns zero, so its value is saved to a + * scrachpad register to be read, that is why we don't read it from + * register ippdexpcr1 itself. */ ippdexpcr1 = in_le32(&scfg->sparecr[7]); out_be32(&rcpm->ippdexpcr1, ippdexpcr1); -- 2.17.1

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[U-Boot] [PATCH 1/1] board/freescale/ls1028a: Secure boot: Adds sec_init call.
by Udit Agarwal 22 Oct '19

22 Oct '19

Adds sec_init call to initialise the job ring parameters for secure boot operations. Signed-off-by: Udit Agarwal <udit.agarwal(a)nxp.com> --- board/freescale/ls1028a/ls1028a.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c index 6b126bcf44..a92b5b1079 100644 --- a/board/freescale/ls1028a/ls1028a.c +++ b/board/freescale/ls1028a/ls1028a.c @@ -64,6 +64,10 @@ int board_init(void) gd->env_addr = (ulong)&default_environment[0]; #endif +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif + #ifdef CONFIG_FSL_LS_PPA ppa_init(); #endif -- 2.17.1

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[U-Boot] [PATCH] configs: ls1012afrwy: Add CONFIG_ENV_ADDR for LS1012AFRWY
by Kuldeep Singh 22 Oct '19

22 Oct '19

This configuration helps in picking the environment from flash before DDR init. Signed-off-by: Kuldeep Singh <kuldeep.singh(a)nxp.com> --- include/configs/ls1012afrwy.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h index 12e6437a05..14e63204c6 100644 --- a/include/configs/ls1012afrwy.h +++ b/include/configs/ls1012afrwy.h @@ -23,6 +23,11 @@ #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END 0x9fffffff +/* ENV */ +#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FSL_QSPI_BASE + \ + CONFIG_ENV_OFFSET) + #ifndef CONFIG_SPL_BUILD #undef BOOT_TARGET_DEVICES #define BOOT_TARGET_DEVICES(func) \ -- 2.17.1

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[U-Boot] [v2] armv7: ls102xa: Correct endianness of SCFG_SPARECR8 read
by Biwen Li 22 Oct '19

22 Oct '19

The patch corrects endianness of register SCFG_SPARECR8 read in_le32 -> in_be32 Signed-off-by: Biwen Li <biwen.li(a)nxp.com> --- Change in v2: - update subject and description arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c index bb169aaaf4..00b6ad48ce 100644 --- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c +++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c @@ -72,7 +72,7 @@ static void __secure ls1_deepsleep_irq_cfg(void) * returns zero, so its value is saved to a scrachpad register to be * read, that is why we don't read it from register ippdexpcr1 itself. */ - ippdexpcr1 = in_le32(&scfg->sparecr[7]); + ippdexpcr1 = in_be32(&scfg->sparecr[7]); out_be32(&rcpm->ippdexpcr1, ippdexpcr1); if (ippdexpcr0 & RCPM_IPPDEXPCR0_ETSEC) -- 2.17.1

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[U-Boot] [PATCH] armv8: fsl-layerscape: Make USB masters snoopable
by Ran Wang 22 Oct '19

22 Oct '19

Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang <ran.wang_1(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 9 +++++++++ arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 6 ++++++ 2 files changed, 15 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index b508bc9..17c0502 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -636,10 +636,19 @@ void fsl_lsch2_early_init_f(void) #endif #endif /* Make SEC reads and writes snoopable */ +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) + setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | + SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP | + SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP | + SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP | + SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP | + SCFG_SNPCNFGCR_SATAWRSNP); +#else setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_SATARDSNP | SCFG_SNPCNFGCR_SATAWRSNP); +#endif /* * Enable snoop requests and DVM message requests for diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index b4b7c34..524961d 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -409,6 +409,12 @@ struct ccsr_gur { #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 #define SCFG_SNPCNFGCR_SATARDSNP 0x00800000 #define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000 +#define SCFG_SNPCNFGCR_USB1RDSNP 0x00200000 +#define SCFG_SNPCNFGCR_USB1WRSNP 0x00100000 +#define SCFG_SNPCNFGCR_USB2RDSNP 0x00008000 +#define SCFG_SNPCNFGCR_USB2WRSNP 0x00010000 +#define SCFG_SNPCNFGCR_USB3RDSNP 0x00002000 +#define SCFG_SNPCNFGCR_USB3WRSNP 0x00004000 /* RGMIIPCR bit definitions*/ #define SCFG_RGMIIPCR_EN_AUTO BIT(3) -- 2.7.4

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[U-Boot] [PATCH v2] armv7: ls102xa: Correct entry of SCFG_QSPI_CLKSEL
by Kuldeep Singh 22 Oct '19

22 Oct '19

Value 0xC is reserved. Replace it with correct value 0x5 which is ClusterPLL/16 Signed-off-by: Ashish Kumar <Ashish.kumar(a)nxp.com> Signed-off-by: Kuldeep Singh <kuldeep.singh(a)nxp.com> --- v2: Reword commit message arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 137cd61804..f2ba182346 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -155,7 +155,7 @@ struct ccsr_gur { #define SCFG_ETSECCMCR_GE0_CLK125 0x00000000 #define SCFG_ETSECCMCR_GE1_CLK125 0x08000000 #define SCFG_PIXCLKCR_PXCKEN 0x80000000 -#define SCFG_QSPI_CLKSEL 0xc0100000 +#define SCFG_QSPI_CLKSEL 0x50100000 #define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000 #define SCFG_SNPCNFGCR_DCU_RD_WR 0x03000000 #define SCFG_SNPCNFGCR_SATA_RD_WR 0x00c00000 -- 2.17.1

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[U-Boot] [RESEND][PATCH v2] configs: ls1012ardb: Add CONFIG_ENV_ADDR for LS1012ARDB
by Kuldeep Singh 22 Oct '19

22 Oct '19

This configuration helps in picking the environment from flash before DDR init. Signed-off-by: Ashish Kumar <Ashish.Kumar(a)nxp.com> Signed-off-by: Kuldeep Singh <kuldeep.singh(a)nxp.com> --- v2: Reword commit message include/configs/ls1012ardb.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index f6640fa499..a5e27404f8 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -17,6 +17,10 @@ #define CONFIG_SYS_MEMTEST_END 0x9fffffff +/* ENV */ +#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FSL_QSPI_BASE + \ + CONFIG_ENV_OFFSET) /* * I2C IO expander */ -- 2.17.1

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[U-Boot] [PATCH v2] armv8: ls1028a: add more personalities support
by Yuantian Tang 22 Oct '19

22 Oct '19

Add LS1027A, LS1018A and LS1017A personalities support to LS1028A processor soc family. LS1028A processor is the prime personality of LS1028A soc family. LS1027A processor is a lower funtionality version of QorIQ LS1028A which does not support the multimedia subsystems, such as LCD controller, GPU, and eDP PHY. The QorIQ LS1018A and LS1017A are low power versions of the QorIQ LS1028A and LS1027A processors, respectively which integrate single 64-bit Arm A72 core. Signed-off-by: Tang Yuantian <andy.tang(a)nxp.com> --- v2: - refine description arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 3 +++ arch/arm/include/asm/arch-fsl-layerscape/soc.h | 3 +++ 2 files changed, 6 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 3e2a24fe80..dee96afe2d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -58,6 +58,9 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(LS1026A, LS1026A, 2), CPU_TYPE_ENTRY(LS2040A, LS2040A, 4), CPU_TYPE_ENTRY(LS1012A, LS1012A, 1), + CPU_TYPE_ENTRY(LS1017A, LS1017A, 1), + CPU_TYPE_ENTRY(LS1018A, LS1018A, 1), + CPU_TYPE_ENTRY(LS1027A, LS1027A, 2), CPU_TYPE_ENTRY(LS1028A, LS1028A, 2), CPU_TYPE_ENTRY(LS1088A, LS1088A, 8), CPU_TYPE_ENTRY(LS1084A, LS1084A, 8), diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -83,6 +83,9 @@ enum boot_src get_boot_src(void); /* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */ #define SVR_LS1043A_P23 0x879202 #define SVR_LS1023A_P23 0x87920A +#define SVR_LS1017A 0x870B24 +#define SVR_LS1018A 0x870B20 +#define SVR_LS1027A 0x870B04 #define SVR_LS1028A 0x870B00 #define SVR_LS1046A 0x870700 #define SVR_LS1026A 0x870708 -- 2.17.1

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[U-Boot] Issues with driver binding and probing
by Aaron Williams 21 Oct '19

21 Oct '19

Hi all, I have an issue where I have a nexus driver and a sub serial driver on top of it. The base nexus driver is getting bound and probed properly, however the serial drivers (pci-console) below it are not. My device tree looks something like this: pci-console-nexus@0x03000000 { /* Remote PCI console buffer location */ compatible = "marvell,pci-console-nexus"; status = "okay"; #address-cells = <2>; #size-cells = <1>; skip-init; num-consoles = <8>; reg = <0 0x03000000 0 0x40000>; ranges = <0 0 0 0x3000100 0x4000>, <1 0 0 0x3004100 0x4000>, <2 0 0 0x3008100 0x4000>, <3 0 0 0x300c100 0x4000>, <4 0 0 0x3010100 0x4000>, <5 0 0 0x3014100 0x4000>, <6 0 0 0x3018100 0x4000>, <7 0 0 0x301c100 0x4000>; console@0 { compatible = "marvell,pci-console"; status = "okay"; reg = <0 0 0x4000>; tx-buffer-size = <0x2f80>; rx-buffer-size = <0x1000>; }; ... console@7 { compatible = "marvell,pci-console"; status = "okay"; reg = <7 0 0x4000>; tx-buffer-size = <0x2f80>; rx-buffer-size = <0x1000>; }; }; When U-Boot binds the drivers it sees and binds pci-console-nexus but it never even attempts to go any deeper in the device tree. Both drivers are used. The nexus datastructure is a shared resouce that can be used by ATF. I added a bind function in the nexus driver that basically does: dev_for_each_subnode(node, parent) { ret = device_bind_driver_to_node(parent, DRIVER_NAME, ofnode_get_name(node), node, &dev); get_uclass(UCLASS_SERIAL, &uc); dev->uclass = uic; } With this I see the consoles in the dm tree and uclass list, but the sequences don't seem to be getting set. What I notice when I type dm uclass is: uclass 60: serial - * serial@87e028000000 @ 7fbeb3360, seq 0, (req 0) - serial@87e029000000 @ 7fbeb3430, seq -1, (req 1) - console@0 @ 7fbeb3660 - console@1 @ 7fbeb3780 - console@2 @ 7fbeb38a0 - console@3 @ 7fbeb39c0 - console@4 @ 7fbeb3ae0 - console@5 @ 7fbeb3c00 - console@6 @ 7fbeb3d20 - console@7 @ 7fbeb3e40 - * pci-bootcmd@0x03fff000 @ 7fbeb3f60, seq 1, (req -1) Does anyone have any ideas on how I should properly handle this? It seems that whatever I'm doing is overly complicated and I'm missing something for the DM layer to not go deeper into the tree past the nexus layer. static const struct udevice_id octeontx_pcie_console_nexus_serial_id[] = { { .compatible = "marvell,pci-console-nexus", }, { }, }; U_BOOT_DRIVER(octeontx_pcie_console_nexus) = { .name = DRIVER_NAME "-nexus", .id = UCLASS_MISC, .flags = DM_FLAG_PRE_RELOC, .of_match = of_match_ptr(octeontx_pcie_console_nexus_serial_id), .ofdata_to_platdata = octeontx_pcie_console_nexus_ofdata_to_platdata, .platdata_auto_alloc_size = sizeof(struct octeontx_pcie_console_plat_data), .bind = octeontx_pcie_console_nexus_bind, .probe = octeontx_pcie_console_nexus_probe, .priv_auto_alloc_size = sizeof(struct octeontx_pcie_console_nexus_priv), }; static const struct dm_serial_ops octeontx_pcie_console_ops = { .setbrg = octeontx_pcie_console_setbrg, .getc = octeontx_pcie_console_getc, .putc = octeontx_pcie_console_putc, .pending = octeontx_pcie_console_pending, .clear = octeontx_pcie_console_clear, }; static const struct udevice_id octeontx_pcie_console_serial_id[] = { { .compatible = "marvell,pci-console", }, { }, }; U_BOOT_DRIVER(octeontx_pcie_console) = { .name = DRIVER_NAME, .id = UCLASS_SERIAL, .ops = &octeontx_pcie_console_ops, .of_match = of_match_ptr(octeontx_pcie_console_serial_id), .probe = octeontx_pcie_console_probe, .ofdata_to_platdata = octeontx_pcie_console_ofdata_to_platdata, .remove = octeontx_pcie_console_remove, .priv_auto_alloc_size = sizeof(struct octeontx_pcie_console_priv), .platdata_auto_alloc_size = sizeof(struct octeontx_pcie_console_plat_data), .flags = DM_FLAG_OS_PREPARE | DM_FLAG_PRE_RELOC, }; -Aaron

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