September 2019 - U-Boot

[U-Boot] [PATCH] sunxi: set PIO voltage to hardware-detected value on startup on H6
by Icenowy Zheng 25 Oct '19

25 Oct '19

The Allwinner H6 SoC has a register to set the PIO banks' voltage. When it mismatches the real voltage supplied to the VCC to the PIO supply, the PIO will work improperly. The PIO controller also has a register that contains the status of each VCC rail of the PIO supplies, and it has the same definition with the configuration register. so we can just copy the content of this register to the configuration register at startup, to ensure the configuration is correct at startup stage. Signed-off-by: Icenowy Zheng <icenowy(a)aosc.io> --- arch/arm/include/asm/arch-sunxi/gpio.h | 3 +++ arch/arm/mach-sunxi/board.c | 9 +++++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 40a3f845d0..a646ea6a3c 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -73,6 +73,9 @@ struct sunxi_gpio_reg { struct sunxi_gpio_int gpio_int; }; +#define SUN50I_H6_GPIO_POW_MOD_SEL 0x340 +#define SUN50I_H6_GPIO_POW_MOD_VAL 0x348 + #define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_L) ? \ &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \ &((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_L]) diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index c6dd7b8e54..bd3b5d8303 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -65,6 +65,7 @@ struct mm_region *mem_map = sunxi_mem_map; static int gpio_init(void) { + __maybe__unused uint val; #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F) #if defined(CONFIG_MACH_SUN4I) || \ defined(CONFIG_MACH_SUN7I) || \ @@ -139,6 +140,14 @@ static int gpio_init(void) #error Unsupported console port number. Please fix pin mux settings in board.c #endif +#ifdef CONFIG_MACH_SUN50I_H6 + /* Update PIO power bias configuration by copy hardware detected value */ + val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL); + writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL); + val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL); + writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL); +#endif + return 0; } -- 2.18.1

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[U-Boot] python3 support for pylibfdt
by Peter Robinson 25 Oct '19

25 Oct '19

Hi Simon, With the EOL of python2 soon I've been looking at the Fedora U-Boot builds to see what it would take to move over to python3. There's a couple of issues building the bundled pylibfdt, the first is the Makefile hard codes python2, the second is that the generated libfdt_wrap.c doesn't seem to find the python3 version of Python.h (errors below). It seems upstream now supports building pylibfdt with dtc 1.5.0 but I couldn't quite work out how this fits into the U-Boot bundled version. Is there plans to be able to support pylibfdt with python3? Regards, Peter gcc -O2 -g -pipe -Wall -Werror=format-security -Wp,-D_FORTIFY_SOURCE=2 -Wp,-D_GLIBCXX_ASSERTIONS -fexceptions -fstack-protector-strong -grecord-gcc-switches -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -fasynchronous-unwind-tables -fstack-clash-protection -o scripts/dtc/dtc scripts/dtc/dtc.o scripts/dtc/flattree.o scripts/dtc/fstree.o scripts/dtc/data.o scripts/dtc/livetree.o scripts/dtc/treesource.o scripts/dtc/srcpos.o scripts/dtc/checks.o scripts/dtc/util.o scripts/dtc/dtc-lexer.lex.o scripts/dtc/dtc-parser.tab.o BUILDSTDERR: set -e; : ' CHK include/generated/generic-asm-offsets.h'; mkdir -p include/generated/; (set -e; echo "#ifndef __GENERIC_ASM_OFFSETS_H__"; echo "#define __GENERIC_ASM_OFFSETS_H__"; echo "/*"; echo " * DO NOT MODIFY."; echo " *"; echo " * This file was generated by Kbuild"; escripts/dtc/pylibfdt/libfdt_wrap.c:154:11: fatal error: Python.h: No such file or directory BUILDSTDERR: 154 | # include <Python.h> BUILDSTDERR: | ^~~~~~~~~~ BUILDSTDERR: compilation terminated. BUILDSTDERR: error: command 'gcc' failed with exit status 1 BUILDSTDERR: make[4]: *** [/builddir/build/BUILD/u-boot-2019.07-rc4/scripts/dtc/pylibfdt/Makefile:27: scripts/dtc/pylibfdt/_libfdt.so] Error 1 BUILDSTDERR: make[3]: *** [/builddir/build/BUILD/u-boot-2019.07-rc4/scripts/Makefile.build:432: scripts/dtc/pylibfdt] Error 2 BUILDSTDERR: make[2]: *** [/builddir/build/BUILD/u-boot-2019.07-rc4/scripts/Makefile.build:432: scripts/dtc] Error 2 BUILDSTDERR: make[1]: *** [/builddir/build/BUILD/u-boot-2019.07-rc4/Makefile:528: scripts] Error 2 BUILDSTDERR: make: *** [Makefile:148: sub-make] Error 2 BUILDSTDERR: error: Bad exit status from /var/tmp/rpm-tmp.Ca2SD2 (%build)

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[U-Boot] [PATCH 0/7] am57xx: Implement Android 10 boot flow
by Sam Protsenko 24 Oct '19

24 Oct '19

Android 10 brings a lot of new requirements for bootloaders: [1]. This patch series attempts to implement such a boot process on BeagleBoard X15 platform. Some common code is added too, which can be reused later for other platforms. [1] https://source.android.com/devices/bootloader Sam Protsenko (7): image: android: Add functions for handling dtb field image: android: Add routine to get dtbo params cmd: bootimg: Add bootimg command configs: am57xx_evm: Enable Android commands env: ti: boot: Respect slot_suffix in AVB commands env: ti: boot: Boot Android with dynamic partitions arm: ti: boot: Use correct dtb and dtbo on Android boot cmd/Kconfig | 8 + cmd/Makefile | 1 + cmd/bootimg.c | 177 ++++++++++++++++++++ common/Makefile | 2 +- common/image-android.c | 245 ++++++++++++++++++++++++++++ configs/am57xx_evm_defconfig | 8 +- configs/am57xx_hs_evm_defconfig | 6 + configs/am57xx_hs_evm_usb_defconfig | 8 +- include/configs/ti_armv7_common.h | 7 + include/environment/ti/boot.h | 145 ++++++++-------- include/image.h | 7 + 11 files changed, 546 insertions(+), 68 deletions(-) create mode 100644 cmd/bootimg.c -- 2.23.0

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[U-Boot] [PATCH 1/3] mtd: spi: Add a new option SPL_SPI_FLASH_MTD to Kconfig
by Schrempf Frieder 23 Oct '19

23 Oct '19

From: Frieder Schrempf <frieder.schrempf(a)kontron.de> To allow SPI_FLASH_MTD being enabled separately in SPL we add a new option. The only user currently is the stm32mp15_basic board. Signed-off-by: Frieder Schrempf <frieder.schrempf(a)kontron.de> --- drivers/mtd/spi/Kconfig | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index d3b007a731..f5cb7f6577 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -196,4 +196,12 @@ config SPI_FLASH_MTD If unsure, say N +config SPL_SPI_FLASH_MTD + bool "SPI flash MTD support for SPL" + depends on SPI_FLASH + help + Enable the MTD support for the SPI flash layer in SPL. + + If unsure, say N + endmenu # menu "SPI Flash Support" -- 2.17.1

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[U-Boot] [PATCH 1/6] spi: fsl_qspi: Fix DDR mode setting for latest iMX platforms
by Ye Li 23 Oct '19

23 Oct '19

On latest iMX platforms like iMX7D/iMX6UL/iMX8MQ, the QSPI controller is updated to have TDH field in FLSHCR register. According to reference manual, this TDH must be set to 1 when DDR_EN is set. Otherwise, the TX DDR delay logic won't be enabled. Another issue in DDR mode is the MCR register will be overwritten in every read/write/erase operation. This causes DDR_EN been cleared while TDH=1, then no clk2x output for TX data shift and all operations will fail. Signed-off-by: Ye Li <ye.li(a)nxp.com> --- drivers/spi/fsl_qspi.c | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 41abe19..8845986 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -399,7 +399,7 @@ static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len) qspi_write32(priv->flags, &regs->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | - QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + mcr_reg); rx_addr = (void *)(uintptr_t)(priv->cur_amba_base + priv->sf_addr); /* Read out the data directly from the AHB buffer. */ @@ -429,6 +429,14 @@ static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv) reg |= BIT(29); qspi_write32(priv->flags, &regs->mcr, reg); + + /* Enable the TDH to 1 for some platforms like imx6ul, imx7d, etc + * These two bits are reserved on other platforms + */ + reg = qspi_read32(priv->flags, &regs->flshcr); + reg &= ~(BIT(17)); + reg |= BIT(16); + qspi_write32(priv->flags, &regs->flshcr, reg); } /* @@ -482,7 +490,7 @@ static void qspi_op_rdbank(struct fsl_qspi_priv *priv, u8 *rxbuf, u32 len) mcr_reg = qspi_read32(priv->flags, &regs->mcr); qspi_write32(priv->flags, &regs->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | - QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + mcr_reg); qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS); qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base); @@ -527,7 +535,7 @@ static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len) mcr_reg = qspi_read32(priv->flags, &regs->mcr); qspi_write32(priv->flags, &regs->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | - QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + mcr_reg); qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS); qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base); @@ -573,7 +581,7 @@ static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len) mcr_reg = qspi_read32(priv->flags, &regs->mcr); qspi_write32(priv->flags, &regs->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | - QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + mcr_reg); qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS); to_or_from = priv->sf_addr + priv->cur_amba_base; @@ -625,7 +633,7 @@ static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len) mcr_reg = qspi_read32(priv->flags, &regs->mcr); qspi_write32(priv->flags, &regs->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | - QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + mcr_reg); qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS); status_reg = 0; @@ -700,7 +708,7 @@ static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len) mcr_reg = qspi_read32(priv->flags, &regs->mcr); qspi_write32(priv->flags, &regs->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | - QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + mcr_reg); qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS); qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base); @@ -737,7 +745,7 @@ static void qspi_op_erase(struct fsl_qspi_priv *priv) mcr_reg = qspi_read32(priv->flags, &regs->mcr); qspi_write32(priv->flags, &regs->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | - QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + mcr_reg); qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS); to_or_from = priv->sf_addr + priv->cur_amba_base; @@ -900,15 +908,9 @@ static int fsl_qspi_probe(struct udevice *bus) return ret; } - mcr_val = qspi_read32(priv->flags, &priv->regs->mcr); - - /* Set endianness to LE for i.mx */ - if (IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7)) - mcr_val = QSPI_MCR_END_CFD_LE; - qspi_write32(priv->flags, &priv->regs->mcr, QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK | - (mcr_val & QSPI_MCR_END_CFD_MASK)); + QSPI_MCR_END_CFD_LE); qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK | QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0); -- 2.7.4

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[U-Boot] [PATCH] board: stm32mp1: fixup the usb product id for USB download gadget
by Patrick Delaunay 23 Oct '19

23 Oct '19

Select the correct USB product id used by the download gadget for ST stm32mp1 boards. The board stm32mp1 select the correct product id, as defined in http://www.linux-usb.org/usb.ids for the STMicroelectronics vendor id = 0x0483 (CONFIG_USB_GADGET_VENDOR_NUM): - dfu = 0xdf11 : STM Device in DFU mode it is the value used by ROM code and reused for stm32prog command - fasboot = 0x0afb : Android Fastboot device - others = 0x5720 (CONFIG_USB_GADGET_PRODUCT_NUM) Mass Storage Device it is used for UMS command / usb_dnl_ums This patch avoid conflict when the same USB VID/PID is used for ums, fastboot or dfu command (two different protocols associated to the same PID). Signed-off-by: Patrick Delaunay <patrick.delaunay(a)st.com> --- board/st/stm32mp1/stm32mp1.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 18f9b84876..126af30173 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -233,6 +233,23 @@ int g_dnl_board_usb_cable_connected(void) return dwc2_udc_B_session_valid(dwc2_udc_otg); } + +#define STM32MP1_G_DNL_DFU_PRODUCT_NUM 0xdf11 +#define STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM 0x0afb + +int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) +{ + if (!strcmp(name, "usb_dnl_dfu")) + put_unaligned(STM32MP1_G_DNL_DFU_PRODUCT_NUM, &dev->idProduct); + else if (!strcmp(name, "usb_dnl_fastboot")) + put_unaligned(STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM, + &dev->idProduct); + else + put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, &dev->idProduct); + + return 0; +} + #endif /* CONFIG_USB_GADGET */ #ifdef CONFIG_LED -- 2.17.1

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[U-Boot] [PATCH] configs: stm32f746-disco: Fix ramdisk_addr_r
by Patrice Chotard 23 Oct '19

23 Oct '19

Set ramdisk_addr_r to 0xC0600000. Reported-by: Christophe Priouzeau <christophe.priouzeau(a)st.com> Signed-off-by: Patrice Chotard <patrice.chotard(a)st.com> --- include/configs/stm32f746-disco.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index a24127d1a7..cc26f83e74 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -55,7 +55,7 @@ "pxefile_addr_r=0xC0008000\0" \ "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ - "ramdisk_addr_r=0xD0900000\0" \ + "ramdisk_addr_r=0xC0600000\0" \ BOOTENV /* -- 2.17.1

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[U-Boot] [PATCH 0/5] Disable CONFIG_NET flag for STM32F4 and STM32H7 boards
by Patrice Chotard 23 Oct '19

23 Oct '19

All STM32F4 and STM32H7 boards have CONFIG_NET flags enable in their defconfig whereas network support was never added. Simply disable CONFIG_NET to avoid following compilation warning: ===================== WARNING ====================== This board does not use CONFIG_DM_ETH (Driver Model for Ethernet drivers). Please update the board to use CONFIG_DM_ETH before the v2020.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/migration.rst for more info. ==================================================== Patrice Chotard (5): configs: stm32f429-discovery: Disable CONFIG_NET flag configs: stm32f429-evaluation: Disable CONFIG_NET flag configs: stm32f469-discovery: Disable CONFIG_NET flag configs: stm32h743-disco: Disable CONFIG_NET flag configs: stm32h743-eval: Disable CONFIG_NET flag configs/stm32f429-discovery_defconfig | 1 + configs/stm32f429-evaluation_defconfig | 2 +- configs/stm32f469-discovery_defconfig | 2 +- configs/stm32h743-disco_defconfig | 1 + configs/stm32h743-eval_defconfig | 1 + 5 files changed, 5 insertions(+), 2 deletions(-) -- 2.17.1

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[U-Boot] [PATCH 0/2] spi-nor-core: Fix small sector erase with SFDP
by Vignesh Raghavendra 22 Oct '19

22 Oct '19

First patch improves error reporting on erase/write failures Second patch makes sure small sector is used even when SFDP is enabled and CONFIG_SPI_FLASH_USE_4K_SECTORS is set. Jagan, Could you please consider these patches for next -rc? Vignesh Raghavendra (2): mtd: spi-nor-core: Use dev_err for reporting erase/write failures mtd: spi-nor-core: Replace MTD_SPI_NOR_USE_4K_SECTORS with SPI_FLASH_USE_4K_SECTORS drivers/mtd/spi/spi-nor-core.c | 8 ++++---- drivers/mtd/spi/spi-nor-ids.c | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) -- 2.23.0

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[U-Boot] [PATCH v3 0/3] env: Add CONFIG_ENV_FULL_SUPPORT
by Patrick Delaunay 22 Oct '19

22 Oct '19

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