August 2019 - U-Boot

[U-Boot] [PATCH V3 01/10] spi: hsspi: allow to be used on bcm6858 and bcm63158
by Philippe Reynes 12 Oct '19

12 Oct '19

From: Kursad Oney <kursad.oney(a)broadcom.com> This IP exists in both MIPS and ARM cores, so we also allow to use this driver on bcm6858 and bcm63158. Signed-off-by: Kursad Oney <kursad.oney(a)broadcom.com> Reviewed-by: Philippe Reynes <philippe.reynes(a)softathome.com> --- drivers/spi/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Changelog: v3: - no change v2: - add dependancy on bcm6858 and bcm63158 instead of removing mips dependancy (thanks Daniel) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index f459c0a..932d2d9 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -67,7 +67,7 @@ config ATMEL_SPI config BCM63XX_HSSPI bool "BCM63XX HSSPI driver" - depends on ARCH_BMIPS + depends on (ARCH_BMIPS || ARCH_BCM6858 || ARCH_BCM63158) help Enable the BCM6328 HSSPI driver. This driver can be used to access the SPI NOR flash on platforms embedding this Broadcom -- 2.7.4

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[U-Boot] [PATCH v3 00/57] ram: rk3399: Add LPDDR4 support
by Jagan Teki 12 Oct '19

12 Oct '19

This is next revison of lpddr4 support on rk3399 compared to previous set[1]. It has some changes based on the commit orders and squashing few patches together and rest is same. Thanks to - YouMin Chen - Akash Gajjar - Kever Yang for supporting all the help on this work. Changes for v3: - squash set_rate code in one patch - tested in Rockpro64 and Rock-PI-4 - order them in proper way - rebase on master Changes for v2: - handle LPDDR4 code as part of CONFIG_RAM_RK3399_LPDDR4 - support data_training and set_rate via sdram_rk3399_ops - add proper sys_reg_enc macros - add new patch to rename variable sdram_params with params - fix few commit messages. patch 0001 - 0018: add dram config enc macro patch 0019: configure phy IO in ds odt patch 0020: add LPDDR4 config patch 0021 - 0043: lpddr4 data training changes patch 0044 - 0046: syscon pmu support patch 0047: set 50MHz ddr clock patch 0048: set 400MHz ddr clock patch 0049: LPDDR4-400 timings patch 0050: LPDDR4-800 timings patch 0051 - 0052: lpddr4 set rate patch 0053: enable lpddr4 support on Rockpro64 patch 0054: enable lpddr4 support on Rock-PI 4 patch 0055: add LPDDR-100 timings via dts patch 0056: use LPDDR-100 timings on Rockpro64 patch 0057: use LPDDR-100 timings on Rock-PI 4 [1] https://patchwork.ozlabs.org/cover/1116734/ Any inputs? Jagan. Jagan Teki (57): ram: rk3399: Add ddrtype enc macro ram: rk3399: Add channel number encoder macro ram: rk3399: Add row_3_4 enc macro ram: rk3399: Add chipinfo macro ram: rk3399: Add rank enc macro ram: rk3399: Add column enc macro ram: rk3399: Add bk enc macro ram: rk3399: Add dbw enc macro ram: rk3399: Add cs0_rw macro ram: rk3399: Add cs1_rw macro ram: rk3399: Add bw enc macro ram: rk3399: Rename sys_reg with sys_reg2 ram: rk3399: Update cs0_row to use sys_reg3 ram: rk3399: Update cs1_row to use sys_reg3 ram: rk3399: Add cs1_col enc macro ram: rk3399: Add ddr version enc macro ram: rk3399: Add ddrtimingC0 ram: rk3399: Add DdrMode ram: rk3399: Configure phy IO in ds odt ram: rockchip: Kconfig: Add RK3399 LPDDR4 entry ram: rk3399: Add lpddr4 rank mask for ca training ram: rk3399: Add lpddr4 rank mask for wdql training ram: rk3399: Move mode_sel assignment ram: rk3399: Don't wait for PLL lock in lpddr4 ram: rk3399: Avoid two channel ZQ Cal Start at the same time ram: rk3399: Configure PHY_898, PHY_919 for lpddr4 ram: rk3399: Configure BOOSTP_EN, BOOSTN_EN for lpddr4 ram: rk3399: Configure SLEWP_EN, SLEWN_EN for lpddr4 ram: rk3399: Configure PHY RX_CM_INPUT for lpddr4 ram: rk3399: Map chipselect for lpddr4 ram: rk3399: Configure tsel write ca for lpddr4 ram: rk3399: Don't disable dfi dram clk for lpddr4, rank 1 ram: rk3399: Add IO settings ram: sdram: Configure lpddr4 tsel rd, wr based on IO settings ram: rk3399: Add tsel control clock drive ram: rk3399: Configure soc odt support ram: rk3399: Get lpddr4 tsel_rd_en from io settings ram: rk3399: Update lpddr4 vref based on io settings ram: rk3399: Update lpddr4 mode_sel based on io settings ram: rk3399: Update lpddr4 vref_mode_ac ram: rk3399: Simplify data training first argument ram: rk3399: Handle data training via ops ram: rk3399: Add LPPDR4 mr detection arm: include: rockchip: Add rk3399 pmu file rockchip: rk3399: syscon: Add pmu support rockchip: dts: rk3399: Add u-boot, dm-pre-reloc for pmu clk: rockchip: rk3399: Set 50MHz ddr clock clk: rockchip: rk3399: Set 400MHz ddr clock ram: rk3399: Add LPPDDR4-400 timings inc ram: rk3399: Add LPPDDR4-800 timings inc ram: rk3399: Add set_rate sdram rk3399 ops ram: rk3399: Add lpddr4 set rate support configs: rockpro64: Enable LPDDR4 support configs: rock-pi-4: Enable LPDDR4 support rockchip: dts: rk3399: Add LPDDR4-100 timings rockchip: dts: rk3399: rockpro64: Use LPDDR4-100 dtsi rockchip: dts: rk3399: rock-pi-4: Use LPDDR4-100 dtsi arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 1 + arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 1 + arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi | 1537 +++++++++++++++ arch/arm/dts/rk3399-u-boot.dtsi | 4 + .../include/asm/arch-rockchip/pmu_rk3399.h | 72 + .../include/asm/arch-rockchip/sdram_common.h | 31 + .../include/asm/arch-rockchip/sdram_rk3399.h | 29 +- arch/arm/mach-rockchip/rk3399/syscon_rk3399.c | 8 + configs/rock-pi-4-rk3399_defconfig | 1 + configs/rockpro64-rk3399_defconfig | 1 + drivers/clk/rockchip/clk_rk3399.c | 8 + drivers/ram/rockchip/Kconfig | 7 + .../ram/rockchip/sdram-rk3399-lpddr4-400.inc | 1570 +++++++++++++++ .../ram/rockchip/sdram-rk3399-lpddr4-800.inc | 1570 +++++++++++++++ drivers/ram/rockchip/sdram_rk3399.c | 1726 ++++++++++++++--- 15 files changed, 6317 insertions(+), 249 deletions(-) create mode 100644 arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi create mode 100644 arch/arm/include/asm/arch-rockchip/pmu_rk3399.h create mode 100644 drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc create mode 100644 drivers/ram/rockchip/sdram-rk3399-lpddr4-800.inc -- 2.18.0.321.gffc6fa0e3

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[U-Boot] [RESEND PATCH 1/2] dm: Tidy up dump output when there are many devices
by Patrick Delaunay 12 Oct '19

12 Oct '19

At present the 'Index' column of 'dm tree' assumes there is two digits, this patch increase it to 3 digits. It also aligns output of 'dm uclass', assuming the same 3 digits index. The boards with CONFIG_PINCTRL_FULL activated have one pinconfig by pin configuration, so they can have more than 100 devices pinconfig (for example with stm32mp157c-ev1 board we have 106 pinconfig node). Signed-off-by: Patrick Delaunay <patrick.delaunay(a)st.com> --- stm32mp157c-ev1 trace before the patch STM32MP> dm tree Class Index Probed Driver Name ----------------------------------------------------------- root 0 [ + ] root_driver root_driver sysreset 0 [ ] syscon_reboot |-- reboot .... pinctrl 0 [ + ] pinctrl_stm32 | |-- pin-controller@50002000 gpio 0 [ + ] gpio_stm32 | | |-- gpio@50002000 gpio 1 [ + ] gpio_stm32 | | |-- gpio@50003000 ... gpio 9 [ ] gpio_stm32 | | |-- gpio@5000b000 gpio 10 [ ] gpio_stm32 | | |-- gpio@5000c000 pinconfig 0 [ ] pinconfig | | |-- adc12-usb-pwr-pins-0 pinconfig 95 [ ] pinconfig | | |-- uart7-0 ... pinconfig 99 [ ] pinconfig | | `-- pins .... pinctrl 1 [ + ] pinctrl_stm32 | |-- pin-controller-z@54004000 gpio 11 [ + ] gpio_stm32 | | |-- gpio@54004000 pinconfig 100 [ + ] pinconfig | | |-- i2c4-0 pinconfig 101 [ ] pinconfig | | | `-- pins .... STM32MP> dm uclass ..... uclass 60: pinconfig 0 adc12-usb-pwr-pins-0 @ fdf56140 1 pins @ fdf56198 ... 8 cec-sleep-1 @ fdf56400 9 pins @ fdf56458 10 * rgmii-0 @ fdf564b0, seq 5, (req -1) 11 pins1 @ fdf56508 ... 98 usbotg_hs-0 @ fdf582f0 99 pins @ fdf58348 100 * i2c4-0 @ fdf58450, seq 0, (req -1) 101 pins @ fdf584a8 .... Full trace with the patch STM32MP> dm tree Class Index Probed Driver Name ----------------------------------------------------------- root 0 [ + ] root_driver root_driver sysreset 0 [ ] syscon_reboot |-- reboot simple_bus 0 [ + ] generic_simple_bus |-- soc serial 0 [ + ] serial_stm32 | |-- serial@40010000 i2c 0 [ ] stm32f7-i2c | |-- i2c@40013000 i2c_generi 0 [ ] stmfx | | `-- stmfx@42 i2c 1 [ ] stm32f7-i2c | |-- i2c@40015000 usb 0 [ ] dwc2-udc-otg | |-- usb-otg@49000000 hwspinlock 0 [ + ] hwspinlock_stm32mp1 | |-- hwspinlock@4c000000 mailbox 0 [ ] stm32_ipcc | |-- mailbox@4c001000 misc 0 [ + ] stm32-rcc | |-- rcc@50000000 clk 0 [ + ] stm32mp1_clk | | |-- stm32mp1_clk reset 0 [ + ] stm32_rcc_reset | | `-- stm32_rcc_reset syscon 0 [ + ] stmp32mp_syscon | |-- pwr@50001000 pmic 0 [ + ] stm32mp_pwr_pmic | | `-- pwr-regulators regulator 0 [ + ] stm32mp_pwr_regulato | | |-- reg11 regulator 1 [ + ] stm32mp_pwr_regulato | | |-- reg18 regulator 2 [ + ] stm32mp_pwr_regulato | | `-- usb33 syscon 1 [ ] syscon | |-- interrupt-controller@5000d000 syscon 2 [ + ] stmp32mp_syscon | |-- syscon@50020000 mtd 0 [ + ] stm32_fmc2_nand | |-- nand-controller@58002000 spi 0 [ ] stm32_qspi | |-- spi@58003000 spi_flash 0 [ ] spi_flash_std | | |-- mx66l51235l@0 spi_flash 1 [ ] spi_flash_std | | `-- mx66l51235l@1 mmc 0 [ + ] stm32_sdmmc2 | |-- sdmmc@58005000 blk 0 [ + ] mmc_blk | | `-- sdmmc(a)58005000.blk mmc 1 [ + ] stm32_sdmmc2 | |-- sdmmc@58007000 blk 1 [ ] mmc_blk | | `-- sdmmc(a)58007000.blk eth 0 [ + ] eth_eqos | |-- ethernet@5800a000 usb 0 [ ] ehci_generic | |-- usbh-ehci@5800d000 phy 0 [ ] stm32-usbphyc | |-- usbphyc@5a006000 i2c 2 [ + ] stm32f7-i2c | |-- i2c@5c002000 pmic 1 [ + ] stpmic1_pmic | | `-- stpmic@33 regulator 3 [ + ] stpmic1_buck | | |-- buck1 regulator 4 [ + ] stpmic1_buck | | |-- buck2 regulator 5 [ + ] stpmic1_buck | | |-- buck3 regulator 6 [ + ] stpmic1_buck | | |-- buck4 regulator 7 [ + ] stpmic1_ldo | | |-- ldo1 regulator 8 [ + ] stpmic1_ldo | | |-- ldo2 regulator 9 [ + ] stpmic1_ldo | | |-- ldo3 regulator 10 [ + ] stpmic1_ldo | | |-- ldo4 regulator 11 [ + ] stpmic1_ldo | | |-- ldo5 regulator 12 [ + ] stpmic1_ldo | | |-- ldo6 regulator 13 [ + ] stpmic1_vref_ddr | | |-- vref_ddr regulator 14 [ + ] stpmic1_boost | | |-- boost regulator 15 [ + ] stpmic1_pwr_sw | | |-- pwr_sw1 regulator 16 [ + ] stpmic1_pwr_sw | | |-- pwr_sw2 sysreset 1 [ ] stpmic1-sysreset | | `-- stpmic1-sysreset rtc 0 [ ] rtc-stm32 | |-- rtc@5c004000 misc 1 [ + ] stm32mp_bsec | |-- nvmem@5c005000 pinctrl 0 [ + ] pinctrl_stm32 | |-- pin-controller@50002000 gpio 0 [ + ] gpio_stm32 | | |-- gpio@50002000 gpio 1 [ + ] gpio_stm32 | | |-- gpio@50003000 gpio 2 [ + ] gpio_stm32 | | |-- gpio@50004000 gpio 3 [ + ] gpio_stm32 | | |-- gpio@50005000 gpio 4 [ + ] gpio_stm32 | | |-- gpio@50006000 gpio 5 [ + ] gpio_stm32 | | |-- gpio@50007000 gpio 6 [ + ] gpio_stm32 | | |-- gpio@50008000 gpio 7 [ + ] gpio_stm32 | | |-- gpio@50009000 gpio 8 [ ] gpio_stm32 | | |-- gpio@5000a000 gpio 9 [ ] gpio_stm32 | | |-- gpio@5000b000 gpio 10 [ ] gpio_stm32 | | |-- gpio@5000c000 pinconfig 0 [ ] pinconfig | | |-- adc12-usb-pwr-pins-0 pinconfig 1 [ ] pinconfig | | | `-- pins pinconfig 2 [ ] pinconfig | | |-- cec-0 pinconfig 3 [ ] pinconfig | | | `-- pins pinconfig 4 [ ] pinconfig | | |-- cec-sleep-0 pinconfig 5 [ ] pinconfig | | | `-- pins pinconfig 6 [ ] pinconfig | | |-- cec-1 pinconfig 7 [ ] pinconfig | | | `-- pins pinconfig 8 [ ] pinconfig | | |-- cec-sleep-1 pinconfig 9 [ ] pinconfig | | | `-- pins pinconfig 10 [ + ] pinconfig | | |-- rgmii-0 pinconfig 11 [ ] pinconfig | | | |-- pins1 pinconfig 12 [ ] pinconfig | | | |-- pins2 pinconfig 13 [ ] pinconfig | | | `-- pins3 pinconfig 14 [ ] pinconfig | | |-- rgmii-sleep-0 pinconfig 15 [ ] pinconfig | | | `-- pins1 pinconfig 16 [ + ] pinconfig | | |-- fmc-0 pinconfig 17 [ ] pinconfig | | | |-- pins1 pinconfig 18 [ ] pinconfig | | | `-- pins2 pinconfig 19 [ ] pinconfig | | |-- fmc-sleep-0 pinconfig 20 [ ] pinconfig | | | `-- pins pinconfig 21 [ ] pinconfig | | |-- i2c1-0 pinconfig 22 [ ] pinconfig | | | `-- pins pinconfig 23 [ ] pinconfig | | |-- i2c1-1 pinconfig 24 [ ] pinconfig | | | `-- pins pinconfig 25 [ ] pinconfig | | |-- i2c1-2 pinconfig 26 [ ] pinconfig | | | `-- pins pinconfig 27 [ ] pinconfig | | |-- i2c2-0 pinconfig 28 [ ] pinconfig | | | `-- pins pinconfig 29 [ ] pinconfig | | |-- i2c2-1 pinconfig 30 [ ] pinconfig | | | `-- pins pinconfig 31 [ ] pinconfig | | |-- i2c2-2 pinconfig 32 [ ] pinconfig | | | `-- pins pinconfig 33 [ ] pinconfig | | |-- i2c5-0 pinconfig 34 [ ] pinconfig | | | `-- pins pinconfig 35 [ ] pinconfig | | |-- i2c5-1 pinconfig 36 [ ] pinconfig | | | `-- pins pinconfig 37 [ ] pinconfig | | |-- ltdc-a-0 pinconfig 38 [ ] pinconfig | | | `-- pins pinconfig 39 [ ] pinconfig | | |-- ltdc-a-1 pinconfig 40 [ ] pinconfig | | | `-- pins pinconfig 41 [ ] pinconfig | | |-- ltdc-b-0 pinconfig 42 [ ] pinconfig | | | `-- pins pinconfig 43 [ ] pinconfig | | |-- ltdc-b-1 pinconfig 44 [ ] pinconfig | | | `-- pins pinconfig 45 [ ] pinconfig | | |-- m-can1-0 pinconfig 46 [ ] pinconfig | | | |-- pins1 pinconfig 47 [ ] pinconfig | | | `-- pins2 pinconfig 48 [ ] pinconfig | | |-- m_can1-sleep@0 pinconfig 49 [ ] pinconfig | | | `-- pins pinconfig 50 [ ] pinconfig | | |-- pwm2-0 pinconfig 51 [ ] pinconfig | | | `-- pins pinconfig 52 [ ] pinconfig | | |-- pwm8-0 pinconfig 53 [ ] pinconfig | | | `-- pins pinconfig 54 [ ] pinconfig | | |-- pwm12-0 pinconfig 55 [ ] pinconfig | | | `-- pins pinconfig 56 [ ] pinconfig | | |-- qspi-clk-0 pinconfig 57 [ ] pinconfig | | | `-- pins pinconfig 58 [ ] pinconfig | | |-- qspi-bk1-0 pinconfig 59 [ ] pinconfig | | | |-- pins1 pinconfig 60 [ ] pinconfig | | | `-- pins2 pinconfig 61 [ ] pinconfig | | |-- qspi-bk2-0 pinconfig 62 [ ] pinconfig | | | |-- pins1 pinconfig 63 [ ] pinconfig | | | `-- pins2 pinconfig 64 [ + ] pinconfig | | |-- sdmmc1-b4-0 pinconfig 65 [ ] pinconfig | | | `-- pins pinconfig 66 [ ] pinconfig | | |-- sdmmc1-b4-od-0 pinconfig 67 [ ] pinconfig | | | |-- pins1 pinconfig 68 [ ] pinconfig | | | `-- pins2 pinconfig 69 [ ] pinconfig | | |-- sdmmc1-b4-sleep-0 pinconfig 70 [ ] pinconfig | | | `-- pins pinconfig 71 [ + ] pinconfig | | |-- sdmmc1-dir-0 pinconfig 72 [ ] pinconfig | | | |-- pins1 pinconfig 73 [ ] pinconfig | | | `-- pins2 pinconfig 74 [ ] pinconfig | | |-- sdmmc1-dir-sleep-0 pinconfig 75 [ ] pinconfig | | | `-- pins pinconfig 76 [ ] pinconfig | | |-- sdmmc2-b4-0 pinconfig 77 [ ] pinconfig | | | `-- pins pinconfig 78 [ ] pinconfig | | |-- sdmmc2-d47-0 pinconfig 79 [ ] pinconfig | | | `-- pins pinconfig 80 [ ] pinconfig | | |-- spdifrx-0 pinconfig 81 [ ] pinconfig | | | `-- pins pinconfig 82 [ ] pinconfig | | |-- spdifrx-1 pinconfig 83 [ ] pinconfig | | | `-- pins pinconfig 84 [ ] pinconfig | | |-- spi2-0 pinconfig 85 [ ] pinconfig | | | |-- pins1 pinconfig 86 [ ] pinconfig | | | `-- pins2 pinconfig 87 [ ] pinconfig | | |-- stusb1600-0 pinconfig 88 [ ] pinconfig | | | `-- pins pinconfig 89 [ + ] pinconfig | | |-- uart4-0 pinconfig 90 [ ] pinconfig | | | |-- pins1 pinconfig 91 [ ] pinconfig | | | `-- pins2 pinconfig 92 [ ] pinconfig | | |-- uart4-1 pinconfig 93 [ ] pinconfig | | | |-- pins1 pinconfig 94 [ ] pinconfig | | | `-- pins2 pinconfig 95 [ ] pinconfig | | |-- uart7-0 pinconfig 96 [ ] pinconfig | | | |-- pins1 pinconfig 97 [ ] pinconfig | | | `-- pins2 pinconfig 98 [ ] pinconfig | | `-- usbotg_hs-0 pinconfig 99 [ ] pinconfig | | `-- pins pinctrl 1 [ + ] pinctrl_stm32 | |-- pin-controller-z@54004000 gpio 11 [ + ] gpio_stm32 | | |-- gpio@54004000 pinconfig 100 [ + ] pinconfig | | |-- i2c4-0 pinconfig 101 [ ] pinconfig | | | `-- pins pinconfig 102 [ ] pinconfig | | |-- i2c4-1 pinconfig 103 [ ] pinconfig | | | `-- pins pinconfig 104 [ ] pinconfig | | `-- spi1-0 pinconfig 105 [ ] pinconfig | | |-- pins1 pinconfig 106 [ ] pinconfig | | `-- pins2 ram 0 [ ] stm32mp1_ddr | `-- ddr@5A003000 regulator 17 [ + ] gpio regulator |-- regulator-sd_switch led 0 [ + ] gpio_led |-- led led 1 [ + ] gpio_led | |-- red led 2 [ + ] gpio_led | |-- green led 3 [ + ] gpio_led | |-- orange led 4 [ ] gpio_led | `-- blue clk 1 [ + ] fixed_rate_clock |-- clk-hse clk 2 [ + ] fixed_rate_clock |-- clk-hsi clk 3 [ + ] fixed_rate_clock |-- clk-lse clk 4 [ + ] fixed_rate_clock |-- clk-lsi clk 5 [ + ] fixed_rate_clock `-- clk-csi STM32MP> dm uclass uclass 0: root 0 * root_driver @ fdf4b0a8, seq 0, (req -1) uclass 13: adc uclass 17: blk 0 * sdmmc(a)58005000.blk @ fdf4be70, seq 0, (req -1) 1 sdmmc(a)58007000.blk @ fdf4c0f8 uclass 21: clk 0 * stm32mp1_clk @ fdf4b668, seq 0, (req -1) 1 * clk-hse @ fdf4fab8, seq 2, (req -1) 2 * clk-hsi @ fdf4fb40, seq 1, (req -1) 3 * clk-lse @ fdf4fbc8, seq 5, (req -1) 4 * clk-lsi @ fdf4fc50, seq 4, (req -1) 5 * clk-csi @ fdf4fcd8, seq 3, (req -1) EFI: Initializing UCLASS_EFI uclass 26: efi uclass 27: eth 0 * ethernet@5800a000 @ fdf4c208, seq 0, (req 0) uclass 30: gpio 0 * gpio@50002000 @ fdf4cdf0, seq 0, (req 0) 1 * gpio@50003000 @ fdf4ce48, seq 1, (req 1) 2 * gpio@50004000 @ fdf4cea0, seq 2, (req 2) 3 * gpio@50005000 @ fdf4cef8, seq 3, (req 3) 4 * gpio@50006000 @ fdf4cf50, seq 4, (req 4) 5 * gpio@50007000 @ fdf4cfa8, seq 5, (req 5) 6 * gpio@50008000 @ fdf4d000, seq 6, (req 6) 7 * gpio@50009000 @ fdf4d058, seq 7, (req 7) 8 gpio@5000a000 @ fdf4d0b0, seq -1, (req 8) 9 gpio@5000b000 @ fdf4d108, seq -1, (req 9) 10 gpio@5000c000 @ fdf4d160, seq -1, (req 10) 11 * gpio@54004000 @ fdf4f490, seq 25, (req 25) uclass 31: hwspinlock 0 * hwspinlock@4c000000 @ fdf4b500, seq 0, (req -1) uclass 32: i2c 0 i2c@40013000 @ fdf4b2b8, seq -1, (req 1) 1 i2c@40015000 @ fdf4b398, seq -1, (req 4) 2 * i2c@5c002000 @ fdf4c380, seq 3, (req 3) uclass 34: i2c_generic 0 stmfx@42 @ fdf4b330 uclass 40: led 0 * led @ fdf4f8b0, seq 0, (req -1) 1 * red @ fdf4f918, seq 1, (req -1) 2 * green @ fdf4f980, seq 2, (req -1) 3 * orange @ fdf4f9e8, seq 3, (req -1) 4 blue @ fdf4fa50 uclass 42: mailbox 0 mailbox@4c001000 @ fdf4b578 uclass 43: usb_mass_storage uclass 46: misc 0 * rcc@50000000 @ fdf4b5f0, seq 0, (req -1) 1 * nvmem@5c005000 @ fdf4ccf0, seq 1, (req -1) uclass 47: mmc 0 * sdmmc@58005000 @ fdf4bca8, seq 0, (req 0) 1 * sdmmc@58007000 @ fdf4bf50, seq 1, (req 1) uclass 49: mtd 0 * nand-controller@58002000 @ fdf4bac8, seq 0, (req -1) uclass 50: nop uclass 59: phy 0 usbphyc@5a006000 @ fdf4c328 uclass 60: pinconfig 0 adc12-usb-pwr-pins-0 @ fdf4d1d8 1 pins @ fdf4d230 2 cec-0 @ fdf4d288 3 pins @ fdf4d2e0 4 cec-sleep-0 @ fdf4d338 5 pins @ fdf4d390 6 cec-1 @ fdf4d3e8 7 pins @ fdf4d440 8 cec-sleep-1 @ fdf4d498 9 pins @ fdf4d4f0 10 * rgmii-0 @ fdf4d548, seq 5, (req -1) 11 pins1 @ fdf4d5a0 12 pins2 @ fdf4d5f8 13 pins3 @ fdf4d650 14 rgmii-sleep-0 @ fdf4d6a8 15 pins1 @ fdf4d700 16 * fmc-0 @ fdf4d758, seq 2, (req -1) 17 pins1 @ fdf4d7b0 18 pins2 @ fdf4d808 19 fmc-sleep-0 @ fdf4d860 20 pins @ fdf4d8b8 21 i2c1-0 @ fdf4d910 22 pins @ fdf4d968 23 i2c1-1 @ fdf4d9c0 24 pins @ fdf4da18 25 i2c1-2 @ fdf4da70 26 pins @ fdf4dac8 27 i2c2-0 @ fdf4db20 28 pins @ fdf4db78 29 i2c2-1 @ fdf4dbd0 30 pins @ fdf4dc28 31 i2c2-2 @ fdf4dc80 32 pins @ fdf4dcd8 33 i2c5-0 @ fdf4dd30 34 pins @ fdf4dd88 35 i2c5-1 @ fdf4dde0 36 pins @ fdf4de38 37 ltdc-a-0 @ fdf4de90 38 pins @ fdf4dee8 39 ltdc-a-1 @ fdf4df40 40 pins @ fdf4df98 41 ltdc-b-0 @ fdf4dff0 42 pins @ fdf4e048 43 ltdc-b-1 @ fdf4e0a0 44 pins @ fdf4e0f8 45 m-can1-0 @ fdf4e150 46 pins1 @ fdf4e1a8 47 pins2 @ fdf4e200 48 m_can1-sleep@0 @ fdf4e258 49 pins @ fdf4e2b0 50 pwm2-0 @ fdf4e308 51 pins @ fdf4e360 52 pwm8-0 @ fdf4e3b8 53 pins @ fdf4e410 54 pwm12-0 @ fdf4e468 55 pins @ fdf4e4c0 56 qspi-clk-0 @ fdf4e518 57 pins @ fdf4e570 58 qspi-bk1-0 @ fdf4e5c8 59 pins1 @ fdf4e620 60 pins2 @ fdf4e678 61 qspi-bk2-0 @ fdf4e6d0 62 pins1 @ fdf4e728 63 pins2 @ fdf4e780 64 * sdmmc1-b4-0 @ fdf4e7d8, seq 3, (req -1) 65 pins @ fdf4e830 66 sdmmc1-b4-od-0 @ fdf4e888 67 pins1 @ fdf4e8e0 68 pins2 @ fdf4e938 69 sdmmc1-b4-sleep-0 @ fdf4e990 70 pins @ fdf4e9e8 71 * sdmmc1-dir-0 @ fdf4ea40, seq 4, (req -1) 72 pins1 @ fdf4ea98 73 pins2 @ fdf4eaf0 74 sdmmc1-dir-sleep-0 @ fdf4eb48 75 pins @ fdf4eba0 76 sdmmc2-b4-0 @ fdf4ebf8 77 pins @ fdf4ec50 78 sdmmc2-d47-0 @ fdf4eca8 79 pins @ fdf4ed00 80 spdifrx-0 @ fdf4ed58 81 pins @ fdf4edb0 82 spdifrx-1 @ fdf4ee08 83 pins @ fdf4ee60 84 spi2-0 @ fdf4eeb8 85 pins1 @ fdf4ef10 86 pins2 @ fdf4ef68 87 stusb1600-0 @ fdf4efc0 88 pins @ fdf4f018 89 * uart4-0 @ fdf4f070, seq 1, (req -1) 90 pins1 @ fdf4f0c8 91 pins2 @ fdf4f120 92 uart4-1 @ fdf4f178 93 pins1 @ fdf4f1d0 94 pins2 @ fdf4f228 95 uart7-0 @ fdf4f280 96 pins1 @ fdf4f2d8 97 pins2 @ fdf4f330 98 usbotg_hs-0 @ fdf4f388 99 pins @ fdf4f3e0 100 * i2c4-0 @ fdf4f4e8, seq 0, (req -1) 101 pins @ fdf4f540 102 i2c4-1 @ fdf4f598 103 pins @ fdf4f5f0 104 spi1-0 @ fdf4f648 105 pins1 @ fdf4f6a0 106 pins2 @ fdf4f6f8 uclass 61: pinctrl 0 * pin-controller@50002000 @ fdf4cd78, seq 0, (req 0) 1 * pin-controller-z@54004000 @ fdf4f438, seq 1, (req 1) uclass 62: pmic 0 * pwr-regulators @ fdf4b7d0, seq 0, (req -1) 1 * stpmic@33 @ fdf4c3d8, seq 1, (req -1) uclass 66: ram 0 ddr@5A003000 @ fdf4f770 uclass 67: regulator 0 * reg11 @ fdf4b848, seq 0, (req -1) 1 * reg18 @ fdf4b8d8, seq 1, (req -1) 2 * usb33 @ fdf4b968, seq 2, (req -1) 3 * buck1 @ fdf4c440, seq 3, (req -1) 4 * buck2 @ fdf4c4d0, seq 4, (req -1) 5 * buck3 @ fdf4c560, seq 5, (req -1) 6 * buck4 @ fdf4c5f0, seq 6, (req -1) 7 * ldo1 @ fdf4c680, seq 7, (req -1) 8 * ldo2 @ fdf4c710, seq 8, (req -1) 9 * ldo3 @ fdf4c7a0, seq 9, (req -1) 10 * ldo4 @ fdf4c830, seq 10, (req -1) 11 * ldo5 @ fdf4c8c0, seq 11, (req -1) 12 * ldo6 @ fdf4c950, seq 12, (req -1) 13 * vref_ddr @ fdf4c9e0, seq 13, (req -1) 14 * boost @ fdf4ca70, seq 14, (req -1) 15 * pwr_sw1 @ fdf4cb00, seq 15, (req -1) 16 * pwr_sw2 @ fdf4cb90, seq 16, (req -1) 17 * regulator-sd_switch @ fdf4f7c8, seq 17, (req -1) uclass 68: remoteproc uclass 69: reset 0 * stm32_rcc_reset @ fdf4b6e0, seq 0, (req -1) uclass 70: rtc 0 rtc@5c004000 @ fdf4cc98 uclass 72: serial 0 * serial@40010000 @ fdf4b220, seq 0, (req 0) uclass 73: simple_bus 0 * soc @ fdf4b198, seq 0, (req -1) uclass 76: spi 0 spi@58003000 @ fdf4bb40, seq -1, (req 0) uclass 77: spi_flash 0 mx66l51235l@0 @ fdf4bbb8 1 mx66l51235l@1 @ fdf4bc20 uclass 78: spi_generic uclass 80: syscon 0 * pwr@50001000 @ fdf4b758, seq 0, (req -1) 1 interrupt-controller@5000d000 @ fdf4b9f8 2 * syscon@50020000 @ fdf4ba50, seq 1, (req -1) uclass 81: sysreset 0 reboot @ fdf4b120 1 stpmic1-sysreset @ fdf4cc20 uclass 86: usb 0 usbh-ehci@5800d000 @ fdf4c2b0 uclass 87: usb_dev_generic uclass 88: usb_hub uclass 89: usb 0 usb-otg@49000000 @ fdf4b410, seq -1, (req 0) drivers/core/dump.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/core/dump.c b/drivers/core/dump.c index 8fbfd93..4704049 100644 --- a/drivers/core/dump.c +++ b/drivers/core/dump.c @@ -16,7 +16,7 @@ static void show_devices(struct udevice *dev, int depth, int last_flag) struct udevice *child; /* print the first 20 characters to not break the tree-format. */ - printf(" %-10.10s %2d [ %c ] %-20.20s ", dev->uclass->uc_drv->name, + printf(" %-10.10s %3d [ %c ] %-20.20s ", dev->uclass->uc_drv->name, dev_get_uclass_index(dev, NULL), dev->flags & DM_FLAG_ACTIVATED ? '+' : ' ', dev->driver->name); @@ -64,7 +64,7 @@ void dm_dump_all(void) */ static void dm_display_line(struct udevice *dev, int index) { - printf("%i %c %s @ %08lx", index, + printf("%-3i %c %s @ %08lx", index, dev->flags & DM_FLAG_ACTIVATED ? '*' : ' ', dev->name, (ulong)map_to_sysmem(dev)); if (dev->seq != -1 || dev->req_seq != -1) -- 2.7.4

3 5

[U-Boot] [PATCH] common/memsize: panic if maxsize is not power of two
by Iru Cai 11 Oct '19

11 Oct '19

The memory write and recover loop in get_ram_size() work correctly only if maxsize is power of two, otherwise the function will return a small size. Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- common/memsize.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/common/memsize.c b/common/memsize.c index 13b0047786..f627149a05 100644 --- a/common/memsize.c +++ b/common/memsize.c @@ -33,6 +33,10 @@ long get_ram_size(long *base, long maxsize) long size; int i = 0; + if ((maxsize & (maxsize - 1)) != 0) { + panic("maxsize must be power of 2!"); + } + for (cnt = (maxsize / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) { addr = base + cnt; /* pointer arith! */ sync(); -- 2.23.0

2 1

[U-Boot] [PATCH v2] ata: ahci allow 64-bit DMA for SATA
by Roman Kapl 11 Oct '19

11 Oct '19

Allow 64-bit DMA on AHCI. If not supported by the host controller, at least print a message and fail. Signed-off-by: Roman Kapl <rka(a)sysgo.com> --- Please disregard the previous patch, I've send a wrong version that does not even compile. drivers/ata/ahci.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index 9a08575053..fd4df60a17 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -50,6 +50,8 @@ struct ahci_uc_priv *probe_ent = NULL; #define WAIT_MS_FLUSH 5000 #define WAIT_MS_LINKUP 200 +#define AHCI_CAP_S64A (1u << 31) + __weak void __iomem *ahci_port_base(void __iomem *base, u32 port) { return base + 0x100 + (port * 0x80); @@ -503,9 +505,15 @@ static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port, } for (i = 0; i < sg_count; i++) { - ahci_sg->addr = - cpu_to_le32((unsigned long) buf + i * MAX_DATA_BYTE_COUNT); - ahci_sg->addr_hi = 0; + /* We assume virt=phys */ + phys_addr_t pa = (unsigned long)buf + i * MAX_DATA_BYTE_COUNT; + + ahci_sg->addr = cpu_to_le32(pa & U32_MAX); + ahci_sg->addr_hi = cpu_to_le32((pa >> 32) & U32_MAX); + if (ahci_sg->addr_hi && !(uc_priv->cap & AHCI_CAP_S64A)) { + printf("Error: DMA address too high\n"); + return -1; + } ahci_sg->flags_size = cpu_to_le32(0x3fffff & (buf_len < MAX_DATA_BYTE_COUNT ? (buf_len - 1) -- 2.22.0

2 1

[U-Boot] [PATCH 0/8] arm: meson: add Video support for G12A and SEI510 board
by Neil Armstrong 11 Oct '19

11 Oct '19

This patchset adds Amlogic G12A support for HDMI & Composite video output like the Amlogic GXBB/GXL/GXM, by syncing from the latest Linux VPU DRM driver. It also adds VPU/VAPB/HDMI Clock & VPU Power Domain support. Finally it adds the necessary config to show a logo from a fastboot flashed partition on the SEI510 board. U200 and Odroid-N2 config support will be added later. Neil Armstrong (8): power: domain: meson-gx-pwrc: add G12A support clk: meson: g12a: add support for VPU/HDMI clocks video: meson: remove power domain get video: meson: sync with linux drm-misc tree video: meson: add compatible for Amlogic G12A arm: meson: board-g12a: Setup VPU in fdt ARM: dts: meson-g12a: add U-Boot specific DT for graphics configs: sei510: enable Video Display support arch/arm/dts/meson-g12a-sei510-u-boot.dtsi | 7 + arch/arm/dts/meson-g12a-u-boot.dtsi | 29 + arch/arm/dts/meson-g12a-u200-u-boot.dtsi | 7 + arch/arm/dts/meson-g12b-odroid-n2-u-boot.dtsi | 7 + arch/arm/mach-meson/board-g12a.c | 5 + configs/sei510_defconfig | 11 + drivers/clk/meson/g12a.c | 620 +++++++++++++++++- drivers/power/domain/meson-gx-pwrc-vpu.c | 155 ++++- drivers/video/meson/meson_dw_hdmi.c | 61 +- drivers/video/meson/meson_plane.c | 47 +- drivers/video/meson/meson_registers.h | 373 ++++++++++- drivers/video/meson/meson_vclk.c | 233 +++++-- drivers/video/meson/meson_venc.c | 169 ++++- drivers/video/meson/meson_vpu.c | 11 +- drivers/video/meson/meson_vpu.h | 2 + drivers/video/meson/meson_vpu_init.c | 205 ++++-- include/configs/sei510.h | 12 + 17 files changed, 1757 insertions(+), 197 deletions(-) create mode 100644 arch/arm/dts/meson-g12a-sei510-u-boot.dtsi create mode 100644 arch/arm/dts/meson-g12a-u-boot.dtsi create mode 100644 arch/arm/dts/meson-g12a-u200-u-boot.dtsi create mode 100644 arch/arm/dts/meson-g12b-odroid-n2-u-boot.dtsi -- 2.22.0

2 18

[U-Boot] [PATCH 1/5] ARM: socfpga: vining_fpga: Rename VINING|FPGA
by Marek Vasut 09 Oct '19

09 Oct '19

The company Samtec was merged into Softing, migrate the board over to the new name and update copyright headers. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Silvio Fricke <silvio.fricke(a)softing.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> --- arch/arm/dts/socfpga_cyclone5_vining_fpga.dts | 2 +- arch/arm/mach-socfpga/Kconfig | 10 +++++----- board/{samtec => softing}/vining_fpga/MAINTAINERS | 0 board/{samtec => softing}/vining_fpga/Makefile | 0 .../vining_fpga/qts/iocsr_config.h | 0 .../vining_fpga/qts/pinmux_config.h | 0 .../{samtec => softing}/vining_fpga/qts/pll_config.h | 0 .../vining_fpga/qts/sdram_config.h | 0 board/{samtec => softing}/vining_fpga/socfpga.c | 0 configs/socfpga_vining_fpga_defconfig | 6 +++--- include/configs/socfpga_vining_fpga.h | 12 ++++++------ 11 files changed, 15 insertions(+), 15 deletions(-) rename board/{samtec => softing}/vining_fpga/MAINTAINERS (100%) rename board/{samtec => softing}/vining_fpga/Makefile (100%) rename board/{samtec => softing}/vining_fpga/qts/iocsr_config.h (100%) rename board/{samtec => softing}/vining_fpga/qts/pinmux_config.h (100%) rename board/{samtec => softing}/vining_fpga/qts/pll_config.h (100%) rename board/{samtec => softing}/vining_fpga/qts/sdram_config.h (100%) rename board/{samtec => softing}/vining_fpga/socfpga.c (100%) diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts index ac57f41cb5..be52fbf43d 100644 --- a/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts +++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts @@ -8,7 +8,7 @@ #include <dt-bindings/input/input.h> / { - model = "samtec VIN|ING FPGA"; + model = "Softing VIN|ING FPGA"; compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga"; chosen { diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 1d914648e3..5762b425a7 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -100,8 +100,8 @@ config TARGET_SOCFPGA_IS1 bool "IS1 (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 -config TARGET_SOCFPGA_SAMTEC_VINING_FPGA - bool "samtec VIN|ING FPGA (Cyclone V)" +config TARGET_SOCFPGA_SOFTING_VINING_FPGA + bool "Softing VIN|ING FPGA (Cyclone V)" select BOARD_LATE_INIT select TARGET_SOCFPGA_CYCLONE5 @@ -145,7 +145,7 @@ config SYS_BOARD default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "sr1500" if TARGET_SOCFPGA_SR1500 default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK - default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA + default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA config SYS_VENDOR default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK @@ -155,7 +155,7 @@ config SYS_VENDOR default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES - default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA + default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO @@ -178,6 +178,6 @@ config SYS_CONFIG_NAME default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK - default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA + default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA endif diff --git a/board/samtec/vining_fpga/MAINTAINERS b/board/softing/vining_fpga/MAINTAINERS similarity index 100% rename from board/samtec/vining_fpga/MAINTAINERS rename to board/softing/vining_fpga/MAINTAINERS diff --git a/board/samtec/vining_fpga/Makefile b/board/softing/vining_fpga/Makefile similarity index 100% rename from board/samtec/vining_fpga/Makefile rename to board/softing/vining_fpga/Makefile diff --git a/board/samtec/vining_fpga/qts/iocsr_config.h b/board/softing/vining_fpga/qts/iocsr_config.h similarity index 100% rename from board/samtec/vining_fpga/qts/iocsr_config.h rename to board/softing/vining_fpga/qts/iocsr_config.h diff --git a/board/samtec/vining_fpga/qts/pinmux_config.h b/board/softing/vining_fpga/qts/pinmux_config.h similarity index 100% rename from board/samtec/vining_fpga/qts/pinmux_config.h rename to board/softing/vining_fpga/qts/pinmux_config.h diff --git a/board/samtec/vining_fpga/qts/pll_config.h b/board/softing/vining_fpga/qts/pll_config.h similarity index 100% rename from board/samtec/vining_fpga/qts/pll_config.h rename to board/softing/vining_fpga/qts/pll_config.h diff --git a/board/samtec/vining_fpga/qts/sdram_config.h b/board/softing/vining_fpga/qts/sdram_config.h similarity index 100% rename from board/samtec/vining_fpga/qts/sdram_config.h rename to board/softing/vining_fpga/qts/sdram_config.h diff --git a/board/samtec/vining_fpga/socfpga.c b/board/softing/vining_fpga/socfpga.c similarity index 100% rename from board/samtec/vining_fpga/socfpga.c rename to board/softing/vining_fpga/socfpga.c diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index 958f146e1c..9621f6ec68 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y -CONFIG_TARGET_SOCFPGA_SAMTEC_VINING_FPGA=y +CONFIG_TARGET_SOCFPGA_SOFTING_VINING_FPGA=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_BOOTDELAY=5 @@ -32,7 +32,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),64k(env1),64k(env2),256k(samtec1),256k(samtec2),-(rcvrfs);" +CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),64k(env1),64k(env2),256k(softing1),256k(softing2),-(rcvrfs);" CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set @@ -83,7 +83,7 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_DWC2=y CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="samtec" +CONFIG_USB_GADGET_MANUFACTURER="softing" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h index 29a92b9146..cdca65ae95 100644 --- a/include/configs/socfpga_vining_fpga.h +++ b/include/configs/socfpga_vining_fpga.h @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2015 Marek Vasut <marex(a)denx.de> + * Copyright (C) 2015-2019 Marek Vasut <marex(a)denx.de> */ -#ifndef __CONFIG_SAMTEC_VINING_FPGA_H__ -#define __CONFIG_SAMTEC_VINING_FPGA_H__ +#ifndef __CONFIG_SOFTING_VINING_FPGA_H__ +#define __CONFIG_SOFTING_VINING_FPGA_H__ #include <asm/arch/base_addr_ac5.h> @@ -60,8 +60,8 @@ "1m(u-boot)," \ "64k(env1)," \ "64k(env2)," \ - "256k(samtec1)," \ - "256k(samtec2)," \ + "256k(softing1)," \ + "256k(softing2)," \ "-(rcvrfs)\0" /* Recovery */ \ "mtdparts_1=ff705000.spi.1:" \ "32m(rootfs)," \ @@ -159,4 +159,4 @@ /* The rest of the configuration is shared */ #include <configs/socfpga_common.h> -#endif /* __CONFIG_SAMTEC_VINING_FPGA_H__ */ +#endif /* __CONFIG_SOFTING_VINING_FPGA_H__ */ -- 2.20.1

2 14

[U-Boot] [PATCH] reset: socfpga: release more A10 peripherals out of reset
by tien.fong.chee＠intel.com 09 Oct '19

09 Oct '19

From: Tien Fong Chee <tien.fong.chee(a)intel.com> Current implementation almost release all peripherals out of reset for gen5, but A10 has more peripherals than gen5, hence this patch is required to release the rest of peripherals to support old kernels. Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> --- drivers/reset/reset-socfpga.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c index cb8312619f..d8b8b25fc3 100644 --- a/drivers/reset/reset-socfpga.c +++ b/drivers/reset/reset-socfpga.c @@ -127,6 +127,9 @@ static int socfpga_reset_remove(struct udevice *dev) if (socfpga_reset_keep_enabled()) { puts("Deasserting all peripheral resets\n"); writel(0, data->modrst_base + 4); +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) + writel(0, data->modrst_base + 8); +#endif } return 0; -- 2.13.0

4 6

[U-Boot] [PATCH] cmd: reset: add parameters to specify reboot_mode
by Simon Goldschmidt 09 Oct '19

09 Oct '19

This patch adds parameter support for the 'reset' command to specify the reboot mode (cold vs. warm). Checking these parameters is implemented in the DM implementation. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> --- cmd/boot.c | 4 ++-- drivers/sysreset/sysreset-uclass.c | 17 ++++++++++++++++- 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/cmd/boot.c b/cmd/boot.c index 9150fce80b..c3f33a9ca3 100644 --- a/cmd/boot.c +++ b/cmd/boot.c @@ -56,9 +56,9 @@ U_BOOT_CMD( #endif U_BOOT_CMD( - reset, 1, 0, do_reset, + reset, 2, 0, do_reset, "Perform RESET of the CPU", - "" + "[<cold|warm>] - type of reboot" ); #ifdef CONFIG_CMD_POWEROFF diff --git a/drivers/sysreset/sysreset-uclass.c b/drivers/sysreset/sysreset-uclass.c index ad831c703a..fbda3f44f2 100644 --- a/drivers/sysreset/sysreset-uclass.c +++ b/drivers/sysreset/sysreset-uclass.c @@ -111,9 +111,24 @@ void reset_cpu(ulong addr) int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { + enum sysreset_t reboot_mode = SYSRESET_COLD; + + if (argc > 1 && argv[1]) { + switch (*argv[1]) { + case 'w': + reboot_mode = SYSRESET_WARM; + printf("warm "); + break; + case 'c': + reboot_mode = SYSRESET_COLD; + printf("cold "); + break; + } + } + printf("resetting ...\n"); - sysreset_walk_halt(SYSRESET_COLD); + sysreset_walk_halt(reboot_mode); return 0; } -- 2.20.1

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[U-Boot] [PATCH V2] usb: ehci-mx6: Fix bus enumeration for DM case
by Marek Vasut 09 Oct '19

09 Oct '19

The EHCI iMX6 driver is only partly converted to DT probing and still uses a tremendous amount of hard-coded addresses. Worse, the driver uses hard-coded SoC-model-specific base addresses, which are derived from values protected by SoC-specific macros, hence the driver is also compiled for a specific SoC model. Even worse, the driver depends on specific sequential indexing of the controllers, from which it derives offsets in the PHY and ANATOP register sets. However, when the driver is probed from DT, the indexing is not correct. In fact, each controller has index 0. This patch derives the index for DT probing case from the controller base addresses, which is not the way this should be done, however it is the least intrusive approach, favorable this close to release. The necessary steps to convert this driver fully to DT probing are described inside the patch, however this should be done in the next release and depends on iMX clock driver patches. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Abel Vesa <abel.vesa(a)nxp.com> Cc: Adam Ford <aford173(a)gmail.com> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Ludwig Zenz <lzenz(a)dh-electronics.com> Cc: Lukasz Majewski <lukma(a)denx.de> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Vagrant Cascadian <vagrant(a)debian.org> --- V2: Derive the controller index from it's base address --- drivers/usb/host/ehci-mx6.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index 33abfeada0..e9e6ed596d 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -503,6 +503,42 @@ static int ehci_usb_ofdata_to_platdata(struct udevice *dev) return 0; } +static int ehci_usb_bind(struct udevice *dev) +{ + /* + * TODO: + * This driver is only partly converted to DT probing and still uses + * a tremendous amount of hard-coded addresses. To make things worse, + * the driver depends on specific sequential indexing of controllers, + * from which it derives offsets in the PHY and ANATOP register sets. + * + * Here we attempt to calculate these indexes from DT information as + * well as we can. The USB controllers on all existing iMX6/iMX7 SoCs + * are placed next to each other, at addresses incremented by 0x200. + * Thus, the index is derived from the multiple of 0x200 offset from + * the first controller address. + * + * However, to complete conversion of this driver to DT probing, the + * following has to be done: + * - DM clock framework support for iMX must be implemented + * - usb_power_config() has to be converted to clock framework + * -> Thus, the ad-hoc "index" variable goes away. + * - USB PHY handling has to be factored out into separate driver + * -> Thus, the ad-hoc "index" variable goes away from the PHY + * code, the PHY driver must parse it's address from DT. This + * USB driver must find the PHY driver via DT phandle. + * -> usb_power_config() shall be moved to PHY driver + * With these changes in place, the ad-hoc indexing goes away and + * the driver is fully converted to DT probing. + */ + fdt_size_t size; + fdt_addr_t addr = devfdt_get_addr_size_index(dev, 0, &size); + + dev->req_seq = (addr - USB_BASE_ADDR) / size; + + return 0; +} + static int ehci_usb_probe(struct udevice *dev) { struct usb_platdata *plat = dev_get_platdata(dev); @@ -564,6 +600,7 @@ U_BOOT_DRIVER(usb_mx6) = { .id = UCLASS_USB, .of_match = mx6_usb_ids, .ofdata_to_platdata = ehci_usb_ofdata_to_platdata, + .bind = ehci_usb_bind, .probe = ehci_usb_probe, .remove = ehci_deregister, .ops = &ehci_usb_ops, -- 2.20.1

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