June 2019 - U-Boot

[U-Boot] [PATCH 1/1] colibri imx6/t20: enable CONFIG_SYS_WHITE_ON_BLACK
by Igor Opaniuk 06 Jun '19

06 Jun '19

From: Igor Opaniuk <igor.opaniuk(a)toradex.com> Enable CONFIG_SYS_WHITE_ON_BLACK by default for DM_VIDEO enabled configurations, where env("splashimage") is used for showing Toradex boot logo. Signed-off-by: Igor Opaniuk <igor.opaniuk(a)toradex.com> --- configs/colibri_imx6_defconfig | 1 + configs/colibri_t20_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig index 72e9128a69..9e307dae32 100644 --- a/configs/colibri_imx6_defconfig +++ b/configs/colibri_imx6_defconfig @@ -85,3 +85,4 @@ CONFIG_DM_VIDEO=y CONFIG_VIDEO_IPUV3=y CONFIG_FAT_WRITE=y CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig index 15fb9555f3..d1bfd3c87a 100644 --- a/configs/colibri_t20_defconfig +++ b/configs/colibri_t20_defconfig @@ -64,3 +64,4 @@ CONFIG_DM_VIDEO=y CONFIG_VIDEO_TEGRA20=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SYS_WHITE_ON_BLACK=y -- 2.17.1

2 1

[U-Boot] [PATCH] usb: dwc3: Handle case where setup_phy is not needed
by Siva Durga Prasad Paladugu 06 Jun '19

06 Jun '19

If CONFIG_PHY is not enabled then the dwc3_setup_phy() returns ENOTSUPP which can be still valid and intentional so modify error check to handle this -ENOTSUPP. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> --- drivers/usb/dwc3/dwc3-generic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index 3e6c494..a261d8d 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -47,7 +47,7 @@ static int dwc3_generic_peripheral_probe(struct udevice *dev) struct dwc3 *dwc3 = &priv->dwc3; rc = dwc3_setup_phy(dev, &priv->phys, &priv->num_phys); - if (rc) + if (rc && rc != -ENOTSUPP) return rc; dwc3->regs = map_physmem(priv->base, DWC3_OTG_REGS_END, MAP_NOCACHE); -- 2.7.4

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[U-Boot] [PATCH v8 1/3] rockchip: rk3399: Add Nanopi NEO4 board support
by Jagan Teki 06 Jun '19

06 Jun '19

Add initial support for Nanopi NEO4 board. Specification - Rockchip RK3399 - 1GB DDR3-1866 - SD card slot - eMMC Socket - RTL8211E 1Gbps - AP6212 WiFI/BT - HDMI In/Out, DP, MIPI CSI - USB 3.0, 2.0 - USB Type C power and data - GPIO expansion ports - DC 5V/3A Commit details of rk3399-nanopi-neo4.dts sync from Linux: "arm64: dts: rockchip: Add Nanopi NEO4 initial support" (sha1: 092470b537f19788d957aed12d835a179b606014) Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- Changes for v8: - Add TPL support - Now the bootchain is rkbin (TPL) -> SPL -> U-Boot proper arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi | 6 +++ arch/arm/dts/rk3399-nanopi-neo4.dts | 50 +++++++++++++++++ board/rockchip/evb_rk3399/MAINTAINERS | 6 +++ configs/nanopi-neo4-rk3399_defconfig | 60 +++++++++++++++++++++ 5 files changed, 123 insertions(+) create mode 100644 arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-nanopi-neo4.dts create mode 100644 configs/nanopi-neo4-rk3399_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index adaca524c3..529c506b4d 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -108,6 +108,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-gru-bob.dtb \ rk3399-nanopc-t4.dtb \ rk3399-nanopi-m4.dtb \ + rk3399-nanopi-neo4.dtb \ rk3399-orangepi.dtb \ rk3399-puma-ddr1333.dtb \ rk3399-puma-ddr1600.dtb \ diff --git a/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi new file mode 100644 index 0000000000..7d22528f49 --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki <jagan(a)amarulasolutions.com> + */ + +#include "rk3399-nanopi4-u-boot.dtsi" diff --git a/arch/arm/dts/rk3399-nanopi-neo4.dts b/arch/arm/dts/rk3399-nanopi-neo4.dts new file mode 100644 index 0000000000..195410b089 --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi-neo4.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Amarula Solutions B.V. + * Author: Jagan Teki <jagan(a)amarulasolutions.com> + */ + +/dts-v1/; + +#include "rk3399-nanopi4.dtsi" + +/ { + model = "FriendlyARM NanoPi NEO4"; + compatible = "friendlyarm,nanopi-neo4", "rockchip,rk3399"; + + vdd_5v: vdd-5v { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v"; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v0_core: vcc5v0-core { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_core"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_5v>; + }; + + vcc5v0_usb1: vcc5v0-usb1 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb1"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&vcc3v3_sys { + vin-supply = <&vcc5v0_core>; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_usb1>; +}; + +&vbus_typec { + regulator-always-on; + vin-supply = <&vdd_5v>; +}; diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index f55c92f80c..1f51f65160 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -18,6 +18,12 @@ S: Maintained F: configs/nanopi-m4-rk3399_defconfig F: arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi +NANOPI-NEO4 +M: Jagan Teki <jagan(a)amarulasolutions.com> +S: Maintained +F: configs/nanopi-neo4-rk3399_defconfig +F: arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi + ORANGEPI-RK3399 M: Jagan Teki <jagan(a)amarulasolutions.com> S: Maintained diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig new file mode 100644 index 0000000000..97a94cbc36 --- /dev/null +++ b/configs/nanopi-neo4-rk3399_defconfig @@ -0,0 +1,60 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-neo4.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-neo4" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_TPL=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y -- 2.18.0.321.gffc6fa0e3

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[U-Boot] [PATCH 0/6] imx8: support container
by Peng Fan 06 Jun '19

06 Jun '19

This patchset is to support i.MX8 container loading from SPL, i.MX8 AHAB secure boot not support FIT image, so we need to use container image. Currently still use a fixed offset for the 2nd container(u-boot.cnt), future patches will drop this fixed offset and use dynamaic offset according to the size of 1st container for spl. Only MMC is supported now, future patches will also support SPI/NOR/NAND following similar style as mmc part, if the mmc part is ok. Build pass: https://travis-ci.org/MrVan/u-boot/builds/529180267 Peng Fan (6): imx: mach-imx: clean up Makefile spl: Add function to get u-boot raw sector imx8: support parsing i.MX8 Container file spl: mmc: support loading i.MX container format file imx: add container target imx8qxp_mek: switch to use container image Makefile | 8 ++ arch/arm/include/asm/arch-imx8/image.h | 56 +++++++++++ arch/arm/mach-imx/Makefile | 26 +++-- arch/arm/mach-imx/imx8/Kconfig | 13 +++ arch/arm/mach-imx/imx8/Makefile | 4 + arch/arm/mach-imx/imx8/parse-container.c | 120 ++++++++++++++++++++++++ board/freescale/imx8qxp_mek/README | 4 +- board/freescale/imx8qxp_mek/uboot-container.cfg | 13 +++ common/spl/spl_mmc.c | 21 ++++- configs/imx8qxp_mek_defconfig | 5 +- include/spl.h | 12 +++ 11 files changed, 268 insertions(+), 14 deletions(-) create mode 100644 arch/arm/include/asm/arch-imx8/image.h create mode 100644 arch/arm/mach-imx/imx8/parse-container.c create mode 100644 board/freescale/imx8qxp_mek/uboot-container.cfg -- 2.16.4

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[U-Boot] i.MX8MM mapped register access causes crashes
by Schrempf Frieder 06 Jun '19

06 Jun '19

Hi Peng, I'm still trying to get my i.MX8MM board running with mainline U-Boot. I'm using your patches and added some modifications, so I'm now able to run SPL and U-Boot proper. One problem I have is, that accessing some regions in the memory map for peripheral register access, U-Boot crashes or hangs. Example: => md 0x302d0000 302d0000: 00000743 0000e031 00000000 00000000 C...1........... 302d0010: ffffffff ffffffff ffffffff 00000000 ................ 302d0020: 00000000 001012ec"Synchronous Abort" handler, esr 0x96000210 elr: 0000000040251b84 lr : 0000000040251ba0 (reloc) elr: 00000000bffa3b84 lr : 00000000bffa3ba0 x0 : 00000000bffb9000 x1 : 00000000308800b4 x2 : 00000000bff6e9b4 x3 : 00000000302d0028 x4 : 0000000000000000 x5 : 00000000bffb96a2 x6 : 0000000000000004 x7 : 00000000bbf3c330 x8 : 00000000bbf3c2f0 x9 : 000000000000000c x10: 00000000ffffffd8 x11: 0000000000000006 x12: 000000000001869f x13: 0000000000004238 x14: 00000000bbf3c59c x15: 0000000000000008 x16: 000000000000b900 x17: 000000000000ae80 x18: 00000000bbf41d70 x19: 0000000000000038 x20: 00000000302d0020 x21: 00000000302d0020 x22: 00000000bffb8e5f x23: 0000000000000008 x24: 0000000000000004 x25: 0000000000000004 x26: 0000000000000004 x27: 00000000bbf3c3b8 x28: 0000000000000002 x29: 00000000bbf3c330 Do you have any idea what might be wrong or how I could debug this issue? Thanks, Frieder

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[U-Boot] [PATCH 1/3] board/friendlyarm: Add support for friendlyarm nanopi neo4 board
by Shyam Saini 06 Jun '19

06 Jun '19

This initial support includes: Linux v5.2-rc1 Custom U-Boot Arm Trusted Firmware v2.0 Buildroot default packages Signed-off-by: Shyam Saini <shyam.saini(a)amarulasolutions.com> --- .gitlab-ci.yml | 1 + DEVELOPERS | 2 ++ board/friendlyarm/nanopi-neo4/extlinux.conf | 4 +++ board/friendlyarm/nanopi-neo4/genimage.cfg | 22 ++++++++++++ board/friendlyarm/nanopi-neo4/post-build.sh | 9 +++++ board/friendlyarm/nanopi-neo4/readme.txt | 53 +++++++++++++++++++++++++++ configs/nanopi_neo4_defconfig | 55 +++++++++++++++++++++++++++++ 7 files changed, 146 insertions(+) create mode 100644 board/friendlyarm/nanopi-neo4/extlinux.conf create mode 100644 board/friendlyarm/nanopi-neo4/genimage.cfg create mode 100755 board/friendlyarm/nanopi-neo4/post-build.sh create mode 100644 board/friendlyarm/nanopi-neo4/readme.txt create mode 100644 configs/nanopi_neo4_defconfig diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 5ed1b8f4d5..2f41bcf7c6 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -181,6 +181,7 @@ nanopi_m1_defconfig: { extends: .defconfig } nanopi_m1_plus_defconfig: { extends: .defconfig } nanopi_m4_defconfig: { extends: .defconfig } nanopi_neo_defconfig: { extends: .defconfig } +nanopi_neo4_defconfig: { extends: .defconfig } nexbox_a95x_defconfig: { extends: .defconfig } nitrogen6sx_defconfig: { extends: .defconfig } nitrogen6x_defconfig: { extends: .defconfig } diff --git a/DEVELOPERS b/DEVELOPERS index e2ea103d83..55fb022218 100644 --- a/DEVELOPERS +++ b/DEVELOPERS @@ -2044,10 +2044,12 @@ F: package/wolfssl/ N: Shyam Saini <shyam.saini(a)amarulasolutions.com> F: board/friendlyarm/nanopc-t4/ F: board/friendlyarm/nanopi-m4/ +F: board/friendlyarm/nanopi-neo4/ F: board/olimex/a33_olinuxino/ F: board/orangepi/orangepi-rk3399/ F: configs/nanopc_t4_defconfig F: configs/nanopi_m4_defconfig +F: configs/nanopi_neo4_defconfig F: configs/olimex_a33_olinuxino_defconfig F: configs/orangepi_rk3399_defconfig diff --git a/board/friendlyarm/nanopi-neo4/extlinux.conf b/board/friendlyarm/nanopi-neo4/extlinux.conf new file mode 100644 index 0000000000..91eef67fb9 --- /dev/null +++ b/board/friendlyarm/nanopi-neo4/extlinux.conf @@ -0,0 +1,4 @@ +label NanoPi Neo4 linux + kernel /boot/Image + devicetree /boot/rk3399-nanopi-neo4.dtb + append earlycon=uart8250,mmio32,0xff1a0000 root=/dev/mmcblk1p1 rootwait diff --git a/board/friendlyarm/nanopi-neo4/genimage.cfg b/board/friendlyarm/nanopi-neo4/genimage.cfg new file mode 100644 index 0000000000..b8c1cd5220 --- /dev/null +++ b/board/friendlyarm/nanopi-neo4/genimage.cfg @@ -0,0 +1,22 @@ +image sdcard.img { + hdimage { + } + + partition u-boot-tpl-spl-dtb { + in-partition-table = "no" + image = "u-boot-tpl-spl-dtb.img" + offset = 32K + } + + partition u-boot-dtb { + in-partition-table = "no" + image = "u-boot.itb" + offset = 8M + size = 30M + } + + partition rootfs { + partition-type = 0x83 + image = "rootfs.ext4" + } +} diff --git a/board/friendlyarm/nanopi-neo4/post-build.sh b/board/friendlyarm/nanopi-neo4/post-build.sh new file mode 100755 index 0000000000..e852ba6adf --- /dev/null +++ b/board/friendlyarm/nanopi-neo4/post-build.sh @@ -0,0 +1,9 @@ +#!/bin/sh + +MKIMAGE=$HOST_DIR/bin/mkimage +BOARD_DIR="$(dirname $0)" + +$MKIMAGE -n rk3399 -T rksd -d $BINARIES_DIR/u-boot-tpl-dtb.bin $BINARIES_DIR/u-boot-tpl-dtb.img +cat $BINARIES_DIR/u-boot-tpl-dtb.img $BINARIES_DIR/u-boot-spl-dtb.bin > $BINARIES_DIR/u-boot-tpl-spl-dtb.img + +install -m 0644 -D $BOARD_DIR/extlinux.conf $TARGET_DIR/boot/extlinux/extlinux.conf diff --git a/board/friendlyarm/nanopi-neo4/readme.txt b/board/friendlyarm/nanopi-neo4/readme.txt new file mode 100644 index 0000000000..07e3491459 --- /dev/null +++ b/board/friendlyarm/nanopi-neo4/readme.txt @@ -0,0 +1,53 @@ +Intro +===== + +NanoPi Neo4 is a RK3399 SoC based ARM64 board. + + +Official wiki: http://wiki.friendlyarm.com/wiki/index.php/NanoPi_NEO4 +Mainline wiki: https://wiki.amarulasolutions.com/bsp/rockchip/rk3399/neo4.html + +Build +===== + +Run NanoPi Neo4 configuration + + $ make nanopi_neo4_defconfig + +To build, run make comamnd. + + $ make + +Files created in output directory +================================= + +output/images + +├── bl31.bin +├── bl31.elf +├── Image +├── rk3399-nanopi-neo4.dtb +├── rootfs.ext2 +├── rootfs.ext4 -> rootfs.ext2 +├── rootfs.tar +├── sdcard.img +├── u-boot.bin +├── u-boot.itb +├── u-boot-spl-dtb.bin +├── u-boot-tpl-dtb.bin +├── u-boot-tpl-dtb.img +└── u-boot-tpl-spl-dtb.img + +Creating bootable SD card: +========================= + +Simply invoke (as root) + + # dd if=output/images/sdcard.img of=/dev/sdX && sync + +Where X is your SD card device + +Serial console +-------------- + +Baudrate for this board is 1500000 diff --git a/configs/nanopi_neo4_defconfig b/configs/nanopi_neo4_defconfig new file mode 100644 index 0000000000..f75f4367a9 --- /dev/null +++ b/configs/nanopi_neo4_defconfig @@ -0,0 +1,55 @@ +# Architecture +BR2_aarch64=y +BR2_cortex_a72_a53=y + +# Linux headers 5.1 series +BR2_KERNEL_HEADERS_5_1=y + +# Firmware +BR2_TARGET_ARM_TRUSTED_FIRMWARE=y +BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_GIT=y +BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_REPO_URL="https://github.com/ARM-software/arm-trusted-firmware" +BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_REPO_VERSION="v2.0" +BR2_TARGET_ARM_TRUSTED_FIRMWARE_PLATFORM="rk3399" +BR2_TARGET_ARM_TRUSTED_FIRMWARE_BL31=y + +# Bootloader +BR2_TARGET_UBOOT=y +BR2_TARGET_UBOOT_BUILD_SYSTEM_KCONFIG=y +BR2_TARGET_UBOOT_CUSTOM_GIT=y +BR2_TARGET_UBOOT_CUSTOM_REPO_URL="https://github.com/amarula/u-boot-amarula.git" +BR2_TARGET_UBOOT_CUSTOM_REPO_VERSION="dd2b180c457d35de195707dfa0b57a83b97fb275" +BR2_TARGET_UBOOT_BOARD_DEFCONFIG="nanopi-neo4-rk3399" +BR2_TARGET_UBOOT_NEEDS_DTC=y +BR2_TARGET_UBOOT_NEEDS_PYLIBFDT=y +BR2_TARGET_UBOOT_NEEDS_PYELFTOOLS=y +BR2_TARGET_UBOOT_NEEDS_ATF_BL31=y +BR2_TARGET_UBOOT_NEEDS_ATF_BL31_ELF=y +BR2_TARGET_UBOOT_FORMAT_CUSTOM=y +BR2_TARGET_UBOOT_FORMAT_CUSTOM_NAME="u-boot.itb" +BR2_TARGET_UBOOT_SPL=y +BR2_TARGET_UBOOT_SPL_NAME="spl/u-boot-spl-dtb.bin tpl/u-boot-tpl-dtb.bin" + +# Kernel +BR2_LINUX_KERNEL=y +BR2_LINUX_KERNEL_CUSTOM_VERSION=y +BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="v5.2-rc1" +BR2_LINUX_KERNEL_USE_ARCH_DEFAULT_CONFIG=y +BR2_LINUX_KERNEL_DTS_SUPPORT=y +BR2_LINUX_KERNEL_INTREE_DTS_NAME="rockchip/rk3399-nanopi-neo4" +BR2_LINUX_KERNEL_INSTALL_TARGET=y +BR2_LINUX_KERNEL_NEEDS_HOST_OPENSSL=y + +# Filesystem +BR2_TARGET_GENERIC_HOSTNAME="NanoPi Neo4" +BR2_TARGET_GENERIC_ISSUE="Welcome to NanoPi Neo4!" +BR2_TARGET_ROOTFS_EXT2=y +BR2_TARGET_ROOTFS_EXT2_4=y +BR2_TARGET_ROOTFS_EXT2_SIZE="512M" +BR2_PACKAGE_HOST_DOSFSTOOLS=y +BR2_PACKAGE_HOST_GENIMAGE=y +BR2_PACKAGE_HOST_MTOOLS=y +BR2_PACKAGE_HOST_UBOOT_TOOLS=y +BR2_ROOTFS_POST_IMAGE_SCRIPT="support/scripts/genimage.sh" +BR2_ROOTFS_POST_SCRIPT_ARGS="-c board/friendlyarm/nanopi-neo4/genimage.cfg" +BR2_ROOTFS_POST_BUILD_SCRIPT="board/friendlyarm/nanopi-neo4/post-build.sh" -- 2.11.0

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[U-Boot] x86: SPI flash broken with SPI NOR
by Simon Glass 06 Jun '19

06 Jun '19

Hi Bin, I find that 'sf test 0 1000' does not work anymore since this commit: c4e8862308 mtd: spi: Switch to new SPI NOR framework Have you seen any problems? This seems to prevent proper SPI flash writing (not sure about reading). Also, it seemed to increase code size on samus by >2KB. Regards, Simon

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[U-Boot] [PATCH] lib: Makefile: build fdtdec_common.c when OF_LIBFDT selected
by Peng Fan 06 Jun '19

06 Jun '19

When build SPL_OF_PLATDATA on i.MX6, meet issue the fdtdec_get_int not defined, however fdtdec.c will use fdtdec_get_int, so let's compile fdtdec_common.c when OF_LIBFDT selected. Signed-off-by: Peng Fan <peng.fan(a)nxp.com> --- lib/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/Makefile b/lib/Makefile index 09c45b8122..66ab6295a5 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -88,7 +88,7 @@ obj-y += crc32.o obj-$(CONFIG_CRC32C) += crc32c.o obj-y += ctype.o obj-y += div64.o -obj-$(CONFIG_OF_LIBFDT) += fdtdec.o +obj-$(CONFIG_OF_LIBFDT) += fdtdec.o fdtdec_common.o obj-y += hang.o obj-y += linux_compat.o obj-y += linux_string.o -- 2.16.4

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[U-Boot] [PATCH] board/km: update maintainer e-mail
by holger.brunck＠ch.abb.com 05 Jun '19

05 Jun '19

From: Holger Brunck <holger.brunck(a)ch.abb.com> Signed-off-by: Holger Brunck <holger.brunck(a)ch.abb.com> --- board/keymile/km83xx/MAINTAINERS | 2 +- board/keymile/km_arm/MAINTAINERS | 2 +- board/keymile/kmp204x/MAINTAINERS | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/board/keymile/km83xx/MAINTAINERS b/board/keymile/km83xx/MAINTAINERS index 63b06517ac3..94e0d572e22 100644 --- a/board/keymile/km83xx/MAINTAINERS +++ b/board/keymile/km83xx/MAINTAINERS @@ -1,5 +1,5 @@ KM83XX BOARD -M: Holger Brunck <holger.brunck(a)keymile.com> +M: Holger Brunck <holger.brunck(a)ch.abb.com> S: Maintained F: board/keymile/km83xx/ F: include/configs/km8360.h diff --git a/board/keymile/km_arm/MAINTAINERS b/board/keymile/km_arm/MAINTAINERS index 079c8036772..d156e8574bd 100644 --- a/board/keymile/km_arm/MAINTAINERS +++ b/board/keymile/km_arm/MAINTAINERS @@ -1,5 +1,5 @@ KM_ARM BOARD -M: Valentin Longchamp <valentin.longchamp(a)keymile.com> +M: Valentin Longchamp <valentin.longchamp(a)ch.abb.com> S: Maintained F: board/keymile/km_arm/ F: include/configs/km_kirkwood.h diff --git a/board/keymile/kmp204x/MAINTAINERS b/board/keymile/kmp204x/MAINTAINERS index 93b6bad0a8b..c5170c97e71 100644 --- a/board/keymile/kmp204x/MAINTAINERS +++ b/board/keymile/kmp204x/MAINTAINERS @@ -1,5 +1,5 @@ KMP204X BOARD -M: Valentin Longchamp <valentin.longchamp(a)keymile.com> +M: Valentin Longchamp <valentin.longchamp(a)ch.abb.com> S: Maintained F: board/keymile/kmp204x/ F: include/configs/kmp204x.h -- 2.20.1.390.gb5101f9297

2 1

[U-Boot] [PATCH V2] ARM: DTS: imx6q-logicpd: Resync with Linux 5.1
by Adam Ford 05 Jun '19

05 Jun '19

Resync imx6q-logicpd with Kernel 5.1.5 Signed-off-by: Adam Ford <aford173(a)gmail.com> --- V2: Re-sync with 5.1.5 from linux-stable branch diff --git a/arch/arm/dts/imx6-logicpd-baseboard.dtsi b/arch/arm/dts/imx6-logicpd-baseboard.dtsi index 303c09334b..c40a7af6eb 100644 --- a/arch/arm/dts/imx6-logicpd-baseboard.dtsi +++ b/arch/arm/dts/imx6-logicpd-baseboard.dtsi @@ -1,45 +1,6 @@ -/* - * Copyright 2018 Logic PD, Inc. - * Based on SabreSD, Copyright 2016 Freescale Semiconductor, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2019 Logic PD, Inc. / { keyboard { @@ -68,6 +29,7 @@ debounce-interval = <10>; wakeup-source; }; + btn3 { gpios = <&pcf8575 3 GPIO_ACTIVE_LOW>; label = "btn3"; @@ -81,7 +43,7 @@ leds { compatible = "gpio-leds"; - gen_led0 { + gen-led0 { label = "led0"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_led0>; @@ -89,25 +51,27 @@ linux,default-trigger = "cpu0"; }; - gen_led1 { + gen-led1 { label = "led1"; gpios = <&pcf8575 8 GPIO_ACTIVE_HIGH>; }; - gen_led2 { + gen-led2 { label = "led2"; gpios = <&pcf8575 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; - gen_led3 { + gen-led3 { label = "led3"; gpios = <&pcf8575 10 GPIO_ACTIVE_HIGH>; linux,default-trigger = "default-on"; }; }; - reg_usb_otg_vbus: regulator-otg-vbus@0 { + reg_usb_otg_vbus: regulator-otg-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb_otg>; compatible = "regulator-fixed"; regulator-name = "usb_otg_vbus"; regulator-min-microvolt = <5000000>; @@ -116,14 +80,19 @@ enable-active-high; }; - reg_usb_h1_vbus: regulator-usbh1vbus@1 { + reg_usb_h1_vbus: regulator-usb-h1-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>; compatible = "regulator-fixed"; regulator-name = "usb_h1_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; + gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; }; - reg_3v3: regulator-3v3@2 { + reg_3v3: regulator-3v3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_3v3>; compatible = "regulator-fixed"; @@ -131,13 +100,14 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; enable-active-high; regulator-always-on; }; - reg_enet: regulator-ethernet@3 { + reg_enet: regulator-ethernet { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet_pwr>; + pinctrl-0 = <&pinctrl_reg_enet>; compatible = "regulator-fixed"; regulator-name = "ethernet-supply"; regulator-min-microvolt = <3300000>; @@ -148,7 +118,7 @@ vin-supply = <&sw4_reg>; }; - reg_audio: regulator-audio@4 { + reg_audio: regulator-audio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_audio>; compatible = "regulator-fixed"; @@ -157,11 +127,10 @@ regulator-max-microvolt = <3300000>; gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>; enable-active-high; - regulator-always-on; vin-supply = <&reg_3v3>; }; - reg_hdmi: regulator-hdmi@5 { + reg_hdmi: regulator-hdmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_hdmi>; compatible = "regulator-fixed"; @@ -173,7 +142,7 @@ vin-supply = <&reg_3v3>; }; - reg_uart3: regulator-uart3@6 { + reg_uart3: regulator-uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_uart3>; compatible = "regulator-fixed"; @@ -184,7 +153,7 @@ vin-supply = <&reg_3v3>; }; - reg_1v8: regulator-1v8@7 { + reg_1v8: regulator-1v8 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_1v8>; compatible = "regulator-fixed"; @@ -195,21 +164,21 @@ vin-supply = <&reg_3v3>; }; - reg_pcie: regulator@8 { + reg_pcie: regulator-pcie { compatible = "regulator-fixed"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie_reg>; - regulator-name = "MPCIE_3V3"; + pinctrl-0 = <&pinctrl_reg_pcie>; + regulator-name = "mpcie_3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; enable-active-high; }; - mipi_pwr: regulator@9 { + reg_mipi: regulator-mipi { compatible = "regulator-fixed"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mipi_pwr>; + pinctrl-0 = <&pinctrl_reg_mipi>; regulator-name = "mipi_pwr_en"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; @@ -221,7 +190,7 @@ compatible = "fsl,imx-audio-wm8962"; model = "wm8962-audio"; ssi-controller = <&ssi2>; - audio-codec = <&codec>; + audio-codec = <&wm8962>; audio-routing = "Headphone Jack", "HPOUTL", "Headphone Jack", "HPOUTR", @@ -246,34 +215,10 @@ status = "disabled"; }; -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <&reg_usb_h1_vbus>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <&reg_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-reset-duration = <10>; phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; phy-supply = <&reg_enet>; @@ -282,23 +227,13 @@ status = "okay"; }; -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - no-1-8-v; - keep-power-in-suspend; - status = "okay"; -}; - &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; clock-frequency = <400000>; status = "okay"; - codec: wm8962@1a { + wm8962: audio-codec@1a { compatible = "wlf,wm8962"; reg = <0x1a>; clocks = <&clks IMX6QDL_CLK_CKO>; @@ -330,9 +265,9 @@ reg = <0x10>; clocks = <&clks IMX6QDL_CLK_CKO>; clock-names = "xclk"; - DOVDD-supply = <&mipi_pwr>; - AVDD-supply = <&mipi_pwr>; - DVDD-supply = <&mipi_pwr>; + DOVDD-supply = <&reg_mipi>; + AVDD-supply = <&reg_mipi>; + DVDD-supply = <&reg_mipi>; reset-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; powerdown-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; @@ -361,6 +296,11 @@ }; }; +&ipu1_csi1_from_mipi_vc1 { + clock-lanes = <0>; + data-lanes = <1 2>; +}; + &mipi_csi { status = "okay"; @@ -379,17 +319,52 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; - status = "okay"; vpcie-supply = <&reg_pcie>; - /* fsl,max-link-speed = <2>; */ + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; }; &ssi2 { status = "okay"; }; -&iomuxc { +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; +&usbh1 { + vbus-supply = <&reg_usb_h1_vbus>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <&reg_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + dr_mode = "otg"; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + vmmc-supply = <&reg_3v3>; + no-1-8-v; + keep-power-in-suspend; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&iomuxc { pinctrl_audmux: audmuxgrp { fsl,pins = < MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 @@ -399,21 +374,49 @@ >; }; - pinctrl_i2c1: i2c1 { + pinctrl_ecspi1: ecspi1grp { fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x100b1 >; }; - pinctrl_enet_pwr: enet_pwr { + pinctrl_enet: enetgrp { fsl,pins = < - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* ENET_INT */ + MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1b0b0 /* ETHR_nRST */ >; }; - pinctrl_mipi_pwr: pwr_mipi { - fsl,pins = <MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b1>; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_led0: led0grp { + fsl,pins = < + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 + >; }; pinctrl_ov5640: ov5640grp { @@ -423,174 +426,132 @@ >; }; - pinctrl_reg_hdmi: reg_hdmi { + pinctrl_pcf8574: pcf8575grp { fsl,pins = < - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 >; }; - pinctrl_uart3: uart3grp { + pinctrl_pcie: pciegrp { fsl,pins = < - MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 >; }; - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0xd17059 - MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x130b0 - >; + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; }; - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x100b1 - >; + pinctrl_reg_1v8: reg1v8grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0 + >; }; - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17069 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10069 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17069 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17069 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17069 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17069 - >; - }; - - pinctrl_usdhc2_100mhz: h100-usdhc2-100mhz { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 - >; + pinctrl_reg_3v3: reg3v3grp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0 + >; }; - pinctrl_usdhc2_200mhz: h100-usdhc2-200mhz { + pinctrl_reg_audio: reg-audiogrp { fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 >; }; - pinctrl_enet: enetgrp { + pinctrl_reg_enet: reg-enetgrp { fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* ENET_INT */ - MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1b0b0 /* ETHR_nRST */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 >; }; - pinctrl_reg_audio: audio-reg { + pinctrl_reg_hdmi: reg-hdmigrp { fsl,pins = < - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 >; }; - pinctrl_pcie: pcie { - fsl,pins = < - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 - >; + pinctrl_reg_mipi: reg-mipigrp { + fsl,pins = <MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b1>; }; - pinctrl_pcie_reg: pciereggrp { + pinctrl_reg_pcie: reg-pciegrp { fsl,pins = < MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 >; }; - pinctrl_pcf8574: pcf8575-pins { + pinctrl_reg_uart3: reguart3grp { + fsl,pins = < + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 + >; + }; + + pinctrl_reg_usb_h1_vbus: usbh1grp { fsl,pins = < - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 >; }; - pinctrl_lcd: lcdgrp { + pinctrl_reg_usb_otg: reg-usb-otggrp { fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 /* R_LCD_DCLK */ - MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x100b0 /* R_LCD_PANEL_PWR */ - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 /* R_LCD_HSYNC */ - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 /* R_LCD_VSYNC */ - MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10 /* R_LCD_MDISP */ - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 >; }; - pinctrl_pwm3: pwm3grp { + pinctrl_uart3: uart3grp { fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 >; }; - pinctrl_reg_uart3: uart3reg { + pinctrl_usbotg: usbotggrp { fsl,pins = < - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0xd17059 >; }; - pinctrl_reg_3v3: reg-3v3 { + pinctrl_usdhc2: usdhc2grp { fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17069 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10069 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17069 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17069 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17069 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17069 >; }; - pinctrl_reg_1v8: reg-1v8 { + pinctrl_usdhc2_100mhz: h100-usdhc2-100mhz { fsl,pins = < - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 >; }; - pinctrl_led0: led0 { + pinctrl_usdhc2_200mhz: h100-usdhc2-200mhz { fsl,pins = < - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 >; }; + }; diff --git a/arch/arm/dts/imx6-logicpd-som.dtsi b/arch/arm/dts/imx6-logicpd-som.dtsi index 3fc50babf0..7ceae35732 100644 --- a/arch/arm/dts/imx6-logicpd-som.dtsi +++ b/arch/arm/dts/imx6-logicpd-som.dtsi @@ -1,16 +1,6 @@ -/* - * Copyright 2018 Logic PD - * This file is adapted from imx6qdl-sabresd.dtsi. - * Copyright 2012 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2019 Logic PD, Inc. #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> @@ -20,7 +10,8 @@ stdout-path = &uart1; }; - memory { + memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x80000000>; }; @@ -35,17 +26,6 @@ }; }; -/* Reroute power feeding the CPU to come from the external PMIC */ -&reg_arm -{ - vin-supply = <&sw1a_reg>; -}; - -&reg_soc -{ - vin-supply = <&sw1c_reg>; -}; - &clks { assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>; @@ -56,8 +36,8 @@ &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; nand-on-flash-bbt; + status = "okay"; }; &i2c3 { @@ -66,7 +46,7 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - pmic: pfuze100@08 { + pfuze100: pmic@8 { compatible = "fsl,pfuze100"; reg = <0x08>; @@ -94,20 +74,19 @@ regulator-max-microvolt = <3300000>; regulator-name = "gen_3v3"; regulator-boot-on; - /* regulator-always-on; */ }; sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; regulator-name = "sw3a_vddr"; regulator-boot-on; regulator-always-on; }; sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; regulator-name = "sw3b_vddr"; regulator-boot-on; regulator-always-on; @@ -152,8 +131,8 @@ vgen3_reg: vgen3 { regulator-name = "gen_vadj_0"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; }; vgen4_reg: vgen4 { @@ -164,8 +143,8 @@ }; vgen5_reg: vgen5 { - regulator-name = "gen_adj_1"; - regulator-min-microvolt = <3300000>; + regulator-name = "gen_vadj_1"; + regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; @@ -185,44 +164,75 @@ }; }; - temp_sense0: tmp102@4a { + temperature-sensor@49 { compatible = "ti,tmp102"; - reg = <0x4a>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tempsense>; + reg = <0x49>; interrupt-parent = <&gpio6>; interrupts = <15 IRQ_TYPE_LEVEL_LOW>; #thermal-sensor-cells = <1>; }; - temp_sense1: tmp102@49 { + temperature-sensor@4a { compatible = "ti,tmp102"; - reg = <0x49>; + reg = <0x4a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tempsense>; interrupt-parent = <&gpio6>; interrupts = <15 IRQ_TYPE_LEVEL_LOW>; #thermal-sensor-cells = <1>; }; - mfg_eeprom: at24@51 { + eeprom@51 { compatible = "atmel,24c64"; pagesize = <32>; - read-only; + read-only; /* Manufacturing EEPROM programmed at factory */ reg = <0x51>; }; - user_eeprom: at24@52 { + eeprom@52 { compatible = "atmel,24c64"; pagesize = <32>; reg = <0x52>; }; }; +/* Reroute power feeding the CPU to come from the external PMIC */ +&reg_arm +{ + vin-supply = <&sw1a_reg>; +}; + +&reg_soc +{ + vin-supply = <&sw1c_reg>; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; - pinctrl_hog: hoggrp { + pinctrl_gpmi_nand: gpmi-nandgrp { fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < /* Enable ARM Debugger */ MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x1b0b0 MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x1b0b0 MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x1b0b0 @@ -246,30 +256,16 @@ >; }; - pinctrl_gpmi_nand: gpminandgrp { + pinctrl_i2c3: i2c3grp { fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1 + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 >; }; - pinctrl_i2c3: i2c3grp { + pinctrl_tempsense: tempsensegrp { fsl,pins = < - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 >; }; @@ -282,7 +278,7 @@ pinctrl_uart2: uart2grp { fsl,pins = < - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x13059 /* BT_EN */ + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x13059 /* BT_EN */ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 @@ -313,12 +309,6 @@ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* WLAN_EN */ >; }; - - pinctrl_tempsense: tempsensegrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Temp Sense Alert */ - >; - }; }; &snvs_poweroff { @@ -334,8 +324,9 @@ &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; uart-has-rtscts; + status = "okay"; + bluetooth { compatible = "ti,wl1837-st"; enable-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; @@ -347,9 +338,9 @@ pinctrl-0 = <&pinctrl_usdhc1>; non-removable; keep-power-in-suspend; - enable-sdio-wakeup; - status = "okay"; + wakeup-source; vmmc-supply = <&sw2_reg>; + status = "okay"; }; &usdhc3 { @@ -360,9 +351,10 @@ keep-power-in-suspend; wakeup-source; vmmc-supply = <&reg_wl18xx_vmmc>; - status = "okay"; #address-cells = <1>; #size-cells = <0>; + status = "okay"; + wlcore: wlcore@2 { compatible = "ti,wl1837"; reg = <2>; diff --git a/arch/arm/dts/imx6q-logicpd.dts b/arch/arm/dts/imx6q-logicpd.dts index dcea784477..45eb0b7f75 100644 --- a/arch/arm/dts/imx6q-logicpd.dts +++ b/arch/arm/dts/imx6q-logicpd.dts @@ -1,45 +1,6 @@ -/* - * Copyright 2018 Logic PD, Inc. - * Based on SabreSD, Copyright 2016 Freescale Semiconductor, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2019 Logic PD, Inc. /dts-v1/; #include "imx6q.dtsi" @@ -47,10 +8,10 @@ #include "imx6-logicpd-baseboard.dtsi" / { - model = "Logic PD i.MX6QD SOM-M3 (HDMI)"; + model = "Logic PD i.MX6QD SOM-M3"; compatible = "fsl,imx6q"; - backlight: backlight_lvds { + backlight: backlight-lvds { compatible = "pwm-backlight"; pwms = <&pwm3 0 20000>; brightness-levels = <0 4 8 16 32 64 128 255>; @@ -58,6 +19,16 @@ power-supply = <&reg_lcd>; }; + panel-lvds0 { + compatible = "okaya,rs800480t-7x0gp"; + + port { + panel_in_lvds0: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + reg_lcd: regulator-lcd { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcd_reg>; @@ -72,7 +43,7 @@ startup-delay-us = <500000>; }; - lcd_reset: lcd_reset { + reg_lcd_reset: regulator-lcd-reset { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcd_reset>; compatible = "regulator-fixed"; @@ -84,17 +55,17 @@ regulator-always-on; vin-supply = <&reg_lcd>; }; +}; - panel-lvds0 { - compatible = "ampire,am800480b3tmqw"; - backlight = <&backlight>; - - port { - panel_in_lvds0: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>, + <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>, + <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, + <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>; }; &hdmi { @@ -102,22 +73,6 @@ status = "okay"; }; -&i2c1 { - ili_touch: ilitouch@26 { - compatible = "ili,ili2117a"; - reg = <0x26>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touchscreen>; - interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_RISING>; - ili2117a,poll-period = <10>; - ili2117a,max-touch = <2>; - }; -}; - -&reg_hdmi { - regulator-always-on; -}; - &ldb { status = "okay"; @@ -128,7 +83,6 @@ port@4 { reg = <4>; - lvds0_out: endpoint { remote-endpoint = <&panel_in_lvds0>; }; @@ -137,23 +91,12 @@ }; -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>, - <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>, - <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, - <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, - <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, - <&clks IMX6QDL_CLK_PLL2_PFD2_396M>; -}; - &pwm3 { status = "okay"; }; -&usdhc2 { - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; +&reg_hdmi { + regulator-always-on; /* Without this, the level shifter on HDMI doesn't turn on */ }; &iomuxc { @@ -165,7 +108,7 @@ pinctrl_lcd_reset: lcdreset { fsl,pins = < - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 /* LCD_nRESET */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 /* LCD_nRESET */ >; }; @@ -175,4 +118,3 @@ >; }; }; - -- 2.17.1

2 1