June 2019 - U-Boot

[U-Boot] [PATCH v3 1/1] lib/vsprintf: allow printing upper case GUIDs
by Heinrich Schuchardt 08 Jun '19

08 Jun '19

In the UEFI context GUIDs are expected to be rendered in upper case. The patch uses the formerly unused bit 1 of the parameter str_format of function uuid_bin_to_str() to indicate if we need upper or lower case output. Function uuid_string() in vsprint.c is adjusted to correctly set the bit depending on the print format code. %pUb: 01020304-0506-0708-090a-0b0c0d0e0f10 %pUB: 01020304-0506-0708-090A-0B0C0D0E0F10 %pUl: 04030201-0605-0807-090a-0b0c0d0e0f10 %pUL: 04030201-0605-0807-090A-0B0C0D0E0F10 Up to this point only a diagnostic message in mount_ubifs() using '%pUB' is concerned by the change. Further patches are needed to adjust the UEFI subsystem. A unit test is provided inside the ut_print command. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- v3: use BIT(n) style for bits of bitmask v2: add missing sprintf() statement in unit test --- include/uuid.h | 10 ++++++---- lib/uuid.c | 18 ++++++++++++------ lib/vsprintf.c | 14 ++++++++------ test/print_ut.c | 23 +++++++++++++++++++++++ 4 files changed, 49 insertions(+), 16 deletions(-) diff --git a/include/uuid.h b/include/uuid.h index 124bbce8a2..abcc325eae 100644 --- a/include/uuid.h +++ b/include/uuid.h @@ -6,6 +6,8 @@ #ifndef __UUID_H__ #define __UUID_H__ +#include <linux/bitops.h> + /* This is structure is in big-endian */ struct uuid { unsigned int time_low; @@ -16,10 +18,10 @@ struct uuid { unsigned char node[6]; } __packed; -enum { - UUID_STR_FORMAT_STD, - UUID_STR_FORMAT_GUID -}; +/* Bits of a bitmask specifying the output format for GUIDs */ +#define UUID_STR_FORMAT_STD 0 +#define UUID_STR_FORMAT_GUID BIT(0) +#define UUID_STR_UPPER_CASE BIT(1) #define UUID_STR_LEN 36 #define UUID_BIN_LEN sizeof(struct uuid) diff --git a/lib/uuid.c b/lib/uuid.c index fa20ee39fc..14d7f8ce7e 100644 --- a/lib/uuid.c +++ b/lib/uuid.c @@ -187,9 +187,10 @@ int uuid_str_to_bin(char *uuid_str, unsigned char *uuid_bin, int str_format) /* * uuid_bin_to_str() - convert big endian binary data to string UUID or GUID. * - * @param uuid_bin - pointer to binary data of UUID (big endian) [16B] - * @param uuid_str - pointer to allocated array for output string [37B] - * @str_format - UUID string format: 0 - UUID; 1 - GUID + * @param uuid_bin: pointer to binary data of UUID (big endian) [16B] + * @param uuid_str: pointer to allocated array for output string [37B] + * @str_format: bit 0: 0 - UUID; 1 - GUID + * bit 1: 0 - lower case; 2 - upper case */ void uuid_bin_to_str(unsigned char *uuid_bin, char *uuid_str, int str_format) { @@ -198,6 +199,7 @@ void uuid_bin_to_str(unsigned char *uuid_bin, char *uuid_str, int str_format) const u8 guid_char_order[UUID_BIN_LEN] = {3, 2, 1, 0, 5, 4, 7, 6, 8, 9, 10, 11, 12, 13, 14, 15}; const u8 *char_order; + const char *format; int i; /* @@ -205,13 +207,17 @@ void uuid_bin_to_str(unsigned char *uuid_bin, char *uuid_str, int str_format) * 4B-2B-2B-2B-6B * be be be be be */ - if (str_format == UUID_STR_FORMAT_STD) + if (str_format & UUID_STR_FORMAT_GUID) + char_order = guid_char_order; + else char_order = uuid_char_order; + if (str_format & UUID_STR_UPPER_CASE) + format = "%02X"; else - char_order = guid_char_order; + format = "%02x"; for (i = 0; i < 16; i++) { - sprintf(uuid_str, "%02x", uuid_bin[char_order[i]]); + sprintf(uuid_str, format, uuid_bin[char_order[i]]); uuid_str += 2; switch (i) { case 3: diff --git a/lib/vsprintf.c b/lib/vsprintf.c index 2403825dc9..f1332df0f3 100644 --- a/lib/vsprintf.c +++ b/lib/vsprintf.c @@ -382,29 +382,31 @@ static char *ip4_addr_string(char *buf, char *end, u8 *addr, int field_width, #ifdef CONFIG_LIB_UUID /* - * This works (roughly) the same way as linux's, but we currently always - * print lower-case (ie. we just keep %pUB and %pUL for compat with linux), - * mostly just because that is what uuid_bin_to_str() supports. + * This works (roughly) the same way as Linux's. * * %pUb: 01020304-0506-0708-090a-0b0c0d0e0f10 + * %pUB: 01020304-0506-0708-090A-0B0C0D0E0F10 * %pUl: 04030201-0605-0807-090a-0b0c0d0e0f10 + * %pUL: 04030201-0605-0807-090A-0B0C0D0E0F10 */ static char *uuid_string(char *buf, char *end, u8 *addr, int field_width, int precision, int flags, const char *fmt) { char uuid[UUID_STR_LEN + 1]; - int str_format = UUID_STR_FORMAT_STD; + int str_format; switch (*(++fmt)) { case 'L': + str_format = UUID_STR_FORMAT_GUID | UUID_STR_UPPER_CASE; + break; case 'l': str_format = UUID_STR_FORMAT_GUID; break; case 'B': - case 'b': - /* this is the default */ + str_format = UUID_STR_FORMAT_STD | UUID_STR_UPPER_CASE; break; default: + str_format = UUID_STR_FORMAT_STD; break; } diff --git a/test/print_ut.c b/test/print_ut.c index 0bc548dca8..a3b9974ad2 100644 --- a/test/print_ut.c +++ b/test/print_ut.c @@ -15,6 +15,26 @@ #define FAKE_BUILD_TAG "jenkins-u-boot-denx_uboot_dm-master-build-aarch64" \ "and a lot more text to come" +/* Test printing GUIDs */ +static void guid_ut_print(void) +{ +#if CONFIG_IS_ENABLED(LIB_UUID) + unsigned char guid[16] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 + }; + char str[40]; + + sprintf(str, "%pUb", guid); + assert(!strcmp("01020304-0506-0708-090a-0b0c0d0e0f10", str)); + sprintf(str, "%pUB", guid); + assert(!strcmp("01020304-0506-0708-090A-0B0C0D0E0F10", str)); + sprintf(str, "%pUl", guid); + assert(!strcmp("04030201-0605-0807-090a-0b0c0d0e0f10", str)); + sprintf(str, "%pUL", guid); + assert(!strcmp("04030201-0605-0807-090A-0B0C0D0E0F10", str)); +#endif +} + /* Test efi_loader specific printing */ static void efi_ut_print(void) { @@ -117,6 +137,9 @@ static int do_ut_print(cmd_tbl_t *cmdtp, int flag, int argc, /* Test efi_loader specific printing */ efi_ut_print(); + /* Test printing GUIDs */ + guid_ut_print(); + printf("%s: Everything went swimmingly\n", __func__); return 0; } -- 2.20.1

2 1

[U-Boot] Kconfig options for several boards
by Linder Pascal 07 Jun '19

07 Jun '19

Hi everyone, I would like to turn on configurations for several Keymile boards, which are all using the Kirkwood architecture. Now, I do not want to change every defconfig file one after the other. Until now, we have used a common header file, but with the conversion to Kconfig another method has to be elaborated. While searching in the U-Boot source code, I found two different manners to fulfill our needs: * in arch/arm/mach-kirkwood/Kconfig: config TARGET_KM_KIRKWOOD bool "KM_KIRKWOOD Board" select BOARD_LATE_INIT select DM select DM_SPI select DM_SPI_FLASH imply CMD_CRAMFS imply CMD_DIAG imply FS_CRAMFS * in board/keymile/km_arm/Kconfig: config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select DM select DM_SPI select DM_SPI_FLASH Which one do you guys prefer and for what reasons? Also, I would like to know what the dummy keyword is doing in the second proposition (found that in every usage of BOARD_SPECIFIC_OPTIONS). Many thanks in advance! Sincerely, Pascal Linder Student Telekommunikation Netzwerke und Sicherheit Klasse T-3b

2 1

[U-Boot] [PATCH v4 0/5] net: ethernet: ti: Introduce am654 gigabit eth switch subsystem driver
by Keerthy 07 Jun '19

07 Jun '19

Add new driver for the TI AM65x SoC Gigabit Ethernet Switch subsystem (CPSW NUSS). It has two ports and provides Ethernet packet communication for the device and can be configured as an Ethernet switch. CPSW NUSS features: the Reduced Gigabit Media Independent Interface (RGMII), Reduced Media Independent Interface (RMII), and the Management Data Input/Output (MDIO) interface for physical layer device (PHY) management. The TI AM65x SoC has integrated two-port Gigabit Ethernet Switch subsystem into device MCU domain named MCU_CPSW0. One Ethernet port (port 1) with selectable RGMII and RMII interfaces and an internal Communications Port Programming Interface (CPPI) port (Host port 0). Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels and on RX channels operating by TI am654 NAVSS Unified DMA Peripheral Root Complex (UDMA-P) controller. Tested for tftp and booting to kernel on am654-evm. Grygorii Strashko (4): net: ethernet: ti: Introduce am654 gigabit eth switch subsystem driver arm64: dts: k3-am654-base-board: add mcu cpsw nuss pinmux and phy defs configs: am65x_evm_a53: enable networking arm64: dts: ti: k3-am65: add mcu cpsw node Keerthy (1): driver: net: ti: cpsw-mdio: use phys_addr_t for mdio_base addr Changes in v4: * Patch1 caused dra7 config build warnings corrected them. Testing: 1) Build tested am3/4 and dra7. 2) Booted to kernel using cpsw tftp. arch/arm/dts/k3-am65.dtsi | 2 + arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 170 ++++ configs/am65x_evm_a53_defconfig | 7 + drivers/net/ti/Kconfig | 8 + drivers/net/ti/Makefile | 1 + drivers/net/ti/am65-cpsw-nuss.c | 794 +++++++++++++++++++ drivers/net/ti/cpsw_mdio.c | 4 +- drivers/net/ti/cpsw_mdio.h | 2 +- 8 files changed, 985 insertions(+), 3 deletions(-) create mode 100644 drivers/net/ti/am65-cpsw-nuss.c -- 2.17.1

2 10

[U-Boot] Pull request: u-boot-spi/master
by Jagan Teki 07 Jun '19

07 Jun '19

Hi Tom, Please pull this PR. Summary: - mpc8xxx spi driver fixes (Mario) - mpc8xxx spi dm conversion (Mario, Jagan) - SPI DM Migration update (Jagan) The following changes since commit 748198cb8d32d41bc35e6f492bac9948f339bece: Revert "Makefile: Prioritize external dtb if defined" (2019-05-19 18:09:35 -0400) are available in the Git repository at: git://git.denx.de/u-boot-spi.git master for you to fetch changes up to 93842e580cee40c9d3e70de625e4bd826a749e65: dm: MIGRATION: Update migration status for SPI (2019-05-20 22:18:54 +0530) ---------------------------------------------------------------- Jagan Teki (2): spi: mpc8xxx: Convert to DM dm: MIGRATION: Update migration status for SPI Mario Six (17): spi: mpc8xxx: Use short type names spi: mpc8xxx: Fix comments spi: mpc8xxx: Rename camel-case variables spi: mpc8xxx: Fix space after cast spi: mpc8xxx: Fix function names in strings spi: mpc8xxx: Replace defines with enums spi: mpc8xxx: Use IO accessors spi: mpc8xxx: Simplify if spi: mpc8xxx: Get rid of is_read spi: mpc8xxx: Simplify logic a bit spi: mpc8xxx: Reduce scope of loop variables spi: mpc8xxx: Make code more readable spi: mpc8xxx: Rename variable spi: mpc8xxx: Document LEN setting better spi: mpc8xxx: Re-order transfer setup spi: mpc8xxx: Fix if check spi: mpc8xxx: Use get_timer doc/driver-model/MIGRATION.txt | 6 +- drivers/spi/Kconfig | 10 +- drivers/spi/mpc8xxx_spi.c | 279 +++++++++++++++++++++++++++-------------- 3 files changed, 194 insertions(+), 101 deletions(-)

4 7

[U-Boot] [PATCH] ids8313: Start DM/DT conversion
by Mario Six 07 Jun '19

07 Jun '19

This commit does the minimal possible conversion so that the ids8313 board still compiles with the recent SPI DM conversion: * Add a device tree (for now a 1-to-1 copy of the mpc8313erdb board's DT from the Linux kernel sources) * Remove the legacy CS switching mechanism from the board file * Enable enough config options to that the board compiles Signed-off-by: Mario Six <mario.six(a)gdsys.cc> --- arch/powerpc/dts/Makefile | 1 + arch/powerpc/dts/ids8313.dts | 405 +++++++++++++++++++++++++++++++++++ board/ids/ids8313/ids8313.c | 32 --- configs/ids8313_defconfig | 6 +- 4 files changed, 411 insertions(+), 33 deletions(-) create mode 100644 arch/powerpc/dts/ids8313.dts diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index 6a28f802c2..f43f46870c 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -3,6 +3,7 @@ dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb dtb-$(CONFIG_TARGET_MCR3000) += mcr3000.dtb dtb-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.dtb +dtb-$(CONFIG_TARGET_IDS8313) += ids8313.dtb targets += $(dtb-y) diff --git a/arch/powerpc/dts/ids8313.dts b/arch/powerpc/dts/ids8313.dts new file mode 100644 index 0000000000..a8315795b2 --- /dev/null +++ b/arch/powerpc/dts/ids8313.dts @@ -0,0 +1,405 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * MPC8313E RDB Device Tree Source + * + * Copyright 2005, 2006, 2007 Freescale Semiconductor Inc. + */ + +/dts-v1/; + +/ { + model = "MPC8313ERDB"; + compatible = "MPC8313ERDB", "MPC831xRDB", "MPC83xxRDB"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet0; + ethernet1 = &enet1; + serial0 = &serial0; + serial1 = &serial1; + pci0 = &pci0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8313@0 { + device_type = "cpu"; + reg = <0x0>; + d-cache-line-size = <32>; + i-cache-line-size = <32>; + d-cache-size = <16384>; + i-cache-size = <16384>; + timebase-frequency = <0>; // from bootloader + bus-frequency = <0>; // from bootloader + clock-frequency = <0>; // from bootloader + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x08000000>; // 128MB at 0 + }; + + localbus@e0005000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,mpc8313-elbc", "fsl,elbc", "simple-bus"; + reg = <0xe0005000 0x1000>; + interrupts = <77 0x8>; + interrupt-parent = <&ipic>; + + // CS0 and CS1 are swapped when + // booting from nand, but the + // addresses are the same. + ranges = <0x0 0x0 0xfe000000 0x00800000 + 0x1 0x0 0xe2800000 0x00008000 + 0x2 0x0 0xf0000000 0x00020000 + 0x3 0x0 0xfa000000 0x00008000>; + + flash@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x800000>; + bank-width = <2>; + device-width = <1>; + }; + + nand@1,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8313-fcm-nand", + "fsl,elbc-fcm-nand"; + reg = <0x1 0x0 0x2000>; + + u-boot@0 { + reg = <0x0 0x100000>; + read-only; + }; + + kernel@100000 { + reg = <0x100000 0x300000>; + }; + + fs@400000 { + reg = <0x400000 0x1c00000>; + }; + }; + }; + + soc8313@e0000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + ranges = <0x0 0xe0000000 0x00100000>; + reg = <0xe0000000 0x00000200>; + bus-frequency = <0>; + + wdt@200 { + device_type = "watchdog"; + compatible = "mpc83xx_wdt"; + reg = <0x200 0x100>; + }; + + sleep-nexus { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + sleep = <&pmc 0x03000000>; + ranges; + + i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <14 0x8>; + interrupt-parent = <&ipic>; + dfsrr; + rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; + }; + + crypto@30000 { + compatible = "fsl,sec2.2", "fsl,sec2.1", + "fsl,sec2.0"; + reg = <0x30000 0x10000>; + interrupts = <11 0x8>; + interrupt-parent = <&ipic>; + fsl,num-channels = <1>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0x4c>; + fsl,descriptor-types-mask = <0x0122003f>; + }; + }; + + i2c@3100 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + compatible = "fsl-i2c"; + reg = <0x3100 0x100>; + interrupts = <15 0x8>; + interrupt-parent = <&ipic>; + dfsrr; + }; + + spi@7000 { + cell-index = <0>; + compatible = "fsl,spi"; + reg = <0x7000 0x1000>; + interrupts = <16 0x8>; + interrupt-parent = <&ipic>; + mode = "cpu"; + }; + + /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */ + usb@23000 { + compatible = "fsl-usb2-dr"; + reg = <0x23000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&ipic>; + interrupts = <38 0x8>; + phy_type = "utmi_wide"; + sleep = <&pmc 0x00300000>; + }; + + ptp_clock@24E00 { + compatible = "fsl,etsec-ptp"; + reg = <0x24E00 0xB0>; + interrupts = <12 0x8 13 0x8>; + interrupt-parent = < &ipic >; + fsl,tclk-period = <10>; + fsl,tmr-prsc = <100>; + fsl,tmr-add = <0x999999A4>; + fsl,tmr-fiper1 = <0x3B9AC9F6>; + fsl,tmr-fiper2 = <0x00018696>; + fsl,max-adj = <659999998>; + }; + + enet0: ethernet@24000 { + #address-cells = <1>; + #size-cells = <1>; + sleep = <&pmc 0x20000000>; + ranges = <0x0 0x24000 0x1000>; + + cell-index = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x24000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <37 0x8 36 0x8 35 0x8>; + interrupt-parent = <&ipic>; + tbi-handle = < &tbi0 >; + /* Vitesse 7385 isn't on the MDIO bus */ + fixed-link = <1 1 1000 0 0>; + fsl,magic-packet; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-mdio"; + reg = <0x520 0x20>; + phy4: ethernet-phy@4 { + interrupt-parent = <&ipic>; + interrupts = <20 0x8>; + reg = <0x4>; + }; + tbi0: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + + enet1: ethernet@25000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <1>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x25000 0x1000>; + ranges = <0x0 0x25000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <34 0x8 33 0x8 32 0x8>; + interrupt-parent = <&ipic>; + tbi-handle = < &tbi1 >; + phy-handle = < &phy4 >; + sleep = <&pmc 0x10000000>; + fsl,magic-packet; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x520 0x20>; + + tbi1: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + + + }; + + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <0>; + interrupts = <9 0x8>; + interrupt-parent = <&ipic>; + }; + + serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x4600 0x100>; + clock-frequency = <0>; + interrupts = <10 0x8>; + interrupt-parent = <&ipic>; + }; + + /* IPIC + * interrupts cell = <intr #, sense> + * sense values match linux IORESOURCE_IRQ_* defines: + * sense == 8: Level, low assertion + * sense == 2: Edge, high-to-low change + */ + ipic: pic@700 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x700 0x100>; + device_type = "ipic"; + }; + + pmc: power@b00 { + compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc"; + reg = <0xb00 0x100 0xa00 0x100>; + interrupts = <80 8>; + interrupt-parent = <&ipic>; + fsl,mpc8313-wakeup-timer = <&gtm1>; + + /* Remove this (or change to "okay") if you have + * a REVA3 or later board, if you apply one of the + * workarounds listed in section 8.5 of the board + * manual, or if you are adapting this device tree + * to a different board. + */ + status = "fail"; + }; + + gtm1: timer@500 { + compatible = "fsl,mpc8313-gtm", "fsl,gtm"; + reg = <0x500 0x100>; + interrupts = <90 8 78 8 84 8 72 8>; + interrupt-parent = <&ipic>; + }; + + timer@600 { + compatible = "fsl,mpc8313-gtm", "fsl,gtm"; + reg = <0x600 0x100>; + interrupts = <91 8 79 8 85 8 73 8>; + interrupt-parent = <&ipic>; + }; + }; + + sleep-nexus { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + sleep = <&pmc 0x00010000>; + ranges; + + pci0: pci@e0008500 { + cell-index = <1>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + /* IDSEL 0x0E -mini PCI */ + 0x7000 0x0 0x0 0x1 &ipic 18 0x8 + 0x7000 0x0 0x0 0x2 &ipic 18 0x8 + 0x7000 0x0 0x0 0x3 &ipic 18 0x8 + 0x7000 0x0 0x0 0x4 &ipic 18 0x8 + + /* IDSEL 0x0F - PCI slot */ + 0x7800 0x0 0x0 0x1 &ipic 17 0x8 + 0x7800 0x0 0x0 0x2 &ipic 18 0x8 + 0x7800 0x0 0x0 0x3 &ipic 17 0x8 + 0x7800 0x0 0x0 0x4 &ipic 18 0x8>; + interrupt-parent = <&ipic>; + interrupts = <66 0x8>; + bus-range = <0x0 0x0>; + ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 + 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 + 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>; + clock-frequency = <66666666>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0xe0008500 0x100 /* internal registers */ + 0xe0008300 0x8>; /* config space access registers */ + compatible = "fsl,mpc8349-pci"; + device_type = "pci"; + }; + + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8313-dma", "fsl,elo-dma"; + reg = <0xe00082a8 4>; + ranges = <0 0xe0008100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + + dma-channel@0 { + compatible = "fsl,mpc8313-dma-channel", + "fsl,elo-dma-channel"; + reg = <0 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + }; + + dma-channel@80 { + compatible = "fsl,mpc8313-dma-channel", + "fsl,elo-dma-channel"; + reg = <0x80 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <1>; + }; + + dma-channel@100 { + compatible = "fsl,mpc8313-dma-channel", + "fsl,elo-dma-channel"; + reg = <0x100 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <2>; + }; + + dma-channel@180 { + compatible = "fsl,mpc8313-dma-channel", + "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <3>; + }; + }; + }; +}; diff --git a/board/ids/ids8313/ids8313.c b/board/ids/ids8313/ids8313.c index caa36064f0..630a36191d 100644 --- a/board/ids/ids8313/ids8313.c +++ b/board/ids/ids8313/ids8313.c @@ -177,35 +177,3 @@ int misc_init_r(void) return 0; } #endif - -#ifdef CONFIG_MPC8XXX_SPI -/* - * The following are used to control the SPI chip selects - */ -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && ((cs >= 0) && (cs <= 2)); -} - -void spi_cs_activate(struct spi_slave *slave) -{ - gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; - u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE; - - /* select the spi_cs channel */ - out_8(spi_base, 1 << slave->cs); - /* activate the spi_cs */ - clrbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; - u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE; - - /* select the spi_cs channel */ - out_8(spi_base, 1 << slave->cs); - /* deactivate the spi_cs */ - setbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK); -} -#endif diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig index 43454a122b..796e93570a 100644 --- a/configs/ids8313_defconfig +++ b/configs/ids8313_defconfig @@ -146,8 +146,12 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=ff800000.flash,nand0=e1000000.flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:7m(dum),768k(BOOT-BIN),128k(BOOT-ENV),128k(BOOT-REDENV);e1000000.flash:-(ubi)" CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="ids8313" CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_I2C=y +CONFIG_DM_GPIO=y +CONFIG_MPC8XXX_GPIO=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y @@ -161,5 +165,5 @@ CONFIG_TSEC_ENET=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_MPC8XXX_SPI=y -CONFIG_OF_LIBFDT=y -- 2.21.0

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[U-Boot] [PATCH 0/3] efi_loader: correct event signaling
by Heinrich Schuchardt 07 Jun '19

07 Jun '19

This patch series fixes problems in signaling events. When calling SignalEvent() with an event in signaled state only EFI_SUCCESS shall be returned without any side effects. In ExitBootServices() only timers shall be stopped not all events. Heinrich Schuchardt (3): efi_loader: RegisterProtocolNotify event signaling efi_loader: SignalEvent for event in signaled state efi_loader: event signaling in ExitBootServices include/efi_loader.h | 2 +- lib/efi_loader/efi_boottime.c | 45 +++++++++++++++++++++-------------- lib/efi_loader/efi_console.c | 4 ++-- lib/efi_loader/efi_memory.c | 2 +- lib/efi_loader/efi_runtime.c | 2 +- 5 files changed, 32 insertions(+), 23 deletions(-) -- 2.20.1

1 3

[U-Boot] Pull request for UEFI sub-system for v2019.07-rc4 (2)
by Heinrich Schuchardt 07 Jun '19

07 Jun '19

The following changes since commit 8a802a2eefd36865eaa3d927d1db7af63bb2d922: Merge tag 'rockchip-for-v2019.07-rc3' of git://git.denx.de/u-boot-rockchip (2019-05-31 07:17:09 -0400) are available in the Git repository at: git://git.denx.de/u-boot-efi.git tags/efi-2019-07-rc4-2 for you to fetch changes up to 4b27a761321fd17536e02644d0ec0373150eb570: cmd: env: add -nv option for UEFI non-volatile variable (2019-06-04 23:56:14 +0200) Travis CI has no complains: https://travis-ci.org/xypron2/u-boot/builds/541464942 Primary key fingerprint: 6DC4 F9C7 1F29 A6FA 06B7 6D33 C481 DBBC 2C05 1AC4 ---------------------------------------------------------------- Pull request for UEFI sub-system for v2019.07-rc4-2 Support for managing the non-volatile attribute of UEFI variables is added though we do not have a backend for persistence yet. Error messages for changes of UEFI variables are provided. UEFI boottime service implementations are corrected. ---------------------------------------------------------------- AKASHI Takahiro (6): efi_loader: bootmgr: print a message when loading from BootNext failed cmd: env: print a message when setting UEFI variable failed efi_loader: variable: support non-volatile attribute efi_loader: bootmgr: make BootNext non-volatile cmd: efidebug: make some boot variables non-volatile cmd: env: add -nv option for UEFI non-volatile variable Heinrich Schuchardt (6): efi_loader: DisconnectController() with no driver lib: time: export usec_to_tick() efi_loader: check timer events in Stall() efi_loader: fix EnableCursor() efi_loader: close protocols in UnloadImage() efi_loader: notify memory map changes arch/arm/mach-rockchip/rk_timer.c | 7 ----- cmd/efidebug.c | 3 +++ cmd/nvedit.c | 3 ++- cmd/nvedit_efi.c | 25 +++++++++++++++--- include/time.h | 9 +++++++ lib/efi_loader/efi_bootmgr.c | 9 +++++-- lib/efi_loader/efi_boottime.c | 55 +++++++++++++++++++++++++++++++++++---- lib/efi_loader/efi_console.c | 1 + lib/efi_loader/efi_memory.c | 11 ++++++++ lib/efi_loader/efi_variable.c | 12 ++++++--- lib/time.c | 2 +- 11 files changed, 114 insertions(+), 23 deletions(-)

2 1

[U-Boot] [PATCH] net: eth-uclass: No warning for using ROM MAC
by Trent Piepho 06 Jun '19

06 Jun '19

Using a ROM burned in MAC address is the normal way devices that have this ability will store their MAC. It's normal operation and a warning message isn't appropriate. Make it a debug message, as it is in non-DM_ETH code paths that do this. Signed-off-by: Trent Piepho <tpiepho(a)impinj.com> --- net/eth-uclass.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/net/eth-uclass.c b/net/eth-uclass.c index 031d558625..dae4987355 100644 --- a/net/eth-uclass.c +++ b/net/eth-uclass.c @@ -533,8 +533,7 @@ static int eth_post_probe(struct udevice *dev) memcpy(pdata->enetaddr, env_enetaddr, ARP_HLEN); } else if (is_valid_ethaddr(pdata->enetaddr)) { eth_env_set_enetaddr_by_index("eth", dev->seq, pdata->enetaddr); - printf("\nWarning: %s using MAC address from ROM\n", - dev->name); + debug("%s using MAC address from ROM\n", dev->name); } else if (is_zero_ethaddr(pdata->enetaddr) || !is_valid_ethaddr(pdata->enetaddr)) { #ifdef CONFIG_NET_RANDOM_ETHADDR -- 2.14.5

1 0

[U-Boot] [PATCH v6 00/15] Add Support for eMMC in Am65x-evm
by Faiz Abbas 06 Jun '19

06 Jun '19

Add Support for eMMC in TI's AM65x-evm. The series starts by syncing the sdhci0 node from the kernel. Then it adds APIs and changes to the driver required for handling the driver's integrated phy. The current maximum supported speed is DDR52. Higher speeds and tuning support will be added in a subsequent series. Changes in v6: 1. Squashed one more dependency for clk_200mhz from Andreas's patches[1] into patch 1. Patches now build without any help from the other series. 2. Improved line wrapping in patch 8. Changes in v5: Patches were tested with Andreas's system firmware patches[1] but can now be independently merged cleanly on latest U-boot. Changes in v4: 1. Dropped the patch including regmap_read_poll_timeout() because that support was already added by someone else 2. Fixed a NULL pointer exception in patch 8. 3. Rebased on top of latest master 4. Added extra patches to support GPT partitions in user partition 5. Added Support for environment in eMMC by default Changes in v3: Patch 9: Got rid of variable ret Changes in v2: Patch 9: Fixed return value Patch 12: Fixed spacing [1] https://www.mail-archive.com/u-boot@lists.denx.de/msg325811.html Faiz Abbas (15): arm64: dts: k3: Sync sdhci0 node from kernel and change driver name mmc: am654_sdhci: Remove quirks regmap: Add API regmap_init_mem_index() mmc: sdhci: Add support for sdhci-caps-mask mmc: sdhci: Make sdhci_set_clock() non static arm: dts: k3: Add phy specific properties to SD card node mmc: sdhci: Make set_ios_post() return int mmc: am654_sdhci: Add Support for PHY configs: am65x_evm: Enable CONFIG_REGMAP mmc: am654_sdhci: Use f_max in mmc_config mmc: sdhci: Add support for HOST_CONTROL2 and setting UHS timings mmc: am654_sdhci: Add a platform specific set_control_reg() callback configs: am65x: Add configs to support environment in eMMC am65x_evm: Add Support for creating a filesystem GPT partition in eMMC configs: am65x_evm_a53: Add Support for creating GPT partitions arch/arm/dts/k3-am65-main.dtsi | 22 ++ arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 30 +- arch/arm/dts/k3-am654-base-board.dts | 28 ++ arch/arm/dts/k3-am654-r5-base-board.dts | 38 +++ configs/am65x_evm_a53_defconfig | 11 +- configs/am65x_evm_r5_defconfig | 4 +- drivers/core/regmap.c | 42 +++ drivers/mmc/Kconfig | 9 +- drivers/mmc/Makefile | 2 +- drivers/mmc/am654_sdhci.c | 333 +++++++++++++++++++ drivers/mmc/k3_arsan_sdhci.c | 109 ------ drivers/mmc/sdhci.c | 47 ++- drivers/mmc/xenon_sdhci.c | 4 +- drivers/mmc/zynq_sdhci.c | 31 +- include/configs/am65x_evm.h | 19 +- include/regmap.h | 2 + include/sdhci.h | 22 +- 17 files changed, 568 insertions(+), 185 deletions(-) create mode 100644 drivers/mmc/am654_sdhci.c delete mode 100644 drivers/mmc/k3_arsan_sdhci.c -- 2.19.2

3 19

[U-Boot] [PATCH v2] armv8: ls1046afrwy: Add support for LS1046AFRWY platform
by Vabhav Sharma 06 Jun '19

06 Jun '19

LS1046AFRWY board supports LS1046A family SoCs. This patch add base support for this board. Board support's 4GB ddr memory, i2c, micro-click module,microSD card, serial console,qspi nor flash,ifc nand flash,qsgmii network interface, usb 3.0 and serdes interface to support two x1gen3 pcie interface. Signed-off-by: Camelia Groza <camelia.groza(a)nxp.com> Signed-off-by: Madalin Bucur <madalin.bucur(a)nxp.com> Signed-off-by: Pankit Garg <pankit.garg(a)nxp.com> Signed-off-by: Pramod Kumar <pramod.kumar_1(a)nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat(a)nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma(a)nxp.com> --- Changes in v2: - Incorporated review comments from Prabhakar Kushwaha - Removed non tfa boot support changes - Removed PMIC and DEEP sleep config - Unset CONFIG_SPI_FLASH_BAR in defconfig - Updated mtd-id for QSPI nor in mtdparts variable arch/arm/Kconfig | 15 ++ arch/arm/cpu/armv8/Kconfig | 1 + arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c | 2 + arch/arm/dts/Makefile | 1 + arch/arm/dts/fsl-ls1046a-frwy.dts | 34 ++++ board/freescale/ls1046afrwy/Kconfig | 17 ++ board/freescale/ls1046afrwy/MAINTAINERS | 7 + board/freescale/ls1046afrwy/Makefile | 7 + board/freescale/ls1046afrwy/README | 76 +++++++ board/freescale/ls1046afrwy/ddr.c | 19 ++ board/freescale/ls1046afrwy/eth.c | 114 +++++++++++ board/freescale/ls1046afrwy/ls1046afrwy.c | 223 +++++++++++++++++++++ configs/ls1046afrwy_tfa_defconfig | 59 ++++++ include/configs/ls1046a_common.h | 13 +- include/configs/ls1046afrwy.h | 136 +++++++++++++ include/fm_eth.h | 12 ++ 16 files changed, 734 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/fsl-ls1046a-frwy.dts create mode 100644 board/freescale/ls1046afrwy/Kconfig create mode 100644 board/freescale/ls1046afrwy/MAINTAINERS create mode 100644 board/freescale/ls1046afrwy/Makefile create mode 100644 board/freescale/ls1046afrwy/README create mode 100644 board/freescale/ls1046afrwy/ddr.c create mode 100644 board/freescale/ls1046afrwy/eth.c create mode 100644 board/freescale/ls1046afrwy/ls1046afrwy.c create mode 100644 configs/ls1046afrwy_tfa_defconfig create mode 100644 include/configs/ls1046afrwy.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 01ff57c..d9ad32c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1406,6 +1406,20 @@ config TARGET_LS1046ARDB development platform that supports the QorIQ LS1046A Layerscape Architecture processor. +config TARGET_LS1046AFRWY + bool "Support ls1046afrwy" + select ARCH_LS1046A + select ARM64 + select ARMV8_MULTIENTRY + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + select DM_SPI_FLASH if DM_SPI + imply SCSI + help + Support for Freescale LS1046AFRWY platform. + The LS1046A Freeway Board (FRWY) is a high-performance + development platform that supports the QorIQ LS1046A + Layerscape Architecture processor. config TARGET_H2200 bool "Support h2200" select CPU_PXA @@ -1697,6 +1711,7 @@ source "board/freescale/ls1021aiot/Kconfig" source "board/freescale/ls1046aqds/Kconfig" source "board/freescale/ls1043ardb/Kconfig" source "board/freescale/ls1046ardb/Kconfig" +source "board/freescale/ls1046afrwy/Kconfig" source "board/freescale/ls1012aqds/Kconfig" source "board/freescale/ls1012ardb/Kconfig" source "board/freescale/ls1012afrdm/Kconfig" diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 8a97d5b..92a2b58 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -107,6 +107,7 @@ config PSCI_RESET !TARGET_LS1028ARDB && !TARGET_LS1028AQDS && \ !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \ !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \ + !TARGET_LS1046AFRWY && \ !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \ !TARGET_LX2160AQDS && \ !ARCH_UNIPHIER && !TARGET_S32V234EVB diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c index f8310f2..caa4862 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2019 NXP */ #include <common.h> @@ -33,6 +34,7 @@ static struct serdes_config serdes1_cfg_tbl[] = { SGMII_FM1_DTSEC6} }, {0x2223, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, SGMII_2500_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x3040, {NONE, NONE, QSGMII_FM1_A, NONE} }, {} }; diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e0c54bf..fd14b3a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -342,6 +342,7 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ fsl-ls1046a-qds-duart.dtb \ fsl-ls1046a-qds-lpuart.dtb \ fsl-ls1046a-rdb.dtb \ + fsl-ls1046a-frwy.dtb \ fsl-ls1012a-qds.dtb \ fsl-ls1012a-rdb.dtb \ fsl-ls1012a-2g5rdb.dtb \ diff --git a/arch/arm/dts/fsl-ls1046a-frwy.dts b/arch/arm/dts/fsl-ls1046a-frwy.dts new file mode 100644 index 0000000..3d41e3b --- /dev/null +++ b/arch/arm/dts/fsl-ls1046a-frwy.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Device Tree Include file for NXP Layerscape-1046A family SoC. + * + * Copyright 2019 NXP + * + */ + +/dts-v1/; +/include/ "fsl-ls1046a.dtsi" + +/ { + model = "LS1046A FRWY Board"; + + aliases { + spi0 = &qspi; + }; + +}; + +&qspi { + bus-num = <0>; + status = "okay"; + + qflash0: mt25qu512abb8esf@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <50000000>; + reg = <0>; + }; + +}; + diff --git a/board/freescale/ls1046afrwy/Kconfig b/board/freescale/ls1046afrwy/Kconfig new file mode 100644 index 0000000..6a4c3e9 --- /dev/null +++ b/board/freescale/ls1046afrwy/Kconfig @@ -0,0 +1,17 @@ + +if TARGET_LS1046AFRWY + +config SYS_BOARD + default "ls1046afrwy" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1046afrwy" + +source "board/freescale/common/Kconfig" +endif diff --git a/board/freescale/ls1046afrwy/MAINTAINERS b/board/freescale/ls1046afrwy/MAINTAINERS new file mode 100644 index 0000000..357d23e --- /dev/null +++ b/board/freescale/ls1046afrwy/MAINTAINERS @@ -0,0 +1,7 @@ +LS1046AFRWY BOARD +M: Pramod Kumar <pramod.kumar_1(a)nxp.com> +S: Maintained +F: board/freescale/ls1046afrwy/ +F: board/freescale/ls1046afrwy/ls1046afrwy.c +F: include/configs/ls1046afrwy.h +F: configs/ls1046afrwy_tfa_defconfig diff --git a/board/freescale/ls1046afrwy/Makefile b/board/freescale/ls1046afrwy/Makefile new file mode 100644 index 0000000..c70f5cd --- /dev/null +++ b/board/freescale/ls1046afrwy/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2019 NXP + +obj-y += ddr.o +obj-y += ls1046afrwy.o +obj-$(CONFIG_NET) += eth.o diff --git a/board/freescale/ls1046afrwy/README b/board/freescale/ls1046afrwy/README new file mode 100644 index 0000000..d7b5a77 --- /dev/null +++ b/board/freescale/ls1046afrwy/README @@ -0,0 +1,76 @@ +Overview +-------- +The LS1046A Freeway Board (iFRWY) is a high-performance computing, +evaluation, and development platform that supports the QorIQ LS1046A +LayerScape Architecture processor. The FRWY-LS1046A provides SW development +platform for the Freescale LS1046A processor series, with a complete +debugging environment. The FRWY-LS1046A is lead-free and RoHS-compliant. + +LS1046A SoC Overview +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A +SoC overview. + + FRWY-LS1046A board Overview + ----------------------- + - SERDES1 Connections, 4 lanes supporting: + - Lane0: Unused + - Lane1: Unused + - Lane2: QSGMII + - Lane3: Unused + - SERDES2 Connections, 4 lanes supporting: + - Lane0: Unused + - Lane1: PCIe3 with PCIe x1 slot + - Lane2: Unused + - Lane3: PCIe3 with PCIe x1 slot + - DDR Controller + - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s + -IFC/Local Bus + - One 512 MB NAND flash with ECC support + - USB 3.0 + - Two Type A port + - SDHC: connects directly to a full microSD slot + - QSPI: 64 MB high-speed flash Memory for boot code and storage + - 4 I2C controllers + - UART + - Two 4-pin serial ports at up to 115.2 Kbit/s + - Two DB9 D-Type connectors supporting one Serial port each + - ARM JTAG support + +Memory map from core's view +---------------------------- +Start Address End Address Description Size +0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB +0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB +0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB +0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB +0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB +0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB +0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - CPLD 4KB +0x00_8000_0000 - 0x00_FFFF_FFFF DRAM1 2GB +0x05_0000_0000 - 0x05_07FF_FFFF QMAN S/W Portal 128M +0x05_0800_0000 - 0x05_0FFF_FFFF BMAN S/W Portal 128M +0x08_8000_0000 - 0x09_FFFF_FFFF DRAM2 6GB +0x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1 32G +0x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2 32G +0x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3 32G + +QSPI flash map: +Start Address End Address Description Size +0x00_4000_0000 - 0x00_400F_FFFF RCW + PBI + BL2 1MB +0x00_4010_0000 - 0x00_404F_FFFF FIP Image + (Bl31 + BL32(optee. + bin) + Bl33(uboot) + + headers for secure + boot) 4MB +0x00_4050_0000 - 0x00_405F_FFFF Boot Firmware Env 1MB +0x00_4060_0000 - 0x00_408F_FFFF Secure boot headers 3MB +0x00_4090_0000 - 0x00_4093_FFFF FMan ucode 256KB +0x00_4094_0000 - 0x00_4097_FFFF QE/uQE firmware 256KB +0x00_409C_0000 - 0x00_409F_FFFF Reserved 256KB +0x00_4100_0000 - 0x00_43FF_FFFF FIT Image 48MB + +Booting Options +--------------- +a) QSPI boot +b) microSD boot diff --git a/board/freescale/ls1046afrwy/ddr.c b/board/freescale/ls1046afrwy/ddr.c new file mode 100644 index 0000000..daf17e0 --- /dev/null +++ b/board/freescale/ls1046afrwy/ddr.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <common.h> +#include <fsl_ddr_sdram.h> + +DECLARE_GLOBAL_DATA_PTR; + +int fsl_initdram(void) +{ + gd->ram_size = tfa_get_dram_size(); + + if (!gd->ram_size) + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; +} diff --git a/board/freescale/ls1046afrwy/eth.c b/board/freescale/ls1046afrwy/eth.c new file mode 100644 index 0000000..9f8bd92 --- /dev/null +++ b/board/freescale/ls1046afrwy/eth.c @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ +#include <common.h> +#include <asm/io.h> +#include <netdev.h> +#include <fm_eth.h> +#include <fsl_dtsec.h> +#include <fsl_mdio.h> +#include <malloc.h> + +#include "../common/fman.h" + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FMAN_ENET + struct memac_mdio_info dtsec_mdio_info; + struct mii_dev *dev; + u32 srds_s1; + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + + srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; + + dtsec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; + + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fm_memac_mdio_init(bis, &dtsec_mdio_info); + + /* QSGMII on lane B, MAC 6/5/10/1 */ + fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC10, QSGMII_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT4_PHY_ADDR); + + switch (srds_s1) { + case 0x3040: + break; + default: + printf("Invalid SerDes protocol 0x%x for LS1046AFRWY\n", + srds_s1); + break; + } + + dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); + fm_info_set_mdio(FM1_DTSEC6, dev); + fm_info_set_mdio(FM1_DTSEC5, dev); + fm_info_set_mdio(FM1_DTSEC10, dev); + fm_info_set_mdio(FM1_DTSEC1, dev); + + cpu_eth_init(bis); +#endif + + return pci_eth_init(bis); +} + +#ifdef CONFIG_FMAN_ENET +int fdt_update_ethernet_dt(void *blob) +{ + u32 srds_s1; + int i, prop; + int offset, nodeoff; + const char *path; + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + + srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; + + /* Cycle through all aliases */ + for (prop = 0; ; prop++) { + const char *name; + + /* FDT might have been edited, recompute the offset */ + offset = fdt_first_property_offset(blob, + fdt_path_offset(blob, + "/aliases") + ); + /* Select property number 'prop' */ + for (i = 0; i < prop; i++) + offset = fdt_next_property_offset(blob, offset); + + if (offset < 0) + break; + + path = fdt_getprop_by_offset(blob, offset, &name, NULL); + nodeoff = fdt_path_offset(blob, path); + + switch (srds_s1) { + case 0x3040: + if (!strcmp(name, "ethernet1")) + fdt_status_disabled(blob, nodeoff); + if (!strcmp(name, "ethernet2")) + fdt_status_disabled(blob, nodeoff); + if (!strcmp(name, "ethernet3")) + fdt_status_disabled(blob, nodeoff); + if (!strcmp(name, "ethernet6")) + fdt_status_disabled(blob, nodeoff); + break; + default: + printf("%s:Invalid SerDes prtcl 0x%x for LS1046AFRWY\n", + __func__, srds_s1); + break; + } + } + + return 0; +} +#endif diff --git a/board/freescale/ls1046afrwy/ls1046afrwy.c b/board/freescale/ls1046afrwy/ls1046afrwy.c new file mode 100644 index 0000000..41412a7 --- /dev/null +++ b/board/freescale/ls1046afrwy/ls1046afrwy.c @@ -0,0 +1,223 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <common.h> +#include <i2c.h> +#include <fdt_support.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/fsl_serdes.h> +#include <asm/arch/soc.h> +#include <asm/arch-fsl-layerscape/fsl_icid.h> +#include <hwconfig.h> +#include <ahci.h> +#include <mmc.h> +#include <scsi.h> +#include <fm_eth.h> +#include <fsl_csu.h> +#include <fsl_esdhc.h> +#include <fsl_sec.h> +#include <fsl_dspi.h> + +#define LS1046A_PORSR1_REG 0x1EE0000 +#define BOOT_SRC_SD 0x20000000 +#define BOOT_SRC_MASK 0xFF800000 +#define BOARD_REV_GPIO 13 +#define USB2_SEL_MASK 0x00000100 + +#define BYTE_SWAP_32(word) ((((word) & 0xff000000) >> 24) | \ +(((word) & 0x00ff0000) >> 8) | \ +(((word) & 0x0000ff00) << 8) | \ +(((word) & 0x000000ff) << 24)) +#define SPI_MCR_REG 0x2100000 + +DECLARE_GLOBAL_DATA_PTR; + +int select_i2c_ch_pca9547(u8 ch) +{ + int ret; + + ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); + if (ret) { + puts("PCA: failed to select proper channel\n"); + return ret; + } + + return 0; +} + +static inline void demux_select_usb2(void) +{ + u32 val; + struct ccsr_gpio *pgpio = (void *)(GPIO3_BASE_ADDR); + + val = in_be32(&pgpio->gpdir); + val |= USB2_SEL_MASK; + out_be32(&pgpio->gpdir, val); + + val = in_be32(&pgpio->gpdat); + val |= USB2_SEL_MASK; + out_be32(&pgpio->gpdat, val); +} + +static inline void set_spi_cs_signal_inactive(void) +{ + /* default: all CS signals inactive state is high */ + uint mcr_val; + uint mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK | + DSPI_MCR_CRXF | DSPI_MCR_CTXF; + + mcr_val = in_be32(SPI_MCR_REG); + mcr_val |= DSPI_MCR_HALT; + out_be32(SPI_MCR_REG, mcr_val); + out_be32(SPI_MCR_REG, mcr_cfg_val); + mcr_val = in_be32(SPI_MCR_REG); + mcr_val &= ~DSPI_MCR_HALT; + out_be32(SPI_MCR_REG, mcr_val); +} + +int board_early_init_f(void) +{ + fsl_lsch2_early_init_f(); + + return 0; +} + +static inline uint8_t get_board_version(void) +{ + u8 val; + struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR); + + val = (in_le32(&pgpio->gpdat) >> BOARD_REV_GPIO) & 0x03; + + return val; +} + +int checkboard(void) +{ + static const char *freq[2] = {"100.00MHZ", "100.00MHZ"}; + u32 boot_src; + u8 rev; + + rev = get_board_version(); + switch (rev) { + case 0x00: + puts("Board: LS1046AFRWY, Rev: A, boot from "); + break; + case 0x01: + puts("Board: LS1046AFRWY, Rev: B, boot from "); + break; + default: + puts("Board: LS1046AFRWY, Rev: Unknown, boot from "); + break; + } + boot_src = BYTE_SWAP_32(readl(LS1046A_PORSR1_REG)); + + if ((boot_src & BOOT_SRC_MASK) == BOOT_SRC_SD) + puts("SD\n"); + else + puts("QSPI\n"); + printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[0], freq[1]); + + return 0; +} + +int board_init(void) +{ +#ifdef CONFIG_SECURE_BOOT + /* + * In case of Secure Boot, the IBR configures the SMMU + * to allow only Secure transactions. + * SMMU must be reset in bypass mode. + * Set the ClientPD bit and Clear the USFCFG Bit + */ + u32 val; +val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_SCR0, val); + val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_NSCR0, val); +#endif + +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif + + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + return 0; +} + +int board_setup_core_volt(u32 vdd) +{ + return 0; +} + +void config_board_mux(void) +{ +#ifdef CONFIG_HAS_FSL_XHCI_USB + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + u32 usb_pwrfault; + /* + * USB2 is used, configure mux to USB2_DRVVBUS/USB2_PWRFAULT + * USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA + */ + out_be32(&scfg->rcwpmuxcr0, 0x3300); +#ifdef CONFIG_HAS_FSL_IIC3 + /* IIC3 is used, configure mux to use IIC3_SCL/IIC3/SDA */ + out_be32(&scfg->rcwpmuxcr0, 0x0000); +#endif + out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); + usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << + SCFG_USBPWRFAULT_USB3_SHIFT) | + (SCFG_USBPWRFAULT_DEDICATED << + SCFG_USBPWRFAULT_USB2_SHIFT) | + (SCFG_USBPWRFAULT_SHARED << + SCFG_USBPWRFAULT_USB1_SHIFT); + out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); +#ifndef CONFIG_HAS_FSL_IIC3 + /* + * LS1046A FRWY board has demultiplexer NX3DV42GU with GPIO3_23 as input + * to select I2C3_USB2_SEL_IO + * I2C3_USB2_SEL = 0: I2C3_SCL/SDA signals are routed to + * I2C3 header (default) + * I2C3_USB2_SEL = 1: USB2_DRVVBUS/PWRFAULT signals are routed to + * USB2 port + * programmed to select USB2 by setting GPIO3_23 output to one + */ + demux_select_usb2(); +#endif +#endif + set_spi_cs_signal_inactive(); +} + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + config_board_mux(); + return 0; +} +#endif + +int ft_board_setup(void *blob, bd_t *bd) +{ + u64 base[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + + /* fixup DT for the two DDR banks */ + base[0] = gd->bd->bi_dram[0].start; + size[0] = gd->bd->bi_dram[0].size; + base[1] = gd->bd->bi_dram[1].start; + size[1] = gd->bd->bi_dram[1].size; + + fdt_fixup_memory_banks(blob, base, size, 2); + ft_cpu_setup(blob, bd); + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); +#endif + + fdt_fixup_icid(blob); + + return 0; +} diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig new file mode 100644 index 0000000..32cd778 --- /dev/null +++ b/configs/ls1046afrwy_tfa_defconfig @@ -0,0 +1,59 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1046AFRWY=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_QSPI_AHB_INIT=y +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" +CONFIG_MISC_INIT_R=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-frwy" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_DM=y +CONFIG_FSL_CAAM=y +CONFIG_FSL_ESDHC=y +CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_BAR is not set +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y +CONFIG_PHY_GIGE=y +CONFIG_PHY_VITESSE=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y +CONFIG_DM_SCSI=y +CONFIG_SATA_CEVA=y +CONFIG_SCSI_AHCI=y +CONFIG_SCSI=y +CONFIG_AHCI=y diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 34b4756..59c43f1 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2016 Freescale Semiconductor + * Copyright 2019 NXP */ #ifndef __LS1046A_COMMON_H @@ -202,6 +203,15 @@ #include <config_distro_bootcmd.h> #endif +#if defined(CONFIG_TARGET_LS1046AFRWY) +#define LS1046A_BOOT_SRC_AND_HDR\ + "boot_scripts=ls1046afrwy_boot.scr\0" \ + "boot_script_hdr=hdr_ls1046afrwy_bs.out\0" +#else +#define LS1046A_BOOT_SRC_AND_HDR\ + "boot_scripts=ls1046ardb_boot.scr\0" \ + "boot_script_hdr=hdr_ls1046ardb_bs.out\0" +#endif #ifndef SPL_NO_MISC /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -232,8 +242,7 @@ "console=ttyS0,115200\0" \ CONFIG_MTDPARTS_DEFAULT "\0" \ BOOTENV \ - "boot_scripts=ls1046ardb_boot.scr\0" \ - "boot_script_hdr=hdr_ls1046ardb_bs.out\0" \ + LS1046A_BOOT_SRC_AND_HDR \ "scan_dev_for_boot_part=" \ "part list ${devtype} ${devnum} devplist; " \ "env exists devplist || setenv devplist 1; " \ diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h new file mode 100644 index 0000000..791bb8d --- /dev/null +++ b/include/configs/ls1046afrwy.h @@ -0,0 +1,136 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#ifndef __LS1046AFRWY_H__ +#define __LS1046AFRWY_H__ + +#include "ls1046a_common.h" + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 + +#define CONFIG_LAYERSCAPE_NS_ACCESS + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 + +#define CONFIG_SYS_UBOOT_BASE 0x40100000 + +/* IFC */ +#define CONFIG_FSL_IFC +/* + * NAND Flash Definitions + */ +#define CONFIG_NAND_FSL_IFC + +#define CONFIG_SYS_NAND_BASE 0x7e800000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE + +#define CONFIG_SYS_NAND_CSPR_EXT (0x0) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_NAND \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ + | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x7) | \ + FTIM0_NAND_TWH(0xa)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0xe) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ + FTIM2_NAND_TREH(0xa) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE + +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +/* IFC Timing Params */ +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 +#define I2C_RETIMER_ADDR 0x18 + +/* I2C bus multiplexer */ +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ +#define I2C_MUX_CH_DEFAULT 0x1 /* Channel 0*/ +#define I2C_MUX_CH_RTC 0x1 /* Channel 0*/ + +/* RTC */ +#define RTC +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 0 I2C bus 0*/ +#define CONFIG_SYS_RTC_BUS_NUM 0 + +/* + * Environment + */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */ +#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */ + +/* FMan */ +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET + +#define QSGMII_PORT1_PHY_ADDR 0x1c +#define QSGMII_PORT2_PHY_ADDR 0x1d +#define QSGMII_PORT3_PHY_ADDR 0x1e +#define QSGMII_PORT4_PHY_ADDR 0x1f + +#define FDT_SEQ_MACADDR_FROM_ENV + +#define CONFIG_ETHPRIME "FM1@DTSEC3" + +#endif + +/* QSPI device */ +#ifdef CONFIG_FSL_QSPI +#define FSL_QSPI_FLASH_SIZE SZ_64M +#define FSL_QSPI_FLASH_NUM 1 +#endif + +#undef CONFIG_BOOTCOMMAND +#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ + "env exists secureboot && esbc_halt;;" +#define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \ + "env exists secureboot && esbc_halt;" + +#include <asm/fsl_secure_boot.h> + +#endif /* __LS1046AFRWY_H__ */ diff --git a/include/fm_eth.h b/include/fm_eth.h index 2e2ba75..729ad63 100644 --- a/include/fm_eth.h +++ b/include/fm_eth.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2009-2012 Freescale Semiconductor, Inc. + * Copyright 2019 NXP */ #ifndef __FM_ETH_H__ @@ -41,8 +42,19 @@ enum fm_eth_type { FM_ETH_10G_E, }; +/* Historically, on FMan v3 platforms, the first MDIO bus has been used for + * Clause 22 PHYs and the second MDIO bus for 10G Clause 45 PHYs (thus the + * TGEC name). + * + * On LS1046A-FRWY, the QSGMII PHY is connected to the second MDIO bus, + * and no TGEC ports are present on-board. + */ #ifdef CONFIG_SYS_FMAN_V3 +#ifdef CONFIG_TARGET_LS1046AFRWY +#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000) +#else #define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfc000) +#endif #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000) #if (CONFIG_SYS_NUM_FMAN == 2) #define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfc000) -- 2.7.4

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