June 2019 - U-Boot

[U-Boot] [PATCH] spl: imx6: Provide a SPL_SIZE_LIMIT default
by Fabio Estevam 11 Jun '19

11 Jun '19

As explained in include/configs/imx6_spl.h. the i.MX6 SPL size limit is 68KB (4KB header + 64KB max size). Provide such limit for all i.MX6 boards that use SPL to detect SPL size overflow in build time. Signed-off-by: Fabio Estevam <festevam(a)gmail.com> --- Hi Tom and Stefano, In order to build fine for all mx6 boards the following patch is needed: https://lists.denx.de/pipermail/u-boot/2019-May/370224.html Ran buildman successfully for all imx6 boards. common/spl/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index ac2f470032..48f6b39a75 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -28,6 +28,7 @@ config SPL_FRAMEWORK config SPL_SIZE_LIMIT int "Maximum size of SPL image" depends on SPL + default 69632 if ARCH_MX6 default 0 help Specifies the maximum length of the U-Boot SPL image. -- 2.17.1

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[U-Boot] [PATCH v2] pinctrl: imx: Define imx6_pinctrl_soc_info in .data section
by Lukasz Majewski 11 Jun '19

11 Jun '19

This commit is necessary to be able to re-use the pinctrl code in early SPL to properly configure pins. The problem is that those "static" structures (without explicit initialization) are placed in the SDRAM area, which corresponds to u-boot proper (not even SPL). Hence, when one wants to configure pins before relocation via DTS/DM, the board hangs (imx6q SoC powered one) as only OCRAM area is available (0x009xxxxx). This commit prevents from this issue by moving the imx6_pinctrl_soc_info structure to data section (from BSS). Signed-off-by: Lukasz Majewski <lukma(a)denx.de> --- Changes in v2: - Use __section(".data") instead of rewritting the code to use calloc() (less intrusive commit) drivers/pinctrl/nxp/pinctrl-imx6.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/nxp/pinctrl-imx6.c b/drivers/pinctrl/nxp/pinctrl-imx6.c index d7c95bb738..0c1e7a9c05 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx6.c +++ b/drivers/pinctrl/nxp/pinctrl-imx6.c @@ -10,7 +10,7 @@ #include "pinctrl-imx.h" -static struct imx_pinctrl_soc_info imx6_pinctrl_soc_info; +static struct imx_pinctrl_soc_info imx6_pinctrl_soc_info __section(".data"); /* FIXME Before reloaction, BSS is overlapped with DT area */ static struct imx_pinctrl_soc_info imx6ul_pinctrl_soc_info = { -- 2.11.0

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[U-Boot] [PATCH V2] imx8: cpu: get temperature when print cpu desc
by sbabic＠denx.de 11 Jun '19

11 Jun '19

> Read the temperature when print cpu inforation. > Signed-off-by: Peng Fan <peng.fan(a)nxp.com> Applied to u-boot-imx, master, thanks ! Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic(a)denx.de =====================================================================

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[U-Boot] [PATCH] arm: imx8: factor out uart init code
by Anatolij Gustschin 11 Jun '19

11 Jun '19

New imx8 boards started adding duplicated UART init code. Factor out this to common function sc_pm_setup_uart(). Signed-off-by: Anatolij Gustschin <agust(a)denx.de> Cc: Peng Fan <peng.fan(a)nxp.com> --- arch/arm/include/asm/arch-imx8/sys_proto.h | 2 ++ arch/arm/mach-imx/imx8/Makefile | 2 +- arch/arm/mach-imx/imx8/misc.c | 26 ++++++++++++++++++++++ board/freescale/imx8qm_mek/imx8qm_mek.c | 16 +++---------- board/freescale/imx8qxp_mek/imx8qxp_mek.c | 16 +++---------- 5 files changed, 35 insertions(+), 27 deletions(-) create mode 100644 arch/arm/mach-imx/imx8/misc.c diff --git a/arch/arm/include/asm/arch-imx8/sys_proto.h b/arch/arm/include/asm/arch-imx8/sys_proto.h index 73ffaba7d5..3f5bbe9dcc 100644 --- a/arch/arm/include/asm/arch-imx8/sys_proto.h +++ b/arch/arm/include/asm/arch-imx8/sys_proto.h @@ -3,6 +3,7 @@ * Copyright 2018 NXP */ +#include <asm/arch/sci/sci.h> #include <asm/mach-imx/sys_proto.h> #include <linux/types.h> @@ -17,3 +18,4 @@ struct pass_over_info_t { enum boot_device get_boot_device(void); int print_bootinfo(void); +int sc_pm_setup_uart(sc_rsrc_t uart_rsrc, sc_pm_clock_rate_t clk_rate); diff --git a/arch/arm/mach-imx/imx8/Makefile b/arch/arm/mach-imx/imx8/Makefile index 31ad169ccf..92b5c56acb 100644 --- a/arch/arm/mach-imx/imx8/Makefile +++ b/arch/arm/mach-imx/imx8/Makefile @@ -4,4 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += cpu.o iomux.o +obj-y += cpu.o iomux.o misc.o diff --git a/arch/arm/mach-imx/imx8/misc.c b/arch/arm/mach-imx/imx8/misc.c new file mode 100644 index 0000000000..5fe23d2080 --- /dev/null +++ b/arch/arm/mach-imx/imx8/misc.c @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <common.h> +#include <asm/arch/sci/sci.h> + +int sc_pm_setup_uart(sc_rsrc_t uart_rsrc, sc_pm_clock_rate_t clk_rate) +{ + sc_pm_clock_rate_t rate = clk_rate; + int ret; + + /* Power up UARTn */ + ret = sc_pm_set_resource_power_mode(-1, uart_rsrc, SC_PM_PW_MODE_ON); + if (ret) + return ret; + + /* Set UARTn clock root to 'rate' MHz */ + ret = sc_pm_set_clock_rate(-1, uart_rsrc, 2, &rate); + if (ret) + return ret; + + /* Enable UARTn clock root */ + ret = sc_pm_clock_enable(-1, uart_rsrc, 2, true, false); + if (ret) + return ret; + + return 0; +} diff --git a/board/freescale/imx8qm_mek/imx8qm_mek.c b/board/freescale/imx8qm_mek/imx8qm_mek.c index e69efc4dd6..249c29e0f2 100644 --- a/board/freescale/imx8qm_mek/imx8qm_mek.c +++ b/board/freescale/imx8qm_mek/imx8qm_mek.c @@ -34,21 +34,11 @@ static void setup_iomux_uart(void) int board_early_init_f(void) { + sc_pm_clock_rate_t rate = SC_80MHZ; int ret; - /* Set UART0 clock root to 80 MHz */ - sc_pm_clock_rate_t rate = 80000000; - - /* Power up UART0 */ - ret = sc_pm_set_resource_power_mode(-1, SC_R_UART_0, SC_PM_PW_MODE_ON); - if (ret) - return ret; - ret = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, &rate); - if (ret) - return ret; - - /* Enable UART0 clock root */ - ret = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false); + /* Set UART0 clock root to 80 MHz */ + ret = sc_pm_setup_uart(SC_R_UART_0, rate); if (ret) return ret; diff --git a/board/freescale/imx8qxp_mek/imx8qxp_mek.c b/board/freescale/imx8qxp_mek/imx8qxp_mek.c index 63cd605b6a..1038f26d69 100644 --- a/board/freescale/imx8qxp_mek/imx8qxp_mek.c +++ b/board/freescale/imx8qxp_mek/imx8qxp_mek.c @@ -40,21 +40,11 @@ static void setup_iomux_uart(void) int board_early_init_f(void) { + sc_pm_clock_rate_t rate = SC_80MHZ; int ret; - /* Set UART0 clock root to 80 MHz */ - sc_pm_clock_rate_t rate = 80000000; - - /* Power up UART0 */ - ret = sc_pm_set_resource_power_mode(-1, SC_R_UART_0, SC_PM_PW_MODE_ON); - if (ret) - return ret; - ret = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, &rate); - if (ret) - return ret; - - /* Enable UART0 clock root */ - ret = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false); + /* Set UART0 clock root to 80 MHz */ + ret = sc_pm_setup_uart(SC_R_UART_0, rate); if (ret) return ret; -- 2.17.1

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[U-Boot] [PATCH v4 00/13] clk: Port Linux common clock framework [CCF] to U-boot (tag: 5.0-rc3)
by Lukasz Majewski 11 Jun '19

11 Jun '19

This patch series brings the files from Linux kernel to provide clocks support as it is used on the Linux kernel with common clock framework [CCF] setup. This series also fixes several problems with current clocks and provides sandbox tests for functions addded to clk-uclass.c file. Repository: https://github.com/lmajewski/u-boot-dfu/commits/CCF-v4 Changes in v4: - New patch - None - None - None - New patch - None - Port some more Linux code to facilitate imx8 code porting (most notably flags) - Explicitly use container_of() based macro to provide struct clk in various places (e.g. gate2, mux, etc) Following patches has been squashed: http://patchwork.ozlabs.org/patch/1093141/ http://patchwork.ozlabs.org/patch/1093142/ http://patchwork.ozlabs.org/patch/1093146/ - New patch Changes in v3: - New patch - The rate information is now cached into struct clk field - The clk_get_parent() is used to get pointer to the parent struct clk - Replace -ENODEV with -ENOENT - Use **clkp instead of **c - New patch - New patch Lukasz Majewski (13): clk: doc: Add documentation entry for Common Clock Framework [CCF] (i.MX) dm: Fix documentation entry as there is no UCLASS_CLOCK uclass clk: Remove clock ID check in .get_rate() of clk_fixed_* clk: Extend struct clk to provide information regarding clock rate clk: Extend struct clk to provide clock type agnostic flags clk: Provide struct clk for fixed rate clock (clk_fixed_rate.c) dm: clk: Define clk_get_parent() for clk operations dm: clk: Define clk_get_parent_rate() for clk operations dm: clk: Define clk_get_by_id() for clk operations clk: test: Provide unit test for clk_get_by_id() method clk: test: Provide unit test for clk_get_parent_rate() method clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: 5.0-rc3) dm: clk: Extend clk_get_parent_rate() to support CLK_GET_RATE_NOCACHE flag arch/sandbox/include/asm/clk.h | 16 ++++ doc/imx/clk/ccf.txt | 83 +++++++++++++++++++ drivers/clk/Kconfig | 14 ++++ drivers/clk/Makefile | 2 + drivers/clk/clk-divider.c | 148 ++++++++++++++++++++++++++++++++++ drivers/clk/clk-fixed-factor.c | 87 ++++++++++++++++++++ drivers/clk/clk-mux.c | 164 +++++++++++++++++++++++++++++++++++++ drivers/clk/clk-uclass.c | 60 ++++++++++++++ drivers/clk/clk.c | 56 +++++++++++++ drivers/clk/clk_fixed_factor.c | 3 - drivers/clk/clk_fixed_rate.c | 8 +- drivers/clk/clk_sandbox_test.c | 49 +++++++++++ drivers/clk/imx/Kconfig | 9 +++ drivers/clk/imx/Makefile | 2 + drivers/clk/imx/clk-gate2.c | 113 ++++++++++++++++++++++++++ drivers/clk/imx/clk-imx6q.c | 179 +++++++++++++++++++++++++++++++++++++++++ drivers/clk/imx/clk-pfd.c | 91 +++++++++++++++++++++ drivers/clk/imx/clk-pllv3.c | 83 +++++++++++++++++++ drivers/clk/imx/clk.h | 75 +++++++++++++++++ include/clk.h | 37 ++++++++- include/linux/clk-provider.h | 115 ++++++++++++++++++++++++++ test/dm/clk.c | 4 +- 22 files changed, 1390 insertions(+), 8 deletions(-) create mode 100644 doc/imx/clk/ccf.txt create mode 100644 drivers/clk/clk-divider.c create mode 100644 drivers/clk/clk-fixed-factor.c create mode 100644 drivers/clk/clk-mux.c create mode 100644 drivers/clk/clk.c create mode 100644 drivers/clk/imx/clk-gate2.c create mode 100644 drivers/clk/imx/clk-imx6q.c create mode 100644 drivers/clk/imx/clk-pfd.c create mode 100644 drivers/clk/imx/clk-pllv3.c create mode 100644 drivers/clk/imx/clk.h create mode 100644 include/linux/clk-provider.h -- 2.11.0

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[U-Boot] [PATCH v1 0/4] DM: Convert i.MX28 gpio, pinmux and eth drivers to DM/DTS
by Lukasz Majewski 11 Jun '19

11 Jun '19

This patch series converts some i.MX28 drivers to use DM/DTS. Converted drivers: - mxs_gpio.c - gpio driver - pinctrl-mxs.c - pinmux driver - Adjust fec_eth.c to support also i.MX28 SoC. This patch series shall help with coordinated i.MX28 DM/DTS conversion and avoidance of effort duplication. After applying this series it is possible to use ETH on i.MX28 board with following DTS description: &mac0 { phy-mode = "rmii"; pinctrl-names = "default"; pinctrl-0 = <&mac0_pins_a>; phy-supply = <&reg_fec_3v3>; phy-reset-gpios = <&gpio2 13 GPIO_ACTIVE_LOW>; phy-reset-duration = <1>; phy-reset-post-delay = <1>; status = "okay"; fixed-link { speed = <100>; full-duplex; }; }; Travis-CI: https://travis-ci.org/lmajewski/u-boot-dfu/builds/543773376 Applied on top of u-boot/master branch SHA1: dbbb1c43f26cb28b64df80b72fffbaf2801e8a30 Lukasz Majewski (4): DTS: imx28: Copy imx28 device tree related files from Linux kernel (v5.1.2) imx: net: Enable support for i.MX28 DM_ETH in the fec_mxc.c driver DM: mxs: gpio: Add support for DM/DTS in the mxs_gpio.c driver (DM_GPIO) imx: pinctrl: Add support for i.MX28 mxs pinctrl driver arch/arm/dts/imx28-pinfunc.h | 506 +++++++++++++ arch/arm/dts/imx28.dtsi | 1330 ++++++++++++++++++++++++++++++++++ arch/arm/dts/mxs-pinfunc.h | 31 + arch/arm/include/asm/arch-mxs/gpio.h | 28 + drivers/gpio/mxs_gpio.c | 149 ++++ drivers/net/Kconfig | 2 +- drivers/net/fec_mxc.c | 1 + drivers/pinctrl/nxp/Kconfig | 10 + drivers/pinctrl/nxp/Makefile | 1 + drivers/pinctrl/nxp/pinctrl-mxs.c | 164 +++++ 10 files changed, 2221 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx28-pinfunc.h create mode 100644 arch/arm/dts/imx28.dtsi create mode 100644 arch/arm/dts/mxs-pinfunc.h create mode 100644 drivers/pinctrl/nxp/pinctrl-mxs.c -- 2.11.0

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[U-Boot] [PATCH v2 0/6] - Add Ethernet support for stm32mpu
by Christophe Roullier 11 Jun '19

11 Jun '19

Support all PHY config: PHY_MODE (MII,GMII, RMII, RGMII) Phy wo crystal (25Mhz and 50 Mhz), No 125Mhz from PHY config Changes in v2: -remark from Joe Hershberger to replace "int interface" with "phy_interface_t interface" and manage return values "-1", "0" with PHY_INTERFACE_MODE_NONE and PHY_INTERFACE_MODE_MII Christophe Roullier (5): board: stm32mp1: Add board_interface_eth_init net: dwc_eth_qos: add Ethernet stm32mp1 support ARM: dts: stm32: Add Ethernet support on stm32mp1 stm32mp1: Add Ethernet support for stm32mp1 board configs: stm32mp15: Enable Ethernet feature Patrick Delaunay (1): stm32mp1: clk: use the correct identifier for ethck arch/arm/dts/stm32mp157-pinctrl.dtsi | 9 +- arch/arm/dts/stm32mp157c-ev1.dts | 2 +- arch/arm/dts/stm32mp157c.dtsi | 16 +- board/st/stm32mp1/stm32mp1.c | 68 ++++- configs/stm32mp15_basic_defconfig | 2 + drivers/clk/clk_stm32mp1.c | 2 +- drivers/net/dwc_eth_qos.c | 435 +++++++++++++++++++++++---- include/configs/stm32mp1.h | 12 +- 8 files changed, 480 insertions(+), 66 deletions(-) -- 2.17.1

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[U-Boot] [PATCH v2 0/3] Add Avenger96 board support
by Manivannan Sadhasivam 11 Jun '19

11 Jun '19

Hello, This patchset adds board support for Avenger96, a 96Boards Consumer Edition board from Arrow Electronics. This board is based on the STM32MP1 MPU and the board support is added under st boards since there are no significance changes required to boot u-boot on this board other than the dts. More information about this board can be found in 96Boards website: https://www.96boards.org/product/avenger96/ Thanks, Mani Changes in v2: * Added missing `u-boot,dm-pre-reloc` property to UART and SDMMC nodes and verified SPL boot. Manivannan Sadhasivam (3): arm: dts: stm32mp157: Add missing pinctrl definitions board: stm32mp1: Add Avenger96 board support arm: mach-stm32mp: Add newline to the MAC error message arch/arm/dts/Makefile | 1 + arch/arm/dts/stm32mp157-pinctrl.dtsi | 63 +++ .../arm/dts/stm32mp157a-avenger96-u-boot.dtsi | 191 +++++++++ arch/arm/dts/stm32mp157a-avenger96.dts | 362 ++++++++++++++++++ arch/arm/mach-stm32mp/cpu.c | 2 +- board/st/stm32mp1/README | 23 ++ 6 files changed, 641 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp157a-avenger96.dts -- 2.17.1

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[U-Boot] [PATCH v1] net: use block layer in net driver
by Yinbo Zhu 11 Jun '19

11 Jun '19

From: Yinbo Zhu <yinbo.zhu(a)nxp.com> At present the MMC subsystem maintains its own list of MMC devices. This cannot work with driver model when CONFIG_BLK is enabled, use blk_dread to replace previous mmc read interface, Signed-off-by: Yinbo Zhu <yinbo.zhu(a)nxp.com> --- drivers/net/phy/cortina.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c index a04a118f90..2337c3403c 100644 --- a/drivers/net/phy/cortina.c +++ b/drivers/net/phy/cortina.c @@ -176,7 +176,7 @@ void cs4340_upload_firmware(struct phy_device *phydev) printf("MMC read: dev # %u, block # %u, count %u ...\n", dev, blk, cnt); mmc_init(mmc); - (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, + (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt, addr); } #endif -- 2.17.1

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[U-Boot] [PATCH] i2c: designware: Get clock rate from clock DM
by Ley Foon Tan 11 Jun '19

11 Jun '19

Get clock rate from clock DM if CONFIG_CLK is enabled. Otherwise, uses IC_CLK define. Signed-off-by: Ley Foon Tan <ley.foon.tan(a)intel.com> --- drivers/i2c/designware_i2c.c | 54 +++++++++++++++++++++++++++++------- 1 file changed, 44 insertions(+), 10 deletions(-) diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index 9ccc2411a6..a1ed30650c 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -4,6 +4,7 @@ * Vipin Kumar, ST Micoelectronics, vipin.kumar(a)st.com. */ +#include <clk.h> #include <common.h> #include <dm.h> #include <i2c.h> @@ -35,6 +36,9 @@ struct dw_i2c { struct i2c_regs *regs; struct dw_scl_sda_cfg *scl_sda_cfg; struct reset_ctl_bulk resets; +#if CONFIG_IS_ENABLED(CLK) + struct clk clk; +#endif }; #ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED @@ -78,7 +82,7 @@ static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable) */ static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base, struct dw_scl_sda_cfg *scl_sda_cfg, - unsigned int speed) + unsigned int speed, u32 bus_mhz) { unsigned int cntl; unsigned int hcnt, lcnt; @@ -104,8 +108,8 @@ static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base, hcnt = scl_sda_cfg->fs_hcnt; lcnt = scl_sda_cfg->fs_lcnt; } else { - hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO; - lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO; + hcnt = (bus_mhz * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO; + lcnt = (bus_mhz * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO; } writel(hcnt, &i2c_base->ic_hs_scl_hcnt); writel(lcnt, &i2c_base->ic_hs_scl_lcnt); @@ -118,8 +122,8 @@ static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base, hcnt = scl_sda_cfg->ss_hcnt; lcnt = scl_sda_cfg->ss_lcnt; } else { - hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO; - lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO; + hcnt = (bus_mhz * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO; + lcnt = (bus_mhz * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO; } writel(hcnt, &i2c_base->ic_ss_scl_hcnt); writel(lcnt, &i2c_base->ic_ss_scl_lcnt); @@ -132,8 +136,8 @@ static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base, hcnt = scl_sda_cfg->fs_hcnt; lcnt = scl_sda_cfg->fs_lcnt; } else { - hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO; - lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO; + hcnt = (bus_mhz * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO; + lcnt = (bus_mhz * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO; } writel(hcnt, &i2c_base->ic_fs_scl_hcnt); writel(lcnt, &i2c_base->ic_fs_scl_lcnt); @@ -388,7 +392,7 @@ static int __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr) writel(IC_TX_TL, &i2c_base->ic_tx_tl); writel(IC_STOP_DET, &i2c_base->ic_intr_mask); #ifndef CONFIG_DM_I2C - __dw_i2c_set_bus_speed(i2c_base, NULL, speed); + __dw_i2c_set_bus_speed(i2c_base, NULL, speed, IC_CLK); writel(slaveaddr, &i2c_base->ic_sar); #endif @@ -433,7 +437,7 @@ static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap, unsigned int speed) { adap->speed = speed; - return __dw_i2c_set_bus_speed(i2c_get_base(adap), NULL, speed); + return __dw_i2c_set_bus_speed(i2c_get_base(adap), NULL, speed, IC_CLK); } static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) @@ -523,8 +527,20 @@ static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) { struct dw_i2c *i2c = dev_get_priv(bus); + ulong rate; + +#if CONFIG_IS_ENABLED(CLK) + rate = clk_get_rate(&i2c->clk); + if (IS_ERR_VALUE(rate)) + return -EINVAL; - return __dw_i2c_set_bus_speed(i2c->regs, i2c->scl_sda_cfg, speed); + /* Convert to MHz */ + rate /= 1000000; +#else + rate = IC_CLK; +#endif + return __dw_i2c_set_bus_speed(i2c->regs, i2c->scl_sda_cfg, speed, + rate); } static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr, @@ -568,6 +584,19 @@ static int designware_i2c_probe(struct udevice *bus) else reset_deassert_bulk(&priv->resets); +#if CONFIG_IS_ENABLED(CLK) + ret = clk_get_by_index(bus, 0, &priv->clk); + if (ret) + return ret; + + ret = clk_enable(&priv->clk); + if (ret && ret != -ENOSYS && ret != -ENOTSUPP) { + clk_free(&priv->clk); + dev_err(bus, "failed to enable clock\n"); + return ret; + } +#endif + return __dw_i2c_init(priv->regs, 0, 0); } @@ -575,6 +604,11 @@ static int designware_i2c_remove(struct udevice *dev) { struct dw_i2c *priv = dev_get_priv(dev); +#if CONFIG_IS_ENABLED(CLK) + clk_disable(&priv->clk); + clk_free(&priv->clk); +#endif + return reset_release_bulk(&priv->resets); } -- 2.19.0

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