April 2019 - U-Boot

[U-Boot] [PATCH 5/5] MAINTAINERS: change spi driver entry
by Weijie Gao 26 Apr '19

26 Apr '19

Change mtk_qspi.c to mtk_spimem.c Signed-off-by: Weijie Gao <weijie.gao(a)mediatek.com> --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index aa4b3bc..e8a8192 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -202,7 +202,7 @@ F: drivers/mmc/mtk-sd.c F: drivers/pinctrl/mediatek/ F: drivers/power/domain/mtk-power-domain.c F: drivers/ram/mediatek/ -F: drivers/spi/mtk_qspi.c +F: drivers/spi/mtk_spimem.c F: drivers/timer/mtk_timer.c F: drivers/watchdog/mtk_wdt.c F: drivers/net/mtk_eth.c -- 1.9.1

1 0

[U-Boot] [PATCH 4/5] arm: dts: change MT7629 to use spi-mem rather than qspi
by Weijie Gao 26 Apr '19

26 Apr '19

The original mtk_qspi driver has been removed. We change MT7629 to use newly added mtk-spimem driver. Signed-off-by: Weijie Gao <weijie.gao(a)mediatek.com> --- arch/arm/dts/mt7629-rfb.dts | 18 +++++++++++++----- arch/arm/dts/mt7629.dtsi | 14 ++++++++++---- 2 files changed, 23 insertions(+), 9 deletions(-) diff --git a/arch/arm/dts/mt7629-rfb.dts b/arch/arm/dts/mt7629-rfb.dts index 4612218..a55ffa6 100644 --- a/arch/arm/dts/mt7629-rfb.dts +++ b/arch/arm/dts/mt7629-rfb.dts @@ -13,7 +13,7 @@ compatible = "mediatek,mt7629-rfb", "mediatek,mt7629"; aliases { - spi0 = &qspi; + spi0 = &spimem; }; chosen { @@ -34,7 +34,14 @@ }; &pinctrl { - qspi_pins: qspi-pins { + snfi_pins: snfi-pins { + mux { + function = "flash"; + groups = "snfi"; + }; + }; + + snor_pins: snor-pins { mux { function = "flash"; groups = "spi_nor"; @@ -56,9 +63,10 @@ }; }; -&qspi { - pinctrl-names = "default"; - pinctrl-0 = <&qspi_pins>; +&spimem { + pinctrl-names = "default", "snor_mmap"; + pinctrl-0 = <&snfi_pins>; + pinctrl-1 = <&snor_pins>; status = "okay"; spi-flash@0{ diff --git a/arch/arm/dts/mt7629.dtsi b/arch/arm/dts/mt7629.dtsi index c87115e..9dedb88 100644 --- a/arch/arm/dts/mt7629.dtsi +++ b/arch/arm/dts/mt7629.dtsi @@ -215,10 +215,16 @@ status = "disabled"; }; - qspi: qspi@11014000 { - compatible = "mediatek,mt7629-qspi"; - reg = <0x11014000 0xe0>, <0x30000000 0x10000000>; - reg-names = "reg_base", "mem_base"; + spimem: spimem@1100d000 { + compatible = "mediatek,mtk-spimem"; + reg = <0x1100d000 0x2000>; + clocks = <&pericfg CLK_PERI_NFI_PD>, + <&pericfg CLK_PERI_SNFI_PD>; + clock-names = "nfi_clk", "pad_clk"; + assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>, + <&topckgen CLK_TOP_NFI_INFRA_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>, + <&topckgen CLK_TOP_UNIVPLL2_D8>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; -- 1.9.1

1 0

[U-Boot] [PATCH 2/5] spi: remove obsolete mtk_qspi driver
by Weijie Gao 26 Apr '19

26 Apr '19

Since u-boot has added the spi-mem framework and replaced the spi-nor framework, the mtk_qspi is no longer compatible with the new spi-nor driver. Remove this driver, and a new driver will be added later. Cc: Jagan Teki <jagan(a)openedev.com> Signed-off-by: Weijie Gao <weijie.gao(a)mediatek.com> --- drivers/spi/Kconfig | 8 -- drivers/spi/Makefile | 1 - drivers/spi/mtk_qspi.c | 359 ------------------------------------------------- 3 files changed, 368 deletions(-) delete mode 100644 drivers/spi/mtk_qspi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index fb794ad..92d7ca6 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -139,14 +139,6 @@ config MT7621_SPI the SPI NOR flash on platforms embedding this Ralink / MediaTek SPI core, like MT7621/7628/7688. -config MTK_QSPI - bool "Mediatek QSPI driver" - imply SPI_FLASH_BAR - help - Enable the Mediatek QSPI driver. This driver can be - used to access the SPI NOR flash on platforms embedding this - Mediatek QSPI IP core. - config MVEBU_A3700_SPI bool "Marvell Armada 3700 SPI driver" select CLK_ARMADA_3720 diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 8be9a4b..f1e3bec 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -36,7 +36,6 @@ obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o -obj-$(CONFIG_MTK_QSPI) += mtk_qspi.o obj-$(CONFIG_MT7621_SPI) += mt7621_spi.o obj-$(CONFIG_MSCC_BB_SPI) += mscc_bb_spi.o obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o diff --git a/drivers/spi/mtk_qspi.c b/drivers/spi/mtk_qspi.c deleted file mode 100644 index b510733..0000000 --- a/drivers/spi/mtk_qspi.c +++ /dev/null @@ -1,359 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2018 MediaTek, Inc. - * Author : Guochun.Mao(a)mediatek.com - */ - -#include <common.h> -#include <dm.h> -#include <malloc.h> -#include <spi.h> -#include <asm/io.h> -#include <linux/iopoll.h> -#include <linux/ioport.h> - -/* Register Offset */ -struct mtk_qspi_regs { - u32 cmd; - u32 cnt; - u32 rdsr; - u32 rdata; - u32 radr[3]; - u32 wdata; - u32 prgdata[6]; - u32 shreg[10]; - u32 cfg[2]; - u32 shreg10; - u32 mode_mon; - u32 status[4]; - u32 flash_time; - u32 flash_cfg; - u32 reserved_0[3]; - u32 sf_time; - u32 pp_dw_data; - u32 reserved_1; - u32 delsel_0[2]; - u32 intrstus; - u32 intren; - u32 reserved_2; - u32 cfg3; - u32 reserved_3; - u32 chksum; - u32 aaicmd; - u32 wrprot; - u32 radr3; - u32 dual; - u32 delsel_1[3]; -}; - -struct mtk_qspi_platdata { - fdt_addr_t reg_base; - fdt_addr_t mem_base; -}; - -struct mtk_qspi_priv { - struct mtk_qspi_regs *regs; - unsigned long *mem_base; - u8 op; - u8 tx[3]; /* only record max 3 bytes paras, when it's address. */ - u32 txlen; /* dout buffer length - op code length */ - u8 *rx; - u32 rxlen; -}; - -#define MTK_QSPI_CMD_POLLINGREG_US 500000 -#define MTK_QSPI_WRBUF_SIZE 256 -#define MTK_QSPI_COMMAND_ENABLE 0x30 - -/* NOR flash controller commands */ -#define MTK_QSPI_RD_TRIGGER BIT(0) -#define MTK_QSPI_READSTATUS BIT(1) -#define MTK_QSPI_PRG_CMD BIT(2) -#define MTK_QSPI_WR_TRIGGER BIT(4) -#define MTK_QSPI_WRITESTATUS BIT(5) -#define MTK_QSPI_AUTOINC BIT(7) - -#define MTK_QSPI_MAX_RX_TX_SHIFT 0x6 -#define MTK_QSPI_MAX_SHIFT 0x8 - -#define MTK_QSPI_WR_BUF_ENABLE 0x1 -#define MTK_QSPI_WR_BUF_DISABLE 0x0 - -static int mtk_qspi_execute_cmd(struct mtk_qspi_priv *priv, u8 cmd) -{ - u8 tmp; - u8 val = cmd & ~MTK_QSPI_AUTOINC; - - writeb(cmd, &priv->regs->cmd); - - return readb_poll_timeout(&priv->regs->cmd, tmp, !(val & tmp), - MTK_QSPI_CMD_POLLINGREG_US); -} - -static int mtk_qspi_tx_rx(struct mtk_qspi_priv *priv) -{ - int len = 1 + priv->txlen + priv->rxlen; - int i, ret, idx; - - if (len > MTK_QSPI_MAX_SHIFT) - return -ERR_INVAL; - - writeb(len * 8, &priv->regs->cnt); - - /* start at PRGDATA5, go down to PRGDATA0 */ - idx = MTK_QSPI_MAX_RX_TX_SHIFT - 1; - - /* opcode */ - writeb(priv->op, &priv->regs->prgdata[idx]); - idx--; - - /* program TX data */ - for (i = 0; i < priv->txlen; i++, idx--) - writeb(priv->tx[i], &priv->regs->prgdata[idx]); - - /* clear out rest of TX registers */ - while (idx >= 0) { - writeb(0, &priv->regs->prgdata[idx]); - idx--; - } - - ret = mtk_qspi_execute_cmd(priv, MTK_QSPI_PRG_CMD); - if (ret) - return ret; - - /* restart at first RX byte */ - idx = priv->rxlen - 1; - - /* read out RX data */ - for (i = 0; i < priv->rxlen; i++, idx--) - priv->rx[i] = readb(&priv->regs->shreg[idx]); - - return 0; -} - -static int mtk_qspi_read(struct mtk_qspi_priv *priv, - u32 addr, u8 *buf, u32 len) -{ - memcpy(buf, (u8 *)priv->mem_base + addr, len); - return 0; -} - -static void mtk_qspi_set_addr(struct mtk_qspi_priv *priv, u32 addr) -{ - int i; - - for (i = 0; i < 3; i++) { - writeb(addr & 0xff, &priv->regs->radr[i]); - addr >>= 8; - } -} - -static int mtk_qspi_write_single_byte(struct mtk_qspi_priv *priv, - u32 addr, u32 length, const u8 *data) -{ - int i, ret; - - mtk_qspi_set_addr(priv, addr); - - for (i = 0; i < length; i++) { - writeb(*data++, &priv->regs->wdata); - ret = mtk_qspi_execute_cmd(priv, MTK_QSPI_WR_TRIGGER); - if (ret < 0) - return ret; - } - return 0; -} - -static int mtk_qspi_write_buffer(struct mtk_qspi_priv *priv, u32 addr, - const u8 *buf) -{ - int i, data; - - mtk_qspi_set_addr(priv, addr); - - for (i = 0; i < MTK_QSPI_WRBUF_SIZE; i += 4) { - data = buf[i + 3] << 24 | buf[i + 2] << 16 | - buf[i + 1] << 8 | buf[i]; - writel(data, &priv->regs->pp_dw_data); - } - - return mtk_qspi_execute_cmd(priv, MTK_QSPI_WR_TRIGGER); -} - -static int mtk_qspi_write(struct mtk_qspi_priv *priv, - u32 addr, const u8 *buf, u32 len) -{ - int ret; - - /* setting pre-fetch buffer for page program */ - writel(MTK_QSPI_WR_BUF_ENABLE, &priv->regs->cfg[1]); - while (len >= MTK_QSPI_WRBUF_SIZE) { - ret = mtk_qspi_write_buffer(priv, addr, buf); - if (ret < 0) - return ret; - - len -= MTK_QSPI_WRBUF_SIZE; - addr += MTK_QSPI_WRBUF_SIZE; - buf += MTK_QSPI_WRBUF_SIZE; - } - /* disable pre-fetch buffer for page program */ - writel(MTK_QSPI_WR_BUF_DISABLE, &priv->regs->cfg[1]); - - if (len) - return mtk_qspi_write_single_byte(priv, addr, len, buf); - - return 0; -} - -static int mtk_qspi_claim_bus(struct udevice *dev) -{ - /* nothing to do */ - return 0; -} - -static int mtk_qspi_release_bus(struct udevice *dev) -{ - /* nothing to do */ - return 0; -} - -static int mtk_qspi_transfer(struct mtk_qspi_priv *priv, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) -{ - u32 bytes = DIV_ROUND_UP(bitlen, 8); - u32 addr; - - if (!bytes) - return -ERR_INVAL; - - if (dout) { - if (flags & SPI_XFER_BEGIN) { - /* parse op code and potential paras first */ - priv->op = *(u8 *)dout; - if (bytes > 1) - memcpy(priv->tx, (u8 *)dout + 1, - bytes <= 4 ? bytes - 1 : 3); - priv->txlen = bytes - 1; - } - - if (flags == SPI_XFER_ONCE) { - /* operations without receiving or sending data. - * for example: erase, write flash register or write - * enable... - */ - priv->rx = NULL; - priv->rxlen = 0; - return mtk_qspi_tx_rx(priv); - } - - if (flags & SPI_XFER_END) { - /* here, dout should be data to be written. - * and priv->tx should be filled 3Bytes address. - */ - addr = priv->tx[0] << 16 | priv->tx[1] << 8 | - priv->tx[2]; - return mtk_qspi_write(priv, addr, (u8 *)dout, bytes); - } - } - - if (din) { - if (priv->txlen >= 3) { - /* if run to here, priv->tx[] should be the address - * where read data from, - * and, din is the buf to receive data. - */ - addr = priv->tx[0] << 16 | priv->tx[1] << 8 | - priv->tx[2]; - return mtk_qspi_read(priv, addr, (u8 *)din, bytes); - } - - /* should be reading flash's register */ - priv->rx = (u8 *)din; - priv->rxlen = bytes; - return mtk_qspi_tx_rx(priv); - } - - return 0; -} - -static int mtk_qspi_xfer(struct udevice *dev, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) -{ - struct udevice *bus = dev->parent; - struct mtk_qspi_priv *priv = dev_get_priv(bus); - - return mtk_qspi_transfer(priv, bitlen, dout, din, flags); -} - -static int mtk_qspi_set_speed(struct udevice *bus, uint speed) -{ - /* nothing to do */ - return 0; -} - -static int mtk_qspi_set_mode(struct udevice *bus, uint mode) -{ - /* nothing to do */ - return 0; -} - -static int mtk_qspi_ofdata_to_platdata(struct udevice *bus) -{ - struct resource res_reg, res_mem; - struct mtk_qspi_platdata *plat = bus->platdata; - int ret; - - ret = dev_read_resource_byname(bus, "reg_base", &res_reg); - if (ret) { - debug("can't get reg_base resource(ret = %d)\n", ret); - return -ENOMEM; - } - - ret = dev_read_resource_byname(bus, "mem_base", &res_mem); - if (ret) { - debug("can't get map_base resource(ret = %d)\n", ret); - return -ENOMEM; - } - - plat->mem_base = res_mem.start; - plat->reg_base = res_reg.start; - - return 0; -} - -static int mtk_qspi_probe(struct udevice *bus) -{ - struct mtk_qspi_platdata *plat = dev_get_platdata(bus); - struct mtk_qspi_priv *priv = dev_get_priv(bus); - - priv->regs = (struct mtk_qspi_regs *)plat->reg_base; - priv->mem_base = (unsigned long *)plat->mem_base; - - writel(MTK_QSPI_COMMAND_ENABLE, &priv->regs->wrprot); - - return 0; -} - -static const struct dm_spi_ops mtk_qspi_ops = { - .claim_bus = mtk_qspi_claim_bus, - .release_bus = mtk_qspi_release_bus, - .xfer = mtk_qspi_xfer, - .set_speed = mtk_qspi_set_speed, - .set_mode = mtk_qspi_set_mode, -}; - -static const struct udevice_id mtk_qspi_ids[] = { - { .compatible = "mediatek,mt7629-qspi" }, - { } -}; - -U_BOOT_DRIVER(mtk_qspi) = { - .name = "mtk_qspi", - .id = UCLASS_SPI, - .of_match = mtk_qspi_ids, - .ops = &mtk_qspi_ops, - .ofdata_to_platdata = mtk_qspi_ofdata_to_platdata, - .platdata_auto_alloc_size = sizeof(struct mtk_qspi_platdata), - .priv_auto_alloc_size = sizeof(struct mtk_qspi_priv), - .probe = mtk_qspi_probe, -}; -- 1.9.1

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[U-Boot] [PATCH 0/5] Add spi-mem driver for MediaTek MT7629 SoC
by Weijie Gao 26 Apr '19

26 Apr '19

Since u-boot has added the spi-mem framework and replaced the spi-nor framework, the mtk_qspi is no longer compatible with the new spi-nor driver. This patch series add a new spi-mem driver to replace the mtk_qspi driver. Weijie Gao (5): mtd: spi-nor: fix page program issue when using spi-mem driver spi: remove obsolete mtk_qspi driver spi: add spi-mem driver for MediaTek MT7629 SoC arm: dts: change MT7629 to use spi-mem rather than qspi MAINTAINERS: change spi driver entry MAINTAINERS | 2 +- arch/arm/dts/mt7629-rfb.dts | 18 ++- arch/arm/dts/mt7629.dtsi | 14 +- drivers/mtd/spi/spi-nor-core.c | 27 +--- drivers/spi/Kconfig | 15 +- drivers/spi/Makefile | 2 +- drivers/spi/mtk_qspi.c | 359 ----------------------------------------- drivers/spi/mtk_spimem.c | 325 +++++++++++++++++++++++++++++++++++++ 8 files changed, 366 insertions(+), 396 deletions(-) delete mode 100644 drivers/spi/mtk_qspi.c create mode 100644 drivers/spi/mtk_spimem.c -- 1.9.1

1 0

[U-Boot] [PATCH 1/2] watchdog: add sp805 watchdog support
by Qiang Zhao 26 Apr '19

26 Apr '19

sp805 is watchdog on some NXP layerscape SoCs, Now add its driver in uboot. Signed-off-by: Zhao Qiang <qiang.zhao(a)nxp.com> --- MAINTAINERS | 1 + common/board_f.c | 2 +- drivers/watchdog/Kconfig | 8 +++++ drivers/watchdog/Makefile | 1 + drivers/watchdog/sp805_wdt.c | 70 ++++++++++++++++++++++++++++++++++++ 5 files changed, 81 insertions(+), 1 deletion(-) create mode 100644 drivers/watchdog/sp805_wdt.c diff --git a/MAINTAINERS b/MAINTAINERS index 8f237128b2..e8e7a92802 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -410,6 +410,7 @@ FREESCALE QORIQ M: York Sun <york.sun(a)nxp.com> S: Maintained T: git git://git.denx.de/u-boot-fsl-qoriq.git +F: drivers/watchdog/sp805_wdt.c I2C M: Heiko Schocher <hs(a)denx.de> diff --git a/common/board_f.c b/common/board_f.c index 88d770071c..06bfff6e50 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -91,7 +91,7 @@ static int init_func_watchdog_init(void) (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \ defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG) || \ defined(CONFIG_DESIGNWARE_WATCHDOG) || \ - defined(CONFIG_IMX_WATCHDOG)) + defined(CONFIG_IMX_WATCHDOG) || defined(CONFIG_WDT_SP805)) hw_watchdog_init(); puts(" Watchdog enabled\n"); # endif diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index b06c5447f6..9ca8c729b7 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -95,6 +95,14 @@ config WDT_ORION Select this to enable Orion watchdog timer, which can be found on some Marvell Armada chips. +config WDT_SP805 + bool "SP805 watchdog timer support" + depends on FSL_LAYERSCAPE + select HW_WATCHDOG + help + Select this to enable SP805 watchdog timer, which can be found on some + nxp layerscape chips. + config WDT_CDNS bool "Cadence watchdog timer support" depends on WDT diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 19c631bb58..eb285bde24 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -25,3 +25,4 @@ obj-$(CONFIG_BCM2835_WDT) += bcm2835_wdt.o obj-$(CONFIG_WDT_ORION) += orion_wdt.o obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o obj-$(CONFIG_MPC8xx_WATCHDOG) += mpc8xx_wdt.o +obj-$(CONFIG_WDT_SP805) += sp805_wdt.o diff --git a/drivers/watchdog/sp805_wdt.c b/drivers/watchdog/sp805_wdt.c new file mode 100644 index 0000000000..64604a09e7 --- /dev/null +++ b/drivers/watchdog/sp805_wdt.c @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Watchdog driver for SP805 on some Layerscape SoC + * + * Copyright 2019 NXP + */ + +#include <asm/io.h> +#include <common.h> +#include <linux/bitops.h> +#include <watchdog.h> + +#define SP805_WDT_ADDR_BASE 0xc000000 +#define WDTLOAD 0x000 +#define WDTCONTROL 0x008 +#define WDTINTCLR 0x00C +#define WDTLOCK 0xC00 + +#define TIME_OUT_SECS 15 +#define SYS_FSL_WDT_CLK_DIV 16 +#define INT_ENABLE BIT(0) +#define RESET_ENABLE BIT(1) +#define UNLOCK 0x1ACCE551 +#define LOCK 0x00000001 +#define INT_MASK BIT(0) + +DECLARE_GLOBAL_DATA_PTR; + +void hw_watchdog_reset(void) +{ + writel(UNLOCK, SP805_WDT_ADDR_BASE + WDTLOCK); + writel(INT_MASK, SP805_WDT_ADDR_BASE + WDTINTCLR); + writel(LOCK, SP805_WDT_ADDR_BASE + WDTLOCK); + readl(SP805_WDT_ADDR_BASE + WDTLOCK); +} + +void hw_watchdog_init(void) +{ + u32 load_value; + /* sp805 runs counter with given value twice, so when the timeout is + * set 15s, the gd->bus_clk is less than 9162MHz, the load_value will + * not overflow. + */ + load_value = (TIME_OUT_SECS / 2) * (gd->bus_clk / SYS_FSL_WDT_CLK_DIV); + + writel(UNLOCK, SP805_WDT_ADDR_BASE + WDTLOCK); + writel(load_value, SP805_WDT_ADDR_BASE + WDTLOAD); + writel(INT_MASK, SP805_WDT_ADDR_BASE + WDTINTCLR); + writel(INT_ENABLE | RESET_ENABLE, SP805_WDT_ADDR_BASE + WDTCONTROL); + writel(LOCK, SP805_WDT_ADDR_BASE + WDTLOCK); + readl(SP805_WDT_ADDR_BASE + WDTLOCK); +} + +static int do_wdt_test(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + writel(UNLOCK, SP805_WDT_ADDR_BASE + WDTLOCK); + writel(INT_MASK, SP805_WDT_ADDR_BASE + WDTINTCLR); + writel(LOCK, SP805_WDT_ADDR_BASE + WDTLOCK); + readl(SP805_WDT_ADDR_BASE + WDTLOCK); + while (1) { + /* + * spin to test watchdog + */ + } + return 0; +} + +U_BOOT_CMD(wdt_test, 1, 1, do_wdt_test, "test watchdog", + "when run this command, the uboot will reset"); -- 2.17.1

3 4

[U-Boot] [PATCH] qspi: Add code to send only aligned data to TxFIFO
by Rajat Srivastava 26 Apr '19

26 Apr '19

Some Freescale QSPI controllers require driver to send only 16 bytes aligned data to TxFIFO while performing flash write operation. The extra data is not actually written on flash. The patch enables driver to send 16 bytes aligned data to TxFIFO, provided the config is enabled. The reason behind this behaviour of controller is still not clear and discussion with hardware team is ongoing. The patch will be updated before sending it to upstream. Signed-off-by: Rajat Srivastava <rajat.srivastava(a)nxp.com> --- drivers/spi/fsl_qspi.c | 29 ++++++++++++++++++++++------- 1 file changed, 22 insertions(+), 7 deletions(-) diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 1d26c6344b..b93e89ff32 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -676,20 +676,35 @@ static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len) tx_size = (len > TX_BUFFER_SIZE) ? TX_BUFFER_SIZE : len; - size = tx_size / 16; + size = tx_size / 4; + for (i = 0; i < size; i++) { + memcpy(&data, txbuf, 4); + data = qspi_endian_xchg(data); + qspi_write32(priv->flags, &regs->tbdr, data); + txbuf += 4; + } +#if defined(CONFIG_FSL_SPI_ALIGNED_TXFIFO) /* - * There must be atleast 128bit data - * available in TX FIFO for any pop operation + * There must be at least 16 bytes of data + * available in TX FIFO for any POP operation */ - if (tx_size % 16) - size++; - for (i = 0; i < size * 4; i++) { + size = (((tx_size/16) + 1) * 4) - size; + for (i = 0; i < size; i++) { + data = 0; memcpy(&data, txbuf, 4); data = qspi_endian_xchg(data); qspi_write32(priv->flags, &regs->tbdr, data); txbuf += 4; } - +#else + size = tx_size % 4; + if (size) { + data = 0; + memcpy(&data, txbuf, size); + data = qspi_endian_xchg(data); + qspi_write32(priv->flags, &regs->tbdr, data); + } +#endif qspi_write32(priv->flags, &regs->ipcr, (seqid << QSPI_IPCR_SEQID_SHIFT) | tx_size); while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK) -- 2.17.1

2 1

[U-Boot] [PATCH 00/40] x86: Add support for booting from TPL
by Simon Glass 26 Apr '19

26 Apr '19

At present SPL is used on 64-bit platforms, to allow SPL to be built as a 32-bit program and U-Boot proper to be built as 64-bit. However it is useful to be able to use SPL on any x86 platform, where U-Boot needs to be updated in the field. Then SPL can select which U-Boot to run (A or B) and most of the code can be updated. Similarly, using TPL allows both SPL and U-Boot to be updated. This is the best approach, since it means that all of U-Boot proper as well as SPL (in particular SDRAM init) can be updated in the field. This provides for the smallest possible amount of read-only (non-updateable) code: just the TPL code. This series contains a number of changes to allow x86 boards to use TPL, SPL and U-Boot proper. As a test, it is enabled for samus with a new chromebook_samus_tpl board. Simon Glass (40): binman: Don't generate an error in 'text' entry constructor binman: Don't show image-skip message by default binman: Add a missing comment in Entry_vblock dm: core: Fix translate condition in ofnode_get_addr_size() cros_ec: Use a hyphen in the uclass name spl: Allow sandbox to build a device-tree file RFC: binman: Allow sections to have an offset x86: start64: Fix copyright message x86: mp_init: Use proper error numbers x86: Add a way to reinit the cpu x86: dts: Add device-tree labels for rtc and reset x86: Update a stale comment about ifdtool x86: Support SPL and TPL x86: Support booting with TPL x86: Add a handoff header file x86: broadwell: Improve SDRAM debugging output x86: broadwell: Allow SDRAM init from SPL x86: Move init of debug UART to cpu.c x86: broadwell: Split CPU init x86: Add support for starting from SPL/TPL x86: Allow 16-bit init to be in TPL x86: broadwell: Allow booting from SPL x86: broadwell: Select refcode and CPU code for SPL x86: Add common Intel code for SPL x86: Support saving MRC data from SPL x86: Add a simple TPL implementations x86: mrccache: Add more debugging x86: Add a sysreset driver for the Intel PCH x86: Support TPL in Intel common code x86: Don't set up MTRRs in SPL x86: Don't generate a bootstage report in SPL x86: Support PCI VGA ROM when TPL is used x86: sysreset: Implement the get_last() method x86: Add documention on the samus flashmap x86: samus: Update device tree for SPL x86: samus: Update device tree for verified boot x86: Update device tree for TPL x86: Update device tree for Chromium OS verified boot x86: Fix device-tree indentation x86: samus: Add a target to boot through TPL Makefile | 1 + arch/Kconfig | 30 + arch/x86/Kconfig | 10 +- arch/x86/Makefile | 16 +- arch/x86/cpu/Makefile | 15 +- arch/x86/cpu/broadwell/Kconfig | 1 + arch/x86/cpu/broadwell/Makefile | 23 +- arch/x86/cpu/broadwell/cpu.c | 676 +-------------------- arch/x86/cpu/broadwell/cpu_from_spl.c | 63 ++ arch/x86/cpu/broadwell/cpu_full.c | 694 ++++++++++++++++++++++ arch/x86/cpu/broadwell/northbridge.c | 93 +++ arch/x86/cpu/broadwell/sdram.c | 136 +---- arch/x86/cpu/i386/cpu.c | 113 ++-- arch/x86/cpu/intel_common/Makefile | 17 +- arch/x86/cpu/intel_common/car.S | 2 +- arch/x86/cpu/intel_common/cpu_from_spl.c | 27 + arch/x86/cpu/mp_init.c | 10 +- arch/x86/cpu/start64.S | 2 +- arch/x86/cpu/start_from_spl.S | 71 +++ arch/x86/cpu/start_from_tpl.S | 50 ++ arch/x86/cpu/u-boot-spl.lds | 2 +- arch/x86/cpu/x86_64/cpu.c | 5 + arch/x86/dts/chromebook_samus.dts | 60 +- arch/x86/dts/reset.dtsi | 2 +- arch/x86/dts/rtc.dtsi | 2 +- arch/x86/dts/u-boot.dtsi | 154 +++-- arch/x86/include/asm/handoff.h | 15 + arch/x86/include/asm/mrccache.h | 11 + arch/x86/include/asm/spl.h | 17 +- arch/x86/include/asm/u-boot-x86.h | 20 + arch/x86/lib/Makefile | 9 +- arch/x86/lib/bootm.c | 2 +- arch/x86/lib/init_helpers.c | 5 +- arch/x86/lib/mrccache.c | 52 +- arch/x86/lib/spl.c | 44 +- arch/x86/lib/tpl.c | 118 ++++ board/google/Kconfig | 8 + board/google/chromebook_samus/Kconfig | 14 +- board/google/chromebook_samus/MAINTAINERS | 7 + configs/chromebook_samus_tpl_defconfig | 80 +++ doc/README.x86 | 14 + drivers/core/ofnode.c | 2 +- drivers/misc/cros_ec.c | 2 +- drivers/pci/pci_rom.c | 2 +- drivers/sysreset/Kconfig | 9 + drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_intel_pch.c | 125 ++++ drivers/sysreset/sysreset_x86.c | 6 + include/configs/chromebook_link.h | 3 - include/configs/chromebook_samus.h | 3 + include/configs/qemu-x86.h | 3 - scripts/Makefile.spl | 24 +- tools/binman/bsection.py | 5 +- tools/binman/control.py | 4 +- tools/binman/etype/section.py | 3 +- tools/binman/etype/text.py | 4 +- tools/binman/etype/vblock.py | 1 + 57 files changed, 1933 insertions(+), 955 deletions(-) create mode 100644 arch/x86/cpu/broadwell/cpu_from_spl.c create mode 100644 arch/x86/cpu/broadwell/cpu_full.c create mode 100644 arch/x86/cpu/intel_common/cpu_from_spl.c create mode 100644 arch/x86/cpu/start_from_spl.S create mode 100644 arch/x86/cpu/start_from_tpl.S create mode 100644 arch/x86/include/asm/handoff.h create mode 100644 arch/x86/lib/tpl.c create mode 100644 configs/chromebook_samus_tpl_defconfig create mode 100644 drivers/sysreset/sysreset_intel_pch.c -- 2.20.1.495.gaa96b0ce6b-goog

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[U-Boot] [PATCH] arm: dts: k3-am654: Sync IOPAD macros with Linux
by Andreas Dannenberg 26 Apr '19

26 Apr '19

Transition to the IOPAD macros as used in Linux in which the pin mux mode is specified using a dedicated parameter while also dropping the related MUX_MODEx macros that are no longer needed. This transition will allow us to keep both Linux and U-Boot DTS in sync more easily. Signed-off-by: Andreas Dannenberg <dannenberg(a)ti.com> --- arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 46 ++++++++++---------- arch/arm/dts/k3-am654-r5-base-board.dts | 10 ++--- include/dt-bindings/pinctrl/k3-am65.h | 15 +------ 3 files changed, 30 insertions(+), 41 deletions(-) diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi index c5d23d0203..dc8b05c263 100644 --- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi @@ -144,41 +144,41 @@ u-boot,dm-spl; main_uart0_pins_default: main_uart0_pins_default { pinctrl-single,pins = < - AM65X_IOPAD(0x01e4, PIN_INPUT | MUX_MODE0) /* (AF11) UART0_RXD */ - AM65X_IOPAD(0x01e8, PIN_OUTPUT | MUX_MODE0) /* (AE11) UART0_TXD */ - AM65X_IOPAD(0x01ec, PIN_INPUT | MUX_MODE0) /* (AG11) UART0_CTSn */ - AM65X_IOPAD(0x01f0, PIN_OUTPUT | MUX_MODE0) /* (AD11) UART0_RTSn */ + AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */ + AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */ + AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */ + AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */ >; u-boot,dm-spl; }; main_mmc0_pins_default: main_mmc0_pins_default { pinctrl-single,pins = < - AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (B25) MMC0_CLK */ - AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP | MUX_MODE0) /* (B27) MMC0_CMD */ - AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP | MUX_MODE0) /* (A26) MMC0_DAT0 */ - AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP | MUX_MODE0) /* (E25) MMC0_DAT1 */ - AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP | MUX_MODE0) /* (C26) MMC0_DAT2 */ - AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP | MUX_MODE0) /* (A25) MMC0_DAT3 */ - AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP | MUX_MODE0) /* (E24) MMC0_DAT4 */ - AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP | MUX_MODE0) /* (A24) MMC0_DAT5 */ - AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP | MUX_MODE0) /* (B26) MMC0_DAT6 */ - AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP | MUX_MODE0) /* (D25) MMC0_DAT7 */ - AM65X_IOPAD(0x01b0, PIN_INPUT | MUX_MODE0) /* (C25) MMC0_DS */ + AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */ + AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */ + AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */ + AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */ + AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */ + AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */ + AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */ + AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */ + AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */ + AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */ + AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */ >; u-boot,dm-spl; }; main_mmc1_pins_default: main_mmc1_pins_default { pinctrl-single,pins = < - AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (C27) MMC1_CLK */ - AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP | MUX_MODE0) /* (C28) MMC1_CMD */ - AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP | MUX_MODE0) /* (D28) MMC1_DAT0 */ - AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP | MUX_MODE0) /* (E27) MMC1_DAT1 */ - AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP | MUX_MODE0) /* (D26) MMC1_DAT2 */ - AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP | MUX_MODE0) /* (D27) MMC1_DAT3 */ - AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP | MUX_MODE0) /* (B24) MMC1_SDCD */ - AM65X_IOPAD(0x02e0, PIN_INPUT | MUX_MODE0) /* (C24) MMC1_SDWP */ + AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */ + AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */ + AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */ + AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */ + AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */ + AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */ + AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */ + AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */ >; u-boot,dm-spl; }; diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts index 72039ac870..a07038be70 100644 --- a/arch/arm/dts/k3-am654-r5-base-board.dts +++ b/arch/arm/dts/k3-am654-r5-base-board.dts @@ -116,17 +116,17 @@ u-boot,dm-spl; wkup_uart0_pins_default: wkup_uart0_pins_default { pinctrl-single,pins = < - AM65X_WKUP_IOPAD(0x00a0, PIN_INPUT | MUX_MODE0) /* (AB1) WKUP_UART0_RXD */ - AM65X_WKUP_IOPAD(0x00a4, PIN_OUTPUT | MUX_MODE0) /* (AB5) WKUP_UART0_TXD */ - AM65X_WKUP_IOPAD(0x00c8, PIN_INPUT | MUX_MODE1) /* (AC2) WKUP_GPIO0_6.WKUP_UART0_CTSn */ - AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT | MUX_MODE1) /* (AC1) WKUP_GPIO0_7.WKUP_UART0_RTSn */ + AM65X_WKUP_IOPAD(0x00a0, PIN_INPUT, 0) /* (AB1) WKUP_UART0_RXD */ + AM65X_WKUP_IOPAD(0x00a4, PIN_OUTPUT, 0) /* (AB5) WKUP_UART0_TXD */ + AM65X_WKUP_IOPAD(0x00c8, PIN_INPUT, 1) /* (AC2) WKUP_GPIO0_6.WKUP_UART0_CTSn */ + AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 1) /* (AC1) WKUP_GPIO0_7.WKUP_UART0_RTSn */ >; u-boot,dm-spl; }; wkup_vtt_pins_default: wkup_vtt_pins_default { pinctrl-single,pins = < - AM65X_WKUP_IOPAD(0x0040, PIN_OUTPUT_PULLUP | MUX_MODE7) /* WKUP_GPIO0_28 */ + AM65X_WKUP_IOPAD(0x0040, PIN_OUTPUT_PULLUP, 7) /* WKUP_GPIO0_28 */ >; u-boot,dm-spl; }; diff --git a/include/dt-bindings/pinctrl/k3-am65.h b/include/dt-bindings/pinctrl/k3-am65.h index c86c9fd4ce..a67521cdc4 100644 --- a/include/dt-bindings/pinctrl/k3-am65.h +++ b/include/dt-bindings/pinctrl/k3-am65.h @@ -7,17 +7,6 @@ #ifndef _DT_BINDINGS_PINCTRL_TI_K3_AM65_H #define _DT_BINDINGS_PINCTRL_TI_K3_AM65_H -/* K3 mux mode options for each pin. See TRM for options */ -#define MUX_MODE0 0 -#define MUX_MODE1 1 -#define MUX_MODE2 2 -#define MUX_MODE3 3 -#define MUX_MODE4 4 -#define MUX_MODE5 5 -#define MUX_MODE6 6 -#define MUX_MODE7 7 -#define MUX_MODE15 15 - #define PULL_DISABLE (1 << 16) #define PULL_UP (1 << 17) #define INPUT_EN (1 << 18) @@ -43,7 +32,7 @@ #define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) #define PIN_INPUT_PULLDOWN (INPUT_EN) -#define AM65X_IOPAD(pa, val) (((pa) & 0x1fff)) (val) -#define AM65X_WKUP_IOPAD(pa, val) (((pa) & 0x1fff)) (val) +#define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #endif -- 2.17.1

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[U-Boot] [PATCH V2] imx8: cpu: get temperature when print cpu desc
by Peng Fan 26 Apr '19

26 Apr '19

Read the temperature when print cpu inforation. Signed-off-by: Peng Fan <peng.fan(a)nxp.com> --- V2: Fix build warning when CONFIG_IMX_SCU_THERMAL not defined. Hi Stefano, I not post the whole series, not posted out this specific patch, the v1 patch https://patchwork.ozlabs.org/patch/1084464/ or do you expect the repost the whole series? arch/arm/mach-imx/imx8/cpu.c | 40 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 4bbc956f9d..1ee7ea649d 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -11,6 +11,7 @@ #include <dm/lists.h> #include <dm/uclass.h> #include <errno.h> +#include <thermal.h> #include <asm/arch/sci/sci.h> #include <asm/arch/sys_proto.h> #include <asm/arch-imx/cpu.h> @@ -571,15 +572,50 @@ const char *get_core_name(void) return "?"; } +#if IS_ENABLED(CONFIG_IMX_SCU_THERMAL) +static int cpu_imx_get_temp(void) +{ + struct udevice *thermal_dev; + int cpu_tmp, ret; + + ret = uclass_get_device_by_name(UCLASS_THERMAL, "cpu-thermal0", + &thermal_dev); + + if (!ret) { + ret = thermal_get_temp(thermal_dev, &cpu_tmp); + if (ret) + return 0xdeadbeef; + } else { + return 0xdeadbeef; + } + + return cpu_tmp; +} +#else +static int cpu_imx_get_temp(void) +{ + return 0; +} +#endif + int cpu_imx_get_desc(struct udevice *dev, char *buf, int size) { struct cpu_imx_platdata *plat = dev_get_platdata(dev); + int ret; if (size < 100) return -ENOSPC; - snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz\n", - plat->type, plat->rev, plat->name, plat->freq_mhz); + ret = snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz", + plat->type, plat->rev, plat->name, plat->freq_mhz); + + if (IS_ENABLED(CONFIG_IMX_SCU_THERMAL)) { + buf = buf + ret; + size = size - ret; + ret = snprintf(buf, size, " at %dC", cpu_imx_get_temp()); + } + + snprintf(buf + ret, size - ret, "\n"); return 0; } -- 2.16.4

1 0

[U-Boot] [PATCH v2 0/4] Add Cadence PCIe endpoint driver with new uclass
by Ramon Fried 26 Apr '19

26 Apr '19

This patchset adds support for new uclass, UCLASS_PCI_EP allowing new set of PCI endpoint drivers. Included in the patch is also a driver for Cadence PCIe endpoint. Changes in V2: - Removed "pci.h: add missing maskbit" as it was already merged by Simon. - Added PCI endpoint sandbox driver - Added testing for sandbox driver - Addressed issues raised by Simon in UCLASS_PCI_EP class implementation Ramon Fried (4): drivers: pci_ep: Introduce UCLASS_PCI_EP uclass pci_ep: add Cadence PCIe endpoint driver pci_ep: add pci_ep sandbox driver test: pci_ep: add basic pci_ep tests arch/sandbox/dts/test.dts | 4 + configs/sandbox64_defconfig | 2 + configs/sandbox_defconfig | 2 + .../pci_endpoint/cdns,cdns-pcie-ep.txt | 18 + drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/pci_endpoint/Kconfig | 32 ++ drivers/pci_endpoint/Makefile | 8 + drivers/pci_endpoint/pci_ep-uclass.c | 189 +++++++++ drivers/pci_endpoint/pcie-cadence-ep.c | 177 ++++++++ drivers/pci_endpoint/pcie-cadence.h | 309 ++++++++++++++ drivers/pci_endpoint/sandbox-pci_ep.c | 176 ++++++++ include/dm/uclass-id.h | 1 + include/pci_ep.h | 388 ++++++++++++++++++ test/dm/Makefile | 1 + test/dm/pci_ep.c | 45 ++ 16 files changed, 1355 insertions(+) create mode 100644 doc/device-tree-bindings/pci_endpoint/cdns,cdns-pcie-ep.txt create mode 100644 drivers/pci_endpoint/Kconfig create mode 100644 drivers/pci_endpoint/Makefile create mode 100644 drivers/pci_endpoint/pci_ep-uclass.c create mode 100644 drivers/pci_endpoint/pcie-cadence-ep.c create mode 100644 drivers/pci_endpoint/pcie-cadence.h create mode 100644 drivers/pci_endpoint/sandbox-pci_ep.c create mode 100644 include/pci_ep.h create mode 100644 test/dm/pci_ep.c -- 2.21.0

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