April 2019 - U-Boot

[U-Boot] [PATCH] warp7: Fix dfu_alt_info setting after DM conversion
by Pierre-Jean Texier 26 Apr '19

26 Apr '19

After DM conversion, U-Boot is larger than 512 KiB, so we need to increase the "size" of the dfu_alt_info setting. Signed-off-by: Pierre-Jean Texier <pjtexier(a)koncepto.io> --- include/configs/warp7.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/warp7.h b/include/configs/warp7.h index 043f286..4947597 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -39,7 +39,7 @@ #define CONFIG_SERIAL_TAG #define CONFIG_DFU_ENV_SETTINGS \ - "dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \ + "dfu_alt_info=boot raw 0x2 0x1000 mmcpart 1\0" \ #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_DFU_ENV_SETTINGS \ -- 2.7.4

4 3

[U-Boot] [PATCH v1] colibri_vf: fix tab vs. spaces
by Marcel Ziswiler 26 Apr '19

26 Apr '19

From: Marcel Ziswiler <marcel.ziswiler(a)toradex.com> Fix indentation using tab vs. spaces. Signed-off-by: Marcel Ziswiler <marcel.ziswiler(a)toradex.com> --- board/toradex/colibri_vf/MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/toradex/colibri_vf/MAINTAINERS b/board/toradex/colibri_vf/MAINTAINERS index 3ee2b33152..66b2150986 100644 --- a/board/toradex/colibri_vf/MAINTAINERS +++ b/board/toradex/colibri_vf/MAINTAINERS @@ -1,7 +1,7 @@ Colibri VFxx M: Stefan Agner <stefan.agner(a)toradex.com> W: http://developer.toradex.com/software/linux/linux-software -W: https://www.toradex.com/community +W: https://www.toradex.com/community S: Maintained F: board/toradex/colibri_vf/ F: include/configs/colibri_vf.h -- 2.20.1

3 2

[U-Boot] [PATCH v3] ARM: dts: i.MX6Q: fix avoid_unnecessary_addr_size warnings
by Marcel Ziswiler 26 Apr '19

26 Apr '19

From: Marcel Ziswiler <marcel.ziswiler(a)toradex.com> Re-synced the device tree with Linux 5.0. This fixes the following warnings: w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu@2800000/ port@2/endpoint@0:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu@2800000/ port@2/endpoint@1:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu@2800000/ port@2/endpoint@2:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu@2800000/ port@2/endpoint@3:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu@2800000/ port@2/endpoint@4:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu@2800000/ port@3/endpoint@1:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu@2800000/ port@3/endpoint@2:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu@2800000/ port@3/endpoint@3:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) w+arch/arm/dts/imx6-apalis.dtb: Warning (reg_format): /soc/ipu@2800000/ port@3/endpoint@4:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size): /soc/ipu@2800000/port@2/endpoint@0: Relying on default #address-cells value w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size): /soc/ipu@2800000/port@2/endpoint@0: Relying on default #size-cells value w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size): /soc/ipu@2800000/port@2/endpoint@1: Relying on default #address-cells value w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size): /soc/ipu@2800000/port@2/endpoint@1: Relying on default #size-cells value w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size): /soc/ipu@2800000/port@2/endpoint@2: Relying on default #address-cells value w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size): /soc/ipu@2800000/port@2/endpoint@2: Relying on default #size-cells value w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size): /soc/ipu@2800000/port@2/endpoint@3: Relying on default #address-cells value w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size): /soc/ipu@2800000/port@2/endpoint@3: Relying on default #size-cells value w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size): /soc/ipu@2800000/port@2/endpoint@4: Relying on default #address-cells value w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size): /soc/ipu@2800000/port@2/endpoint@4: Relying on default #size-cells value w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size): /soc/ipu@2800000/port@3/endpoint@1: Relying on default #address-cells value w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size): /soc/ipu@2800000/port@3/endpoint@1: Relying on default #size-cells value w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size): /soc/ipu@2800000/port@3/endpoint@2: Relying on default #address-cells value w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size): /soc/ipu@2800000/port@3/endpoint@2: Relying on default #size-cells value w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size): /soc/ipu@2800000/port@3/endpoint@3: Relying on default #address-cells value w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size): /soc/ipu@2800000/port@3/endpoint@3: Relying on default #size-cells value w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size): /soc/ipu@2800000/port@3/endpoint@4: Relying on default #address-cells value w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_default_addr_size): /soc/ipu@2800000/port@3/endpoint@4: Relying on default #size-cells value w+arch/arm/dts/imx6-apalis.dtb: Warning (avoid_unnecessary_addr_size): Failed prerequisite 'avoid_default_addr_size' Signed-off-by: Marcel Ziswiler <marcel.ziswiler(a)toradex.com> Reviewed-by: Fabio Estevam <festevam(a)gmail.com> Reviewed-by: Lukasz Majewski <lukma(a)denx.de> --- Changes in v3: - Added Fabio and Lukasz' reviewed-by tags. Changes in v2: - Re-synced the device tree with Linux 5.0 as suggested by Fabio. arch/arm/dts/imx6q.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/dts/imx6q.dtsi b/arch/arm/dts/imx6q.dtsi index ab1716b6b0..d038f41170 100644 --- a/arch/arm/dts/imx6q.dtsi +++ b/arch/arm/dts/imx6q.dtsi @@ -202,6 +202,7 @@ <&clks IMX6QDL_CLK_GPU2D_CORE>; clock-names = "bus", "core"; power-domains = <&pd_pu>; + #cooling-cells = <2>; }; ipu2: ipu@2800000 { @@ -234,6 +235,8 @@ }; ipu2_di0: port@2 { + #address-cells = <1>; + #size-cells = <0>; reg = <2>; ipu2_di0_disp0: endpoint@0 { @@ -262,6 +265,8 @@ }; ipu2_di1: port@3 { + #address-cells = <1>; + #size-cells = <0>; reg = <3>; ipu2_di1_hdmi: endpoint@1 { -- 2.20.1

2 1

[U-Boot] [PATCH] ARM: imx6q_logic: Allow optional arguments to cmd line
by Adam Ford 26 Apr '19

26 Apr '19

This adds an extra, optional environmental variable called 'optargs' which if enabled allow additional parameters to be passed to the kernel (ie, quiet, cma=128M, etc.) Each script that setups the bootargs will just append this. Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index ad45b106b0..dbf566522f 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -46,11 +46,11 @@ "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ "nandroot=ubi0:rootfs rootfstype=ubifs\0" \ "mmcargs=setenv bootargs console=${console},${baudrate}" \ - " root=PARTUUID=${uuid} rootwait rw\0 ${mtdparts}\0" \ + " root=PARTUUID=${uuid} rootwait rw ${mtdparts} ${optargs}\0" \ "nandargs=setenv bootargs console=${console},${baudrate}" \ - " ubi.mtd=fs root=${nandroot} ${mtdparts}\0" \ + " ubi.mtd=fs root=${nandroot} ${mtdparts} ${optargs}\0" \ "ramargs=setenv bootargs console=${console},${baudrate}" \ - " root=/dev/ram rw ${mtdparts}\0" \ + " root=/dev/ram rw ${mtdparts} ${optargs}\0" \ "loadbootscript=" \ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...;" \ -- 2.17.1

2 1

[U-Boot] [PATCH] dts: imx6ull: add USB aliases to support DM
by Filip Brozovic 26 Apr '19

26 Apr '19

Signed-off-by: Filip Brozovic <fbrozovic(a)gmail.com> --- arch/arm/dts/imx6ull.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/dts/imx6ull.dtsi b/arch/arm/dts/imx6ull.dtsi index 97236d86ea..4598f2f411 100644 --- a/arch/arm/dts/imx6ull.dtsi +++ b/arch/arm/dts/imx6ull.dtsi @@ -46,6 +46,8 @@ spi4 = &ecspi4; usbphy0 = &usbphy1; usbphy1 = &usbphy2; + usb0 = &usbotg1; + usb1 = &usbotg2; }; cpus { -- 2.20.1

2 1

[U-Boot] [PATCH v2 1/2] ARM: imx6: DHCOM i.MX6 PDK: use Kconfig for inclusion of DDR calibration
by Ludwig Zenz 26 Apr '19

26 Apr '19

From: Ludwig Zenz <lzenz(a)dh-electronics.de> The four x16 DDR3 are wired in T-topology. From NXP AN4467: 'Although not required, T-Topologies may also benefit from performing Write Leveling as there are package delays on both the processor and DDR devices that can be de-skewed by performing Write Leveling. Therefore, Freescale recommends determining Write Leveling calibration parameters for all boards, regardless of topology used.' That is why write level calibration is also done. Signed-off-by: Ludwig Zenz <lzenz(a)dh-electronics.com> --- board/dhelectronics/dh_imx6/dh_imx6_spl.c | 32 +++++++++++++++++++++++++------ 1 file changed, 26 insertions(+), 6 deletions(-) diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c index 04e9eab272a..bbd2dc26828 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c +++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c @@ -482,6 +482,29 @@ static void setup_iomux_usb(void) SETUP_IOMUX_PADS(usb_pads); } +/* Perform DDR DRAM calibration */ +static int spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo) +{ + int ret = 0; + +#ifdef CONFIG_MX6_DDRCAL + udelay(100); + ret = mmdc_do_write_level_calibration(sysinfo); + if (ret) { + printf("DDR3: Write level calibration error [%d]\n", ret); + return ret; + } + + ret = mmdc_do_dqs_calibration(sysinfo); + if (ret) { + printf("DDR3: DQS calibration error [%d]\n", ret); + return ret; + } +#endif /* CONFIG_MX6_DDRCAL */ + + return ret; +} + /* DRAM */ static void dhcom_spl_dram_init(void) @@ -509,8 +532,7 @@ static void dhcom_spl_dram_init(void) } /* Perform DDR DRAM calibration */ - udelay(100); - mmdc_do_dqs_calibration(&dhcom_ddr_64bit); + spl_dram_perform_cal(&dhcom_ddr_64bit); } else if (is_cpu_type(MXC_CPU_MX6DL)) { mx6sdl_dram_iocfg(64, &dhcom6sdl_ddr_ioregs, @@ -528,8 +550,7 @@ static void dhcom_spl_dram_init(void) } /* Perform DDR DRAM calibration */ - udelay(100); - mmdc_do_dqs_calibration(&dhcom_ddr_64bit); + spl_dram_perform_cal(&dhcom_ddr_64bit); } else if (is_cpu_type(MXC_CPU_MX6SOLO)) { mx6sdl_dram_iocfg(32, &dhcom6sdl_ddr_ioregs, @@ -552,8 +573,7 @@ static void dhcom_spl_dram_init(void) } /* Perform DDR DRAM calibration */ - udelay(100); - mmdc_do_dqs_calibration(&dhcom_ddr_32bit); + spl_dram_perform_cal(&dhcom_ddr_32bit); } } -- 2.11.0

2 1

[U-Boot] [PATCH] ARM: imx: Fix typo in select option for ZMX25
by Chris Packham 26 Apr '19

26 Apr '19

Correct CPU_ARM926EJS1 to CPU_ARM926EJS. Reported-by: Robert P. J. Day <rpjday(a)crashcourse.ca> Signed-off-by: Chris Packham <judge.packham(a)gmail.com> --- arch/arm/mach-imx/mx2/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/mx2/Kconfig b/arch/arm/mach-imx/mx2/Kconfig index ea308fccab02..30a331ae43b7 100644 --- a/arch/arm/mach-imx/mx2/Kconfig +++ b/arch/arm/mach-imx/mx2/Kconfig @@ -17,7 +17,7 @@ config TARGET_MX25PDK config TARGET_ZMX25 bool "Support zmx25" select BOARD_LATE_INIT - select CPU_ARM926EJS1 + select CPU_ARM926EJS endchoice -- 2.21.0

4 3

[U-Boot] [PATCH v2 2/2] ARM: imx6: update 1GB DDR3 calibration for DHCOM i.MX6qd PDK
by Ludwig Zenz 26 Apr '19

26 Apr '19

The existing calibration values were found to be incorrect in comparison to newly determined values. The new values were generated with the help of 5 boards. They have been determined with the NXP Utility 'DDR Stress Test (2.9.0)'. Signed-off-by: Ludwig Zenz <lzenz(a)dh-electronics.com> --- board/dhelectronics/dh_imx6/dh_imx6_spl.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c index bbd2dc26828..2939389de39 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c +++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c @@ -161,18 +161,18 @@ static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x4g_800 = { }; static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_1066 = { - .p0_mpwldectrl0 = 0x0011000E, - .p0_mpwldectrl1 = 0x000E001B, - .p1_mpwldectrl0 = 0x00190015, - .p1_mpwldectrl1 = 0x00070018, - .p0_mpdgctrl0 = 0x42720306, - .p0_mpdgctrl1 = 0x026F0266, - .p1_mpdgctrl0 = 0x4273030A, - .p1_mpdgctrl1 = 0x02740240, - .p0_mprddlctl = 0x45393B3E, - .p1_mprddlctl = 0x403A3747, - .p0_mpwrdlctl = 0x40434541, - .p1_mpwrdlctl = 0x473E4A3B, + .p0_mpwldectrl0 = 0x001a001a, + .p0_mpwldectrl1 = 0x00260015, + .p0_mpdgctrl0 = 0x030c0320, + .p0_mpdgctrl1 = 0x03100304, + .p0_mprddlctl = 0x432e3538, + .p0_mpwrdlctl = 0x363f423d, + .p1_mpwldectrl0 = 0x0006001e, + .p1_mpwldectrl1 = 0x00050015, + .p1_mpdgctrl0 = 0x031c0324, + .p1_mpdgctrl1 = 0x030c0258, + .p1_mprddlctl = 0x3834313f, + .p1_mpwrdlctl = 0x47374a42, }; static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_800 = { -- 2.11.0

2 1

[U-Boot] [PATCH] riscv: qemu: Use correct SYS_TEXT_BASE for S-mode on 32bit system
by Anup Patel 26 Apr '19

26 Apr '19

For 32bit system, the OpenSBI (or BBL) will jump to 0x80400000 address in S-mode whereas for 64bit system it will jump to 0x80200000 address in S-mode. Currently, the S-mode U-Boot sets SYS_TEXT_BASE to 0x80200000 for both 32bit and 64bit system. This breaks S-mode U-Boot for 32bit system. This patch sets different SYS_TEXT_BASE for 32bit and 64bit system so that S-mode U-Boot works fine for both. Signed-off-by: Anup Patel <anup.patel(a)wdc.com> --- board/emulation/qemu-riscv/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index cf057e7de6..20ea6dc59b 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -14,7 +14,8 @@ config SYS_CONFIG_NAME config SYS_TEXT_BASE default 0x80000000 if !RISCV_SMODE - default 0x80200000 if RISCV_SMODE + default 0x80200000 if RISCV_SMODE && ARCH_RV64I + default 0x80400000 if RISCV_SMODE && ARCH_RV32I config BOARD_SPECIFIC_OPTIONS # dummy def_bool y -- 2.17.1

4 3

[U-Boot] [PATCH] MMC HW partition switching must also invalidate the cache
by Peng Fan 26 Apr '19

26 Apr '19

Hi Jan, > Subject: [EXT] [U-Boot] [PATCH] MMC HW partition switching must also > invalidate the cache > Please add a bit more commit information about why and how. Thanks, Peng. > > Signed-off-by: Jan Šedivý <jans(a)zhinst.com> > --- > > drivers/mmc/mmc.c | 14 ++++++++++++-- > 1 file changed, 12 insertions(+), 2 deletions(-) > > diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index > 456c1b4..3d9a68e 100644 > --- a/drivers/mmc/mmc.c > +++ b/drivers/mmc/mmc.c > @@ -954,8 +954,13 @@ int mmc_switch_part(struct mmc *mmc, unsigned > int part_num) > * to return to representing the raw device. > */ > if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) { > + struct blk_desc *desc = mmc_get_blk_desc(mmc); > + > ret = mmc_set_capacity(mmc, part_num); > - mmc_get_blk_desc(mmc)->hwpart = part_num; > + if (desc && desc->hwpart != part_num) { > + desc->hwpart = part_num; > + blkcache_invalidate(desc->if_type, > desc->devnum); > + } > } > > return ret; > @@ -2673,7 +2678,12 @@ retry: > return err; > > /* The internal partition reset to user partition(0) at every CMD0*/ > - mmc_get_blk_desc(mmc)->hwpart = 0; > + struct blk_desc *desc = mmc_get_blk_desc(mmc); > + > + if (desc && desc->hwpart != 0) { > + desc->hwpart = 0; > + blkcache_invalidate(desc->if_type, desc->devnum); > + } > > /* Test for SD version 2 */ > err = mmc_send_if_cond(mmc); > -- > 1.7.9.5 > > _______________________________________________ > U-Boot mailing list > U-Boot(a)lists.denx.de > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.d > enx.de%2Flistinfo%2Fu-boot&data=02%7C01%7CPeng.Fan%40nxp.com > %7Cb99d933608be4817e5f408d6bef7d8a5%7C686ea1d3bc2b4c6fa92cd99c5 > c301635%7C0%7C1%7C636906369056326740&sdata=k%2Fo2bgjU1bdl > pLyk5nv78yrX3P9fqaVmukcbB2nTvF8%3D&reserved=0

2 1