April 2019 - U-Boot

[U-Boot] [PATCH 1/3] rockchip: rk3399: add tpl support
by Kever Yang 29 Apr '19

29 Apr '19

Rockchip platform suppose to use TPL(run in SRAM) as dram init and SPL(run in DDR SDRAM) as pre-loader, so that the SPL would not be limited by SRAM size. This patch add rk3399-board-tpl.c and its common configs. Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- arch/arm/mach-rockchip/Kconfig | 34 ++++++++- arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rk3399-board-tpl.c | 84 +++++++++++++++++++++++ include/configs/rk3399_common.h | 9 +++ 4 files changed, 127 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-rockchip/rk3399-board-tpl.c diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index d0ed369f55..50add08338 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -154,12 +154,28 @@ config ROCKCHIP_RK3399 bool "Support Rockchip RK3399" select ARM64 select SUPPORT_SPL + select SUPPORT_TPL select SPL + select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL + select TPL_NEEDS_SEPARATE_STACK if TPL select SPL_SEPARATE_BSS select SPL_SERIAL_SUPPORT select SPL_DRIVERS_MISC_SUPPORT select BOARD_LATE_INIT select ROCKCHIP_BROM_HELPER + imply TPL_SERIAL_SUPPORT + imply TPL_LIBCOMMON_SUPPORT + imply TPL_LIBGENERIC_SUPPORT + imply TPL_SYS_MALLOC_SIMPLE + imply TPL_BOOTROM_SUPPORT + imply TPL_DRIVERS_MISC_SUPPORT + imply TPL_OF_CONTROL + imply TPL_DM + imply TPL_REGMAP + imply TPL_SYSCON + imply TPL_RAM + imply TPL_CLK + imply TPL_TINY_MEMSET help The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72 and quad-core Cortex-A53. @@ -168,6 +184,22 @@ config ROCKCHIP_RK3399 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. +if ROCKCHIP_RK3399 + +config TPL_LDSCRIPT + default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds" + +config TPL_TEXT_BASE + default 0xff8c2000 + +config TPL_MAX_SIZE + default 188416 + +config TPL_STACK + default 0xff8effff + +endif + config ROCKCHIP_RV1108 bool "Support Rockchip RV1108" select CPU_V7A @@ -195,7 +227,7 @@ config SPL_ROCKCHIP_BACK_TO_BROM config TPL_ROCKCHIP_BACK_TO_BROM bool "TPL returns to bootrom" - default y if ROCKCHIP_RK3368 + default y select ROCKCHIP_BROM_HELPER depends on TPL help diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index fd62a693fe..846c82d70a 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -12,6 +12,7 @@ obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o obj-tpl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-tpl.o obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o obj-tpl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-tpl.o +obj-tpl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-tpl.o obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o diff --git a/arch/arm/mach-rockchip/rk3399-board-tpl.c b/arch/arm/mach-rockchip/rk3399-board-tpl.c new file mode 100644 index 0000000000..86d3ffe97c --- /dev/null +++ b/arch/arm/mach-rockchip/rk3399-board-tpl.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <ram.h> +#include <spl.h> +#include <asm/io.h> +#include <asm/arch-rockchip/bootrom.h> + +#define TIMER_CHN10_BASE 0xff8680a0 +#define TIMER_END_COUNT_L 0x00 +#define TIMER_END_COUNT_H 0x04 +#define TIMER_INIT_COUNT_L 0x10 +#define TIMER_INIT_COUNT_H 0x14 +#define TIMER_CONTROL_REG 0x1c + +#define TIMER_EN 0x1 +#define TIMER_FMODE (0 << 1) +#define TIMER_RMODE (1 << 1) + +void secure_timer_init(void) +{ + writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L); + writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H); + writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L); + writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H); + writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG); +} + +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); + /* + * Debug UART can be used from here if required: + * + * debug_uart_init(); + * printch('a'); + * printhex8(0x1234); + * printascii("string"); + */ + printascii("U-Boot TPL board init\n"); +#endif + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + secure_timer_init(); + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + pr_err("DRAM init failed: %d\n", ret); + return; + } +} + +void board_return_to_bootrom(void) +{ + back_to_bootrom(BROM_BOOT_NEXTSTAGE); +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_BOOTROM; +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index b977b1faa7..6ae3c1f920 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -18,12 +18,21 @@ #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 #define CONFIG_SYS_LOAD_ADDR 0x00800800 + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TPL_BOOTROM_SUPPORT) +#define CONFIG_SPL_STACK 0x00400000 +#define CONFIG_SPL_TEXT_BASE 0x00000000 +#define CONFIG_SPL_MAX_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x00400000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 +#else #define CONFIG_SPL_STACK 0xff8effff #define CONFIG_SPL_TEXT_BASE 0xff8c2000 #define CONFIG_SPL_MAX_SIZE 0x30000 - 0x2000 /* BSS setup */ #define CONFIG_SPL_BSS_START_ADDR 0xff8e0000 #define CONFIG_SPL_BSS_MAX_SIZE 0x10000 +#endif #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ -- 2.20.1

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[U-Boot] [PATCH 0/8] rockchip: enable spl/tpl for px5-evb
by Kever Yang 29 Apr '19

29 Apr '19

This patch set enable spl/tpl and also suppot ATF elf, and the timer is using rockchip timer, we may switch to stimer based ARM generic timer later if we get STIMER patches mergerd. Kever Yang (8): rockchip: rk3368: support UART2/4 in board_debug_uart_init() rockchip: px5 update dts for spl/tpl rockchip: px5: update SPL size for spl/tpl rockchip: px5: update defconfig for TPL/SPL rockchip: boot0: update CONFIG_ROCKCHIP_SPL_RESERVE_IRAM for SPL only rockchip: dmc: rk3368: update rank number for evb-px5 rockchip: rk3368: remove uart iomux init in SPL rockchip: px5: add timer0 dts node as tick timer arch/arm/dts/rk3368-px5-evb-u-boot.dtsi | 36 ++++++++++++++ arch/arm/include/asm/arch-rockchip/boot0.h | 3 +- arch/arm/mach-rockchip/rk3368-board-spl.c | 13 ----- arch/arm/mach-rockchip/rk3368/rk3368.c | 40 ++++++++++++++++ configs/evb-px5_defconfig | 56 +++++++++++++++++++++- drivers/ram/rockchip/dmc-rk3368.c | 4 ++ include/configs/evb_px5.h | 1 + include/configs/rk3368_common.h | 3 +- 8 files changed, 139 insertions(+), 17 deletions(-) -- 2.20.1

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Re: [U-Boot] U-Boot Security
by Linder Pascal 29 Apr '19

29 Apr '19

Hello everyone, I have created the FIT to be loaded by the SPL and the keys for the signature. Now, I am wondering how the signature is done by U-Boot? Is there an option in menuconfig that points to the key or is it me that has to do it manually? Also, I am wondering how to place the public key inside the U-Boot image? Sincerely, Pascal Linder Student Telekommunikation Netzwerke und Sicherheit Klasse T-3b ________________________________ Von: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> Gesendet: Samstag, 27. April 2019 21:12:03 An: Linder Pascal Betreff: Re: AW: [U-Boot] U-Boot Security Hello Pascal, I can't help you much there, I can only tell you SPL -> U-Boot should be the same as U-Boot -> FIT(Linux). I once tested this and it works, but it's too long ago to remember. And your first mail suggested the latter case (U-Boot -> FIT/Linux) already works for you... Besides, please keep the discussion public (on the mailing list). There are others who know this far better than me and might be able to help more. Regards, Simon On 27.04.19 17:50, Linder Pascal wrote: > Hello Simon, > > > Thanks for your response! Now, I am just wondering how the signature is done by U-Boot. Or is it me that must sign the images manually with mkimage? > > > The key and certificate I have in a directory called keys inside U-Boot. Is there an option in KConfig to create the relation to this key? > > > Summarized, I would like to know how to put the public key into my U-Boot image? > > > Sincerely, > > > Pascal Linder > > Student Telekommunikation Netzwerke und Sicherheit > > Klasse T-3b > > ________________________________ > Von: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> > Gesendet: Mittwoch, 24. April 2019 19:56:51 > An: Linder Pascal; u-boot(a)lists.denx.de > Betreff: Re: [U-Boot] U-Boot Security > > Am 24.04.2019 um 15:55 schrieb Linder Pascal: >> Hello everyone, >> >> >> I want to add some supplementary security to my embedded system. The Flattened Image Tree (FIT) to secure the operating system and the device tree, I have already found. Now, I am wondering if I could also secure U-Boot itself before starting it by the Secondary Program Loader (SPL). Does anyone knows a method to do that? > > Just as U-Boot can load Kernel + DTS as FIT, SPL can load U-Boot as FIT. > See CONFIG_SPL_LOAD_FIT. This FIT containing U-Boot + its DTS can then > be verified, too. > > Regards, > Simon >

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[U-Boot] [PATCH 1/4] ARM: socfpga: Factor out handoff register configuration
by Marek Vasut 29 Apr '19

29 Apr '19

Factor out the code for programming preloader handoff register values, the ISWGRP Handoff 0 and 1. These registers later control which bridges are enabled by the "bridge" command on Gen5 devices. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Chin Liang See <chin.liang.see(a)intel.com> Cc: Dinh Nguyen <dinguyen(a)kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> Cc: Tien Fong Chee <tien.fong.chee(a)intel.com> --- .../include/mach/reset_manager_gen5.h | 1 + arch/arm/mach-socfpga/reset_manager_gen5.c | 25 +++++++++++++++++-- 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h index dd58922cec..5e490d182e 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h @@ -9,6 +9,7 @@ #include <dt-bindings/reset/altr,rst-mgr.h> void reset_deassert_peripherals_handoff(void); +void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h); void socfpga_bridges_reset(int enable); struct socfpga_reset_manager { diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c b/arch/arm/mach-socfpga/reset_manager_gen5.c index 25baef79bc..66af924485 100644 --- a/arch/arm/mach-socfpga/reset_manager_gen5.c +++ b/arch/arm/mach-socfpga/reset_manager_gen5.c @@ -73,6 +73,28 @@ void reset_deassert_peripherals_handoff(void) #define L3REGS_REMAP_HPS2FPGA_MASK 0x08 #define L3REGS_REMAP_OCRAM_MASK 0x01 +void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h) +{ + u32 brgmask = 0x0; + u32 l3rmask = L3REGS_REMAP_OCRAM_MASK; + + if (h2f) + brgmask |= BIT(0); + else + l3rmask |= L3REGS_REMAP_HPS2FPGA_MASK; + + if (lwh2f) + brgmask |= BIT(1); + else + l3rmask |= L3REGS_REMAP_LWHPS2FPGA_MASK; + + if (f2h) + brgmask |= BIT(2); + + writel(brgmask, &sysmgr_regs->iswgrp_handoff[0]); + writel(l3rmask, &sysmgr_regs->iswgrp_handoff[1]); +} + void socfpga_bridges_reset(int enable) { const u32 l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK | @@ -83,8 +105,7 @@ void socfpga_bridges_reset(int enable) /* brdmodrst */ writel(0xffffffff, &reset_manager_base->brg_mod_reset); } else { - writel(0, &sysmgr_regs->iswgrp_handoff[0]); - writel(l3mask, &sysmgr_regs->iswgrp_handoff[1]); + socfpga_bridges_set_handoff_regs(false, false, false); /* Check signal from FPGA. */ if (!fpgamgr_test_fpga_ready()) { -- 2.20.1

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[U-Boot] [PATCH v2 0/4] AE350 support SMP boot from flash
by Andes 29 Apr '19

29 Apr '19

From: Rick Chen <rick(a)andestech.com> In current RISC-V SMP flow, AE350 will encounter the the write failure problem since hart_lottery and available_harts_lock was not in ram address but in flash address when booing from flash. This patch can help to fix the failure problem when AE350 was booting from flash by disabling this two features. Changes in v2: - Fix some typos - Also surround the declaration of prior_stage_fdt_address in arch/riscv/cpu/cpu.c with OF_PRIOR_STAGE - Use CONFIP_XIP to replace CONFIG_HART_LOTTERY and CONFIG_AVAILABLE_HARTS Rick Chen (4): riscv: hart_lottery and available harts features can be selectable riscv: configs: Support AE350 SMP booting from flash flow riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled riscv: configs: AE350 will use CONFIG_OF_PRIOR_STAGE when booting from ram arch/riscv/Kconfig | 10 ++++++++++ arch/riscv/cpu/cpu.c | 5 ++++- arch/riscv/cpu/start.S | 9 ++++++++- arch/riscv/include/asm/global_data.h | 2 ++ arch/riscv/lib/asm-offsets.c | 2 ++ arch/riscv/lib/smp.c | 2 ++ configs/ae350_rv32_defconfig | 2 +- configs/ae350_rv32_xip_defconfig | 36 +++++++++++++++++++++++++++++++++++ configs/ae350_rv64_defconfig | 2 +- configs/ae350_rv64_xip_defconfig | 37 ++++++++++++++++++++++++++++++++++++ 10 files changed, 103 insertions(+), 4 deletions(-) create mode 100644 configs/ae350_rv32_xip_defconfig create mode 100644 configs/ae350_rv64_xip_defconfig -- 2.7.4

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[U-Boot] [PATCH 3/5] spi: add spi-mem driver for MediaTek MT7629 SoC
by Weijie Gao 29 Apr '19

29 Apr '19

This patch adds spi-mem driver for MediaTek MT7629 SoC to access SPI-NOR and SPI-NAND flashes. Cc: Jagan Teki <jagan(a)openedev.com> Signed-off-by: Weijie Gao <weijie.gao(a)mediatek.com> --- drivers/spi/Kconfig | 9 ++ drivers/spi/Makefile | 1 + drivers/spi/mtk_spimem.c | 325 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 335 insertions(+) create mode 100644 drivers/spi/mtk_spimem.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 92d7ca6..cdb726c 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -139,6 +139,15 @@ config MT7621_SPI the SPI NOR flash on platforms embedding this Ralink / MediaTek SPI core, like MT7621/7628/7688. +config MTK_SPIMEM + bool "Mediatek SPI memory controller driver" + depends on SPI_MEM + help + Enable the Mediatek SPI memory controller driver. This driver is + originally based on the MediaTek SNFI IP core. It can only be + used to access SPI memory devices like SPI-NOR or SPI-NAND on + platforms embedding this IP core, like MT7622/M7629. + config MVEBU_A3700_SPI bool "Marvell Armada 3700 SPI driver" select CLK_ARMADA_3720 diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index f1e3bec..71a598e 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o +obj-$(CONFIG_MTK_SPIMEM) += mtk_spimem.o obj-$(CONFIG_MT7621_SPI) += mt7621_spi.o obj-$(CONFIG_MSCC_BB_SPI) += mscc_bb_spi.o obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o diff --git a/drivers/spi/mtk_spimem.c b/drivers/spi/mtk_spimem.c new file mode 100644 index 0000000..ad25160 --- /dev/null +++ b/drivers/spi/mtk_spimem.c @@ -0,0 +1,325 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 MediaTek Inc. All Rights Reserved. + * + * Author: Weijie Gao <weijie.gao(a)mediatek.com> + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <errno.h> +#include <spi.h> +#include <spi-mem.h> +#include <stdbool.h> +#include <dm/pinctrl.h> +#include <linux/bitops.h> +#include <linux/io.h> +#include <linux/iopoll.h> + +#define SNFI_MAC_CTL 0x500 +#define MAC_XIO_SEL BIT(4) +#define SF_MAC_EN BIT(3) +#define SF_TRIG BIT(2) +#define WIP_READY BIT(1) +#define WIP BIT(0) + +#define SNFI_MAC_OUTL 0x504 +#define SNFI_MAC_INL 0x508 + +#define SNFI_MISC_CTL 0x538 +#define SW_RST BIT(28) +#define FIFO_RD_LTC_SHIFT 25 +#define FIFO_RD_LTC GENMASK(26, 25) +#define LATCH_LAT_SHIFT 8 +#define LATCH_LAT GENMASK(9, 8) +#define CS_DESELECT_CYC_SHIFT 0 +#define CS_DESELECT_CYC GENMASK(4, 0) + +#define SNF_STA_CTL1 0x550 +#define SPI_STATE GENMASK(3, 0) + +#define SNFI_GPRAM_OFFSET 0x800 +#define SNFI_GPRAM_SIZE 0x80 + +#define SNFI_POLL_INTERVAL 500000 +#define SNFI_RST_POLL_INTERVAL 1000000 + +struct mtk_spimem_priv { + void __iomem *base; + + struct udevice *dev; + + struct clk nfi_clk; + struct clk pad_clk; +}; + +static int mtk_spimem_adjust_op_size(struct spi_slave *slave, + struct spi_mem_op *op) +{ + u32 nbytes; + + /* + * When there is input data, it will be appended after the output + * data in the GPRAM. So the total size of either pure output data + * or the output+input data must not exceed the GPRAM size. + */ + + nbytes = sizeof(op->cmd.opcode) + op->addr.nbytes + + op->dummy.nbytes; + + if (nbytes + op->data.nbytes <= SNFI_GPRAM_SIZE) + return 0; + + if (nbytes >= SNFI_GPRAM_SIZE) + return -ENOTSUPP; + + op->data.nbytes = SNFI_GPRAM_SIZE - nbytes; + + return 0; +} + +static bool mtk_spimem_supports_op(struct spi_slave *slave, + const struct spi_mem_op *op) +{ + if (op->cmd.buswidth > 1 || op->addr.buswidth > 1 || + op->dummy.buswidth > 1 || op->data.buswidth > 1) + return false; + + return true; +} + +static int mtk_snfi_mac_trigger(struct mtk_spimem_priv *priv, + u32 outlen, u32 inlen) +{ + int ret; + u32 val; + +#ifdef CONFIG_PINCTRL + pinctrl_select_state(priv->dev, "default"); +#endif + + writel(SF_MAC_EN, priv->base + SNFI_MAC_CTL); + writel(outlen, priv->base + SNFI_MAC_OUTL); + writel(inlen, priv->base + SNFI_MAC_INL); + + writel(SF_MAC_EN | SF_TRIG, priv->base + SNFI_MAC_CTL); + + ret = readl_poll_timeout(priv->base + SNFI_MAC_CTL, val, + val & WIP_READY, SNFI_POLL_INTERVAL); + if (ret) { + printf("%s: timed out waiting for WIP_READY\n", __func__); + goto cleanup; + } + + ret = readl_poll_timeout(priv->base + SNFI_MAC_CTL, val, + !(val & WIP), SNFI_POLL_INTERVAL); + if (ret) + printf("%s: timed out waiting for WIP cleared\n", __func__); + + writel(0, priv->base + SNFI_MAC_CTL); + +cleanup: +#ifdef CONFIG_PINCTRL + pinctrl_select_state(priv->dev, "snor_mmap"); +#endif + + return ret; +} + +static int mtk_snfi_mac_reset(struct mtk_spimem_priv *priv) +{ + int ret; + u32 val; + + setbits_32(priv->base + SNFI_MISC_CTL, SW_RST); + + ret = readl_poll_timeout(priv->base + SNF_STA_CTL1, val, + !(val & SPI_STATE), SNFI_POLL_INTERVAL); + if (ret) + printf("%s: failed to reset snfi mac\n", __func__); + + writel((2 << FIFO_RD_LTC_SHIFT) | + (10 << CS_DESELECT_CYC_SHIFT), + priv->base + SNFI_MISC_CTL); + + return ret; +} + +static void mtk_snfi_copy_to_gpram(struct mtk_spimem_priv *priv, + const void *data, size_t len) +{ + void __iomem *gpram = priv->base + SNFI_GPRAM_OFFSET; + size_t i, n = (len + sizeof(u32) - 1) / sizeof(u32); + const u32 *buff = data; + + /* + * The output data will always be copied to the beginning of + * the GPRAM. Uses word write for better performace. + * + * Trailing bytes in the last word are not cared. + */ + + for (i = 0; i < n; i++) + writel(buff[i], gpram + i * sizeof(u32)); +} + +static void mtk_snfi_copy_from_gpram(struct mtk_spimem_priv *priv, + void *data, size_t pos, size_t len) +{ + void __iomem *gpram = priv->base + SNFI_GPRAM_OFFSET; + u8 gpdata[SNFI_GPRAM_SIZE]; + u32 *buff = (u32 *)gpdata; + size_t i, off, end; + + /* Start position in the buffer */ + off = pos & (sizeof(u32) - 1); + + /* End position for copy */ + end = (len + pos + sizeof(u32) - 1) & (~(sizeof(u32) - 1)); + + /* Start position for copy */ + pos &= ~(sizeof(u32) - 1); + + /* + * Read aligned data from GPRAM to buffer first. + * Uses word read for better performace. + */ + i = 0; + while (pos < end) { + buff[i++] = readl(gpram + pos); + pos += sizeof(u32); + } + + /* Copy real data */ + memcpy(data, gpdata + off, len); +} + +static int mtk_spimem_exec_op(struct spi_slave *slave, + const struct spi_mem_op *op) +{ + struct udevice *bus = dev_get_parent(slave->dev); + struct mtk_spimem_priv *priv = dev_get_priv(bus); + u8 gpram_data[SNFI_GPRAM_SIZE]; + u32 i, len = 0, inlen = 0; + int addr_sh; + int ret; + + ret = mtk_snfi_mac_reset(priv); + if (ret) + return ret; + + /* Put opcode */ + gpram_data[len++] = op->cmd.opcode; + + /* Put address */ + addr_sh = (op->addr.nbytes - 1) * 8; + while (addr_sh >= 0) { + gpram_data[len++] = (op->addr.val >> addr_sh) & 0xff; + addr_sh -= 8; + } + + /* Put dummy bytes */ + for (i = 0; i < op->dummy.nbytes; i++) + gpram_data[len++] = 0; + + /* Put output data */ + if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) { + memcpy(gpram_data + len, op->data.buf.out, op->data.nbytes); + len += op->data.nbytes; + } + + /* Copy final output data to GPRAM */ + mtk_snfi_copy_to_gpram(priv, gpram_data, len); + + /* Start one SPI transaction */ + if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN) + inlen = op->data.nbytes; + + ret = mtk_snfi_mac_trigger(priv, len, inlen); + if (ret) + return ret; + + /* Copy input data from GPRAM */ + if (inlen) + mtk_snfi_copy_from_gpram(priv, op->data.buf.in, len, inlen); + + return 0; +} + +static int mtk_spimem_probe(struct udevice *bus) +{ + struct mtk_spimem_priv *priv = dev_get_priv(bus); + int ret; + + priv->base = (void __iomem *)devfdt_get_addr(bus); + if (!priv->base) + return -EINVAL; + + ret = clk_get_by_name(bus, "nfi_clk", &priv->nfi_clk); + if (ret < 0) + return ret; + + ret = clk_get_by_name(bus, "pad_clk", &priv->pad_clk); + if (ret < 0) + return ret; + + clk_enable(&priv->nfi_clk); + clk_enable(&priv->pad_clk); + + priv->dev = bus; + + return 0; +} + +static int mtk_spimem_set_speed(struct udevice *bus, uint speed) +{ + return 0; +} + +static int mtk_spimem_set_mode(struct udevice *bus, uint mode) +{ + if (mode) + return -EINVAL; + + return 0; +} + +static int mtk_spimem_child_pre_probe(struct udevice *dev) +{ + struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev); + + if (plat->cs > 0) { + printf("%s: invalid chip select %u\n", __func__, plat->cs); + return -ENODEV; + } + + return 0; +} + +static const struct spi_controller_mem_ops mem_ops = { + .adjust_op_size = mtk_spimem_adjust_op_size, + .supports_op = mtk_spimem_supports_op, + .exec_op = mtk_spimem_exec_op, +}; + +static const struct dm_spi_ops mtk_spimem_ops = { + .mem_ops = &mem_ops, + .set_speed = mtk_spimem_set_speed, + .set_mode = mtk_spimem_set_mode, +}; + +static const struct udevice_id mtk_spimem_ids[] = { + { .compatible = "mediatek,mtk-spimem" }, + { } +}; + +U_BOOT_DRIVER(mtk_spimem) = { + .name = "mtk_spimem", + .id = UCLASS_SPI, + .of_match = mtk_spimem_ids, + .ops = &mtk_spimem_ops, + .priv_auto_alloc_size = sizeof(struct mtk_spimem_priv), + .probe = mtk_spimem_probe, + .child_pre_probe = mtk_spimem_child_pre_probe, +}; -- 1.9.1

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Re: [U-Boot] [PATCH] riscv: qemu: Use correct SYS_TEXT_BASE for S-mode on 32bit system
by Rick Chen 29 Apr '19

29 Apr '19

Hi Karsten > From: Karsten Merker [mailto:merker@debian.org] > Sent: Friday, April 26, 2019 5:35 PM > To: Rick Jian-Zhi Chen(陳建志) > Cc: Anup Patel; Bin Meng; Lukas Auer; Tom Rini; U-Boot Mailing List; Palmer > Dabbelt > Subject: Re: [U-Boot] [PATCH] riscv: qemu: Use correct SYS_TEXT_BASE for > S-mode on 32bit system > > On Thu, Apr 11, 2019 at 06:52:12AM +0000, Anup Patel wrote: > > For 32bit system, the OpenSBI (or BBL) will jump to 0x80400000 address > > in S-mode whereas for 64bit system it will jump to 0x80200000 address > > in S-mode. > > > > Currently, the S-mode U-Boot sets SYS_TEXT_BASE to 0x80200000 for both > > 32bit and 64bit system. This breaks S-mode U-Boot for 32bit system. > > > > This patch sets different SYS_TEXT_BASE for 32bit and 64bit system so > > that S-mode U-Boot works fine for both. > > > > Signed-off-by: Anup Patel <anup.patel(a)wdc.com> > > --- > > board/emulation/qemu-riscv/Kconfig | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/board/emulation/qemu-riscv/Kconfig > > b/board/emulation/qemu-riscv/Kconfig > > index cf057e7de6..20ea6dc59b 100644 > > --- a/board/emulation/qemu-riscv/Kconfig > > +++ b/board/emulation/qemu-riscv/Kconfig > > @@ -14,7 +14,8 @@ config SYS_CONFIG_NAME > > > > config SYS_TEXT_BASE > > default 0x80000000 if !RISCV_SMODE > > - default 0x80200000 if RISCV_SMODE > > + default 0x80200000 if RISCV_SMODE && ARCH_RV64I > > + default 0x80400000 if RISCV_SMODE && ARCH_RV32I > > > > config BOARD_SPECIFIC_OPTIONS # dummy > > def_bool y > > Hello Rick, > > may I kindly ping you regarding this patch (patchwork entry at > http://patchwork.ozlabs.org/patch/1083725/)? It would be great if you could > commit it soonish as without it the qemu RV32 target is currently non-functional. > > The patch has received two reviews and a tested-by and doesn't touch any > generic code, so it should be safe to apply. > I have applied to u-boot-riscv/master Thanks Rick > Regards, > Karsten > -- > Ich widerspreche hiermit ausdrücklich der Nutzung sowie der Weitergabe meiner > personenbezogenen Daten für Zwecke der Werbung sowie der Markt- oder > Meinungsforschung.

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[U-Boot] [PATCH v5 0/2] colibri imx8qxp 2gb wb it v1.0b module support
by Marcel Ziswiler 29 Apr '19

29 Apr '19

This series fixes building for i.MX8 without SPL and adds support for more lpuart instances, cleans-up and extends the Toradex SKU handling and last but not least introduces support for the Toradex Colibri iMX8QXP 2GB WB IT V1.0B module. This series is available together with the last few clean-up patches on our git server [1] as well. [1] http://git.toradex.com/cgit/u-boot-toradex.git/log/?h=for-next Changes in v5: - Keep alphabetical order of device trees in Makefile. - Order targets in Kconfig alphabetically. - Fix indentation in SPDX. - Remove stale includes from board file. - Take into account ahab-container being platform specific. - Use vidargs instead of multiple discrete video= in configuration. - Fix console baudrate specification. - Remove redundant CONFIG_SYS_MMC_ENV_DEV define and add some clarifying comment. - Fix product name being Colibri iMX8X in a comment. - Remove obsolete CONFIG_NR_DRAM_BANKS. Changes in v4: - Fixed SPDX as well as using SZ_ macros where applicable as suggested by Igor. - Fixed superfluous trailing line continuation introduced by commit 0d331c035a09 ("imx: support i.MX8QM MEK board") in the Makefile plus sorted stuff alphabetically again. - Applied changes similar to commit 3b9ac5415084 ("imx: 8qxp_mek: fix fdt_file and console"). However, note that using ${baudrate} in console= like that won't actually work! - Applied changes similar to commit e5b8f7e665aa ("imx8qxp: mek: enable dm-spl for pm"). Changes in v3: - Added Igor's reviewed-by tag. Changes in v2: - Changed imx-atf git clone command to include initial branch information as suggested by Igor. - Sorted board file includes alphabetically as suggested by Igor. - Got rid of SPL configuration in legacy header file as suggested by Igor and the whole use of SPL on i.MX 8X anyway neither works well nor makes any much sense at all. Marcel Ziswiler (2): imx: fix building for i.mx8 without spl board: toradex: add colibri imx8qxp 2gb wb it v1.0b module support arch/arm/dts/Makefile | 3 +- arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi | 117 +++++++ arch/arm/dts/fsl-imx8qxp-colibri.dts | 328 ++++++++++++++++++ arch/arm/mach-imx/Makefile | 2 + arch/arm/mach-imx/imx8/Kconfig | 12 +- board/toradex/colibri-imx8qxp/Kconfig | 30 ++ board/toradex/colibri-imx8qxp/MAINTAINERS | 9 + board/toradex/colibri-imx8qxp/Makefile | 6 + board/toradex/colibri-imx8qxp/README | 66 ++++ .../toradex/colibri-imx8qxp/colibri-imx8qxp.c | 202 +++++++++++ board/toradex/colibri-imx8qxp/imximage.cfg | 24 ++ configs/colibri-imx8qxp_defconfig | 53 +++ include/configs/colibri-imx8qxp.h | 210 +++++++++++ 13 files changed, 1058 insertions(+), 4 deletions(-) create mode 100644 arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi create mode 100644 arch/arm/dts/fsl-imx8qxp-colibri.dts create mode 100644 board/toradex/colibri-imx8qxp/Kconfig create mode 100644 board/toradex/colibri-imx8qxp/MAINTAINERS create mode 100644 board/toradex/colibri-imx8qxp/Makefile create mode 100644 board/toradex/colibri-imx8qxp/README create mode 100644 board/toradex/colibri-imx8qxp/colibri-imx8qxp.c create mode 100644 board/toradex/colibri-imx8qxp/imximage.cfg create mode 100644 configs/colibri-imx8qxp_defconfig create mode 100644 include/configs/colibri-imx8qxp.h -- 2.20.1

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[U-Boot] [PATCH] imx: add lowlevel init for ARM64
by Peng Fan 29 Apr '19

29 Apr '19

Sometimes we met SERROR, but only to catch it when Linux boots up. Let's enable catching in U-Boot to catch it ealier and ease debug. Signed-off-by: Peng Fan <peng.fan(a)nxp.com> --- arch/arm/mach-imx/Makefile | 2 +- arch/arm/mach-imx/lowlevel.S | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-imx/lowlevel.S diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index c3ed62aed6..37675d0558 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -204,7 +204,7 @@ endif targets += $(addprefix ../../../,SPL spl/u-boot-spl.cfgout u-boot-dtb.cfgout u-boot.cfgout u-boot.uim spl/u-boot-nand-spl.imx) -obj-$(CONFIG_ARM64) += sip.o +obj-$(CONFIG_ARM64) += lowlevel.o sip.o obj-$(CONFIG_MX5) += mx5/ obj-$(CONFIG_MX6) += mx6/ diff --git a/arch/arm/mach-imx/lowlevel.S b/arch/arm/mach-imx/lowlevel.S new file mode 100644 index 0000000000..158fdb7d87 --- /dev/null +++ b/arch/arm/mach-imx/lowlevel.S @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#include <linux/linkage.h> + +ENTRY(lowlevel_init) + mrs x0, CurrentEL + cmp x0, #8 + b.eq 1f + ret +1: + msr daifclr, #4 + + /* set HCR_EL2.AMO to catch SERROR */ + mrs x0, hcr_el2 + orr x0, x0, #0x20 + msr hcr_el2, x0 + isb + ret +ENDPROC(lowlevel_init) -- 2.16.4

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[U-Boot] uboot of platdata question
by Peng Fan 28 Apr '19

28 Apr '19

Hi Simon, We have such piece dtb in device tree, however with SPL_OF_PLATDATA, it failed to compile. It could not correct get address-cells/size-cells from cpus node. Actually It not find the address-cell/size-cell property from cpus node. Do you have any suggestions? /{ cpus { #address-cells = <2>; #size-cells = <0>; /* We have 1 clusters having 4 Cortex-A35 cores */ A35_0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a35"; reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&A35_L2>; }; Traceback (most recent call last): File "./tools/dtoc/dtoc", line 109, in <module> options.output) File "/home/Freenix/work/sw-stash/uboot-upstream/u-boot/tools/dtoc/dtb_platdata.py", line 566, in run_steps plat.scan_reg_sizes() File "/home/Freenix/work/sw-stash/uboot-upstream/u-boot/tools/dtoc/dtb_platdata.py", line 326, in scan_reg_sizes (node.name, len(reg.value), na, ns)) ValueError: Node 'cpu@0' reg property has 2 cells which is not a multiple of na + ns = 2 + 2) make[1]: *** [scripts/Makefile.spl:301: spl/dts/dt-platdata.c] Error 1 make: *** [Makefile:1678: spl/u-boot-spl] Error 2 Thanks, Peng.

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