April 2019 - U-Boot

[U-Boot] [PATCH v2] arm: socfpga: Move Stratix 10 SDRAM driver to DM
by Ley Foon Tan 02 May '19

02 May '19

Convert Stratix 10 SDRAM driver to device model. Get rid of call to socfpga_per_reset() and use reset framework. SPL is changed from calling function in SDRAM driver directly to just probing UCLASS_RAM. Move sdram_s10.h from arch to driver/ddr/altera directory. Signed-off-by: Ley Foon Tan <ley.foon.tan(a)intel.com> --- v1->v2: - Change sdr device tree node enabled by default. - Probe UCLASS_RAM only if CONFIG_ALTERA_SDRAM is enabled. --- arch/arm/dts/socfpga_stratix10.dtsi | 9 + arch/arm/mach-socfpga/spl_s10.c | 11 +- configs/socfpga_stratix10_defconfig | 1 + drivers/ddr/altera/Kconfig | 6 +- drivers/ddr/altera/sdram_s10.c | 246 ++++++++++++------ .../mach => drivers/ddr/altera}/sdram_s10.h | 4 - include/configs/socfpga_stratix10_socdk.h | 5 - 7 files changed, 192 insertions(+), 90 deletions(-) rename {arch/arm/mach-socfpga/include/mach => drivers/ddr/altera}/sdram_s10.h (97%) diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi index d1ae2fabae..bd68a78a37 100755 --- a/arch/arm/dts/socfpga_stratix10.dtsi +++ b/arch/arm/dts/socfpga_stratix10.dtsi @@ -258,6 +258,15 @@ u-boot,dm-pre-reloc; }; + sdr: sdr@f8000400 { + compatible = "altr,sdr-ctl-s10"; + reg = <0xf8000400 0x80>, + <0xf8010000 0x190>, + <0xf8011000 0x500>; + resets = <&rst DDRSCH_RESET>; + u-boot,dm-pre-reloc; + }; + spi0: spi@ffda4000 { compatible = "snps,dw-apb-ssi"; #address-cells = <1>; diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c index a141ffe82a..3d44eabf91 100644 --- a/arch/arm/mach-socfpga/spl_s10.c +++ b/arch/arm/mach-socfpga/spl_s10.c @@ -15,9 +15,9 @@ #include <asm/arch/firewall_s10.h> #include <asm/arch/mailbox_s10.h> #include <asm/arch/reset_manager.h> -#include <asm/arch/sdram_s10.h> #include <asm/arch/system_manager.h> #include <watchdog.h> +#include <dm/uclass.h> DECLARE_GLOBAL_DATA_PTR; @@ -119,6 +119,7 @@ void board_init_f(ulong dummy) { const struct cm_config *cm_default_cfg = cm_get_default_config(); int ret; + struct udevice *dev; #ifdef CONFIG_HW_WATCHDOG /* Ensure watchdog is paused when debugging is happening */ @@ -175,11 +176,13 @@ void board_init_f(ulong dummy) clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADMASK_MEM_RAM0), CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK); - debug("DDR: Initializing Hard Memory Controller\n"); - if (sdram_mmr_init_full(0)) { - puts("DDR: Initialization failed.\n"); +#ifdef CONFIG_ALTERA_SDRAM + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); hang(); } +#endif /* CONFIG_ALTERA_SDRAM */ mbox_init(); diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index 4848013b21..bda6ab6637 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -32,6 +32,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_ALTERA_SDRAM=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig index 8f60b56eb8..112c4ad7c3 100644 --- a/drivers/ddr/altera/Kconfig +++ b/drivers/ddr/altera/Kconfig @@ -1,7 +1,7 @@ config ALTERA_SDRAM bool "SoCFPGA DDR SDRAM driver" - depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 - select RAM if TARGET_SOCFPGA_GEN5 - select SPL_RAM if TARGET_SOCFPGA_GEN5 + depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || TARGET_SOCFPGA_STRATIX10 + select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10 + select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10 help Enable DDR SDRAM controller for the SoCFPGA devices. diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c index e4d4a02ca2..d2f3272609 100644 --- a/drivers/ddr/altera/sdram_s10.c +++ b/drivers/ddr/altera/sdram_s10.c @@ -5,17 +5,32 @@ */ #include <common.h> +#include <dm.h> #include <errno.h> #include <div64.h> #include <fdtdec.h> -#include <asm/io.h> +#include <ram.h> +#include <reset.h> +#include "sdram_s10.h" #include <wait_bit.h> #include <asm/arch/firewall_s10.h> -#include <asm/arch/sdram_s10.h> #include <asm/arch/system_manager.h> #include <asm/arch/reset_manager.h> +#include <asm/io.h> #include <linux/sizes.h> +#ifdef CONFIG_SPL_BUILD + +struct altera_sdram_priv { + struct ram_info info; +}; + +struct altera_sdram_platdata { + void __iomem *hmc; + void __iomem *ddr_sch; + void __iomem *iomhc; +}; + DECLARE_GLOBAL_DATA_PTR; static const struct socfpga_system_manager *sysmgr_regs = @@ -51,25 +66,26 @@ u32 ddr_config[] = { DDR_CONFIG(1, 4, 10, 17), }; -static u32 hmc_readl(u32 reg) +static u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg) { - return readl(((void __iomem *)SOCFPGA_HMC_MMR_IO48_ADDRESS + (reg))); + return readl(plat->iomhc + (reg)); } -static u32 hmc_ecc_readl(u32 reg) +static u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg) { - return readl((void __iomem *)SOCFPGA_SDR_ADDRESS + (reg)); + return readl(plat->hmc + (reg)); } -static u32 hmc_ecc_writel(u32 data, u32 reg) +static u32 hmc_ecc_writel(struct altera_sdram_platdata *plat, + u32 data, u32 reg) { - return writel(data, (void __iomem *)SOCFPGA_SDR_ADDRESS + (reg)); + return writel(data, plat->hmc + (reg)); } -static u32 ddr_sch_writel(u32 data, u32 reg) +static u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data, + u32 reg) { - return writel(data, - (void __iomem *)SOCFPGA_SDR_SCHEDULER_ADDRESS + (reg)); + return writel(data, plat->ddr_sch + (reg)); } int match_ddr_conf(u32 ddr_conf) @@ -83,37 +99,38 @@ int match_ddr_conf(u32 ddr_conf) return 0; } -static int emif_clear(void) +static int emif_clear(struct altera_sdram_platdata *plat) { - hmc_ecc_writel(0, RSTHANDSHAKECTRL); + hmc_ecc_writel(plat, 0, RSTHANDSHAKECTRL); - return wait_for_bit_le32((const void *)(SOCFPGA_SDR_ADDRESS + + return wait_for_bit_le32((const void *)(plat->hmc + RSTHANDSHAKESTAT), DDR_HMC_RSTHANDSHAKE_MASK, false, 1000, false); } -static int emif_reset(void) +static int emif_reset(struct altera_sdram_platdata *plat) { u32 c2s, s2c, ret; - c2s = hmc_ecc_readl(RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK; - s2c = hmc_ecc_readl(RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK; + c2s = hmc_ecc_readl(plat, RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK; + s2c = hmc_ecc_readl(plat, RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK; debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n", - c2s, s2c, hmc_readl(NIOSRESERVED0), hmc_readl(NIOSRESERVED1), - hmc_readl(NIOSRESERVED2), hmc_readl(DRAMSTS)); + c2s, s2c, hmc_readl(plat, NIOSRESERVED0), + hmc_readl(plat, NIOSRESERVED1), hmc_readl(plat, NIOSRESERVED2), + hmc_readl(plat, DRAMSTS)); - if (s2c && emif_clear()) { + if (s2c && emif_clear(plat)) { printf("DDR: emif_clear() failed\n"); return -1; } debug("DDR: Triggerring emif reset\n"); - hmc_ecc_writel(DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL); + hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL); /* if seq2core[3] = 0, we are good */ - ret = wait_for_bit_le32((const void *)(SOCFPGA_SDR_ADDRESS + + ret = wait_for_bit_le32((const void *)(plat->hmc + RSTHANDSHAKESTAT), DDR_HMC_SEQ2CORE_INT_RESP_MASK, false, 1000, false); @@ -122,7 +139,7 @@ static int emif_reset(void) return ret; } - ret = emif_clear(); + ret = emif_clear(plat); if (ret) { printf("DDR: emif_clear() failed\n"); return ret; @@ -240,13 +257,37 @@ static void sdram_size_check(bd_t *bd) debug("DDR: SDRAM size check passed!\n"); } +/** + * sdram_calculate_size() - Calculate SDRAM size + * + * Calculate SDRAM device size based on SDRAM controller parameters. + * Size is specified in bytes. + */ +static phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat) +{ + u32 dramaddrw = hmc_readl(plat, DRAMADDRW); + + phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) + + DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) + + DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) + + DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) + + DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw)); + + size *= (2 << (hmc_ecc_readl(plat, DDRIOCTRL) & + DDR_HMC_DDRIOCTRL_IOSIZE_MSK)); + + return size; +} + /** * sdram_mmr_init_full() - Function to initialize SDRAM MMR * * Initialize the SDRAM MMR. */ -int sdram_mmr_init_full(unsigned int unused) +static int sdram_mmr_init_full(struct udevice *dev) { + struct altera_sdram_platdata *plat = dev->platdata; + struct altera_sdram_priv *priv = dev_get_priv(dev); u32 update_value, io48_value, ddrioctl; u32 i; int ret; @@ -303,19 +344,16 @@ int sdram_mmr_init_full(unsigned int unused) return -1; } - /* release DDR scheduler from reset */ - socfpga_per_reset(SOCFPGA_RESET(SDR), 0); - /* Try 3 times to do a calibration */ for (i = 0; i < 3; i++) { - ret = wait_for_bit_le32((const void *)(SOCFPGA_SDR_ADDRESS + + ret = wait_for_bit_le32((const void *)(plat->hmc + DDRCALSTAT), DDR_HMC_DDRCALSTAT_CAL_MSK, true, 1000, false); if (!ret) break; - emif_reset(); + emif_reset(plat); } if (ret) { @@ -324,16 +362,16 @@ int sdram_mmr_init_full(unsigned int unused) } debug("DDR: Calibration success\n"); - u32 ctrlcfg0 = hmc_readl(CTRLCFG0); - u32 ctrlcfg1 = hmc_readl(CTRLCFG1); - u32 dramaddrw = hmc_readl(DRAMADDRW); - u32 dramtim0 = hmc_readl(DRAMTIMING0); - u32 caltim0 = hmc_readl(CALTIMING0); - u32 caltim1 = hmc_readl(CALTIMING1); - u32 caltim2 = hmc_readl(CALTIMING2); - u32 caltim3 = hmc_readl(CALTIMING3); - u32 caltim4 = hmc_readl(CALTIMING4); - u32 caltim9 = hmc_readl(CALTIMING9); + u32 ctrlcfg0 = hmc_readl(plat, CTRLCFG0); + u32 ctrlcfg1 = hmc_readl(plat, CTRLCFG1); + u32 dramaddrw = hmc_readl(plat, DRAMADDRW); + u32 dramtim0 = hmc_readl(plat, DRAMTIMING0); + u32 caltim0 = hmc_readl(plat, CALTIMING0); + u32 caltim1 = hmc_readl(plat, CALTIMING1); + u32 caltim2 = hmc_readl(plat, CALTIMING2); + u32 caltim3 = hmc_readl(plat, CALTIMING3); + u32 caltim4 = hmc_readl(plat, CALTIMING4); + u32 caltim9 = hmc_readl(plat, CALTIMING9); /* * Configure the DDR IO size [0xFFCFB008] @@ -349,12 +387,12 @@ int sdram_mmr_init_full(unsigned int unused) * bit[9:6] = Minor Release # * bit[14:10] = Major Release # */ - update_value = hmc_readl(NIOSRESERVED0); - hmc_ecc_writel(((update_value & 0xFF) >> 5), DDRIOCTRL); - ddrioctl = hmc_ecc_readl(DDRIOCTRL); + update_value = hmc_readl(plat, NIOSRESERVED0); + hmc_ecc_writel(plat, ((update_value & 0xFF) >> 5), DDRIOCTRL); + ddrioctl = hmc_ecc_readl(plat, DDRIOCTRL); /* enable HPS interface to HMC */ - hmc_ecc_writel(DDR_HMC_HPSINTFCSEL_ENABLE_MASK, HPSINTFCSEL); + hmc_ecc_writel(plat, DDR_HMC_HPSINTFCSEL_ENABLE_MASK, HPSINTFCSEL); /* Set the DDR Configuration */ io48_value = DDR_CONFIG(CTRLCFG1_CFG_ADDR_ORDER(ctrlcfg1), @@ -365,10 +403,10 @@ int sdram_mmr_init_full(unsigned int unused) update_value = match_ddr_conf(io48_value); if (update_value) - ddr_sch_writel(update_value, DDR_SCH_DDRCONF); + ddr_sch_writel(plat, update_value, DDR_SCH_DDRCONF); /* Configure HMC dramaddrw */ - hmc_ecc_writel(hmc_readl(DRAMADDRW), DRAMADDRWIDTH); + hmc_ecc_writel(plat, hmc_readl(plat, DRAMADDRW), DRAMADDRWIDTH); /* * Configure DDR timing @@ -392,7 +430,7 @@ int sdram_mmr_init_full(unsigned int unused) CALTIMING0_CFG_ACT_TO_RDWR(caltim0) + CALTIMING4_CFG_PCH_TO_VALID(caltim4)); - ddr_sch_writel(((CALTIMING0_CFG_ACT_TO_ACT(caltim0) << + ddr_sch_writel(plat, ((CALTIMING0_CFG_ACT_TO_ACT(caltim0) << DDR_SCH_DDRTIMING_ACTTOACT_OFF) | (update_value << DDR_SCH_DDRTIMING_RDTOMISS_OFF) | (io48_value << DDR_SCH_DDRTIMING_WRTOMISS_OFF) | @@ -406,12 +444,12 @@ int sdram_mmr_init_full(unsigned int unused) DDR_SCH_DDRTIMING); /* Configure DDR mode [precharge = 0] */ - ddr_sch_writel(((ddrioctl ? 0 : 1) << + ddr_sch_writel(plat, ((ddrioctl ? 0 : 1) << DDR_SCH_DDRMOD_BWRATIOEXTENDED_OFF), DDR_SCH_DDRMODE); /* Configure the read latency */ - ddr_sch_writel((DRAMTIMING0_CFG_TCL(dramtim0) >> 1) + + ddr_sch_writel(plat, (DRAMTIMING0_CFG_TCL(dramtim0) >> 1) + DDR_READ_LATENCY_DELAY, DDR_SCH_READ_LATENCY); @@ -419,7 +457,7 @@ int sdram_mmr_init_full(unsigned int unused) * Configuring timing values concerning activate commands * [FAWBANK alway 1 because always 4 bank DDR] */ - ddr_sch_writel(((CALTIMING0_CFG_ACT_TO_ACT_DB(caltim0) << + ddr_sch_writel(plat, ((CALTIMING0_CFG_ACT_TO_ACT_DB(caltim0) << DDR_SCH_ACTIVATE_RRD_OFF) | (CALTIMING9_CFG_4_ACT_TO_ACT(caltim9) << DDR_SCH_ACTIVATE_FAW_OFF) | @@ -431,7 +469,7 @@ int sdram_mmr_init_full(unsigned int unused) * Configuring timing values concerning device to device data bus * ownership change */ - ddr_sch_writel(((CALTIMING1_CFG_RD_TO_RD_DC(caltim1) << + ddr_sch_writel(plat, ((CALTIMING1_CFG_RD_TO_RD_DC(caltim1) << DDR_SCH_DEVTODEV_BUSRDTORD_OFF) | (CALTIMING1_CFG_RD_TO_WR_DC(caltim1) << DDR_SCH_DEVTODEV_BUSRDTOWR_OFF) | @@ -440,7 +478,7 @@ int sdram_mmr_init_full(unsigned int unused) DDR_SCH_DEVTODEV); /* assigning the SDRAM size */ - unsigned long long size = sdram_calculate_size(); + unsigned long long size = sdram_calculate_size(plat); /* If the size is invalid, use default Config size */ if (size <= 0) hw_size = PHYS_SDRAM_1_SIZE; @@ -462,18 +500,17 @@ int sdram_mmr_init_full(unsigned int unused) /* Enable or disable the SDRAM ECC */ if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) { - setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1, + setbits_le32(plat->hmc + ECCCTRL1, (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK | DDR_HMC_ECCCTL_CNT_RST_SET_MSK | DDR_HMC_ECCCTL_ECC_EN_SET_MSK)); - clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1, + clrbits_le32(plat->hmc + ECCCTRL1, (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK | DDR_HMC_ECCCTL_CNT_RST_SET_MSK)); - setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL2, + setbits_le32(plat->hmc + ECCCTRL2, (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK | DDR_HMC_ECCCTL2_AWB_EN_SET_MSK)); - writel(DDR_HMC_ERRINTEN_INTMASK, - SOCFPGA_SDR_ADDRESS + ERRINTENS); + hmc_ecc_writel(plat, DDR_HMC_ERRINTEN_INTMASK, ERRINTENS); /* Enable non-secure writes to HMC Adapter for SDRAM ECC */ writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR); @@ -482,39 +519,100 @@ int sdram_mmr_init_full(unsigned int unused) if (!cpu_has_been_warmreset()) sdram_init_ecc_bits(&bd); } else { - clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1, + clrbits_le32(plat->hmc + ECCCTRL1, (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK | DDR_HMC_ECCCTL_CNT_RST_SET_MSK | DDR_HMC_ECCCTL_ECC_EN_SET_MSK)); - clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL2, + clrbits_le32(plat->hmc + ECCCTRL2, (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK | DDR_HMC_ECCCTL2_AWB_EN_SET_MSK)); } sdram_size_check(&bd); + priv->info.base = bd.bi_dram[0].start; + priv->info.size = gd->ram_size; + debug("DDR: HMC init success\n"); return 0; } -/** - * sdram_calculate_size() - Calculate SDRAM size - * - * Calculate SDRAM device size based on SDRAM controller parameters. - * Size is specified in bytes. - */ -phys_size_t sdram_calculate_size(void) +static int altera_sdram_ofdata_to_platdata(struct udevice *dev) { - u32 dramaddrw = hmc_readl(DRAMADDRW); + struct altera_sdram_platdata *plat = dev->platdata; + fdt_addr_t addr; - phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) + - DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) + - DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) + - DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) + - DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw)); + addr = dev_read_addr_index(dev, 0); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + plat->ddr_sch = (void __iomem *)addr; - size *= (2 << (hmc_ecc_readl(DDRIOCTRL) & - DDR_HMC_DDRIOCTRL_IOSIZE_MSK)); + addr = dev_read_addr_index(dev, 1); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + plat->iomhc = (void __iomem *)addr; - return size; + addr = dev_read_addr_index(dev, 2); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + plat->hmc = (void __iomem *)addr; + + return 0; +} + +static int altera_sdram_probe(struct udevice *dev) +{ + int ret; + struct reset_ctl_bulk resets; + + ret = reset_get_bulk(dev, &resets); + if (ret) { + dev_err(dev, "Can't get reset: %d\n", ret); + return -ENODEV; + } + reset_deassert_bulk(&resets); + + if (sdram_mmr_init_full(dev) != 0) { + puts("SDRAM init failed.\n"); + goto failed; + } + + return 0; + +failed: + reset_release_bulk(&resets); + return -ENODEV; } + +static int altera_sdram_get_info(struct udevice *dev, + struct ram_info *info) +{ + struct altera_sdram_priv *priv = dev_get_priv(dev); + + info->base = priv->info.base; + info->size = priv->info.size; + + return 0; +} + +static struct ram_ops altera_sdram_ops = { + .get_info = altera_sdram_get_info, +}; + +static const struct udevice_id altera_sdram_ids[] = { + { .compatible = "altr,sdr-ctl-s10" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(altera_sdram) = { + .name = "altr_sdr_ctl", + .id = UCLASS_RAM, + .of_match = altera_sdram_ids, + .ops = &altera_sdram_ops, + .ofdata_to_platdata = altera_sdram_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct altera_sdram_platdata), + .probe = altera_sdram_probe, + .priv_auto_alloc_size = sizeof(struct altera_sdram_priv), +}; + +#endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/mach-socfpga/include/mach/sdram_s10.h b/drivers/ddr/altera/sdram_s10.h similarity index 97% rename from arch/arm/mach-socfpga/include/mach/sdram_s10.h rename to drivers/ddr/altera/sdram_s10.h index f39206ca1e..096c06cba2 100644 --- a/arch/arm/mach-socfpga/include/mach/sdram_s10.h +++ b/drivers/ddr/altera/sdram_s10.h @@ -7,10 +7,6 @@ #ifndef _SDRAM_S10_H_ #define _SDRAM_S10_H_ -phys_size_t sdram_calculate_size(void); -int sdram_mmr_init_full(unsigned int sdr_phy_reg); -int sdram_calibration_full(void); - #define DDR_TWR 15 #define DDR_READ_LATENCY_DELAY 40 #define DDR_ACTIVATE_FAWBANK 0x1 diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h index 31c267f55d..2af808cadf 100644 --- a/include/configs/socfpga_stratix10_socdk.h +++ b/include/configs/socfpga_stratix10_socdk.h @@ -129,11 +129,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_SYS_MEMTEST_START 0 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE - 0x200000 -/* - * SDRAM controller - */ -#define CONFIG_ALTERA_SDRAM - /* * Serial / UART configurations */ -- 2.19.0

3 7

[U-Boot] [PATCH v2] ARM: am335x: Add phyCORE AM335x R2 support
by Niel Fourie 02 May '19

02 May '19

Support for Phytech phyCORE AM335x R2 SOM (PCL060) on the Phytec phyBOARD-Wega AM335x. CPU : AM335X-GP rev 2.1 Model: Phytec AM335x phyBOARD-WEGA DRAM: 256 MiB NAND: 256 MiB MMC: OMAP SD/MMC: 0 eth0: ethernet@4a100000 Working: - Eth0 - i2C - MMC/SD - NAND - UART - USB (host) Signed-off-by: Niel Fourie <lusus(a)denx.de> --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/am335x-phycore-som.dtsi | 322 +++++++++++++++++++++ arch/arm/dts/am335x-wega-rdk-u-boot.dtsi | 40 +++ arch/arm/dts/am335x-wega-rdk.dts | 23 ++ arch/arm/dts/am335x-wega.dtsi | 230 +++++++++++++++ arch/arm/mach-omap2/Kconfig | 1 + arch/arm/mach-omap2/am33xx/Kconfig | 7 + board/phytec/phycore_am335x_r2/Kconfig | 15 + board/phytec/phycore_am335x_r2/MAINTAINERS | 7 + board/phytec/phycore_am335x_r2/Makefile | 11 + board/phytec/phycore_am335x_r2/board.c | 262 +++++++++++++++++ board/phytec/phycore_am335x_r2/board.h | 24 ++ board/phytec/phycore_am335x_r2/mux.c | 117 ++++++++ configs/phycore-am335x-r2-wega_defconfig | 79 +++++ include/configs/phycore_am335x_r2.h | 138 +++++++++ 15 files changed, 1278 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/am335x-phycore-som.dtsi create mode 100644 arch/arm/dts/am335x-wega-rdk-u-boot.dtsi create mode 100644 arch/arm/dts/am335x-wega-rdk.dts create mode 100644 arch/arm/dts/am335x-wega.dtsi create mode 100644 board/phytec/phycore_am335x_r2/Kconfig create mode 100644 board/phytec/phycore_am335x_r2/MAINTAINERS create mode 100644 board/phytec/phycore_am335x_r2/Makefile create mode 100644 board/phytec/phycore_am335x_r2/board.c create mode 100644 board/phytec/phycore_am335x_r2/board.h create mode 100644 board/phytec/phycore_am335x_r2/mux.c create mode 100644 configs/phycore-am335x-r2-wega_defconfig create mode 100644 include/configs/phycore_am335x_r2.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 5fe998914a..0a876997ed 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -253,7 +253,8 @@ dtb-$(CONFIG_AM33XX) += \ am335x-chiliboard.dtb \ am335x-sl50.dtb \ am335x-base0033.dtb \ - am335x-guardian.dtb + am335x-guardian.dtb \ + am335x-wega-rdk.dtb dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \ am43x-epos-evm.dtb \ am437x-idk-evm.dtb \ diff --git a/arch/arm/dts/am335x-phycore-som.dtsi b/arch/arm/dts/am335x-phycore-som.dtsi new file mode 100644 index 0000000000..8d7c19e5e1 --- /dev/null +++ b/arch/arm/dts/am335x-phycore-som.dtsi @@ -0,0 +1,322 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2015 Phytec Messtechnik GmbH + * Author: Teresa Remmet <t.remmet(a)phytec.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "am33xx.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + model = "Phytec AM335x phyCORE"; + compatible = "phytec,am335x-phycore-som", "ti,am33xx"; + + aliases { + rtc0 = &i2c_rtc; + rtc1 = &rtc; + }; + + cpus { + cpu@0 { + cpu0-supply = <&vdd1_reg>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + regulators { + compatible = "simple-bus"; + + vcc5v: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + }; +}; + +/* Crypto Module */ +&aes { + status = "okay"; +}; + +&sham { + status = "okay"; +}; + +/* Ethernet */ +&am33xx_pinmux { + ethernet0_pins: pinmux_ethernet0 { + pinctrl-single,pins = < + AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ + AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ + AM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE1) /* mii1_txen.rmii1_txen */ + AM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ + AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ + AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ + AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ + AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */ + >; + }; + + mdio_pins: pinmux_mdio { + pinctrl-single,pins = < + /* MDIO */ + AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; +}; + +&cpsw_emac0 { + phy-handle = <&phy0>; + phy-mode = "rmii"; + dual_emac_res_vlan = <1>; +}; + +&davinci_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&mac { + slaves = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&ethernet0_pins>; + status = "okay"; +}; + +/* I2C Busses */ +&am33xx_pinmux { + i2c0_pins: pinmux_i2c0 { + pinctrl-single,pins = < + AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <400000>; + status = "okay"; + + tps: pmic@2d { + reg = <0x2d>; + }; + + i2c_tmp102: temp@4b { + compatible = "ti,tmp102"; + reg = <0x4b>; + status = "disabled"; + }; + + i2c_eeprom: eeprom@52 { + compatible = "atmel,24c32"; + pagesize = <32>; + reg = <0x52>; + status = "disabled"; + }; + + i2c_rtc: rtc@68 { + compatible = "microcrystal,rv4162"; + reg = <0x68>; + status = "disabled"; + }; +}; + +/* NAND memory */ +&am33xx_pinmux { + nandflash_pins: pinmux_nandflash { + pinctrl-single,pins = < + AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ + AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ + AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ + AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ + AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ + AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ + AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ + AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ + AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ + AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ + AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ + AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ + AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ + AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + >; + }; +}; + +&elm { + status = "okay"; +}; + +&gpmc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&nandflash_pins>; + ranges = <0 0 0x08000000 0x1000000>; /* CS0: NAND */ + nandflash: nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ + nand-bus-width = <8>; + ti,nand-ecc-opt = "bch8"; + gpmc,device-nand = "true"; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <30>; + gpmc,cs-wr-off-ns = <30>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <30>; + gpmc,adv-wr-off-ns = <30>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <20>; + gpmc,oe-on-ns = <10>; + gpmc,oe-off-ns = <30>; + gpmc,access-ns = <30>; + gpmc,rd-cycle-ns = <30>; + gpmc,wr-cycle-ns = <30>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <50>; + gpmc,cycle2cycle-diffcsen; + gpmc,clk-activation-ns = <0>; + gpmc,wr-access-ns = <30>; + gpmc,wr-data-mux-bus-ns = <0>; + + ti,elm-id = <&elm>; + + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +/* Power */ +#include "tps65910.dtsi" + +&tps { + vcc1-supply = <&vcc5v>; + vcc2-supply = <&vcc5v>; + vcc3-supply = <&vcc5v>; + vcc4-supply = <&vcc5v>; + vcc5-supply = <&vcc5v>; + vcc6-supply = <&vcc5v>; + vcc7-supply = <&vcc5v>; + vccio-supply = <&vcc5v>; + + regulators { + vrtc_reg: regulator@0 { + regulator-always-on; + }; + + vio_reg: regulator@1 { + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + /* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1378000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd3_reg: regulator@4 { + regulator-always-on; + }; + + vdig1_reg: regulator@5 { + regulator-name = "vdig1_1p8v"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vdig2_reg: regulator@6 { + regulator-always-on; + }; + + vpll_reg: regulator@7 { + regulator-always-on; + }; + + vdac_reg: regulator@8 { + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +/* SPI Busses */ +&am33xx_pinmux { + spi0_pins: pinmux_spi0 { + pinctrl-single,pins = < + AM33XX_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_clk.spi0_clk */ + AM33XX_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_d0.spi0_d0 */ + AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */ + AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ + >; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + status = "okay"; + + serial_flash: m25p80@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <48000000>; + reg = <0x0>; + m25p,fast-read; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + }; +}; diff --git a/arch/arm/dts/am335x-wega-rdk-u-boot.dtsi b/arch/arm/dts/am335x-wega-rdk-u-boot.dtsi new file mode 100644 index 0000000000..b7678e98ff --- /dev/null +++ b/arch/arm/dts/am335x-wega-rdk-u-boot.dtsi @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 DENX Software Engineering GmbH + */ + +/ { + chosen { + #address-cells = <1>; + #size-cells = <1>; + + bootargs = "console=ttyO0,115200 earlyprintk"; + stdout-path = &uart0; + }; + + ocp { + u-boot,dm-spl; + u-boot,dm-pre-reloc; + }; + + memory@80000000 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; + }; +}; + +&scm { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&uart0 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&mmc1 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/dts/am335x-wega-rdk.dts b/arch/arm/dts/am335x-wega-rdk.dts new file mode 100644 index 0000000000..fe50f3041a --- /dev/null +++ b/arch/arm/dts/am335x-wega-rdk.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2015 Phytec Messtechnik GmbH + * Author: Teresa Remmet <t.remmet(a)phytec.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "am335x-phycore-som.dtsi" +#include "am335x-wega.dtsi" + +/* SoM */ +&i2c_eeprom { + status = "okay"; +}; + +&i2c_rtc { + status = "okay"; +}; diff --git a/arch/arm/dts/am335x-wega.dtsi b/arch/arm/dts/am335x-wega.dtsi new file mode 100644 index 0000000000..f3e045dfc4 --- /dev/null +++ b/arch/arm/dts/am335x-wega.dtsi @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2015 Phytec Messtechnik GmbH + * Author: Teresa Remmet <t.remmet(a)phytec.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + model = "Phytec AM335x phyBOARD-WEGA"; + compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx"; + + sound: sound_iface { + compatible = "ti,da830-evm-audio"; + }; + + regulators { + compatible = "simple-bus"; + + vcc3v3: fixedregulator1 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + }; +}; + +/* Audio */ +&am33xx_pinmux { + mcasp0_pins: pinmux_mcasp0 { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9AC, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahclkx.mcasp0_ahclkx */ + AM33XX_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */ + AM33XX_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */ + AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0.mcasp0_axr0 */ + AM33XX_IOPAD(0x9A8, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr1.mcasp0_axr1 */ + >; + }; +}; + +&i2c0 { + tlv320aic3007: tlv320aic3007@18 { + compatible = "ti,tlv320aic3007"; + reg = <0x18>; + AVDD-supply = <&vcc3v3>; + IOVDD-supply = <&vcc3v3>; + DRVDD-supply = <&vcc3v3>; + DVDD-supply = <&vdig1_reg>; + status = "okay"; + }; +}; + +&mcasp0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcasp0_pins>; + op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */ + tdm-slots = <2>; + serial-dir = < + 2 1 0 0 /* # 0: INACTIVE, 1: TX, 2: RX */ + >; + tx-num-evt = <16>; + rt-num-evt = <16>; + status = "okay"; +}; + +&sound { + ti,model = "AM335x-Wega"; + ti,audio-codec = <&tlv320aic3007>; + ti,mcasp-controller = <&mcasp0>; + ti,audio-routing = + "Line Out", "LLOUT", + "Line Out", "RLOUT", + "LINE1L", "Line In", + "LINE1R", "Line In"; + clocks = <&mcasp0_fck>; + clock-names = "mclk"; + status = "okay"; +}; + +/* CAN Busses */ +&am33xx_pinmux { + dcan1_pins: pinmux_dcan1 { + pinctrl-single,pins = < + AM33XX_IOPAD(0x968, PIN_OUTPUT_PULLUP | MUX_MODE2) /* uart0_ctsn.d_can1_tx */ + AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE2) /* uart0_rtsn.d_can1_rx */ + >; + }; +}; + +&dcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&dcan1_pins>; + status = "okay"; +}; + +/* Ethernet */ +&am33xx_pinmux { + ethernet1_pins: pinmux_ethernet1 { + pinctrl-single,pins = < + AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1) /* gpmc_a0.mii2_txen */ + AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a1.mii2_rxdv */ + AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1) /* gpmc_a2.mii2_txd3 */ + AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE1) /* gpmc_a3.mii2_txd2 */ + AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1) /* gpmc_a4.mii2_txd1 */ + AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1) /* gpmc_a5.mii2_txd0 */ + AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a6.mii2_txclk */ + AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a7.mii2_rxclk */ + AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a8.mii2_rxd3 */ + AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a9.mii2_rxd2 */ + AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a10.mii2_rxd1 */ + AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a11.mii2_rxd0 */ + AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_wpn.mii2_rxerr */ + AM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_ben1.mii2_col */ + >; + }; +}; + +&cpsw_emac1 { + phy-handle = <&phy1>; + phy-mode = "mii"; + dual_emac_res_vlan = <2>; +}; + +&davinci_mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mac { + slaves = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&ethernet0_pins &ethernet1_pins>; + dual_emac = <1>; +}; + +/* MMC */ +&am33xx_pinmux { + mmc1_pins: pinmux_mmc1 { + pinctrl-single,pins = < + AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ + AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ + AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ + AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ + AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ + AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ + AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE7) /* spi0_cs1.mmc0_sdcd */ + >; + }; +}; + +&mmc1 { + vmmc-supply = <&vcc3v3>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +/* Power */ +&vdig1_reg { + regulator-boot-on; + regulator-always-on; +}; + +/* UARTs */ +&am33xx_pinmux { + uart0_pins: pinmux_uart0 { + pinctrl-single,pins = < + AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ + AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ + AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */ + AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */ + >; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; + +/* USB */ +&cppi41dma { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1 { + dr_mode = "host"; + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index d29f1ca0b5..3fa9dc89b8 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -186,6 +186,7 @@ source "board/ti/am43xx/Kconfig" source "board/ti/am335x/Kconfig" source "board/compulab/cm_t335/Kconfig" source "board/compulab/cm_t43/Kconfig" +source "board/phytec/phycore_am335x_r2/Kconfig" config SPL_LDSCRIPT default "arch/arm/mach-omap2/u-boot-spl.lds" diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig index 500df1aa11..d6b0ea2246 100644 --- a/arch/arm/mach-omap2/am33xx/Kconfig +++ b/arch/arm/mach-omap2/am33xx/Kconfig @@ -156,6 +156,13 @@ config TARGET_ETAMIN select DM_SERIAL imply CMD_DM +config TARGET_PHYCORE_AM335X_R2 + bool "Support phyCORE AM335X R2" + select DM + select DM_GPIO + select DM_SERIAL + imply CMD_DM + config TARGET_PCM051 bool "Support pcm051" select DM diff --git a/board/phytec/phycore_am335x_r2/Kconfig b/board/phytec/phycore_am335x_r2/Kconfig new file mode 100644 index 0000000000..77055e043c --- /dev/null +++ b/board/phytec/phycore_am335x_r2/Kconfig @@ -0,0 +1,15 @@ +if TARGET_PHYCORE_AM335X_R2 + +config SYS_BOARD + default "phycore_am335x_r2" + +config SYS_VENDOR + default "phytec" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "phycore_am335x_r2" + +endif diff --git a/board/phytec/phycore_am335x_r2/MAINTAINERS b/board/phytec/phycore_am335x_r2/MAINTAINERS new file mode 100644 index 0000000000..e56f30fdc0 --- /dev/null +++ b/board/phytec/phycore_am335x_r2/MAINTAINERS @@ -0,0 +1,7 @@ +phyCORE AM335x R2 WEGA BOARD +M: Niel Fourie <lusus(a)denx.de> +M: Parthiban Nallathambi <pn(a)denx.de> +S: Maintained +F: board/phytec/phycore_am335x_r2 +F: include/configs/phycore_am335x_r2.h +F: configs/phycore-am335x-r2-wega_defconfig diff --git a/board/phytec/phycore_am335x_r2/Makefile b/board/phytec/phycore_am335x_r2/Makefile new file mode 100644 index 0000000000..ff6f8b4221 --- /dev/null +++ b/board/phytec/phycore_am335x_r2/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Makefile +# +# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + +ifdef CONFIG_SPL_BUILD +obj-y += mux.o +endif + +obj-y += board.o diff --git a/board/phytec/phycore_am335x_r2/board.c b/board/phytec/phycore_am335x_r2/board.c new file mode 100644 index 0000000000..ece9edcfbd --- /dev/null +++ b/board/phytec/phycore_am335x_r2/board.c @@ -0,0 +1,262 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * board.c + * + * Board functions for Phytec phyCORE-AM335x R2 (pcl060) based boards + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH + * Copyright (C) 2015 Wadim Egorov, PHYTEC Messtechnik GmbH + * Copyright (C) 2019 DENX Software Engineering GmbH + */ + +#include <common.h> +#include <spl.h> +#include <asm/arch/cpu.h> +#include <asm/arch/ddr_defs.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <fdtdec.h> +#include <power/tps65910.h> +#include <jffs2/load_kernel.h> +#include <mtd_node.h> +#include <fdt_support.h> +#include "board.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_SPL_BUILD + +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +#if CONFIG_IS_ENABLED(OS_BOOT) +int spl_start_uboot(void) +{ + return 1; +} +#endif + +/* DDR RAM defines */ +#define DDR_CLK_MHZ 400 /* DDR_DPLL_MULT value */ + +#define OSC (V_OSCK / 1000000) +const struct dpll_params dpll_ddr = { + DDR_CLK_MHZ, OSC - 1, 1, -1, -1, -1, -1}; + +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr; +} + +const struct ctrl_ioregs ioregs = { + .cm0ioctl = 0x18B, + .cm1ioctl = 0x18B, + .cm2ioctl = 0x18B, + .dt0ioctl = 0x18B, + .dt1ioctl = 0x18B, +}; + +static const struct cmd_control ddr3_cmd_ctrl_data = { + .cmd0csratio = 0x80, + .cmd0iclkout = 0x0, + + .cmd1csratio = 0x80, + .cmd1iclkout = 0x0, + + .cmd2csratio = 0x80, + .cmd2iclkout = 0x0, +}; + +enum { + PHYCORE_R2_MT41K128M16JT_256MB, + PHYCORE_R2_MT41K256M16TW107IT_512MB, + PHYCORE_R2_MT41K512M16HA125IT_1024MB, +}; + +struct am335x_sdram_timings { + struct emif_regs ddr3_emif_reg_data; + struct ddr_data ddr3_data; +}; + +static struct am335x_sdram_timings physom_timings[] = { + [PHYCORE_R2_MT41K128M16JT_256MB] = { + .ddr3_emif_reg_data = { + .sdram_config = 0x61C052B2, + .ref_ctrl = 0x00000C30, + .sdram_tim1 = 0x0AAAD4DB, + .sdram_tim2 = 0x26437FDA, + .sdram_tim3 = 0x501F83FF, + .zq_config = 0x50074BE4, + .emif_ddr_phy_ctlr_1 = 0x7, + .ocp_config = 0x003d3d3d, + }, + .ddr3_data = { + .datardsratio0 = 0x36, + .datawdsratio0 = 0x38, + .datafwsratio0 = 0x99, + .datawrsratio0 = 0x73, + }, + }, + [PHYCORE_R2_MT41K256M16TW107IT_512MB] = { + .ddr3_emif_reg_data = { + .sdram_config = 0x61C05332, + .ref_ctrl = 0x00000C30, + .sdram_tim1 = 0x0AAAD4DB, + .sdram_tim2 = 0x266B7FDA, + .sdram_tim3 = 0x501F867F, + .zq_config = 0x50074BE4, + .emif_ddr_phy_ctlr_1 = 0x7, + .ocp_config = 0x003d3d3d, + }, + .ddr3_data = { + .datardsratio0 = 0x37, + .datawdsratio0 = 0x38, + .datafwsratio0 = 0x92, + .datawrsratio0 = 0x72, + }, + }, + [PHYCORE_R2_MT41K512M16HA125IT_1024MB] = { + .ddr3_emif_reg_data = { + .sdram_config = 0x61C053B2, + .ref_ctrl = 0x00000C30, + .sdram_tim1 = 0x0AAAD4DB, + .sdram_tim2 = 0x268F7FDA, + .sdram_tim3 = 0x501F88BF, + .zq_config = 0x50074BE4, + .emif_ddr_phy_ctlr_1 = 0x7, + .ocp_config = 0x003d3d3d, + }, + .ddr3_data = { + .datardsratio0 = 0x38, + .datawdsratio0 = 0x4d, + .datafwsratio0 = 0x9d, + .datawrsratio0 = 0x82, + }, + }, +}; + +void sdram_init(void) +{ + int ram_type_index = PHYCORE_R2_MT41K128M16JT_256MB; + + if (fdtdec_setup_mem_size_base()) + gd->ram_size = SZ_256M; + + switch (gd->ram_size) { + case SZ_1G: + ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB; + break; + case SZ_512M: + ram_type_index = PHYCORE_R2_MT41K256M16TW107IT_512MB; + break; + case SZ_256M: + default: + ram_type_index = PHYCORE_R2_MT41K128M16JT_256MB; + } + + config_ddr(DDR_CLK_MHZ, &ioregs, + &physom_timings[ram_type_index].ddr3_data, + &ddr3_cmd_ctrl_data, + &physom_timings[ram_type_index].ddr3_emif_reg_data, 0); +} + +const struct dpll_params *get_dpll_mpu_params(void) +{ + int ind = get_sys_clk_index(); + int freq = am335x_get_efuse_mpu_max_freq(cdev); + + switch (freq) { + case MPUPLL_M_1000: + return &dpll_mpu_opp[ind][5]; + case MPUPLL_M_800: + return &dpll_mpu_opp[ind][4]; + case MPUPLL_M_720: + return &dpll_mpu_opp[ind][3]; + case MPUPLL_M_600: + return &dpll_mpu_opp[ind][2]; + case MPUPLL_M_500: + return &dpll_mpu_opp100; + case MPUPLL_M_300: + return &dpll_mpu_opp[ind][0]; + } + + return &dpll_mpu_opp[ind][0]; +} + +void scale_vcores_generic(int freq) +{ + int sil_rev, mpu_vdd; + + /* + * We use a TPS65910 PMIC. For all MPU frequencies we support we use a + * CORE voltage of 1.10V. For MPU voltage we need to switch based on + * the frequency we are running at. + */ +#ifndef CONFIG_DM_I2C + if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) + return; +#else + if (power_tps65910_init(0)) + return; +#endif + /* + * Depending on MPU clock and PG we will need a different + * VDD to drive at that speed. + */ + sil_rev = readl(&cdev->deviceid) >> 28; + mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq); + + /* Tell the TPS65910 to use i2c */ + tps65910_set_i2c_control(); + + /* First update MPU voltage. */ + if (tps65910_voltage_update(MPU, mpu_vdd)) + return; + + /* Second, update the CORE voltage. */ + if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0)) + return; +} + +void scale_vcores(void) +{ + int freq; + + freq = am335x_get_efuse_mpu_max_freq(cdev); + scale_vcores_generic(freq); +} + +void set_uart_mux_conf(void) +{ + enable_uart0_pin_mux(); +} + +void set_mux_conf_regs(void) +{ + enable_i2c0_pin_mux(); + enable_board_pin_mux(); +} +#endif + +/* + * Basic board specific setup. Pinmux has been handled already. + */ +int board_init(void) +{ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + return 0; +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ +#ifdef CONFIG_FDT_FIXUP_PARTITIONS + static const struct node_info nodes[] = { + { "ti,omap2-nand", MTD_DEV_TYPE_NAND, }, + }; + + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); +#endif + return 0; +} +#endif diff --git a/board/phytec/phycore_am335x_r2/board.h b/board/phytec/phycore_am335x_r2/board.h new file mode 100644 index 0000000000..68c3d56aa5 --- /dev/null +++ b/board/phytec/phycore_am335x_r2/board.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * board.h + * + * Phytec phyCORE-AM335x (pcl060) boards information header + * + * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH + * Copyright (C) 2019 DENX Software Engineering GmbH + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * We have three pin mux functions that must exist. We must be able to enable + * uart0, for initial output and i2c0 to access the PMIC. We then have a main + * pinmux function that can be overridden to enable all other pinmux that + * is required on the board. + */ +void enable_uart0_pin_mux(void); +void enable_i2c0_pin_mux(void); +void enable_board_pin_mux(void); +void enable_cbmux_pin_mux(void); +#endif diff --git a/board/phytec/phycore_am335x_r2/mux.c b/board/phytec/phycore_am335x_r2/mux.c new file mode 100644 index 0000000000..5fd452e66d --- /dev/null +++ b/board/phytec/phycore_am335x_r2/mux.c @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * mux.c + * + * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH + * Copyright (C) 2019 DENX Software Engineering GmbH + */ + +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/hardware.h> +#include <asm/arch/mux.h> +#include <asm/io.h> +#include "board.h" + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ + {-1}, +}; + +#ifdef CONFIG_MMC +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ + {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ + {-1}, +}; +#endif + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ + {-1}, +}; + +#ifdef CONFIG_SPI +static struct module_pin_mux spi0_pin_mux[] = { + {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */ + {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | + PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */ + {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */ + {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | + PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */ + {-1}, +}; +#endif + +static struct module_pin_mux rmii1_pin_mux[] = { + {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */ + {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */ + {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */ + {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */ + {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */ + {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */ + {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */ + {-1}, +}; + +static struct module_pin_mux cbmux_pin_mux[] = { + {OFFSET(uart0_ctsn), MODE(7) | RXACTIVE | PULLDOWN_EN}, /* JP3 */ + {OFFSET(uart0_rtsn), MODE(7) | RXACTIVE | PULLUP_EN}, /* JP4 */ + {-1}, +}; + +#ifdef CONFIG_NAND +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ + {-1}, +}; +#endif + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + +void enable_board_pin_mux(void) +{ + configure_module_pin_mux(rmii1_pin_mux); + configure_module_pin_mux(mmc0_pin_mux); + configure_module_pin_mux(cbmux_pin_mux); +#ifdef CONFIG_NAND + configure_module_pin_mux(nand_pin_mux); +#endif +#ifdef CONFIG_SPI + configure_module_pin_mux(spi0_pin_mux); +#endif +} diff --git a/configs/phycore-am335x-r2-wega_defconfig b/configs/phycore-am335x-r2-wega_defconfig new file mode 100644 index 0000000000..832b3b41b0 --- /dev/null +++ b/configs/phycore-am335x-r2-wega_defconfig @@ -0,0 +1,79 @@ +CONFIG_ARM=y +CONFIG_ARCH_OMAP2PLUS=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_AM33XX=y +CONFIG_TARGET_PHYCORE_AM335X_R2=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +# CONFIG_FIT is not set +CONFIG_OF_BOARD_SETUP=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_DEFAULT_FDT_FILE="am335x-wega-rdk.dtb" +CONFIG_VERSION_VARIABLE=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_PAYLOAD="u-boot.img" +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_SPL=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_NAND=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=nand.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),512k(NAND.u-boot),512k(NAND.u-boot.backup1),256k(NAND.u-boot-env),-(NAND.UBI)" +CONFIG_CMD_UBI=y +CONFIG_DOS_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="am335x-wega-rdk" +CONFIG_ENV_IS_IN_FAT=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_FAT_INTERFACE="mmc" +CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_DM_I2C=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_OMAP_HS=y +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y +CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 +CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x100000 +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_OMAP3_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_MUSB_HOST=y +CONFIG_USB_MUSB_GADGET=y +CONFIG_USB_MUSB_TI=y +CONFIG_USB_GADGET=y +CONFIG_USB_ETHER=y +# CONFIG_OMAP_WATCHDOG is not set +CONFIG_FDT_FIXUP_PARTITIONS=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/phycore_am335x_r2.h b/include/configs/phycore_am335x_r2.h new file mode 100644 index 0000000000..a512de8838 --- /dev/null +++ b/include/configs/phycore_am335x_r2.h @@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * phycore_am335x_r2.h + * + * Phytec phyCORE-AM335x R2 (pcl060) boards information header + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH + * Copyright (C) 2019 DENX Software Engineering GmbH + */ + +#ifndef __CONFIG_PHYCORE_AM335x_R2_H +#define __CONFIG_PHYCORE_AM335x_R2_H + +#include <configs/ti_am335x_common.h> + +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_MACH_TYPE MACH_TYPE_SBC_PHYCORE_AM335X +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 + +#ifdef CONFIG_NAND +#define NANDARGS \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "nandargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "nandroot=ubi0:root ubi.mtd=NAND.UBI\0" \ + "nandrootfstype=ubifs rootwait rw fsck.repair=yes\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "ubi part NAND.UBI; " \ + "ubi readvol ${fdtaddr} oftree; " \ + "ubi readvol ${loadaddr} kernel; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" + +#else +#define NANDARGS "" +#endif + +/* set to negative value for no autoboot */ +#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=" \ + "setenv mmcdev " #instance "; "\ + "setenv bootpart " #instance ":1 ; "\ + "setenv rootpart " #instance ":2 ; "\ + "run mmcboot\0" + +#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \ + #devtypel #instance " " + +#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=" \ + "run nandboot\0" + +#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ + #devtypel #instance " " + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(LEGACY_MMC, legacy_mmc, 0) \ + func(MMC, mmc, 1) \ + func(LEGACY_MMC, legacy_mmc, 1) \ + func(NAND, nand, 0) + +#include <config_distro_bootcmd.h> +#include <environment/ti/dfu.h> +#include <environment/ti/mmc.h> + +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_MMC_TI_ARGS \ + DEFAULT_LINUX_BOOT_ENV \ + "bootfile=zImage\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "console=ttyO0,115200n8\0" \ + "optargs=\0" \ + "mmcrootfstype=ext2 rootwait\0" \ + "finduuid=part uuid mmc ${rootpart} uuid\0" \ + "boot_fit=0\0" \ + NANDARGS \ + BOOTENV + +/* Clock Defines */ +#define V_OSCK 25000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +#define CONFIG_POWER_TPS65910 + +#ifdef CONFIG_NAND +/* NAND: device related configs */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +/* NAND: driver related configs */ +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW + +/* NAND: SPL related configs */ +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */ +#endif +#endif /* !CONFIG_NAND */ + +/* CPU */ + +#ifdef CONFIG_SPI_BOOT +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 +#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 +#elif defined(CONFIG_ENV_IS_IN_NAND) +#define CONFIG_ENV_OFFSET 0x000a0000 +#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#endif + +/* + * USB configuration + */ +#define CONFIG_AM335X_USB0 +#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL +#define CONFIG_AM335X_USB1 +#define CONFIG_AM335X_USB1_MODE MUSB_HOST + +#endif /* ! __CONFIG_PHYCORE_AM335x_R2_H */ -- 2.17.2

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[U-Boot] [PATCH 0/3] Add Avenger96 board support
by Manivannan Sadhasivam 02 May '19

02 May '19

Hello, This patchset adds board support for Avenger96, a 96Boards Consumer Edition board from Arrow Electronics. This board is based on the STM32MP1 MPU and the board support is added under st boards since there are no significance changes required to boot u-boot on this board other than the dts. More information about this board can be found in 96Boards website: https://www.96boards.org/product/avenger96/ PS: I only managed to boot u-boot as SSBL with TF-A as FSBL. U-boot SPL way of booting is not working. Thanks, Mani Manivannan Sadhasivam (3): arm: dts: stm32mp157: Add missing pinctrl definitions board: stm32mp1: Add Avenger96 board support arm: mach-stm32mp: Add newline to the MAC error message arch/arm/dts/Makefile | 1 + arch/arm/dts/stm32mp157-pinctrl.dtsi | 63 +++ .../arm/dts/stm32mp157a-avenger96-u-boot.dtsi | 177 +++++++++ arch/arm/dts/stm32mp157a-avenger96.dts | 362 ++++++++++++++++++ arch/arm/mach-stm32mp/cpu.c | 2 +- board/st/stm32mp1/README | 23 ++ 6 files changed, 627 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp157a-avenger96.dts -- 2.17.1

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[U-Boot] [RESEND PATCH] board: toradex: drop support.arm maintainer email
by Marcel Ziswiler 02 May '19

02 May '19

From: Marcel Ziswiler <marcel.ziswiler(a)toradex.com> Drop Toradex ARM Support <support.arm(a)toradex.com> from maintainer email list as this just clogs our support ticketing system. Signed-off-by: Marcel Ziswiler <marcel.ziswiler(a)toradex.com> --- board/toradex/colibri-imx6ull/MAINTAINERS | 1 - board/toradex/colibri_imx7/MAINTAINERS | 1 - 2 files changed, 2 deletions(-) diff --git a/board/toradex/colibri-imx6ull/MAINTAINERS b/board/toradex/colibri-imx6ull/MAINTAINERS index 7cda555984..626c1f94f9 100644 --- a/board/toradex/colibri-imx6ull/MAINTAINERS +++ b/board/toradex/colibri-imx6ull/MAINTAINERS @@ -1,6 +1,5 @@ Colibri iMX6ULL M: Stefan Agner <stefan.agner(a)toradex.com> -M: Toradex ARM Support <support.arm(a)toradex.com> W: http://developer.toradex.com/software/linux/linux-software W: https://www.toradex.com/community S: Maintained diff --git a/board/toradex/colibri_imx7/MAINTAINERS b/board/toradex/colibri_imx7/MAINTAINERS index f55f8045f4..cd0f9c9b2d 100644 --- a/board/toradex/colibri_imx7/MAINTAINERS +++ b/board/toradex/colibri_imx7/MAINTAINERS @@ -1,6 +1,5 @@ Colibri iMX7 M: Stefan Agner <stefan.agner(a)toradex.com> -M: Toradex ARM Support <support.arm(a)toradex.com> W: http://developer.toradex.com/software/linux/linux-software W: https://www.toradex.com/community S: Maintained -- 2.20.1

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[U-Boot] [PATCH v6 0/3] arm64: rockchip: dts: Add rk3399 -u-boot.dtsi files
by Jagan Teki 02 May '19

02 May '19

This series is a rework of v5 patch that send it in separate series[1] All these changes are creating an initial rk3399-u-boot.dtsi and rk3399 board -u-boot.dtsi files and u-boot specific dts changes like - sdram dtsi - sdmmc, u-boot,dm-pre-reloc - spi1, u-boot,dm-pre-reloc Changes for v6: - spilt the existing patch[1] into multiple patches and send as a separate series. [1] https://patchwork.ozlabs.org/patch/1091720/ Any inputs? Jagan. Jagan Teki (3): arm64: rockchip: dts: rk3399: Add board -u-boot.dtsi files arm64: rockchip: dts: Add initial rk3399-u-boot.dtsi file arm64: rockchip: dts: rk3399: Use rk3399-u-boot.dtsi arch/arm/dts/rk3399-evb-u-boot.dtsi | 7 +++++++ arch/arm/dts/rk3399-evb.dts | 2 -- arch/arm/dts/rk3399-ficus-u-boot.dtsi | 6 ++++++ arch/arm/dts/rk3399-ficus.dts | 1 - arch/arm/dts/rk3399-firefly-u-boot.dtsi | 7 +++++++ arch/arm/dts/rk3399-firefly.dts | 2 -- arch/arm/dts/rk3399-gru-bob-u-boot.dtsi | 7 +++++++ arch/arm/dts/rk3399-gru-bob.dts | 1 - arch/arm/dts/rk3399-gru-u-boot.dtsi | 6 ++++++ arch/arm/dts/rk3399-gru.dtsi | 1 - arch/arm/dts/rk3399-puma-ddr1600.dts | 1 + arch/arm/dts/rk3399-puma.dtsi | 3 --- arch/arm/dts/rk3399-rock960-u-boot.dtsi | 6 ++++++ arch/arm/dts/rk3399-rock960.dts | 1 - arch/arm/dts/rk3399-u-boot.dtsi | 12 ++++++++++++ 15 files changed, 52 insertions(+), 11 deletions(-) create mode 100644 arch/arm/dts/rk3399-evb-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-ficus-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-firefly-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-gru-bob-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-gru-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-rock960-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-u-boot.dtsi -- 2.18.0.321.gffc6fa0e3

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[U-Boot] [PATCH] core: ofnode: Fix ASAN-reported stack-buffer-overflow in of_get_address
by Eugeniu Rosca 02 May '19

02 May '19

v2019.04-rc3 sandbox U-Boot fails to boot when compiled with -fsanitize=address and linked against -lasan, reporting [1]. Git bisecting shows that the issue is contributed by v2019.01 commit 1678754f5e2c ("core: ofnode: Fix ofnode_get_addr_index function"). The root cause seems to be the mismatch between sizeof(u64) and sizeof(fdt_size_t) on sandbox. Luckily, thanks to the fact that the size argument of both of_get_address() and fdtdec_get_addr_size_fixed() is optional, we can pass NULL in its place, avoiding the problem. [1] Backtrace reported by ASAN (gcc 8.1.0): $> ./u-boot -d arch/sandbox/dts/sandbox.dtb [..] ================================================================= ==10998==ERROR: AddressSanitizer: stack-buffer-overflow on address 0x7ffcc2331140 at pc 0x0000004eeeb0 bp 0x7ffcc2330f80 sp 0x7ffcc2330f70 WRITE of size 8 at 0x7ffcc2331140 thread T0 #0 0x4eeeaf in of_get_address drivers/core/of_addr.c:154 #1 0x4f7441 in ofnode_get_addr_index drivers/core/ofnode.c:263 #2 0x5b2a78 in sb_eth_ofdata_to_platdata drivers/net/sandbox.c:422 #3 0x4dccd8 in device_probe drivers/core/device.c:407 #4 0x753170 in eth_initialize net/eth-uclass.c:428 #5 0x47d9bf in initr_net common/board_r.c:557 #6 0x6bcfa7 in initcall_run_list lib/initcall.c:30 #7 0x47e1fe in board_init_r common/board_r.c:859 #8 0x4060e5 in main arch/sandbox/cpu/start.c:356 #9 0x7fb8d135482f in __libc_start_main (/lib/x86_64-linux-gnu/libc.so.6+0x2082f) #10 0x40a3a8 in _start (/path/to/u-boot/u-boot+0x40a3a8) Address 0x7ffcc2331140 is located in stack of thread T0 at offset 32 in frame #0 0x4f72b8 in ofnode_get_addr_index drivers/core/ofnode.c:255 This frame has 3 object(s): [32, 36) 'size' <== Memory access at offset 32 partially overflows this variable [96, 100) 'flags' [160, 168) 'node' HINT: this may be a false positive if your program uses some custom stack unwind mechanism or swapcontext (longjmp and C++ exceptions *are* supported) SUMMARY: AddressSanitizer: stack-buffer-overflow drivers/core/of_addr.c:154 in of_get_address Shadow bytes around the buggy address: 0x10001845e1d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0x10001845e1e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0x10001845e1f0: 00 00 00 00 00 00 00 00 00 00 00 00 f1 f1 f1 f1 0x10001845e200: 04 f2 f2 f2 f2 f2 f2 f2 04 f2 f2 f2 f2 f2 f2 f2 0x10001845e210: 04 f2 f2 f2 f3 f3 f3 f3 00 00 00 00 00 00 00 00 =>0x10001845e220: 00 00 00 00 f1 f1 f1 f1[04]f2 f2 f2 f2 f2 f2 f2 0x10001845e230: 04 f2 f2 f2 f2 f2 f2 f2 00 f2 f2 f2 f3 f3 f3 f3 0x10001845e240: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0x10001845e250: 00 00 00 00 f1 f1 f1 f1 00 00 f2 f2 f3 f3 f3 f3 0x10001845e260: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f1 f1 0x10001845e270: f1 f1 00 f2 f2 f2 f3 f3 f3 f3 00 00 00 00 00 00 Shadow byte legend (one shadow byte represents 8 application bytes): Addressable: 00 Partially addressable: 01 02 03 04 05 06 07 Heap left redzone: fa Freed heap region: fd Stack left redzone: f1 Stack mid redzone: f2 Stack right redzone: f3 Stack after return: f5 Stack use after scope: f8 Global redzone: f9 Global init order: f6 Poisoned by user: f7 Container overflow: fc Array cookie: ac Intra object redzone: bb ASan internal: fe Left alloca redzone: ca Right alloca redzone: cb ==10998==ABORTING 'To' list: git log --since=1year drivers/core/ofnode.c | grep "\-by: .*@" | \ sed 's/.*-by: //' | sort | uniq -c | sort -rn 10 Simon Glass <sjg(a)chromium.org> 3 Mario Six <mario.six(a)gdsys.cc> 2 Martin Fuzzey <mfuzzey(a)parkeon.com> 2 Marek Vasut <marek.vasut+renesas(a)gmail.com> 1 Tom Rini <trini(a)konsulko.com> 1 Masahiro Yamada <yamada.masahiro(a)socionext.com> 1 Keerthy <j-keerthy(a)ti.com> 1 Jens Wiklander <jens.wiklander(a)linaro.org> 1 Bin Meng <bmeng.cn(a)gmail.com> Fixes: 1678754f5e2c ("core: ofnode: Fix ofnode_get_addr_index function") Signed-off-by: Eugeniu Rosca <erosca(a)de.adit-jv.com> --- drivers/core/ofnode.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index 0e584c12dc88..8bb5e22555f7 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -254,14 +254,13 @@ int ofnode_read_size(ofnode node, const char *propname) fdt_addr_t ofnode_get_addr_index(ofnode node, int index) { int na, ns; - fdt_size_t size; if (ofnode_is_np(node)) { const __be32 *prop_val; uint flags; prop_val = of_get_address(ofnode_to_np(node), index, - (u64 *)&size, &flags); + NULL, &flags); if (!prop_val) return FDT_ADDR_T_NONE; @@ -278,7 +277,7 @@ fdt_addr_t ofnode_get_addr_index(ofnode node, int index) ns = ofnode_read_simple_size_cells(ofnode_get_parent(node)); return fdtdec_get_addr_size_fixed(gd->fdt_blob, ofnode_to_offset(node), "reg", - index, na, ns, &size, true); + index, na, ns, NULL, true); } return FDT_ADDR_T_NONE; -- 2.21.0

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[U-Boot] [PATCH v3 0/3] Move Stratix 10 SDRAM driver to DM
by Ley Foon Tan 02 May '19

02 May '19

Compile ALTERA_SDRAM driver in SPL only and move Stratix 10 SDRAM driver to DM. v2->v3: ------- - Compile ALTERA_SDRAM driver in SPL only - Separate dts change to new patch - Change to use #if CONFIG_IS_ENABLED(ALTERA_SDRAM) - Add _remove() - Remove #ifdef CONFIG_SPL_BUILD checking in sdram_s10.c History: -------- [v1]: https://patchwork.ozlabs.org/patch/1066765/ [v2]: https://patchwork.ozlabs.org/patch/1089957/ Ley Foon Tan (3): ddr: altera: Compile ALTERA SDRAM in SPL only arm: dts: Stratix10: Add SDRAM node arm: socfpga: Move Stratix 10 SDRAM driver to DM Makefile | 2 +- arch/arm/dts/socfpga_stratix10.dtsi | 9 + arch/arm/mach-socfpga/Kconfig | 4 +- arch/arm/mach-socfpga/spl_s10.c | 16 +- configs/socfpga_stratix10_defconfig | 1 + drivers/Makefile | 2 +- drivers/ddr/altera/Kconfig | 11 +- drivers/ddr/altera/Makefile | 2 +- drivers/ddr/altera/sdram_s10.c | 251 ++++++++++++------ .../mach => drivers/ddr/altera}/sdram_s10.h | 4 - include/configs/socfpga_stratix10_socdk.h | 5 - 11 files changed, 208 insertions(+), 99 deletions(-) rename {arch/arm/mach-socfpga/include/mach => drivers/ddr/altera}/sdram_s10.h (97%) -- 2.19.0

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[U-Boot] [PATCH v2 1/2] RISCV: image: Add booti support.
by Atish Patra 01 May '19

01 May '19

This patch adds booti support for RISC-V Linux kernel. The existing bootm method will also continue to work as it is. It depends on the following kernel patch which adds the header to the flat Image. https://patchwork.kernel.org/patch/10913869/ Tested on HiFive Unleashed and QEMU. Signed-off-by: Atish Patra <atish.patra(a)wdc.com> --- arch/riscv/lib/Makefile | 1 + arch/riscv/lib/image.c | 53 +++++++++++++++++++++++++++++++++++++++++ cmd/Kconfig | 2 +- cmd/booti.c | 8 +++++-- 4 files changed, 61 insertions(+), 3 deletions(-) create mode 100644 arch/riscv/lib/image.c diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index 1c332db436a9..6ae6ebbeafda 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -7,6 +7,7 @@ # Rick Chen, Andes Technology Corporation <rick(a)andestech.com> obj-$(CONFIG_CMD_BOOTM) += bootm.o +obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o obj-$(CONFIG_CMD_GO) += boot.o obj-y += cache.o obj-$(CONFIG_RISCV_RDTIME) += rdtime.o diff --git a/arch/riscv/lib/image.c b/arch/riscv/lib/image.c new file mode 100644 index 000000000000..e8802007c446 --- /dev/null +++ b/arch/riscv/lib/image.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Western Digital Corporation or its affiliates. + * Authors: + * Atish Patra <atish.patra(a)wdc.com> + * Based on arm/lib/image.c + */ + +#include <common.h> +#include <mapmem.h> +#include <errno.h> +#include <linux/sizes.h> +#include <linux/stddef.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* ASCII version of "RISCV" defined in Linux kernel */ +#define LINUX_RISCV_IMAGE_MAGIC 0x5643534952 + +struct linux_image_h { + uint32_t code0; /* Executable code */ + uint32_t code1; /* Executable code */ + uint64_t text_offset; /* Image load offset */ + uint64_t image_size; /* Effective Image size */ + uint64_t res1; /* reserved */ + uint64_t magic; /* Magic number */ + uint32_t res2; /* reserved */ + uint32_t res3; /* reserved */ +}; + +int booti_setup(ulong image, ulong *relocated_addr, ulong *size, + bool force_reloc) +{ + struct linux_image_h *lhdr; + + lhdr = (struct linux_image_h *)map_sysmem(image, 0); + + if (lhdr->magic != LINUX_RISCV_IMAGE_MAGIC) { + puts("Bad Linux RISCV Image magic!\n"); + return -EINVAL; + } + + if (lhdr->image_size == 0) { + puts("Image lacks image_size field, error!\n"); + return -EINVAL; + } + *size = lhdr->image_size; + *relocated_addr = gd->ram_base + lhdr->text_offset; + + unmap_sysmem(lhdr); + + return 0; +} diff --git a/cmd/Kconfig b/cmd/Kconfig index 2bdbfcb3d091..d427b66d3714 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -212,7 +212,7 @@ config CMD_BOOTZ config CMD_BOOTI bool "booti" - depends on ARM64 + depends on ARM64 || RISCV default y help Boot an AArch64 Linux Kernel image from memory. diff --git a/cmd/booti.c b/cmd/booti.c index 04353b68eccc..c22ba9bae2e4 100644 --- a/cmd/booti.c +++ b/cmd/booti.c @@ -77,7 +77,11 @@ int do_booti(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) bootm_disable_interrupts(); images.os.os = IH_OS_LINUX; + #ifdef CONFIG_RISCV_SMODE + images.os.arch = IH_ARCH_RISCV; + #elif CONFIG_ARM64 images.os.arch = IH_ARCH_ARM64; + #endif ret = do_bootm_states(cmdtp, flag, argc, argv, #ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH BOOTM_STATE_RAMDISK | @@ -92,7 +96,7 @@ int do_booti(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_LONGHELP static char booti_help_text[] = "[addr [initrd[:size]] [fdt]]\n" - " - boot arm64 Linux Image stored in memory\n" + " - boot arm64/riscv Linux Image stored in memory\n" "\tThe argument 'initrd' is optional and specifies the address\n" "\tof an initrd in memory. The optional parameter ':size' allows\n" "\tspecifying the size of a RAW initrd.\n" @@ -107,5 +111,5 @@ static char booti_help_text[] = U_BOOT_CMD( booti, CONFIG_SYS_MAXARGS, 1, do_booti, - "boot arm64 Linux Image image from memory", booti_help_text + "boot arm64/riscv Linux Image image from memory", booti_help_text ); -- 2.21.0

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Re: [U-Boot] EFIBootGuard for CIP and SecureBoot
by daniel.sangorrin＠toshiba.co.jp 01 May '19

01 May '19

Hello Francois, Jan, Christian, and all Sorry for the late reply, I was waiting for the administrator of the Boot Architecture mailing list to accept my subscription request, but it seems it will take a bit more time. I will send this reply and hope it will not be blocked. I have also added the u-boot mailing list to Cc, as Tom suggested (although I'm not a member), the CIP mailing list, Jan Kiszka (one of the main developers of Efibootguard) and Christian (an expert in software updates). Background: during the last Linaro connect in Bangkok I was told that Linaro Edge (LEDGE) were working on a secure software update mechanism based on UEFI capsules that would flash firmware updates from a UEFI application, instead of using a Linux agent such as SWUpdate. Then, I had an online meeting with Francois, director of LEDGE. I explained to Francois that in CIP we are using the Linux agent approach right now, and we are also considering the use of a UEFI application (Efibootguard) to arm a watchdog and deal with the state-machine variables (installed, testing, ok, failed..) needed for A/B software updates. Efibootguard sounds like an excellent place to collaborate with Linaro (particularly on the watchdog drivers front) because it does not strictly depend on where the firmware is flashed (UEFI capsule or Linux agent). > On Fri, Apr 19, 2019 at 12:48:51PM +0200, Francois Ozog wrote: > > Hi Daniel, > > > > We will be conducting a UEFI gap analysis to support EFIBootGuard in U-Boot. > > > > As we are working on UEFI SecureBoot implementation in U-Boot, how do > > you expect the boot process to be secured? Would U-Boot UEFI > > SecureBoot verify EFIBootGuard signature and in turn EFIBootGuard will > > check either grub or Linux signature? > > > > Please elaborate on your vision of a secured boot process. Efibootguard is composed of two parts. - A UEFI application that can arm a watchdog and decide what environment (kernel, boot args, etc.) to use next depending on a set of variables (update status, highest revision, etc.) stored in FAT16 partitions. - A Linux application that can read and set those variables from Linux (similar to u-boot's fw_setenv). This functionality is also available in the form of a library. As far as I know, there is no concept of "Secure Booting" in Efibootguard at the moment. Adding signature checks before booting into the selected kernel would be a possible solution. Thanks, Daniel

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[U-Boot] [PATCH 0/6] apalis imx8qm 4gb wb it v1.0b module support
by Marcel Ziswiler 01 May '19

01 May '19

This series adds support for more lpuart instances, support for i2c0, i2c1, i2c2, i2c3, i2c4, fixes support for uSDHC2, fixes CPU frequency reporting, fixes fuse driver and last but not least introduces support for the Toradex Apalis iMX8QM 4GB WB IT V1.0B module. This series is available together with the last few clean-up patches and the Colibri iMX8QXP patch series on our git server [1] as well. [1] http://git.toradex.com/cgit/u-boot-toradex.git/log/?h=for-next Marcel Ziswiler (6): arm: dts: imx8qm: add lpuart1, lpuart2, lpuart3, lpuart4 arm: dts: imx8qm: add support for i2c0, i2c1, i2c2, i2c3 and i2c4 clk: imx8qm: fix usdhc2 clocks imx8qm: fix cpu frequency reporting imx8: fuse: fix fuse driver board: toradex: add apalis imx8qm 4gb wb it v1.0b module support arch/arm/dts/Makefile | 1 + arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi | 128 ++++ arch/arm/dts/fsl-imx8qm-apalis.dts | 615 ++++++++++++++++++++ arch/arm/dts/fsl-imx8qm.dtsi | 155 +++++ arch/arm/mach-imx/imx8/Kconfig | 6 + arch/arm/mach-imx/imx8/cpu.c | 3 +- board/toradex/apalis-imx8qm/Kconfig | 30 + board/toradex/apalis-imx8qm/MAINTAINERS | 9 + board/toradex/apalis-imx8qm/Makefile | 6 + board/toradex/apalis-imx8qm/README | 66 +++ board/toradex/apalis-imx8qm/apalis-imx8qm.c | 157 +++++ board/toradex/apalis-imx8qm/imximage.cfg | 24 + configs/apalis-imx8qm_defconfig | 56 ++ drivers/clk/imx/clk-imx8qm.c | 18 + drivers/misc/imx8/fuse.c | 2 - include/configs/apalis-imx8qm.h | 178 ++++++ 16 files changed, 1451 insertions(+), 3 deletions(-) create mode 100644 arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi create mode 100644 arch/arm/dts/fsl-imx8qm-apalis.dts create mode 100644 board/toradex/apalis-imx8qm/Kconfig create mode 100644 board/toradex/apalis-imx8qm/MAINTAINERS create mode 100644 board/toradex/apalis-imx8qm/Makefile create mode 100644 board/toradex/apalis-imx8qm/README create mode 100644 board/toradex/apalis-imx8qm/apalis-imx8qm.c create mode 100644 board/toradex/apalis-imx8qm/imximage.cfg create mode 100644 configs/apalis-imx8qm_defconfig create mode 100644 include/configs/apalis-imx8qm.h -- 2.20.1

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