April 2019 - U-Boot

[U-Boot] [RFC/RESEND 00/22] Add support for Cavium Octeon-TX CN80XX/CN81XX
by Tim Harvey 16 May '19

16 May '19

The Cavium Octeon-TX 64-bit ARM based SoCs include the CN80XX and CN81XX. These SoC's have peripheral drivers based on PCI ECAM. This series has been tested on the the following Gateworks SBC's: - GW6100 - CN8021 dual A53 800MHz - GW6104 - CN8031 quad A53 1500MHz - GW6300 - CN8020 dual A53 800MHz - GW6304 - CN8030 quad A53 1500MHz These patches all came originally from Cavium's SDK based on a 2017 version of U-Boot and have been refactored a bit to strip out things that didn't make sense that I saw in the original code. These patches apply on top of U-Boot 2018.11 and if needed I can do minor cleanup and rebase on top of master but I can't be the maintainer. I'm also looking for comments on the PCI related patches as I am by far not a PCI expert and am not sure what I've done here is correct for this SoC and the others some of the changes would affect. I'm looking for a maintainer for this - I only have boards with the above SoC's and can't test anything else. I also don't have the resources to be a maintainer of this arch - I'm looking at you Cavium/Marvell as your SDK's use old forks of U-Boot with a slew of patches and there is no reason to not mainline this code. I've added all the cavium/marvell contacts I could find from previous threads about OcteonTX support in U-Boot. The way I'm using this on the above boards is to build u-boot-nodtb.bin and package it into a FIP image that the ATF loads. I can document this process if needed. You can find this series on github [1] Best Regards, Tim [1] https://github.com/Gateworks/uboot-newport/tree/v2018.11-newport-rc1 Tim Harvey (22): arm: introduce ARCH_THUNDERX arm: add thunderx_81xx thunderx: add FDT support thunderx: add thunderx register definitions and misc functions thunderx: move DRAM prints to debug dm: pci: add PCI SR-IOV EA support fdt: add fdtdec_get_pci_bus_range pci: add thunderx pci/ecam driver pci: fix pce enumeration on thunderx arm: include 64bit io accessors gpio: add thunderx gpio driver i2c: add thunderx I2C driver spi: add thunderx SPI driver xhci: add support for cavium thunderx XHCI thunderx_81xx: add support for XHCI thunderx_81xx: enable usb mass storage and usb ethernet ahci: support 64bit systems ahci: set n_ports from host caps ahci: add support for ThunderX AHCI thunderx_81xx: add AHCI support net: add thunderx vnic drivers pci: auto probe thunderx NIC devices arch/arm/Kconfig | 6 +- arch/arm/Makefile | 1 + arch/arm/dts/Makefile | 3 +- arch/arm/dts/thunderx-81xx.dts | 36 + arch/arm/dts/thunderx-81xx.dtsi | 440 +++++ .../arm/include/asm/arch-thunderx}/atf.h | 2 +- .../arm/include/asm/arch-thunderx}/atf_part.h | 0 arch/arm/include/asm/arch-thunderx/fdt.h | 12 + arch/arm/include/asm/arch-thunderx/thunderx.h | 300 ++++ .../include/asm/arch-thunderx}/thunderx_svc.h | 0 .../include/asm/arch-thunderx/thunderx_vnic.h | 15 + arch/arm/include/asm/gpio.h | 2 +- arch/arm/include/asm/io.h | 8 + arch/arm/mach-thunderx/Makefile | 2 + .../thunderx => arch/arm/mach-thunderx}/atf.c | 6 +- arch/arm/mach-thunderx/fdt.c | 218 +++ arch/arm/mach-thunderx/lowlevel_init.S | 31 + arch/arm/mach-thunderx/misc.c | 33 + arch/x86/cpu/baytrail/cpu.c | 3 +- board/cavium/thunderx/Kconfig | 23 +- board/cavium/thunderx/Makefile | 2 +- board/cavium/thunderx/thunderx.c | 60 +- configs/thunderx_81xx_defconfig | 65 + configs/thunderx_88xx_defconfig | 9 +- drivers/ata/ahci.c | 46 +- drivers/gpio/Kconfig | 7 + drivers/gpio/Makefile | 1 + drivers/gpio/thunderx_gpio.c | 189 ++ drivers/i2c/Kconfig | 7 + drivers/i2c/Makefile | 1 + drivers/i2c/designware_i2c.c | 4 +- drivers/i2c/intel_i2c.c | 3 +- drivers/i2c/thunderx_i2c.c | 878 ++++++++++ drivers/mmc/pci_mmc.c | 3 +- drivers/net/Kconfig | 34 + drivers/net/Makefile | 1 + drivers/net/cavium/Makefile | 8 + drivers/net/cavium/nic.h | 569 ++++++ drivers/net/cavium/nic_main.c | 795 +++++++++ drivers/net/cavium/nic_reg.h | 228 +++ drivers/net/cavium/nicvf_main.c | 553 ++++++ drivers/net/cavium/nicvf_queues.c | 1123 ++++++++++++ drivers/net/cavium/nicvf_queues.h | 364 ++++ drivers/net/cavium/q_struct.h | 692 ++++++++ drivers/net/cavium/thunder_bgx.c | 1529 +++++++++++++++++ drivers/net/cavium/thunder_bgx.h | 259 +++ drivers/net/cavium/thunder_xcv.c | 190 ++ drivers/net/cavium/thunderx_smi.c | 388 +++++ drivers/net/e1000.c | 5 +- drivers/net/pch_gbe.c | 3 +- drivers/nvme/nvme.c | 3 +- drivers/pci/Kconfig | 9 + drivers/pci/Makefile | 1 + drivers/pci/pci-uclass.c | 316 +++- drivers/pci/pci_auto.c | 18 + drivers/pci/pci_thunderx.c | 160 ++ drivers/spi/Kconfig | 6 + drivers/spi/Makefile | 1 + drivers/spi/thunderx_spi.c | 448 +++++ drivers/usb/host/ehci-pci.c | 3 +- drivers/usb/host/xhci-pci.c | 10 +- include/ahci.h | 3 + include/configs/thunderx_81xx.h | 82 + include/fdtdec.h | 11 + include/pci.h | 58 +- include/pci_ids.h | 15 + lib/fdtdec.c | 13 + net/eth_legacy.c | 3 + 68 files changed, 10248 insertions(+), 69 deletions(-) create mode 100644 arch/arm/dts/thunderx-81xx.dts create mode 100644 arch/arm/dts/thunderx-81xx.dtsi rename {include/cavium => arch/arm/include/asm/arch-thunderx}/atf.h (96%) rename {include/cavium => arch/arm/include/asm/arch-thunderx}/atf_part.h (100%) create mode 100644 arch/arm/include/asm/arch-thunderx/fdt.h create mode 100644 arch/arm/include/asm/arch-thunderx/thunderx.h rename {include/cavium => arch/arm/include/asm/arch-thunderx}/thunderx_svc.h (100%) create mode 100644 arch/arm/include/asm/arch-thunderx/thunderx_vnic.h create mode 100644 arch/arm/mach-thunderx/Makefile rename {board/cavium/thunderx => arch/arm/mach-thunderx}/atf.c (98%) create mode 100644 arch/arm/mach-thunderx/fdt.c create mode 100644 arch/arm/mach-thunderx/lowlevel_init.S create mode 100644 arch/arm/mach-thunderx/misc.c create mode 100644 configs/thunderx_81xx_defconfig create mode 100644 drivers/gpio/thunderx_gpio.c create mode 100644 drivers/i2c/thunderx_i2c.c create mode 100644 drivers/net/cavium/Makefile create mode 100644 drivers/net/cavium/nic.h create mode 100644 drivers/net/cavium/nic_main.c create mode 100644 drivers/net/cavium/nic_reg.h create mode 100644 drivers/net/cavium/nicvf_main.c create mode 100644 drivers/net/cavium/nicvf_queues.c create mode 100644 drivers/net/cavium/nicvf_queues.h create mode 100644 drivers/net/cavium/q_struct.h create mode 100644 drivers/net/cavium/thunder_bgx.c create mode 100644 drivers/net/cavium/thunder_bgx.h create mode 100644 drivers/net/cavium/thunder_xcv.c create mode 100644 drivers/net/cavium/thunderx_smi.c create mode 100644 drivers/pci/pci_thunderx.c create mode 100755 drivers/spi/thunderx_spi.c create mode 100644 include/configs/thunderx_81xx.h -- 2.17.1

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[U-Boot] [PATCH 0/4] Misc EFI/GPT/UUID fixes
by Eugeniu Rosca 16 May '19

16 May '19

This is a collection of fixes addressing issues on R-Car H3ULCB-KF. All have been tested on H3ULCB-KF and boot-tested on sandbox. Below v1 patch is superseded by this series: - https://patchwork.ozlabs.org/patch/1091802/ ("lib: uuid: Improve randomness of uuid values on RANDOM_UUID=y") Eugeniu Rosca (4): disk: efi: Fix memory leak on 'gpt guid' disk: efi: Fix memory leak on 'gpt verify' cmd: gpt: fix and tidy up help message lib: uuid: Improve randomness of uuid values on RANDOM_UUID=y cmd/gpt.c | 12 ++++++------ disk/part_efi.c | 6 ++++++ lib/uuid.c | 2 ++ 3 files changed, 14 insertions(+), 6 deletions(-) -- 2.21.0

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[U-Boot] [PATCH v1] dm: pinctrl: Remove obsolete function pinctrl_decode_pin_config_dm().
by Christoph Muellner 16 May '19

16 May '19

This reverts commit 5ff776889212c080e3d1a33634ac904405ed6845. As noted in the comment, the function pinctrl_decode_pin_config_dm() only served as a temporary solution. Since the function has no users anymore, we can remove it again. Signed-off-by: Christoph Muellner <christoph.muellner(a)theobroma-systems.com> --- drivers/pinctrl/pinctrl-uclass.c | 22 ---------------------- include/dm/pinctrl.h | 12 ------------ 2 files changed, 34 deletions(-) diff --git a/drivers/pinctrl/pinctrl-uclass.c b/drivers/pinctrl/pinctrl-uclass.c index 0e3260afd1..6db0445067 100644 --- a/drivers/pinctrl/pinctrl-uclass.c +++ b/drivers/pinctrl/pinctrl-uclass.c @@ -27,28 +27,6 @@ int pinctrl_decode_pin_config(const void *blob, int node) return flags; } -/* - * TODO: this function is temporary for v2019.01. - * It should be renamed to pinctrl_decode_pin_config(), - * the original pinctrl_decode_pin_config() function should - * be removed and all callers of the original function should - * be migrated to use the new one. - */ -int pinctrl_decode_pin_config_dm(struct udevice *dev) -{ - int pinconfig = 0; - - if (dev->uclass->uc_drv->id != UCLASS_PINCONFIG) - return -EINVAL; - - if (dev_read_bool(dev, "bias-pull-up")) - pinconfig |= 1 << PIN_CONFIG_BIAS_PULL_UP; - else if (dev_read_bool(dev, "bias-pull-down")) - pinconfig |= 1 << PIN_CONFIG_BIAS_PULL_DOWN; - - return pinconfig; -} - #if CONFIG_IS_ENABLED(PINCTRL_FULL) /** * pinctrl_config_one() - apply pinctrl settings for a single node diff --git a/include/dm/pinctrl.h b/include/dm/pinctrl.h index ff2b82e7c2..63a7d55b88 100644 --- a/include/dm/pinctrl.h +++ b/include/dm/pinctrl.h @@ -355,18 +355,6 @@ int pinctrl_get_periph_id(struct udevice *dev, struct udevice *periph); int pinctrl_decode_pin_config(const void *blob, int node); /** - * pinctrl_decode_pin_config_dm() - decode pin configuration flags - * - * This decodes some of the PIN_CONFIG values into flags, with each value - * being (1 << pin_cfg). This does not support things with values like the - * slew rate. - * - * @pinconfig: Pinconfig udevice - * @return decoded flag value, or -ve on error - */ -int pinctrl_decode_pin_config_dm(struct udevice *dev); - -/** * pinctrl_get_gpio_mux() - get the mux value for a particular GPIO * * This allows the raw mux value for a GPIO to be obtained. It is -- 2.11.0

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[U-Boot] [PATCH] x86: coreboot: make it possible to process unhandled tags
by Christian Gmeiner 16 May '19

16 May '19

coreboot makes it possible to add own entries into coreboot's table at a per mainboard basis. As there might be some custom ones it makes sense to provide a way to process them. Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> --- arch/x86/cpu/coreboot/tables.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/cpu/coreboot/tables.c b/arch/x86/cpu/coreboot/tables.c index bc18b710c9..a7c55c7dd1 100644 --- a/arch/x86/cpu/coreboot/tables.c +++ b/arch/x86/cpu/coreboot/tables.c @@ -109,6 +109,8 @@ static void cb_parse_string(unsigned char *ptr, char **info) *info = (char *)((struct cb_string *)ptr)->string; } +__weak void cb_parse_unhandled(u32 tag, unsigned char *ptr) {} + static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) { struct cb_header *header; @@ -211,6 +213,9 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) case CB_TAG_VBNV: cb_parse_vbnv(ptr, info); break; + default: + cb_parse_unhandled(rec->tag, ptr); + break; } ptr += rec->size; -- 2.20.1

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[U-Boot] [i.MX8MM+CCF 00/41] i.MX8MM + CCF
by Peng Fan 16 May '19

16 May '19

This patch set is based Lukasz V3 CCF patchset, [PATCH v3 00/11] clk: Port Linux common clock framework [CCF] to U-boot (tag: 5.0-rc3) https://github.com/lmajewski/u-boot-dfu/commits/CCF-v3 Added a few fixes to Lukasz's v3 patchset. Introduced clk-gate/composite Added set rate support Per my understanding, U-Boot CCF will not support mux reparent, and support rate prograte setting to parent automatically. So new clk feature added follow this rule. There are many warnings when importing linux ccf code, I did not modify them all. The rest patches are for i.MX8MM, part of legacy clk code are still kept, because we are hard to enable CCF at very early stage, we set malloc space to DRAM when dram initialized in spl stage, so we have limited SRAM for uclass dm and dm clk, so keep the DRAM PLL related setting with legacy clk code which use small ram. The u-boot-spl.bin now is about 100KB without ddr firmware,usb stack and hab, so really large...... I am thinking what we could do to shrink the size, welcome any suggestions. Not expect this patchset could be merged, because of the CCF/clock code change, but since the clock part blocks i.MX8MM upstream, just would like to speed up the development with community and move on. Peng Fan (40): clk: correct get clk_x pointer clk: fixed-factor: fix get clk_fixed_factor clk: introduce clk_dev_binded clk: use clk_dev_binded clk-provider: sync more clk flags from Linux Kernel cmd: clk: print err value when clk_get_rate failed clk: mux: add set parent support clk: export mux/divider ops clk: add clk-gate support divider set rate supporrt clk: fixed_rate: export clk_fixed_rate clk: fixed_rate: add pre reloc flag clk: imx: import clk heplers clk: imx: gate2 add set rate linux: compat: guard PAGE_SIZE drivers: core: use strcmp when find device by name ddr: imx8m: fix ddr firmware location when enable SPL OF imx: add IMX8MQ kconfig entry imx: add IMX8MM kconfig entry imx: imx8mm: add clock bindings header imx: add i.MX8MM cpu type imx: spl: add spl_board_boot_device for i.MX8MM imx8m: update imx-regs for i.MX8MM imx: add get_cpu_rev support for i.MX8MM imx8m: rename clock to clock_imx8mq imx8m: restructure clock.h imx8m: add clk support for i.MX8MM imx8m: soc: probe clk before relocation imx8m: add pin header for i.MX8MM imx: add i.MX8MM PE property imx8m: Fix MMU table issue for OPTEE memory imx8m: set BYPASS ID SWAP to avoid AXI bus errors imx8m: soc: enable SCTR clock before timer init serial: Kconfig: make MXC_UART usable for MX7 and IMX8M clk: imx: add Kconfig entry for i.MX8MM clk: imx: add pll14xx driver clk: add composite clk support clk: imx: add i.MX8MM composite clk support clk: imx: add i.MX8MM clk driver imx: add i.MX8MM EVK board support Ye Li (1): imx8m: Configure trustzone region 0 for non-secure access arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx8mm-evk-u-boot.dtsi | 92 + arch/arm/dts/imx8mm-evk.dts | 235 +++ arch/arm/dts/imx8mm-pinfunc.h | 629 +++++++ arch/arm/dts/imx8mm.dtsi | 733 ++++++++ arch/arm/include/asm/arch-imx/cpu.h | 6 + arch/arm/include/asm/arch-imx8m/clock.h | 493 +---- arch/arm/include/asm/arch-imx8m/clock_imx8mm.h | 387 ++++ arch/arm/include/asm/arch-imx8m/clock_imx8mq.h | 424 +++++ arch/arm/include/asm/arch-imx8m/imx-regs.h | 75 +- arch/arm/include/asm/arch-imx8m/imx8mm_pins.h | 691 +++++++ arch/arm/include/asm/mach-imx/iomux-v3.h | 4 + arch/arm/include/asm/mach-imx/sys_proto.h | 8 + arch/arm/mach-imx/cpu.c | 12 + arch/arm/mach-imx/imx8m/Kconfig | 17 +- arch/arm/mach-imx/imx8m/Makefile | 4 +- arch/arm/mach-imx/imx8m/clock_imx8mm.c | 292 +++ .../arm/mach-imx/imx8m/{clock.c => clock_imx8mq.c} | 5 +- arch/arm/mach-imx/imx8m/clock_slice.c | 461 +++++ arch/arm/mach-imx/imx8m/soc.c | 112 +- arch/arm/mach-imx/spl.c | 8 + board/freescale/imx8mm_evk/Kconfig | 12 + board/freescale/imx8mm_evk/MAINTAINERS | 6 + board/freescale/imx8mm_evk/Makefile | 12 + board/freescale/imx8mm_evk/imx8mm_evk.c | 90 + board/freescale/imx8mm_evk/lpddr4_timing.c | 1980 ++++++++++++++++++++ board/freescale/imx8mm_evk/spl.c | 216 +++ cmd/clk.c | 2 + configs/imx8mm_evk_defconfig | 52 + drivers/clk/Kconfig | 14 + drivers/clk/Makefile | 3 +- drivers/clk/clk-composite.c | 165 ++ drivers/clk/clk-divider.c | 92 +- drivers/clk/clk-fixed-factor.c | 2 +- drivers/clk/clk-gate.c | 151 ++ drivers/clk/clk-mux.c | 76 +- drivers/clk/clk.c | 8 + drivers/clk/clk_fixed_rate.c | 9 +- drivers/clk/imx/Kconfig | 9 + drivers/clk/imx/Makefile | 1 + drivers/clk/imx/clk-composite-8m.c | 170 ++ drivers/clk/imx/clk-gate2.c | 15 +- drivers/clk/imx/clk-imx8mm.c | 415 ++++ drivers/clk/imx/clk-pfd.c | 2 +- drivers/clk/imx/clk-pll14xx.c | 377 ++++ drivers/clk/imx/clk-pllv3.c | 2 +- drivers/clk/imx/clk.h | 106 ++ drivers/core/uclass.c | 2 +- drivers/ddr/imx/imx8m/helper.c | 12 +- drivers/serial/Kconfig | 2 +- include/clk.h | 9 + include/configs/imx8mm_evk.h | 199 ++ include/dt-bindings/clock/imx8mm-clock.h | 244 +++ include/linux/clk-provider.h | 74 + include/linux/compat.h | 2 + 55 files changed, 8728 insertions(+), 494 deletions(-) create mode 100644 arch/arm/dts/imx8mm-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mm-evk.dts create mode 100644 arch/arm/dts/imx8mm-pinfunc.h create mode 100644 arch/arm/dts/imx8mm.dtsi create mode 100644 arch/arm/include/asm/arch-imx8m/clock_imx8mm.h create mode 100644 arch/arm/include/asm/arch-imx8m/clock_imx8mq.h create mode 100644 arch/arm/include/asm/arch-imx8m/imx8mm_pins.h create mode 100644 arch/arm/mach-imx/imx8m/clock_imx8mm.c rename arch/arm/mach-imx/imx8m/{clock.c => clock_imx8mq.c} (99%) create mode 100644 board/freescale/imx8mm_evk/Kconfig create mode 100644 board/freescale/imx8mm_evk/MAINTAINERS create mode 100644 board/freescale/imx8mm_evk/Makefile create mode 100644 board/freescale/imx8mm_evk/imx8mm_evk.c create mode 100644 board/freescale/imx8mm_evk/lpddr4_timing.c create mode 100644 board/freescale/imx8mm_evk/spl.c create mode 100644 configs/imx8mm_evk_defconfig create mode 100644 drivers/clk/clk-composite.c create mode 100644 drivers/clk/clk-gate.c create mode 100644 drivers/clk/imx/clk-composite-8m.c create mode 100644 drivers/clk/imx/clk-imx8mm.c create mode 100644 drivers/clk/imx/clk-pll14xx.c create mode 100644 include/configs/imx8mm_evk.h create mode 100644 include/dt-bindings/clock/imx8mm-clock.h -- 2.16.4

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[U-Boot] [PATCH v3 1/2] net: eth-uclass: Write MAC address to hardware after probe
by Thierry Reding 15 May '19

15 May '19

From: Thierry Reding <treding(a)nvidia.com> In order for the device to use the proper MAC address, which can have been configured in the environment prior to the device being registered, ensure that the MAC address is written after the device has been probed. For devices that are registered before the network stack is initialized, this is already done during eth_initialize(). If the Ethernet device is on a bus that is not initialized on early boot, such as PCI, the device is not available at the time eth_initialize() is called, so we need the MAC address programming to also happen after probe. Acked-by: Joe Hershberger <joe.hershberger(a)ni.com> Signed-off-by: Thierry Reding <treding(a)nvidia.com> --- net/eth-uclass.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/net/eth-uclass.c b/net/eth-uclass.c index 2ef20df19203..4225aabf1fa1 100644 --- a/net/eth-uclass.c +++ b/net/eth-uclass.c @@ -524,6 +524,8 @@ static int eth_post_probe(struct udevice *dev) #endif } + eth_write_hwaddr(dev); + return 0; } -- 2.21.0

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[U-Boot] [PATCH v3 0/2] arm64: zynqmp: pass a PMUFW config object
by Luca Ceresoli 15 May '19

15 May '19

Hi, This patchset aims at solving a long-standing issue in the ZynqMP users community: the management of the PMU firmware configuration object when U-Boot SPL is used. History and status ================== First non-RFC version. The code is now clean and I consider it OK for mainline inclusion. Since RFC v2 the cfg obj is now passed as a binary blob. The code to compile it in the C form has been removed and replaced by a Python tool to convert C to bin. The loading has been fixed and cleaned up according to comments. TODO: move the PMU IPC code to a mailbox uclass driver. Description =========== The Platform Management Unit (PMU) needs a configuration object (cfg obj) to know how to operate the SoC. When using the "Xilinx workflow", the Xilinx FSBL (First Stage Bootloader) has the SPL role. FSBL has a built-in cfg obj and passes it to the PMUFW at runtime before jumping to U-Boot proper. This is just not implemented in the U-Boot code. The best workaround for U-Boot SPL users is to patch [0] the PMUFW itself to have the cfg obj built-in and self-load it. This approach has some drawbacks: among others, it forces to use a different PMUFW binary for each hardware and hardware configuation. It also makes it impossible to change the configuration after boot. The first patch fills the gap by allowing U-Boot SPL to load the cfg obj firmware at runtime. It adds a Kconfig string option to point to the cfg obj in the form of a binary blob. If the option is non-empty, code is enabled to link that file in U-Boot SPL and send the configuration to PMUFW. Patch 2 adds a tool to convert the cfg obj C file (as produced by the Xilinx XSDK proprietary tool) in a binary blob suitable for loading. As suggested by Mike Looijmans it has been implemented as a Python script to make it easily usable. These patches are tested on the UltraZed EV board. Many thanks to Michal Simek for his many suggestions on how to improve this work. [0] https://github.com/topic-embedded-products/meta-topic/blob/master/recipes-b… RFCv1: https://lists.denx.de/pipermail/u-boot/2019-February/360450.html RFCv2: https://lists.denx.de/pipermail/u-boot/2019-March/362464.html Luca Luca Ceresoli (2): arm64: zynqmp: spl: install a PMU firmware config object at runtime arm64: zynqmp: add tool to convert PMU config object .c to binary arch/arm/mach-zynqmp/Kconfig | 17 + arch/arm/mach-zynqmp/Makefile | 4 + arch/arm/mach-zynqmp/include/mach/sys_proto.h | 4 + arch/arm/mach-zynqmp/pm_cfg_obj_convert.py | 302 ++++++++++++++++++ arch/arm/mach-zynqmp/pmu_ipc.c | 112 +++++++ board/xilinx/zynqmp/Makefile | 12 + board/xilinx/zynqmp/pm_cfg_obj.S | 17 + board/xilinx/zynqmp/zynqmp.c | 8 + 8 files changed, 476 insertions(+) create mode 100755 arch/arm/mach-zynqmp/pm_cfg_obj_convert.py create mode 100644 arch/arm/mach-zynqmp/pmu_ipc.c create mode 100644 board/xilinx/zynqmp/pm_cfg_obj.S -- 2.21.0

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[U-Boot] [PATCH] eth: mtk-eth: fix incorrect read of phy-handle
by Weijie Gao 14 May '19

14 May '19

In mt7629-rfb.dts, the phy-handle is a reference to the node phy0, not the node itself: phy-handle = <&phy0>; phy0: ethernet-phy@0 { reg = <0>; } However the driver used ofnode_find_subnode("phy-handle") to read the node. It will always fail. This patch replaces ofnode_find_subnode with dev_read_phandle_with_args to make sure the node can be read correctly. Cc: Joe Hershberger <joe.hershberger(a)ni.com> Signed-off-by: Weijie Gao <weijie.gao(a)mediatek.com> --- drivers/net/mtk_eth.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c index cc09404..0ef814c 100644 --- a/drivers/net/mtk_eth.c +++ b/drivers/net/mtk_eth.c @@ -1130,13 +1130,14 @@ static int mtk_eth_ofdata_to_platdata(struct udevice *dev) &priv->rst_gpio, GPIOD_IS_OUT); } } else { - subnode = ofnode_find_subnode(dev_ofnode(dev), "phy-handle"); - if (!ofnode_valid(subnode)) { + ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, + 0, &args); + if (ret) { printf("error: phy-handle is not specified\n"); return ret; } - priv->phy_addr = ofnode_read_s32_default(subnode, "reg", -1); + priv->phy_addr = ofnode_read_s32_default(args.node, "reg", -1); if (priv->phy_addr < 0) { printf("error: phy address is not specified\n"); return ret; -- 1.9.1

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[U-Boot] [RESEND PATCH 1/2] net: rtl8169: Implement ->hwaddr_write() callback
by Thierry Reding 14 May '19

14 May '19

From: Thierry Reding <treding(a)nvidia.com> Implement this callback that allows the MAC address to be set for the Ethernet card. This is necessary in order for the device to be able to receive packets for the MAC address that U-Boot advertises. Signed-off-by: Thierry Reding <treding(a)nvidia.com> --- drivers/net/rtl8169.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c index a78f3d233f1a..27e27b34176b 100644 --- a/drivers/net/rtl8169.c +++ b/drivers/net/rtl8169.c @@ -941,6 +941,23 @@ static void rtl_halt(struct eth_device *dev) } #endif +#ifdef CONFIG_DM_ETH +static int rtl8169_write_hwaddr(struct udevice *dev) +{ + struct eth_pdata *plat = dev_get_platdata(dev); + unsigned int i; + + RTL_W8(Cfg9346, Cfg9346_Unlock); + + for (i = 0; i < MAC_ADDR_LEN; i++) + RTL_W8(MAC0 + i, plat->enetaddr[i]); + + RTL_W8(Cfg9346, Cfg9346_Lock); + + return 0; +} +#endif + /************************************************************************** INIT - Look for an adapter, this routine's visible to the outside ***************************************************************************/ @@ -1195,6 +1212,7 @@ static const struct eth_ops rtl8169_eth_ops = { .send = rtl8169_eth_send, .recv = rtl8169_eth_recv, .stop = rtl8169_eth_stop, + .write_hwaddr = rtl8169_write_hwaddr, }; static const struct udevice_id rtl8169_eth_ids[] = { -- 2.21.0

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[U-Boot] [PATCH] phy: ti: Init node before reading
by Michal Simek 14 May '19

14 May '19

There is a need to fill node before clk_output_sel is setup. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> Acked-by: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> --- drivers/net/phy/ti.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c index 6db6edd0d0c8..10989dd40309 100644 --- a/drivers/net/phy/ti.c +++ b/drivers/net/phy/ti.c @@ -216,6 +216,10 @@ static int dp83867_of_init(struct phy_device *phydev) /* Optional configuration */ + node = phy_get_ofnode(phydev); + if (!ofnode_valid(node)) + return -EINVAL; + /* * Keep the default value if ti,clk-output-sel is not set * or to high @@ -225,10 +229,6 @@ static int dp83867_of_init(struct phy_device *phydev) ofnode_read_u32_default(node, "ti,clk-output-sel", DP83867_CLK_O_SEL_REF_CLK); - node = phy_get_ofnode(phydev); - if (!ofnode_valid(node)) - return -EINVAL; - if (ofnode_read_bool(node, "ti,max-output-impedance")) dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX; else if (ofnode_read_bool(node, "ti,min-output-impedance")) -- 1.9.1

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