March 2019 - U-Boot

[U-Boot] [BUG] Crash when starting grub-arm.efi on BeagleBone Black
by Heinrich Schuchardt 08 Mar '19

08 Mar '19

On 3/7/19 12:05 PM, Adam Podogrocki wrote: >> Hello Heinrich, >> >> I've checked U-Boot behaviour in following setups: >> >> 1. U-Boot v2018.09/v2018.11 and GRUB commit 72e80c025 (used by us >> in other setups) >> 2. U-Boot v2019.01 and GRUB commit 72e80c025 (used by us in other >> setups) >> 3. U-Boot v2019.01 and GRUB latest commit 9223eff8f These are not commit numbers from git://git.savannah.gnu.org/grub.git So to which repository do they relate? On Google drive you supplied to me GRUB 35b909062. This is also not a valid commit number. First I tried to find the location of the crash that you reported: $ hexedit grub-arm.efi # GRUB 35b909062 000060D4 33 7B 31 68 03 F0 0F 02 4F EA 13 1B 02 9B 5F 18 000060E4 2F 44 04 2A 78 D8 DF E8 02 F0 03 03 43 6A 75 00 000060F4 F0 89 11 B3 08 BB 79 1E 11 F8 01 2F 6A B9 40 F2 00006104 FD 11 00 EB 50 10 FB F7 F8 FC 60 4B 03 EB 81 01 ^^^^^^^^^^^ I analyzed the file with the tool available at https://github.com/xypron/efi_analyzer $ efianalyze grub-arm.efi # GRUB 35b909062 Offset to PE = 80 Machine type: 0x01c2, ARM or Thumb ("interworking") Characteristics 0x30e Image type: PE32 EFI application ImageBase=0x0 SectionAlignment=0x1000 SizeOfImage=0x55000 .reloc.address=0x54000 .reloc.size=0x1000 BaseOfCode=0x1000 AddressOfEntryPoint=0x1000 Number of Sections 4 Section[0] .text Virtual size 0x8000 Virtual address 0x1000 Size of raw data 0x8000 Pointer to raw data 0x1000 End of raw data 0x9000 Section[1] .data Virtual size 0xb000 Virtual address 0x9000 Size of raw data 0xb000 Pointer to raw data 0x9000 End of raw data 0x14000 Section[2] mods Virtual size 0x40000 Virtual address 0x14000 Size of raw data 0x40000 Pointer to raw data 0x14000 End of raw data 0x54000 Section[3] .reloc Virtual size 0x1000 Virtual address 0x54000 Size of raw data 0x1000 Pointer to raw data 0x54000 End of raw data 0x55000 So the entry-point is 0x1000 and the virtual address 0x1000 matches the position in the file. That makes things easy. $ /usr/bin/arm-linux-gnueabihf-objdump -D -b binary -marm grub-arm.efi 1000: e59fc010 ldr ip, [pc, #16] ; 0x1018 1004: e58c0000 str r0, [ip] 1008: e59fc00c ldr ip, [pc, #12] ; 0x101c 100c: e58c1000 str r1, [ip] 1010: e59fc008 ldr ip, [pc, #8] ; 0x1020 1014: e12fff1c bx ip 1018: 0000c914 andeq ip, r0, r4, lsl r9 101c: 0000c910 andeq ip, r0, r0, lsl r9 1020: 0000610d andeq r6, r0, sp, lsl #2 This matches function _start() in grub-core/kern/arm/efi/startup.S: ldr ip, =EXT_C(grub_efi_image_handle) str r0, [ip] ldr ip, =EXT_C(grub_efi_system_table) str r1, [ip] ldr ip, =EXT_C(grub_main) bx ip END So here we first store the image handle and the system table. Then we branch to 610C in thumb mode (bit 0 is set in the address). The entry point is called in U-Boot via 0x47f8765c <efi_start_image+100> ldr r0, [sp, #4] 0x47f87660 <efi_start_image+104> blx r3 So we have first a blx jump to ARM and then a bx jump to THUMB. TODO for me: According to http://infocenter.arm.com/help/topic/com.arm.doc.uan0002a/UAN002A_1176-pan_… depending on the alignment of the blx command this sequence of commands may fail on some ARM11 processors. But the BeagleBone Black has an ARMv7-A and not an ARM11 processor. So nothing to worry us. The further disassembly depends on the start address: /usr/bin/arm-linux-gnueabihf-objdump -D -b binary -marm \ --disassembler-options=force-thumb grub-arm.efi --start-addr=0x6100 00006100 <.data+0x6100>: 6100: b96a cbnz r2, 0x611e 6102: f240 11fd movw r1, #509 ; 0x1fd 6106: eb00 1050 add.w r0, r0, r0, lsr #5 610a: f7fb fcf8 bl 0x1afe 610e: 4b60 ldr r3, [pc, #384] ; (0x6290) 6110: eb03 0181 add.w r1, r3, r1, lsl #2 6114: 684a ldr r2, [r1, #4] 6116: b942 cbnz r2, 0x612a /usr/bin/arm-linux-gnueabihf-objdump -D -b binary -marm \ --disassembler-options=force-thumb grub-arm.efi --start-addr=0x610c 0000610c <.data+0x610c>: 610c: fcf8 4b60 ldc2l 11, cr4, [r8], #384 ; 0x180 ; <UNPREDICTABLE> 6110: eb03 0181 add.w r1, r3, r1, lsl #2 6114: 684a ldr r2, [r1, #4] 6116: b942 cbnz r2, 0x612a 6118: 463a mov r2, r7 611a: 495e ldr r1, [pc, #376] ; (0x6294) So the next instruction after branching is `ldc2l 11, cr4, [r8], #384`. Next I put your grub_arm.efi into directory tftp/ and started U-Boot qemu_arm_defconfig with: qemu-system-arm -machine virt -cpu cortex-a15 \ -bios u-boot.bin -nographic -gdb tcp::1234 -netdev \ user,id=eth0,tftp=tftp,net=192.168.76.0/24,dhcpstart=192.168.76.9 \ -device e1000,netdev=eth0 I displayed the relocation offset with command bdinfo: => bdinfo arch_number = 0x00000000 boot_params = 0x00000000 DRAM bank = 0x00000000 -> start = 0x40000000 -> size = 0x08000000 baudrate = 115200 bps TLB addr = 0x47ff0000 relocaddr = 0x47f4f000 <<<<<< You need this address reloc off = 0x47f4f000 irq_sp = 0x46e0dec0 sp start = 0x46e0deb0 Early malloc usage: 11c / 400 fdt_blob = 0x46e0ded8 In a separate mode I opened GDB: gdb-multiarch u-boot -ex 'target remote localhost:1234' (gdb) add-symbol-file u-boot 0x47f4f000 add symbol table from file "u-boot" at .text_addr = 0x47f4f000 (y or n) y Reading symbols from u-boot...done. (gdb) b efi_start_image Breakpoint 1 at 0x385f8: efi_start_image. (2 locations) (gdb) c Continuing When debugging the ldc2l instruction at 610c caused the same error that you already observed: => bootefi $kernel_addr_r $fdtcontroladdr Found 0 disks ## Starting EFI application at 40400000 ... undefined instruction pc : [<45cb610a>] lr : [<47f87664>] reloc pc : [<fdd6710a>] lr : [<00038664>] sp : 46e0dc28 ip : 45cb610d fp : 47f6a324 r10: 00000003 r9 : 00000000 r8 : 46f11080 r7 : 40400000 r6 : 45e0c040 r5 : 00000000 r4 : 47f4f7c8 r3 : 45cb1000 r2 : 00000000 r1 : 47f4f7c8 r0 : 46f18010 Flags: nZCv IRQs off FIQs off Mode SVC_32 Code: 1e79bb08 2f01f811 f240b96a eb0011fd (f7fb1050) UEFI image [0x45cb0000:0x45d04fff] pc=0x610a '/grub_arm.efi' Resetting CPU ... I have no clue why GRUB would try to transfer data to a co-processor (ldc2l 11, cr4, [r8], #384). As I cannot find a match in git://git.savannah.gnu.org/grub.git I wonder how you ended up with this in your GRUB. I will stop my analysis here. I hope with the information provided you are able to take over. Best regards Heinrich

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[U-Boot] [PATCH V2] ddr: socfpga: Fix EMIF clear timeout
by Marek Vasut 08 Mar '19

08 Mar '19

The current EMIF clear timeout handling code was applying bitwise operations to signed data types and as it was, was extremely hard to read. Replace it with simple wait_for_bit(). Expand the error handling to make it more readable too. This patch also changes the timeout for emif_clear() from 14 hours to 1 second. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Chin Liang See <chin.liang.see(a)intel.com> Cc: Dinh Nguyen <dinguyen(a)kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> Cc: Tien Fong Chee <tien.fong.chee(a)intel.com> --- V2: Subject should read ddr: socfpga: , fix this --- drivers/ddr/altera/sdram_arria10.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c index be5ce778e8..6e6938fdb0 100644 --- a/drivers/ddr/altera/sdram_arria10.c +++ b/drivers/ddr/altera/sdram_arria10.c @@ -133,22 +133,16 @@ static unsigned char ddr_wait_bit(u32 ereg, u32 bit, static int emif_clear(void) { - u32 i = DDR_MAX_TRIES; - u8 ret = 0; - writel(0, DDR_REG_CORE2SEQ); - do { - ret = !wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE, - SEQ2CORE_MASK, 1, 50, 0); - } while (ret && (--i > 0)); - - return !i; + return wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE, + SEQ2CORE_MASK, 0, 1000, 0); } static int emif_reset(void) { u32 c2s, s2c; + int ret; c2s = readl(DDR_REG_CORE2SEQ); s2c = readl(DDR_REG_SEQ2CORE); @@ -159,9 +153,12 @@ static int emif_reset(void) readl(IO48_MMR_NIOS2_RESERVE2), readl(IO48_MMR_DRAMSTS)); - if ((s2c & SEQ2CORE_MASK) && emif_clear()) { - debug("failed emif_clear()\n"); - return -EPERM; + if (s2c & SEQ2CORE_MASK) { + ret = emif_clear(); + if (ret) { + debug("failed emif_clear()\n"); + return -EPERM; + } } writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ); @@ -173,7 +170,8 @@ static int emif_reset(void) debug("emif_reset interrupt acknowledged\n"); } - if (emif_clear()) { + ret = emif_clear(); + if (ret) { debug("emif_clear() failed\n"); return -EPERM; } -- 2.20.1

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[U-Boot] [PATCH] ARM: socfpga: Fix EMIF clear timeout
by Marek Vasut 08 Mar '19

08 Mar '19

The current EMIF clear timeout handling code was applying bitwise operations to signed data types and as it was, was extremely hard to read. Replace it with simple wait_for_bit(). Expand the error handling to make it more readable too. This patch also changes the timeout for emif_clear() from 14 hours to 1 second. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Chin Liang See <chin.liang.see(a)intel.com> Cc: Dinh Nguyen <dinguyen(a)kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> Cc: Tien Fong Chee <tien.fong.chee(a)intel.com> --- drivers/ddr/altera/sdram_arria10.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c index be5ce778e8..6e6938fdb0 100644 --- a/drivers/ddr/altera/sdram_arria10.c +++ b/drivers/ddr/altera/sdram_arria10.c @@ -133,22 +133,16 @@ static unsigned char ddr_wait_bit(u32 ereg, u32 bit, static int emif_clear(void) { - u32 i = DDR_MAX_TRIES; - u8 ret = 0; - writel(0, DDR_REG_CORE2SEQ); - do { - ret = !wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE, - SEQ2CORE_MASK, 1, 50, 0); - } while (ret && (--i > 0)); - - return !i; + return wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE, + SEQ2CORE_MASK, 0, 1000, 0); } static int emif_reset(void) { u32 c2s, s2c; + int ret; c2s = readl(DDR_REG_CORE2SEQ); s2c = readl(DDR_REG_SEQ2CORE); @@ -159,9 +153,12 @@ static int emif_reset(void) readl(IO48_MMR_NIOS2_RESERVE2), readl(IO48_MMR_DRAMSTS)); - if ((s2c & SEQ2CORE_MASK) && emif_clear()) { - debug("failed emif_clear()\n"); - return -EPERM; + if (s2c & SEQ2CORE_MASK) { + ret = emif_clear(); + if (ret) { + debug("failed emif_clear()\n"); + return -EPERM; + } } writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ); @@ -173,7 +170,8 @@ static int emif_reset(void) debug("emif_reset interrupt acknowledged\n"); } - if (emif_clear()) { + ret = emif_clear(); + if (ret) { debug("emif_clear() failed\n"); return -EPERM; } -- 2.20.1

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[U-Boot] [PATCH 1/3] net: eth-uclass: Write MAC address to hardware after probe
by Thierry Reding 08 Mar '19

08 Mar '19

From: Thierry Reding <treding(a)nvidia.com> In order for the device to use the proper MAC address, which can have been configured in the environment prior to the device being registered, ensure that the MAC address is written after the device has been probed. For devices that are registered before the network stack is initialized, this is already done during eth_initialize(). If the Ethernet device is on a bus that is not initialized on early boot, such as PCI, the device is not available at the time eth_initialize() is called, so we need the MAC address programming to also happen after probe. Signed-off-by: Thierry Reding <treding(a)nvidia.com> --- net/eth-uclass.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/net/eth-uclass.c b/net/eth-uclass.c index 2ef20df19203..4225aabf1fa1 100644 --- a/net/eth-uclass.c +++ b/net/eth-uclass.c @@ -524,6 +524,8 @@ static int eth_post_probe(struct udevice *dev) #endif } + eth_write_hwaddr(dev); + return 0; } -- 2.20.1

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[U-Boot] [PATCH 00/12] ARM: tegra: Share cboot code with Tegra210
by Thierry Reding 08 Mar '19

08 Mar '19

From: Thierry Reding <treding(a)nvidia.com> Code to support chainloading by nvtboot was introduced along with Tegar186 support. Since then, support for chainloading U-Boot has been extended to other Tegra SoC generations. This series of patches makes this code more widely available so that it can be reused. Also, the early bootloader responsible for chainloading U-Boot is called cboot nowadays, so the files and functions are renamed to reflect that. Patches 1-6 are preparatory changes that guard various bits of code and header includes with a Kconfig symbol, which makes it easier to support Tegra186 and earlier generations from a larger body of code. Patch 7 makes the save_boot_params() prototype more generic so that it can be reused on 64-bit ARM platforms. Patch 8 is the bulk of the series and moves the nvtboot code to a more central location and renames it. Patches 9-12 build on top of this to extend the cboot functionality with additional features. Thierry Thierry Reding (12): ARM: tegra: Use common header for PMU declarations ARM: tegra: Guard clock code with a Kconfig symbol ARM: tegra: Guard GP pad control code with a Kconfig symbol ARM: tegra: Guard memory controller code with a Kconfig symbol ARM: tegra: Guard pin controller code with a Kconfig symbol ARM: tegra: Guard powergate code with a Kconfig symbol ARM: tegra: Fix save_boot_params() prototype ARM: tegra: Unify Tegra186 builds ARM: tegra: Allow boards to override boot target devices ARM: tegra: Implement cboot_save_boot_params() in C ARM: tegra: Support TZ-only access to PMC ARM: tegra: Implement cboot_get_ethaddr() arch/arm/include/asm/arch-tegra/cboot.h | 45 ++ arch/arm/include/asm/arch-tegra/pmc.h | 20 +- .../asm/{arch-tegra20 => arch-tegra}/pmu.h | 6 +- arch/arm/include/asm/arch-tegra114/pmu.h | 12 - arch/arm/include/asm/arch-tegra124/pmu.h | 13 - arch/arm/include/asm/arch-tegra210/pmu.h | 13 - arch/arm/include/asm/arch-tegra30/pmu.h | 12 - arch/arm/mach-tegra/Kconfig | 30 + arch/arm/mach-tegra/Makefile | 16 +- arch/arm/mach-tegra/board.c | 41 +- arch/arm/mach-tegra/board186.c | 32 - arch/arm/mach-tegra/board2.c | 37 +- arch/arm/mach-tegra/cache.c | 2 + arch/arm/mach-tegra/cboot.c | 558 ++++++++++++++++++ arch/arm/mach-tegra/clock.c | 13 +- arch/arm/mach-tegra/cmd_enterrcm.c | 6 +- arch/arm/mach-tegra/cpu.c | 20 +- arch/arm/mach-tegra/emc.c | 2 +- arch/arm/mach-tegra/lowlevel_init.S | 39 -- arch/arm/mach-tegra/pmc.c | 92 +++ arch/arm/mach-tegra/powergate.c | 11 +- arch/arm/mach-tegra/tegra186/Makefile | 4 - arch/arm/mach-tegra/tegra186/nvtboot_ll.S | 20 - arch/arm/mach-tegra/tegra186/nvtboot_mem.c | 172 ------ board/nvidia/p2771-0000/p2771-0000.c | 10 +- include/configs/tegra-common-post.h | 2 + 26 files changed, 865 insertions(+), 363 deletions(-) create mode 100644 arch/arm/include/asm/arch-tegra/cboot.h rename arch/arm/include/asm/{arch-tegra20 => arch-tegra}/pmu.h (73%) delete mode 100644 arch/arm/include/asm/arch-tegra114/pmu.h delete mode 100644 arch/arm/include/asm/arch-tegra124/pmu.h delete mode 100644 arch/arm/include/asm/arch-tegra210/pmu.h delete mode 100644 arch/arm/include/asm/arch-tegra30/pmu.h delete mode 100644 arch/arm/mach-tegra/board186.c create mode 100644 arch/arm/mach-tegra/cboot.c delete mode 100644 arch/arm/mach-tegra/lowlevel_init.S create mode 100644 arch/arm/mach-tegra/pmc.c delete mode 100644 arch/arm/mach-tegra/tegra186/nvtboot_ll.S delete mode 100644 arch/arm/mach-tegra/tegra186/nvtboot_mem.c -- 2.20.1

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[U-Boot] [PATCH 1/2] phy: rcar: Add R-Car Gen3 PHY driver
by Marek Vasut 08 Mar '19

08 Mar '19

Add a PHY driver for the R-Car Gen3 which allows configuring USB OTG PHY on Gen3 into host mode and toggles VBUS in case a dedicated regulator is present. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- drivers/phy/Kconfig | 8 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-rcar-gen3.c | 161 ++++++++++++++++++++++++++++++++++++ 3 files changed, 170 insertions(+) create mode 100644 drivers/phy/phy-rcar-gen3.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index bcc8e22795..14d82b93ed 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -118,6 +118,14 @@ config PHY_RCAR_GEN2 PHY connected to USBHS module, PCI EHCI module and USB3.0 module and allows configuring the module multiplexing. +config PHY_RCAR_GEN3 + tristate "Renesas R-Car Gen3 USB PHY" + depends on PHY && RCAR_GEN3 && CLK && DM_REGULATOR + default y if RCAR_GEN3 + help + Support for the Renesas R-Car Gen3 USB PHY. This driver operates the + PHY connected to EHCI USB module and controls USB OTG operation. + config PHY_STM32_USBPHYC tristate "STMicroelectronics STM32 SoC USB HS PHY driver" depends on PHY && ARCH_STM32MP diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 1e1e4ca11e..8030d599e7 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_PHY_SANDBOX) += sandbox-phy.o obj-$(CONFIG_$(SPL_)PIPE3_PHY) += ti-pipe3-phy.o obj-$(CONFIG_STI_USB_PHY) += sti_usb_phy.o obj-$(CONFIG_PHY_RCAR_GEN2) += phy-rcar-gen2.o +obj-$(CONFIG_PHY_RCAR_GEN3) += phy-rcar-gen3.o obj-$(CONFIG_PHY_STM32_USBPHYC) += phy-stm32-usbphyc.o obj-$(CONFIG_MESON_GXL_USB_PHY) += meson-gxl-usb2.o meson-gxl-usb3.o obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o diff --git a/drivers/phy/phy-rcar-gen3.c b/drivers/phy/phy-rcar-gen3.c new file mode 100644 index 0000000000..b662935626 --- /dev/null +++ b/drivers/phy/phy-rcar-gen3.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas RCar Gen3 USB PHY driver + * + * Copyright (C) 2018 Marek Vasut <marek.vasut(a)gmail.com> + */ + +#include <common.h> +#include <clk.h> +#include <div64.h> +#include <dm.h> +#include <fdtdec.h> +#include <generic-phy.h> +#include <reset.h> +#include <syscon.h> +#include <usb.h> +#include <asm/io.h> +#include <linux/bitops.h> +#include <power/regulator.h> + +/* USB2.0 Host registers (original offset is +0x200) */ +#define USB2_INT_ENABLE 0x000 +#define USB2_USBCTR 0x00c +#define USB2_SPD_RSM_TIMSET 0x10c +#define USB2_OC_TIMSET 0x110 +#define USB2_COMMCTRL 0x600 +#define USB2_OBINTSTA 0x604 +#define USB2_OBINTEN 0x608 +#define USB2_VBCTRL 0x60c +#define USB2_LINECTRL1 0x610 +#define USB2_ADPCTRL 0x630 + +/* USBCTR */ +#define USB2_USBCTR_PLL_RST BIT(1) + +/* SPD_RSM_TIMSET */ +#define USB2_SPD_RSM_TIMSET_INIT 0x014e029b + +/* OC_TIMSET */ +#define USB2_OC_TIMSET_INIT 0x000209ab + +/* COMMCTRL */ +#define USB2_COMMCTRL_OTG_PERI BIT(31) /* 1 = Peripheral mode */ + +/* LINECTRL1 */ +#define USB2_LINECTRL1_DP_RPD BIT(18) +#define USB2_LINECTRL1_DM_RPD BIT(16) + +/* ADPCTRL */ +#define USB2_ADPCTRL_DRVVBUS BIT(4) + +struct rcar_gen3_phy { + fdt_addr_t regs; + struct clk clk; + struct udevice *vbus_supply; +}; + +static int rcar_gen3_phy_phy_init(struct phy *phy) +{ + struct rcar_gen3_phy *priv = dev_get_priv(phy->dev); + + /* Initialize USB2 part */ + writel(0, priv->regs + USB2_INT_ENABLE); + writel(USB2_SPD_RSM_TIMSET_INIT, priv->regs + USB2_SPD_RSM_TIMSET); + writel(USB2_OC_TIMSET_INIT, priv->regs + USB2_OC_TIMSET); + + setbits_le32(priv->regs + USB2_LINECTRL1, + USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD); + + clrbits_le32(priv->regs + USB2_COMMCTRL, USB2_COMMCTRL_OTG_PERI); + + setbits_le32(priv->regs + USB2_ADPCTRL, USB2_ADPCTRL_DRVVBUS); + + return 0; +} + +static int rcar_gen3_phy_phy_power_on(struct phy *phy) +{ + struct rcar_gen3_phy *priv = dev_get_priv(phy->dev); + int ret; + + if (priv->vbus_supply) { + ret = regulator_set_enable(priv->vbus_supply, true); + if (ret) + return ret; + } + + setbits_le32(priv->regs + USB2_USBCTR, USB2_USBCTR_PLL_RST); + clrbits_le32(priv->regs + USB2_USBCTR, USB2_USBCTR_PLL_RST); + + return 0; +} + +static int rcar_gen3_phy_phy_power_off(struct phy *phy) +{ + struct rcar_gen3_phy *priv = dev_get_priv(phy->dev); + + if (!priv->vbus_supply) + return 0; + + return regulator_set_enable(priv->vbus_supply, false); +} + +static const struct phy_ops rcar_gen3_phy_phy_ops = { + .init = rcar_gen3_phy_phy_init, + .power_on = rcar_gen3_phy_phy_power_on, + .power_off = rcar_gen3_phy_phy_power_off, +}; + +static int rcar_gen3_phy_probe(struct udevice *dev) +{ + struct rcar_gen3_phy *priv = dev_get_priv(dev); + int ret; + + priv->regs = dev_read_addr(dev); + if (priv->regs == FDT_ADDR_T_NONE) + return -EINVAL; + + ret = device_get_supply_regulator(dev, "vbus-supply", + &priv->vbus_supply); + if (ret && ret != -ENOENT) { + pr_err("Failed to get PHY regulator\n"); + return ret; + } + + /* Enable clock */ + ret = clk_get_by_index(dev, 0, &priv->clk); + if (ret) + return ret; + + ret = clk_enable(&priv->clk); + if (ret) + return ret; + + return 0; +} + +static int rcar_gen3_phy_remove(struct udevice *dev) +{ + struct rcar_gen3_phy *priv = dev_get_priv(dev); + + clk_disable(&priv->clk); + clk_free(&priv->clk); + + return 0; +} + +static const struct udevice_id rcar_gen3_phy_of_match[] = { + { .compatible = "renesas,rcar-gen3-usb2-phy", }, + { }, +}; + +U_BOOT_DRIVER(rcar_gen3_phy) = { + .name = "rcar-gen3-phy", + .id = UCLASS_PHY, + .of_match = rcar_gen3_phy_of_match, + .ops = &rcar_gen3_phy_phy_ops, + .probe = rcar_gen3_phy_probe, + .remove = rcar_gen3_phy_remove, + .priv_auto_alloc_size = sizeof(struct rcar_gen3_phy), +}; -- 2.18.0

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[U-Boot] [U-BOOT][V3 PATCH] configs: icore: Fix U-Boot proper loading from nand
by Shyam Saini 08 Mar '19

08 Mar '19

From: Michael Trimarchi <michael(a)amarulasolutions.com> SPL on Engicam i.Core M6 boards enabled DM, so it would require some malloc() pool before relocation in order to load U-Boot proper properly. So, enable SPL malloc() pool of 0x2000 size similarly like what we have used for icore mmc defconfigs. Reviewed-by: Jagan Teki <jagan(a)amarulasolutions.com> Tested-by: Shyam Saini <shyam.saini(a)amarulasolutions.com> Signed-off-by: Michael Trimarchi <michael(a)amarulasolutions.com> --- Changelogs: V2: improve commit message V3: include Changelogs cc Stefano Babic and Fabio Estevam --- configs/imx6dl_icore_nand_defconfig | 1 + configs/imx6q_icore_nand_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/imx6dl_icore_nand_defconfig b/configs/imx6dl_icore_nand_defconfig index c34c515080e9..69c45b948b3a 100644 --- a/configs/imx6dl_icore_nand_defconfig +++ b/configs/imx6dl_icore_nand_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_MX6Q_ENGICAM=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y diff --git a/configs/imx6q_icore_nand_defconfig b/configs/imx6q_icore_nand_defconfig index cf149d615b32..b53a5010e5dd 100644 --- a/configs/imx6q_icore_nand_defconfig +++ b/configs/imx6q_icore_nand_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_MX6Q_ENGICAM=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y -- 2.11.0

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[U-Boot] tools: board config CONFIG_SYS_BOOTM_LEN is being ignored
by Philipp Puschmann 08 Mar '19

08 Mar '19

Hi, i noticed that CONFIG_SYS_BOOTM_LEN, set in board config, and used in common/bootm.c is ignored when compiling the tools like mkimage and fit_check_sign. Instead the default value of 8MB is used and fit_check_sign may fail with "Loading Kernel Image ... Image too large: increase CONFIG_SYS_BOOTM_LEN". Still the U-Boot binary built with the increased CONFIG_SYS_BOOTM_LEN works without any problem. I'm unsure how and where to fix it in a proper way. The Makefile system ist not quite easy to understand and the CONFIG_* options are spread over various files during build time. It may be possible to move this option to Kconfig. Regards, Philipp

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[U-Boot] [PATCH] rockchip: rk3399: add support for chromebook_kevin
by Marty E. Plummer 08 Mar '19

08 Mar '19

What I've got so far. Currently it does not get any further than the following: U-Boot SPL board init spl_early_init SPL malloc() before relocation used 0x23c8 bytes (8 KB) >>SPL: board_init_r() spl_init SPL: Unsupported Boot Device! SPL: failed to boot from all boot devices ERROR ### Please RESET the board ### Posting to the lists so someone could perhaps assist Signed-off-by: Marty E. Plummer <hanetzer(a)startmail.com> --- arch/arm/dts/rk3399-gru-kevin.dts | 1 + arch/arm/mach-rockchip/rk3399-board-spl.c | 6 +- arch/arm/mach-rockchip/rk3399/Kconfig | 3 + board/google/gru/Kconfig | 16 +++ configs/chromebook_kevin_defconfig | 99 +++++++++++++++++++ include/dt-bindings/input/linux-event-codes.h | 1 + 6 files changed, 123 insertions(+), 3 deletions(-) create mode 100644 configs/chromebook_kevin_defconfig diff --git a/arch/arm/dts/rk3399-gru-kevin.dts b/arch/arm/dts/rk3399-gru-kevin.dts index 2cc7c47d6a..c7ead02af8 100644 --- a/arch/arm/dts/rk3399-gru-kevin.dts +++ b/arch/arm/dts/rk3399-gru-kevin.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "rk3399-gru-chromebook.dtsi" +#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi" #include <dt-bindings/input/linux-event-codes.h> /* diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c index ccc136f388..799fb95013 100644 --- a/arch/arm/mach-rockchip/rk3399-board-spl.c +++ b/arch/arm/mach-rockchip/rk3399-board-spl.c @@ -133,7 +133,7 @@ void board_debug_uart_init(void) #define GPIO0_BASE 0xff720000 #define PMUGRF_BASE 0xff320000 struct rk3399_grf_regs * const grf = (void *)GRF_BASE; -#ifdef CONFIG_TARGET_CHROMEBOOK_BOB +#if defined(CONFIG_TARGET_CHROMEBOOK_BOB) || defined(CONFIG_TARGET_CHROMEBOOK_KEVIN) struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE; struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE; #endif @@ -147,7 +147,7 @@ void board_debug_uart_init(void) GRF_GPIO2C1_SEL_MASK, GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT); #else -# ifdef CONFIG_TARGET_CHROMEBOOK_BOB +# if defined(CONFIG_TARGET_CHROMEBOOK_BOB) || defined(CONFIG_TARGET_CHROMEBOOK_KEVIN) rk_setreg(&grf->io_vsel, 1 << 0); /* @@ -187,7 +187,7 @@ void board_init_f(ulong dummy) #ifdef EARLY_UART debug_uart_init(); -# ifdef CONFIG_TARGET_CHROMEBOOK_BOB +#if defined(CONFIG_TARGET_CHROMEBOOK_BOB) || defined(CONFIG_TARGET_CHROMEBOOK_KEVIN) int sum, i; /* diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 2408adb420..9124bc145a 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -62,6 +62,9 @@ config TARGET_CHROMEBOOK_BOB display. It includes a Chrome OS EC (Cortex-M3) to provide access to the keyboard and battery functions. +config TARGET_CHROMEBOOK_KEVIN + bool "Samsung Chromebook Plus (RK3399)" + endchoice config SYS_SOC diff --git a/board/google/gru/Kconfig b/board/google/gru/Kconfig index 61f7bbca98..1455e1481d 100644 --- a/board/google/gru/Kconfig +++ b/board/google/gru/Kconfig @@ -13,3 +13,19 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y endif + +if TARGET_CHROMEBOOK_KEVIN + +config SYS_BOARD + default "gru" + +config SYS_VENDOR + default "google" + +config SYS_CONFIG_NAME + default "gru" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig new file mode 100644 index 0000000000..9e251137ee --- /dev/null +++ b/configs/chromebook_kevin_defconfig @@ -0,0 +1,99 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_BOOT_MODE_REG=0 +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 +# CONFIG_SPL_MMC_SUPPORT is not set +CONFIG_TARGET_CHROMEBOOK_KEVIN=y +CONFIG_DEBUG_UART_BASE=0xff1a0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-kevin.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 +CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_LOG=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-gru-kevin" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_I2C_CROS_EC_TUNNEL=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_I2C_MUX=y +CONFIG_DM_KEYBOARD=y +CONFIG_CROS_EC_KEYB=y +CONFIG_CROS_EC=y +CONFIG_CROS_EC_SPI=y +CONFIG_PWRSEQ=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_ERRNO_STR=y diff --git a/include/dt-bindings/input/linux-event-codes.h b/include/dt-bindings/input/linux-event-codes.h index 87cf351bab..fff5bc75f9 100644 --- a/include/dt-bindings/input/linux-event-codes.h +++ b/include/dt-bindings/input/linux-event-codes.h @@ -749,6 +749,7 @@ #define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */ #define SW_LINEIN_INSERT 0x0d /* set = inserted */ #define SW_MUTE_DEVICE 0x0e /* set = device disabled */ +#define SW_PEN_INSERTED 0x0f /* set = pen inserted */ #define SW_MAX 0x0f #define SW_CNT (SW_MAX+1) -- 2.21.0

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[U-Boot] [U-BOOT][V2 PATCH] configs: icore: Fix U-Boot proper loading from nand
by Shyam Saini 08 Mar '19

08 Mar '19

From: Michael Trimarchi <michael(a)amarulasolutions.com> SPL on Engicam i.Core M6 boards enabled DM, so it would require some malloc() pool before relocation in order to load U-Boot proper properly. So, enable SPL malloc() pool of 0x2000 size similarly like what we have used for icore mmc defconfigs. Reviewed-by: Jagan Teki <jagan(a)amarulasolutions.com> Tested-by: Shyam Saini <shyam.saini(a)amarulasolutions.com> Signed-off-by: Michael Trimarchi <michael(a)amarulasolutions.com> --- configs/imx6dl_icore_nand_defconfig | 1 + configs/imx6q_icore_nand_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/imx6dl_icore_nand_defconfig b/configs/imx6dl_icore_nand_defconfig index c34c515080e9..69c45b948b3a 100644 --- a/configs/imx6dl_icore_nand_defconfig +++ b/configs/imx6dl_icore_nand_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_MX6Q_ENGICAM=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y diff --git a/configs/imx6q_icore_nand_defconfig b/configs/imx6q_icore_nand_defconfig index cf149d615b32..b53a5010e5dd 100644 --- a/configs/imx6q_icore_nand_defconfig +++ b/configs/imx6q_icore_nand_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_MX6Q_ENGICAM=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y -- 2.11.0

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