March 2019 - U-Boot

[U-Boot] [PATCH 1/3] armv8: ls1028a: Add NXP LS1028A SoC support
by Bhaskar Upadhaya 22 Mar '19

22 Mar '19

Overview ======== LS1028A processor integrates two 64-bit Arm Cortex-A72 cores with a GPU and LCD controller, as well as TSN-enabled Ethernet ports and a TSN-enabled switch with four external ports. The high performance Cortex-A72 cores, performing above 16,000 CoreMarks, combined with 2.5 Gbit Ethernet, PCI express Gen 3.0, SATA 3.0, USB 3.0 and Octal/Quad SPI interfaces provide capabilities for a number of industrial and embedded applications. The device provides excellent integration with the new Time-Sensitive Networking standards and enables a number of TSN applications Frequency support: Core: 1300 MHz, DDR: 1600 MT/s, Platform: 400 MHz [default] Core: 800 MHz, DDR: 1300 MT/s, Platform: 400 MHz SerDes protocol support: SerDes1: 0x85bb [default] SerDes2: 0x85be Features Summary ================ Two 32/64-bit Arm® v8 Cortex®-A72 CPUs Arranged as a single cluster of two cores sharing a single 1 MB L2 cache Up to 1.3 GHz operation Single-threaded cores with 32KB L1 data cache and 48KB L1 instruction cache, Support for cluster power-gating Cache coherent interconnect fabric (CCI-400) Hardware managed data coherency Up to 400 MHz operation 32-bit DDR3L/DDR4 SDRAM memory controller with ECC support Up to 1.6 GT/s Supports 32-bit and 16-bit operation Accumulated mode ECC for 32-bit, 16-bit use Supports DDR4 Pseudo-Open Drain mode Support for x8 and x16 devices LCD controller and DisplayPort/eDP interface Supports DisplayPort 1.3 and eDP 1.4 Supports link transfer rate up to HBR2 (5.4 Gbit/s) and display resolution up to 4Kp60 Graphics processing unit Supports Geometry rate 100 Mtri/s and Pixel rate 650 Mpixel/s Supports OpenGL ES 3.0, 2.0, 1.1 Supports OpenCL 1.2, 1.1 TSN-capable Ethernet Switch with four external ports Ethernet Controller (ENETC) with TSN functionality One RGMII interface One 1G/2.5G SerDes-based interface with TSN support Four SerDes lanes with two PLLs for high-speed peripheral interfaces Two PCI Express 3.0 controllers Serial ATA (SATA 6 Gbit/s) controller Up to four SGMII interfaces supporting 1000 Mbps Up to one QSGMII interface Supports 1000Base-KX Up to one 10G-SXGMII Up to one 10G-QXGMII Additional peripheral interfaces Two high-speed USB 3.0 controllers with integrated PHY each supporting host or device modes Two enhanced secure digital host controllers (eSDHC) supporting SD 3.0, eMMC 4.4, eMMC 4.5, and eMMC 5.1 Two controller area network (FlexCAN) modules, each optionally supporting flexible datarate (FD) Three serial peripheral interface (SPI) controllers Flexible SPI interface (FlexSPI) controller with two 8-bit interfaces Eight I2C controllers Six LPUARTs 16550-compliant DUART General Purpose IO (GPIO) Eight FlexTimers/PWM controllers Six asynchronous audio interface (SAI) Support for hardware virtualization and partitioning enforcement QorIQ platform's trust architecture 3.0 Service processor (SP) provides pre-boot initialization and secure-boot capabilities.256 KB On chip RAM for trusted accesses One WatchDog timer per A72 core and one TrustZone WatchDog timer Queue direct memory access controller (qDMA) Enhanced direct memory access controller (eDMA) Global programmable interrupt controller (GIC) Arm generic timer Thermal Monitor Unit (TMU) Multimedia and audio support: Resolution supported: 480p,720p,1080p, and 4K Support audio on serial interfaces with frame synchronization Time Sensitive Network (TSN) support: TSN configuration tool (tsntool) ENETC 1588 two steps timestamping support ENETC TSN driver: Qbv, Qbu, Qci, Qav SWITCH TSN driver: Qbv, Qci, Qbu, Qav, 802.1CB support Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta(a)nxp.com> Signed-off-by: Rai Harninder <harninder.rai(a)nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat(a)nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 39 ++- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 4 + arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 1 + arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 51 ++++ arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c | 88 +++++++ arch/arm/dts/fsl-ls1028a.dtsi | 281 +++++++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 61 +++++ .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 16 ++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 11 + arch/arm/include/asm/arch-fsl-layerscape/soc.h | 1 + .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 2 +- board/freescale/common/qixis.c | 38 +++ board/freescale/common/qixis.h | 2 + 13 files changed, 593 insertions(+), 2 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c create mode 100644 arch/arm/dts/fsl-ls1028a.dtsi diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index f48481f..8ecd095 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -20,6 +20,40 @@ config ARCH_LS1012A select SYS_I2C_MXC_I2C2 imply PANIC_HANG +config ARCH_LS1028A + bool + select ARMV8_SET_SMPEN + select FSL_LSCH3 + select NXP_LSCH3_2 + select SYS_FSL_HAS_CCI400 + select SYS_FSL_SRDS_1 + select SYS_HAS_SERDES + select SYS_FSL_DDR + select SYS_FSL_DDR_LE + select SYS_FSL_DDR_VER_50 + select SYS_FSL_HAS_DDR3 + select SYS_FSL_HAS_DDR4 + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_5 + select SYS_FSL_SEC_LE + select FSL_TZASC_1 + select ARCH_EARLY_INIT_R + select BOARD_EARLY_INIT_F + select SYS_I2C_MXC + select SYS_I2C_MXC_I2C1 + select SYS_I2C_MXC_I2C2 + select SYS_I2C_MXC_I2C3 + select SYS_I2C_MXC_I2C4 + select SYS_I2C_MXC_I2C5 + select SYS_I2C_MXC_I2C6 + select SYS_I2C_MXC_I2C7 + select SYS_I2C_MXC_I2C8 + select SYS_FSL_ERRATUM_A009007 + select SYS_FSL_ERRATUM_A008514 if !TFABOOT + select SYS_FSL_ERRATUM_A009663 if !TFABOOT + select SYS_FSL_ERRATUM_A009942 if !TFABOOT + imply PANIC_HANG + config ARCH_LS1043A bool select ARMV8_SET_SMPEN @@ -244,6 +278,7 @@ config FSL_PCIE_COMPAT string "PCIe compatible of Kernel DT" depends on PCIE_LAYERSCAPE default "fsl,ls1012a-pcie" if ARCH_LS1012A + default "fsl,ls1028a-pcie" if ARCH_LS1028A default "fsl,ls1043a-pcie" if ARCH_LS1043A default "fsl,ls1046a-pcie" if ARCH_LS1046A default "fsl,ls2080a-pcie" if ARCH_LS2080A @@ -343,6 +378,7 @@ config SYS_FSL_ERRATUM_A010539 config MAX_CPUS int "Maximum number of CPUs permitted for Layerscape" + default 2 if ARCH_LS1028A default 4 if ARCH_LS1043A default 4 if ARCH_LS1046A default 16 if ARCH_LS2080A @@ -377,7 +413,7 @@ config QSPI_AHB_INIT config SYS_CCI400_OFFSET hex "Offset for CCI400 base" depends on SYS_FSL_HAS_CCI400 - default 0x3090000 if ARCH_LS1088A + default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A default 0x180000 if FSL_LSCH2 help Offset for CCI400 base @@ -446,6 +482,7 @@ config CLUSTER_CLK_FREQ config SYS_FSL_PCLK_DIV int "Platform clock divider" + default 1 if ARCH_LS1028A default 1 if ARCH_LS1043A default 1 if ARCH_LS1046A default 1 if ARCH_LS1088A diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index e9bc987..a8d3cf9 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -48,3 +48,7 @@ endif ifneq ($(CONFIG_ARCH_LS1088A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls1088a_serdes.o endif + +ifneq ($(CONFIG_ARCH_LS1028A),) +obj-$(CONFIG_SYS_HAS_SERDES) += ls1028a_serdes.o +endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 978d46b..51e077c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -58,6 +58,7 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(LS1026A, LS1026A, 2), CPU_TYPE_ENTRY(LS2040A, LS2040A, 4), CPU_TYPE_ENTRY(LS1012A, LS1012A, 1), + CPU_TYPE_ENTRY(LS1028A, LS1028A, 2), CPU_TYPE_ENTRY(LS1088A, LS1088A, 8), CPU_TYPE_ENTRY(LS1084A, LS1084A, 8), CPU_TYPE_ENTRY(LS1048A, LS1048A, 4), diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc index a0e2621..d82a96c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc @@ -8,6 +8,7 @@ SoC overview 6. LS2088A 7. LS2081A 8. LX2160A + 9. LS1028A LS1043A --------- @@ -328,3 +329,53 @@ LX2160A SoC has 2 more similar SoC personalities 2)LX2080A, few difference w.r.t. LX2160A: a) Eight 64-bit ARM v8 Cortex-A72 CPUs + + +LS1028A +-------- +The QorIQ LS1028A processor integrates two 64-bit Arm® Cortex®-A72 cores with +a GPU and LCD controller, as well as two TSN-enabled Ethernet controllers and +a TSNenabled 4-port switch. + +The high performance Cortex-A72 cores, performing above 16,000 CoreMarks®, +combined with 2.5 Gbit Ethernet, PCI express Gen 3.0, SATA 3.0, USB 3.0 and +Octal/Quad SPI interfaces provide capabilities for a number of industrial and +embedded applications. The device provides excellent integration with the +new Time-Sensitive Networking standard, and enables a number of +TSN applications. + +The LS1028A SoC includes the following function and features: + - Two 64-bit ARM v8 A72 CPUs + - Cache Coherent interconnect (CCI-400) + - One 32-bit DDR3L/DDR4 SDRAM memory controller with ECC + - eDP/Displayport interface + - Graphics processing unit + - One Configurable x4 SerDes + - Ethernet interfaces + - Non-switched: One Ethernet MAC supporting 2.5G, 1G, 100M, 10M, one + ethernet MAC supporting 1G, 100M, 10M. + - Switched: TSN IP to support four 2.5/1G interfaces. + - None of the MACs support MACSEC + - Support for RGMII, SGMII (and 1000Base-KX), SGMII 2.5x, QSGMII + - Support for 10G-SXGMII and 10G-QXGMII. + - Energy efficient Ethernet support (802.3az) + - IEEE 1588 support + - High-speed peripheral interfaces + - Two PCIe 3.0 controllers, one supporting x4 operation + - One serial ATA (SATA 3.0) controller + - Additional peripheral interfaces + - Two high-speed USB 2.0/3.0 controllers with integrated PHY each + supporting host or device modes + - Two Enhanced secure digital host controllers (SD/SDIO/eMMC) + - Two Serial peripheral interface (SPI) controllers + - Eight I2C controllers + - Two UART controllers + - Additional six Industrual UARTs (LPUART). + - One FlexSPI controller + - General Purpose IO (GPIO) + - Two CAN-FD interfaces + - Eight Flextimers with PWM I/O + - Support for hardware virtualization and partitioning enforcement + - Layerscape Trust Architecture + - Service Processor (SP) provides pre-boot initialization and secure-boot + capabilities diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c new file mode 100644 index 0000000..f5f264c --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <common.h> +#include <asm/arch/fsl_serdes.h> + +struct serdes_config { + u32 protocol; + u8 lanes[SRDS_MAX_LANES]; + u8 rcw_lanes[SRDS_MAX_LANES]; +}; + +static struct serdes_config serdes1_cfg_tbl[] = { + /* SerDes 1 */ + {0xE031, {SXGMII1, QXGMII2, NONE, SATA1} }, + {0xB991, {SXGMII1, SGMII1, SGMII2, PCIE1} }, + {0xBB31, {SXGMII1, QXGMII2, PCIE1, PCIE1} }, + {0xCC31, {SXGMII1, QXGMII2, PCIE2, PCIE2} }, + {0xBB51, {SXGMII1, QSGMII_B, PCIE2, PCIE1} }, + {0xCC51, {SXGMII1, QSGMII_B, PCIE2, PCIE2} }, + {0xCC3B, {PCIE1, QXGMII2, PCIE2, PCIE2} }, + {0xCC5B, {PCIE1, QSGMII_B, PCIE2, PCIE2} }, + {0xBB38, {SGMII_T1, QXGMII2, PCIE2, PCIE1} }, + {0xCC38, {SGMII_T1, QXGMII2, PCIE2, PCIE2} }, + {0xBB58, {SGMII_T1, QSGMII_B, PCIE2, PCIE1} }, + {0xEB99, {SGMII1, SGMII1, PCIE2, SATA1} }, + {0xCC99, {SGMII1, SGMII1, PCIE2, PCIE2} }, + {0xBB99, {SGMII1, SGMII1, PCIE2, PCIE1} }, + {0xCC58, {SGMII_T1, QSGMII_B, PCIE2, PCIE2} }, + {0xCC8B, {PCIE1, SGMII_T1, PCIE2, PCIE2} }, + {0x9999, {SGMII1, SGMII2, SGMII3, SGMII4} }, + {0xEB58, {SGMII_T1, QSGMII_B, PCIE2, SATA1} }, + {0xEB8B, {PCIE1, SGMII_T1, PCIE2, SATA1} }, + {0xE8CC, {PCIE1, PCIE1, SGMII_T1, SATA1} }, + {0xEBCC, {PCIE1, PCIE1, PCIE2, SATA1} }, + {0xCCCC, {PCIE1, PCIE1, PCIE2, PCIE2} }, + {0xDDDD, {PCIE1, PCIE1, PCIE1, PCIE1} }, + {} +}; + +static struct serdes_config *serdes_cfg_tbl[] = { + serdes1_cfg_tbl, +}; + +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) +{ + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == cfg) + return ptr->lanes[lane]; + ptr++; + } + + return 0; +} + +int is_serdes_prtcl_valid(int serdes, u32 prtcl) +{ + int i; + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == prtcl) + break; + ptr++; + } + + if (!ptr->protocol) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (ptr->lanes[i] != NONE) + return 1; + } + + return 0; +} diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi new file mode 100644 index 0000000..08deb22 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -0,0 +1,281 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP ls1028a SOC common device tree source + * + * Copyright 2019 NXP + * + */ + +/ { + compatible = "fsl,ls1028a"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; + + clockgen: clocking@1300000 { + compatible = "fsl,ls1028a-clockgen"; + reg = <0x0 0x1300000 0x0 0xa0000>; + #clock-cells = <2>; + clocks = <&sysclk>; + }; + + memory@01080000 { + device_type = "memory"; + reg = <0x00000000 0x01080000 0 0x80000000>; + /* DRAM space - 1, size : 2 GB DRAM */ + }; + + gic: interrupt-controller@6000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ + <0x0 0x06040000 0 0x40000>; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <1 9 0x4>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ + <1 14 0x8>, /* Physical Non-Secure PPI, active-low */ + <1 11 0x8>, /* Virtual PPI, active-low */ + <1 10 0x8>; /* Hypervisor PPI, active-low */ + }; + + fspi: flexspi@20C0000 { + compatible = "nxp,dn-fspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20C0000 0x0 0x10000>, + <0x0 0x20000000 0x0 0x10000000>; /*64MB flash*/ + /* <0x0 0x20000000 0x0 0x4000000>;*/ /*How to incoperate 512M here*/ + reg-names = "FSPI", "FSPI-memory"; + num-cs = <1>; + status = "disabled"; + }; + + serial0: serial@21c0500 { + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21c0500 0x0 0x100>; + clock-frequency = <0>; /* Updated by bootloader */ + interrupts = <0 32 0x1>; /* edge triggered */ + }; + + serial1: serial@21c0600 { + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21c0600 0x0 0x100>; + clock-frequency = <0>; /* Updated by bootloader */ + interrupts = <0 32 0x1>; /* edge triggered */ + }; + + pcie@3400000 { /* rcie_enetc */ + compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie"; + reg = <0x00 0x03400000 0x0 0x80000 + 0x00 0x03480000 0x0 0x40000 /* lut registers */ + 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */ + 0x80 0x00000000 0x0 0x20000>; /* configuration space */ + reg-names = "dbi", "lut", "ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + }; + + pcie@3500000 { + compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie"; + reg = <0x00 0x03500000 0x0 0x80000 + 0x00 0x03580000 0x0 0x40000 /* lut registers */ + 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */ + 0x88 0x00000000 0x0 0x20000>; /* configuration space */ + reg-names = "dbi", "lut", "ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + }; + + enetc_pcie: pcie@1f0000000 { /* rcie_enetc */ + compatible = "fsl,ls-enetc-rcie"; + reg= <0x01 0xf0000000 0x0 0x100000>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0x0>; + /* PF0-6 BAR0 - non-prefetchable memory */ + ranges= <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000>; + }; + + i2c0: i2c@2000000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2000000 0x0 0x10000>; + interrupts = <0 34 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + }; + + i2c1: i2c@2010000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2010000 0x0 0x10000>; + interrupts = <0 34 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + }; + + i2c2: i2c@2020000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2020000 0x0 0x10000>; + interrupts = <0 35 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + }; + + i2c3: i2c@2030000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2030000 0x0 0x10000>; + interrupts = <0 35 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + }; + + i2c4: i2c@2040000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2040000 0x0 0x10000>; + interrupts = <0 74 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + }; + + i2c5: i2c@2050000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2050000 0x0 0x10000>; + interrupts = <0 74 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + }; + + i2c6: i2c@2060000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2060000 0x0 0x10000>; + interrupts = <0 75 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + }; + + i2c7: i2c@2070000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2070000 0x0 0x10000>; + interrupts = <0 75 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + }; + + usb1: usb3@3100000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <0 80 0x4>; + dr_mode = "host"; + }; + + usb2: usb3@3110000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3110000 0x0 0x10000>; + interrupts = <0 81 0x4>; + dr_mode = "host"; + }; + + dspi0: dspi@2100000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2100000 0x0 0x10000>; + interrupts = <0 26 0x4>; + clock-names = "dspi"; + clocks = <&clockgen 4 0>; + num-cs = <5>; + litte-endian; + status = "disabled"; + }; + + dspi1: dspi@2110000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2110000 0x0 0x10000>; + interrupts = <0 26 0x4>; + clock-names = "dspi"; + clocks = <&clockgen 4 0>; + num-cs = <5>; + little-endian; + status = "disabled"; + }; + + dspi2: dspi@2120000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2120000 0x0 0x10000>; + interrupts = <0 26 0x4>; + clock-names = "dspi"; + clocks = <&clockgen 4 0>; + num-cs = <5>; + little-endian; + status = "disabled"; + }; + + esdhc0: esdhc@2140000 { + compatible = "fsl,esdhc"; + reg = <0x0 0x2140000 0x0 0x10000>; + interrupts = <0 28 0x4>; + big-endian; + bus-width = <4>; + }; + + esdhc1: esdhc@2150000 { + compatible = "fsl,esdhc"; + reg = <0x0 0x2150000 0x0 0x10000>; + interrupts = <0 63 0x4>; + big-endian; + non-removable; + bus-width = <4>; + }; + + sata: sata@3200000 { + compatible = "fsl,ls1028a-ahci"; + reg = <0x0 0x3200000 0x0 0x10000>; + interrupts = <0 133 4>; + clocks = <&clockgen 4 1>; + status = "disabled"; + }; + +}; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 903d509..eb21c09 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -229,6 +229,67 @@ #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 +#elif defined(CONFIG_ARCH_LS1028A) +#define CONFIG_SYS_FSL_NUM_CC_PLLS 3 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } +#define CONFIG_GICV3 +#define CONFIG_FSL_TZPC_BP147 +#define CONFIG_FSL_TZASC_400 + +/* TZ Protection Controller Definitions */ +#define TZPC_BASE 0x02200000 +#define TZPCR0SIZE_BASE (TZPC_BASE) +#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) +#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) +#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) +#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) +#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) +#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) +#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) +#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) +#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) + +#define SRDS_MAX_LANES 4 + +#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ +#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M */ +#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */ + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0x06000000 +#define GICR_BASE 0x06040000 + +/* SMMU Definitions */ +#define SMMU_BASE 0x05000000 /* GR0 Base */ + +/* DDR */ +#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE + +#define CONFIG_SYS_FSL_CCSR_GUR_LE +#define CONFIG_SYS_FSL_CCSR_SCFG_LE +#define CONFIG_SYS_FSL_ESDHC_LE +#define CONFIG_SYS_FSL_PEX_LUT_LE + +#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN + +/* SFP */ +#define CONFIG_SYS_FSL_SFP_VER_3_4 +#define CONFIG_SYS_FSL_SFP_LE +#define CONFIG_SYS_FSL_SRK_LE + +/* SEC */ +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 + +/* Security Monitor */ +#define CONFIG_SYS_FSL_SEC_MON_LE + +/* Secure Boot */ +#define CONFIG_ESBC_HDR_LS + +/* DCFG - GUR */ +#define CONFIG_SYS_FSL_CCSR_GUR_LE + #elif defined(CONFIG_FSL_LSCH2) #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index 68354ff..59b224b 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -64,6 +64,22 @@ enum srds_prtcl { QSGMII_B, QSGMII_C, QSGMII_D, + SGMII_T1, + SGMII_T2, + SGMII_T3, + SGMII_T4, + SGMII_S1, + SGMII_S2, + SGMII_S3, + SGMII_S4, + SXGMII1, + SXGMII2, + SXGMII3, + SXGMII4, + QXGMII1, + QXGMII2, + QXGMII3, + QXGMII4, _25GE1, _25GE2, _25GE3, diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 9fab88a..2cd6bb4 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -171,6 +171,11 @@ #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x2000000000ULL #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x2800000000ULL #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x3000000000ULL +#elif CONFIG_ARCH_LS1028A +#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL +#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL +#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL +#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL #else #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL @@ -375,6 +380,12 @@ struct ccsr_gur { #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT #define FSL_CHASSIS3_SRDS1_REGSR 29 #define FSL_CHASSIS3_SRDS2_REGSR 30 +#elif defined(CONFIG_ARCH_LS1028A) +#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 0xFFFF0000 +#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 16 +#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK +#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS1_REGSR 29 #endif #define RCW_SB_EN_REG_INDEX 9 #define RCW_SB_EN_MASK 0x00000400 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 7d95c4e..234440b 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -83,6 +83,7 @@ enum boot_src get_boot_src(void); /* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */ #define SVR_LS1043A_P23 0x879202 #define SVR_LS1023A_P23 0x87920A +#define SVR_LS1028A 0x870B00 #define SVR_LS1046A 0x870700 #define SVR_LS1026A 0x870708 #define SVR_LS1048A 0x870320 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index e017d8b..c53cc57 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -87,7 +87,7 @@ #define FSL_PEX_STREAM_ID_NUM (0x100) #endif -#if defined(CONFIG_ARCH_LS2080A) +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1028A) #define FSL_PEX_STREAM_ID_END 22 #elif defined(CONFIG_ARCH_LS1088A) #define FSL_PEX_STREAM_ID_END 18 diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c index f1b98bc..59337ef 100644 --- a/board/freescale/common/qixis.c +++ b/board/freescale/common/qixis.c @@ -50,6 +50,17 @@ void qixis_write(unsigned int reg, u8 value) } #endif +bool qixis_read_released(void) +{ + bool released; + + /* this data is in little endian */ + QIXIS_WRITE(tagdata, 0xc); + released = QIXIS_READ(tagdata); + + return released; +} + u16 qixis_read_minor(void) { u16 minor; @@ -63,6 +74,27 @@ u16 qixis_read_minor(void) return minor; } +char *qixis_read_date(char *buf) +{ + int i; + time_t time = 0; + struct tm t; + char *ptr = buf; + + /* timestamp is in 32-bit big endian */ + for (i = 8; i <= 11; i++) { + QIXIS_WRITE(tagdata, i); + time = (time << 8) + QIXIS_READ(tagdata); + } + + localtime_r(&time, &t); + sprintf(ptr, "%4d_%02d%02d_%02d%02d", + t.tm_year + 1900, + t.tm_mon + 1, t.tm_mday, t.tm_hour, t.tm_min); + + return buf; +} + char *qixis_read_time(char *result) { time_t time = 0; @@ -142,11 +174,13 @@ static void qixis_reset(void) QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET); } +#ifdef QIXIS_LBMAP_ALTBANK static void qixis_bank_reset(void) { QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE); QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START); } +#endif static void __maybe_unused set_lbmap(int lbmap) { @@ -210,8 +244,12 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar set_lbmap(QIXIS_LBMAP_DFLTBANK); qixis_reset(); } else if (strcmp(argv[1], "altbank") == 0) { +#ifdef QIXIS_LBMAP_ALTBANK set_lbmap(QIXIS_LBMAP_ALTBANK); qixis_bank_reset(); +#else + printf("No Altbank!\n"); +#endif } else if (strcmp(argv[1], "nand") == 0) { #ifdef QIXIS_LBMAP_NAND QIXIS_WRITE(rst_ctl, 0x30); diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h index c11062e..feda0a8 100644 --- a/board/freescale/common/qixis.h +++ b/board/freescale/common/qixis.h @@ -90,7 +90,9 @@ struct qixis { u8 qixis_read(unsigned int reg); void qixis_write(unsigned int reg, u8 value); +bool qixis_read_released(void); u16 qixis_read_minor(void); +char *qixis_read_date(char *buf); char *qixis_read_time(char *result); char *qixis_read_tag(char *buf); const char *byte_to_binary_mask(u8 val, u8 mask, char *buf); -- 1.9.1

2 5

[U-Boot] [PATCH] lib: tiny-printf: Add "%ll" modifier support
by Ley Foon Tan 22 Mar '19

22 Mar '19

Add "%ll" modifier support for tiny printf. - Tested on ARM32 and ARM64 systems. - Tested "%lld", "%llu", "%llx" and "%p" format with minimum and maximum ranges. Compared tiny printf output with full printf. Signed-off-by: Ley Foon Tan <ley.foon.tan(a)intel.com> --- lib/tiny-printf.c | 42 +++++++++++++++++++++++++++++------------- 1 file changed, 29 insertions(+), 13 deletions(-) diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c index ebef92fc9f..692430efac 100644 --- a/lib/tiny-printf.c +++ b/lib/tiny-printf.c @@ -33,8 +33,8 @@ static void out_dgt(struct printf_info *info, char dgt) info->zs = 1; } -static void div_out(struct printf_info *info, unsigned long *num, - unsigned long div) +static void div_out(struct printf_info *info, unsigned long long *num, + unsigned long long div) { unsigned char dgt = 0; @@ -160,8 +160,8 @@ static void ip4_addr_string(struct printf_info *info, u8 *addr) static void pointer(struct printf_info *info, const char *fmt, void *ptr) { #ifdef DEBUG - unsigned long num = (uintptr_t)ptr; - unsigned long div; + unsigned long long num = (uintptr_t)ptr; + unsigned long long div; #endif switch (*fmt) { @@ -199,9 +199,9 @@ static int _vprintf(struct printf_info *info, const char *fmt, va_list va) { char ch; char *p; - unsigned long num; - char buf[12]; - unsigned long div; + unsigned long long num; + char buf[22]; + unsigned long long div; while ((ch = *(fmt++))) { if (ch != '%') { @@ -210,6 +210,7 @@ static int _vprintf(struct printf_info *info, const char *fmt, va_list va) bool lz = false; int width = 0; bool islong = false; + bool islonglong = false; ch = *(fmt++); if (ch == '-') @@ -229,7 +230,13 @@ static int _vprintf(struct printf_info *info, const char *fmt, va_list va) } if (ch == 'l') { ch = *(fmt++); - islong = true; + if (ch == 'l') { + islonglong = true; + ch = *(fmt++); + } else { + islong = true; + } + } info->bf = buf; @@ -242,7 +249,10 @@ static int _vprintf(struct printf_info *info, const char *fmt, va_list va) case 'u': case 'd': div = 1000000000; - if (islong) { + if (islonglong) { + num = va_arg(va, unsigned long long); + div *= div * 10; + } else if (islong) { num = va_arg(va, unsigned long); if (sizeof(long) > 4) div *= div * 10; @@ -251,10 +261,13 @@ static int _vprintf(struct printf_info *info, const char *fmt, va_list va) } if (ch == 'd') { - if (islong && (long)num < 0) { + if (islonglong && (long long)num < 0) { + num = -(long long)num; + out(info, '-'); + } else if (islong && (long)num < 0) { num = -(long)num; out(info, '-'); - } else if (!islong && (int)num < 0) { + } else if ((!islong && !islonglong) && (int)num < 0) { num = -(int)num; out(info, '-'); } @@ -267,9 +280,12 @@ static int _vprintf(struct printf_info *info, const char *fmt, va_list va) } break; case 'x': - if (islong) { + if (islonglong) { + num = va_arg(va, unsigned long long); + div = 1ULL << (sizeof(long long) * 8 - 4); + } else if (islong) { num = va_arg(va, unsigned long); - div = 1UL << (sizeof(long) * 8 - 4); + div = 1ULL << (sizeof(long) * 8 - 4); } else { num = va_arg(va, unsigned int); div = 0x10000000; -- 2.19.0

4 6

[U-Boot] [PATCH v3 00/26] subject: fs: fat: extend FAT write operations
by Akashi, Takahiro 22 Mar '19

22 Mar '19

This patch series[1] is an attempt to address FAT write related issues in an effort of running UEFI SCT (Self-Certification Test) to verify UEFI support on u-boot. SCT is a test platform as well as an extensive collection of test cases for UEFI specification. It can run all the tests automatically and save test results to dedicated log files. AFAIK, what's missing in the current fat file system to safely run SCT without errors (I don't mean test case failures) are: * write a file located under sub-directories * write a file with non-zero offset * delete a file * create a directory What's more, this series contains a file system test; "basic" test is directly derived from test/test-fs.sh. The others, "ext" and "mkdir," are solely for newly added functionality in this patch series. Patch#1 to patch#7 are some sort of preparatory ones. Patch#8 implements write with sub-directories path. Patch#9 to patch#11 implement write with non-zero offset. Patch#12 to patch#16 are related to creating a directory. Patch#17 to patch#20 allows for deleting a file or directory. Patch#21 fixes a minor bug in fs-test.sh. Patch#22 updates a test result summary. Patch#23 to patch#26 add a file system test in U-boot pytest suite. I applied this patch series on top of v2018.09-rc along with a couple of yet-to--be-upstreamed UEFI-related patches, and could successfully run unmodified SCT[2] on qemu-arm(arm64). === future TODO list === 1. set creation (,access and modification) time 2. debug() vs. printf() 3. open()'s parameter checks 4. precisely detect and prevent write() beyond out-of-space 5. create an unique short name from a long file name 6. fat32's fsInfo support Without (5) or (6), fsck may issue warnings. [1] https://git.linaro.org/people/takahiro.akashi/u-boot.git fat_write [2] http://uefi.org/testtools Changes in v3 (Sep 11, 2018) * remove v2's patch#4 which tries to make iterator symbols global * add unlink operation along with a pytest script * use guestmount, if available, for non-root user * remove all the filesystem images created in tests Changes in v2 (Sep 4, 2018) * guard the whole content of fat.h with CONFIG_FS_FAT against a compiler warning * determine total_sect in struct fsdata correctly, depending on fat type (12/16 or 32) * explicitly revert "fs: fat: cannot write to subdirectories" * add test scripts with pytest, mostly the same as RFC, but removing "sudo" for ext4 case AKASHI Takahiro (25): fs: fat: guard the content of include/fat.h fs: fat: extend get_fs_info() for write use fs: fat: handle "." and ".." of root dir correctly with fat_itr_resolve() fs: fat: assure iterator's ->dent belongs to ->clust Revert "fs: fat: cannot write to subdirectories" fs: fat: check and normalize file name fs: fat: write returns error code instead of -1 fs: fat: support write with sub-directory path fs: fat: refactor write interface for a file offset fs: fat: support write with non-zero offset cmd: fat: add offset parameter to fatwrite fs: add mkdir interface fs: fat: remember the starting cluster number of directory fs: fat: support mkdir cmd: fat: add fatmkdir command efi_loader: file: support creating a directory fs: add unlink interface fs: fat: support unlink cmd: fat: add fatrm command efi_loader: implement a file delete fs-test: fix false positive error at Test Case 12 fs-test: update the test result as of v2018.09 test/py: convert fs-test.sh to pytest test/py: fs: add extended write operation test test/py: fs: add fstest/mkdir test Akashi, Takahiro (1): test/py: fs: add fstest/unlink test cmd/fat.c | 34 +- fs/fat/fat.c | 65 +- fs/fat/fat_write.c | 1183 +++++++++++++++++--------- fs/fs.c | 87 ++ include/fat.h | 7 + include/fs.h | 22 + lib/efi_loader/efi_file.c | 28 +- test/fs/fs-test.sh | 24 +- test/py/tests/test_fs/conftest.py | 392 +++++++++ test/py/tests/test_fs/fstest_defs.py | 13 + test/py/tests/test_fs/test_basic.py | 287 +++++++ test/py/tests/test_fs/test_ext.py | 224 +++++ test/py/tests/test_fs/test_mkdir.py | 112 +++ test/py/tests/test_fs/test_unlink.py | 109 +++ 14 files changed, 2136 insertions(+), 451 deletions(-) create mode 100644 test/py/tests/test_fs/conftest.py create mode 100644 test/py/tests/test_fs/fstest_defs.py create mode 100644 test/py/tests/test_fs/test_basic.py create mode 100644 test/py/tests/test_fs/test_ext.py create mode 100644 test/py/tests/test_fs/test_mkdir.py create mode 100644 test/py/tests/test_fs/test_unlink.py -- 2.18.0

9 50

[U-Boot] [PATCHv2 0/6] dm: cache: add dm cache driver
by Dinh Nguyen 22 Mar '19

22 Mar '19

Hi, This is V2 of the series to add a UCLASS_CACHE dm driver to handling the configuration of cache settings. Place this new driver under /drivers/cache. In this initial revision, the driver is only configuring what I think are essential cache settings. The more comprehensive cache settings can be done in the OS. Diffs from v1: - Add a DTS bindings document from Linux for the PL310. - Split up the UCLASS_CACHE addition from the driver patches. - Add a sandbox cache driver. - Add a simple test in test/dm/cache.c - Address comments from Simon Glass. - Add Reviewed-by's from Marek Vasut. Dinh Nguyen (6): Documentation: dts: Add pl310 cache controller dts documentation ARM: pl310: Add macro's for handling tag and data latency mask dm: cache: Create a uclass for cache dm: cache: add the pl310 cache controller driver ARM: socfpga: use the pl310 driver to configure the cache configs: socfpga: add imply pl310 cache controller .../devicetree/bindings/arm/l2c2x0.txt | 114 ++++++++++++++++++ arch/arm/Kconfig | 1 + arch/arm/include/asm/pl310.h | 3 + arch/arm/mach-socfpga/misc.c | 16 +-- drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/cache/Kconfig | 25 ++++ drivers/cache/Makefile | 4 + drivers/cache/cache-l2x0.c | 75 ++++++++++++ drivers/cache/cache-uclass.c | 13 ++ drivers/cache/sandbox_cache.c | 34 ++++++ include/cache.h | 33 +++++ include/dm/uclass-id.h | 1 + test/dm/cache.c | 19 +++ 14 files changed, 328 insertions(+), 13 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/l2c2x0.txt create mode 100644 drivers/cache/Kconfig create mode 100644 drivers/cache/Makefile create mode 100644 drivers/cache/cache-l2x0.c create mode 100644 drivers/cache/cache-uclass.c create mode 100644 drivers/cache/sandbox_cache.c create mode 100644 include/cache.h create mode 100644 test/dm/cache.c -- 2.20.0

2 12

[U-Boot] [PATCH 1/2] common: spl_fit: Default to IH_OS_U_BOOT if FIT_IMAGE_TINY enabled
by Abel Vesa 22 Mar '19

22 Mar '19

If FIT_IMAGE_TINY is enabled, spl_fit_image_get_os returns -ENOTSUPP. In this case, we should default to IH_OS_U_BOOT not to IH_OS_INVALID. Signed-off-by: Abel Vesa <abel.vesa(a)nxp.com> --- common/spl/spl_fit.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index db43626..b190612 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -491,6 +491,8 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, if (!spl_fit_image_get_os(fit, node, &os_type)) debug("Loadable is %s\n", genimg_get_os_name(os_type)); + else + os_type = IH_OS_U_BOOT; if (os_type == IH_OS_U_BOOT) { spl_fit_append_fdt(&image_info, info, sector, -- 2.7.4

3 3

[U-Boot] [PATCH 0/3] thermal: Add multiple instance support
by Keerthy 22 Mar '19

22 Mar '19

This series adds support for multiple sensor tempeatures read & also a cmd option to read out temperatures from u-boot prompt. Keerthy (3): thermal: Add multiple instance support cmd: thermal: Add command line interface to read out temperatures configs: dra7xx_evm_defconfig: Enable TI_DRA7_THERMAL & CMD_THERMAL arch/arm/mach-imx/cpu.c | 2 +- cmd/Kconfig | 5 +++ cmd/Makefile | 1 + cmd/thermal.c | 59 ++++++++++++++++++++++++++++++++ configs/dra7xx_evm_defconfig | 3 ++ drivers/mmc/omap_hsmmc.c | 2 +- drivers/thermal/imx_thermal.c | 2 +- drivers/thermal/thermal-uclass.c | 4 +-- drivers/thermal/ti-bandgap.c | 13 +++++-- include/thermal.h | 6 ++-- 10 files changed, 87 insertions(+), 10 deletions(-) create mode 100644 cmd/thermal.c -- 2.17.1

3 7

[U-Boot] [PATCH v3 00/11] SMP support for RISC-V
by Lukas Auer 22 Mar '19

22 Mar '19

This patch series adds SMP support for RISC-V to U-Boot. It allows U-Boot to run on multi-hart systems (hart is the RISC-V terminology for hardware thread). Images passed to bootm will be started on all harts. The bootm command is currently the only one that will boot images on all harts, bootefi is not yet supported. The patches have been successfully tested on both QEMU (machine and supervisor mode) and the HiFive Unleashed board (supervisor mode), using BBL and OpenSBI. Mainline QEMU requires two patches [1, 2] to run in this configuration. Patch [1] has been dropped and will be replaced with a U-Boot patch. [1]: https://patchwork.ozlabs.org/patch/1039493/ [2]: https://patchwork.ozlabs.org/patch/1039082/ Changes in v3: - Print error if riscv_send_ipi() fails - Adjust error message for failures of riscv_clear_ipi() to match error message for failures of riscv_send_ipi() - New patch to save the hart ID in register tp instead of s0 - Adjust patch to use the new location of the hart ID (register tp) - New patch to hang if relocation of secondary harts fails Changes in v2: - Remove unneeded quotes from NR_CPUS Kconfig entry - Move memory barrier from send_ipi_many() to handle_ipi() - Add check in send_ipi_many so that IPIs are only sent to available harts as indicated by the available_harts mask - Implement hart lottery to pick main hart to run U-Boot - Remove CONFIG_MAIN_HART as it is not required anymore - Register available harts in the available_harts mask - New patch to populate register a0 with the hart ID from the mhartid CSR in machine-mode - New patch to enable SMP on the SiFive FU540, which was previously sent independently Lukas Auer (11): riscv: add infrastructure for calling functions on other harts riscv: import the supervisor binary interface header file riscv: implement IPI platform functions using SBI riscv: delay initialization of caches and debug UART riscv: save hart ID in register tp instead of s0 riscv: add support for multi-hart systems riscv: boot images passed to bootm on all harts riscv: do not rely on hart ID passed by previous boot stage riscv: hang if relocation of secondary harts fails riscv: fu540: enable SMP riscv: qemu: enable SMP arch/riscv/Kconfig | 28 +++++ arch/riscv/cpu/cpu.c | 9 +- arch/riscv/cpu/start.S | 167 +++++++++++++++++++++++++-- arch/riscv/include/asm/csr.h | 1 + arch/riscv/include/asm/global_data.h | 6 + arch/riscv/include/asm/sbi.h | 94 +++++++++++++++ arch/riscv/include/asm/smp.h | 53 +++++++++ arch/riscv/lib/Makefile | 2 + arch/riscv/lib/asm-offsets.c | 1 + arch/riscv/lib/bootm.c | 13 ++- arch/riscv/lib/sbi_ipi.c | 25 ++++ arch/riscv/lib/smp.c | 118 +++++++++++++++++++ board/emulation/qemu-riscv/Kconfig | 1 + board/sifive/fu540/Kconfig | 1 + 14 files changed, 507 insertions(+), 12 deletions(-) create mode 100644 arch/riscv/include/asm/sbi.h create mode 100644 arch/riscv/include/asm/smp.h create mode 100644 arch/riscv/lib/sbi_ipi.c create mode 100644 arch/riscv/lib/smp.c -- 2.20.1

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[U-Boot] [PATCH v2] efi_loader: set image_base and image_size to correct values
by AKASHI Takahiro 22 Mar '19

22 Mar '19

Currently, image's image_base points to an address where the image was temporarily uploaded for further loading. Since efi_loader relocates the image to final destination, image_base and image_size should reflect that. This bug was detected in UEFI SCT, "Loaded Image Protocol Test - test 2," which shows that 'Unload' function doesn't fit into a range suggested by image_base and image_size. TestCase/UEFI/EFI/Protocol/LoadedImage/BlackBoxTest/ LoadedImageBBTestMain.c:1002 Changes in this patch also includes: * reverts a patch, "efi_loader: save image relocation address and size" since newly added fields are no longer needed. * copy PE headers as well since those information will be needed for module loading, in particular, at gurb. (This bug was reported by Heinrich.) Signed-off-by: AKASHI Takahiro <takahiro.akashi(a)linaro.org> Reported-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- lib/efi_loader/efi_image_loader.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/lib/efi_loader/efi_image_loader.c b/lib/efi_loader/efi_image_loader.c index a18ce0a5705e..d1b6c0d3cdf2 100644 --- a/lib/efi_loader/efi_image_loader.c +++ b/lib/efi_loader/efi_image_loader.c @@ -59,10 +59,10 @@ static efi_status_t efi_print_image_info(struct efi_loaded_image_obj *obj, { printf("UEFI image"); printf(" [0x%p:0x%p]", - obj->reloc_base, obj->reloc_base + obj->reloc_size - 1); - if (pc && pc >= obj->reloc_base && - pc < obj->reloc_base + obj->reloc_size) - printf(" pc=0x%zx", pc - obj->reloc_base); + image->image_base, image->image_base + image->image_size - 1); + if (pc && pc >= image->image_base && + pc < image->image_base + image->image_size) + printf(" pc=0x%zx", pc - image->image_base); if (image->file_path) printf(" '%pD'", image->file_path); printf("\n"); @@ -212,7 +212,6 @@ void *efi_load_pe(struct efi_loaded_image_obj *handle, void *efi, int rel_idx = IMAGE_DIRECTORY_ENTRY_BASERELOC; void *entry; uint64_t image_base; - uint64_t image_size; unsigned long virt_size = 0; int supported = 0; @@ -256,7 +255,6 @@ void *efi_load_pe(struct efi_loaded_image_obj *handle, void *efi, IMAGE_NT_HEADERS64 *nt64 = (void *)nt; IMAGE_OPTIONAL_HEADER64 *opt = &nt64->OptionalHeader; image_base = opt->ImageBase; - image_size = opt->SizeOfImage; efi_set_code_and_data_type(loaded_image_info, opt->Subsystem); efi_reloc = efi_alloc(virt_size, loaded_image_info->image_code_type); @@ -272,7 +270,6 @@ void *efi_load_pe(struct efi_loaded_image_obj *handle, void *efi, } else if (nt->OptionalHeader.Magic == IMAGE_NT_OPTIONAL_HDR32_MAGIC) { IMAGE_OPTIONAL_HEADER32 *opt = &nt->OptionalHeader; image_base = opt->ImageBase; - image_size = opt->SizeOfImage; efi_set_code_and_data_type(loaded_image_info, opt->Subsystem); efi_reloc = efi_alloc(virt_size, loaded_image_info->image_code_type); @@ -291,6 +288,11 @@ void *efi_load_pe(struct efi_loaded_image_obj *handle, void *efi, return NULL; } + /* Copy PE headers */ + memcpy(efi_reloc, efi, sizeof(*dos) + sizeof(*nt) + + nt->FileHeader.SizeOfOptionalHeader + + num_sections * sizeof(IMAGE_SECTION_HEADER)); + /* Load sections into RAM */ for (i = num_sections - 1; i >= 0; i--) { IMAGE_SECTION_HEADER *sec = &sections[i]; @@ -315,10 +317,8 @@ void *efi_load_pe(struct efi_loaded_image_obj *handle, void *efi, invalidate_icache_all(); /* Populate the loaded image interface bits */ - loaded_image_info->image_base = efi; - loaded_image_info->image_size = image_size; - handle->reloc_base = efi_reloc; - handle->reloc_size = virt_size; + loaded_image_info->image_base = efi_reloc; + loaded_image_info->image_size = virt_size; return entry; } -- 2.19.0

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[U-Boot] [PATCH 1/1] efi_selftest: check image_base, image_size
by Heinrich Schuchardt 21 Mar '19

21 Mar '19

In efi_selftest_start_image_exit.c test the image_base and image_size are correctly set in the loaded image protocol. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- Hello Takahiro, this relates to your patch efi_loader: set image_base and image_size to correct values https://lists.denx.de/pipermail/u-boot/2018-October/344048.html Could you, please, review this patch. Best regards Heinrich --- lib/efi_selftest/efi_selftest_miniapp_exit.c | 58 ++++++++++++++++++-- 1 file changed, 53 insertions(+), 5 deletions(-) diff --git a/lib/efi_selftest/efi_selftest_miniapp_exit.c b/lib/efi_selftest/efi_selftest_miniapp_exit.c index 2ffdd65b759..baead834294 100644 --- a/lib/efi_selftest/efi_selftest_miniapp_exit.c +++ b/lib/efi_selftest/efi_selftest_miniapp_exit.c @@ -11,22 +11,70 @@ #include <common.h> #include <efi_api.h> -/* +static efi_guid_t loaded_image_protocol_guid = LOADED_IMAGE_GUID; + +/** + * check_loaded_image_protocol() - check image_base/image_size + * + * Try to open the loaded image protocol. Check that this function is located + * between image_base and image_base + image_size. + * + * @image_handle: handle of the loaded image + * @systable: system table + * @return: status code + */ +static efi_status_t EFIAPI check_loaded_image_protocol + (efi_handle_t image_handle, struct efi_system_table *systable) +{ + struct efi_simple_text_output_protocol *cout = systable->con_out; + struct efi_boot_services *boottime = systable->boottime; + struct efi_loaded_image *loaded_image_protocol; + efi_status_t ret; + + /* + * Open the loaded image protocol. + */ + ret = boottime->open_protocol + (image_handle, &loaded_image_protocol_guid, + (void **)&loaded_image_protocol, NULL, + NULL, EFI_OPEN_PROTOCOL_GET_PROTOCOL); + if (ret != EFI_SUCCESS) { + cout->output_string(cout, + L"Could not open loaded image protocol"); + return ret; + } + if ((void *)check_loaded_image_protocol < + loaded_image_protocol->image_base || + (void *)check_loaded_image_protocol >= + loaded_image_protocol->image_base + + loaded_image_protocol->image_size) { + cout->output_string(cout, + L"Incorrect image_base or image_size\n"); + return EFI_NOT_FOUND; + } + return EFI_SUCCESS; +} + +/** * Entry point of the EFI application. * - * @handle handle of the loaded image - * @systable system table - * @return status code + * @handle: handle of the loaded image + * @systable: system table + * @return: status code */ efi_status_t EFIAPI efi_main(efi_handle_t handle, struct efi_system_table *systable) { struct efi_simple_text_output_protocol *con_out = systable->con_out; + efi_status_t ret = EFI_UNSUPPORTED; con_out->output_string(con_out, L"EFI application calling Exit\n"); + if (check_loaded_image_protocol(handle, systable) != EFI_SUCCESS) + ret = EFI_NOT_FOUND; + /* The return value is checked by the calling test */ - systable->boottime->exit(handle, EFI_UNSUPPORTED, 0, NULL); + systable->boottime->exit(handle, ret, 0, NULL); /* * This statement should not be reached. -- 2.19.0

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[U-Boot] [PATCH v3 00/19] ARM: tegra: Miscellaneous improvements
by Thierry Reding 21 Mar '19

21 Mar '19

From: Thierry Reding <treding(a)nvidia.com> The bulk of these changes are an effort to unify Tegra186 builds with builds of prior 64-bit Tegra generations. On top of that there are various improvements that allow data (such as the MAC address and boot arguments) to be passed through from early firmware to the kernel on boot. The last two patches can be applied at a later time if the strndup() addition can't be merged along with the rest of the patches through the Tegra tree. Thierry Thierry Reding (19): ARM: tegra: Use common header for PMU declarations ARM: tegra: Guard clock code with a Kconfig symbol ARM: tegra: Guard GP pad control code with a Kconfig symbol ARM: tegra: Guard memory controller code with a Kconfig symbol ARM: tegra: Guard pin controller code with a Kconfig symbol ARM: tegra: Guard powergate code with a Kconfig symbol ARM: tegra: Fix save_boot_params() prototype ARM: tegra: Allow boards to override boot target devices ARM: tegra: Support TZ-only access to PMC ARM: tegra: Workaround UDC boot issues only if necessary ARM: tegra: Restore DRAM bank count ARM: tegra: Unify Tegra186 builds ARM: tegra: Implement cboot_save_boot_params() in C ARM: tegra: Implement cboot_get_ethaddr() ARM: tegra: Enable position independent build for 64-bit p2371-2180: Pass Ethernet MAC to the kernel p2771-0000: Pass Ethernet MAC to the kernel lib: Implement strndup() ARM: tegra: Import cbootargs value from cboot DTB arch/arm/include/asm/arch-tegra/cboot.h | 45 ++ arch/arm/include/asm/arch-tegra/pmc.h | 20 +- .../asm/{arch-tegra20 => arch-tegra}/pmu.h | 6 +- arch/arm/include/asm/arch-tegra/tegra.h | 6 + arch/arm/include/asm/arch-tegra114/pmu.h | 12 - arch/arm/include/asm/arch-tegra124/pmu.h | 13 - arch/arm/include/asm/arch-tegra210/pmu.h | 13 - arch/arm/include/asm/arch-tegra30/pmu.h | 12 - arch/arm/mach-tegra/Kconfig | 32 + arch/arm/mach-tegra/Makefile | 16 +- arch/arm/mach-tegra/board.c | 41 +- arch/arm/mach-tegra/board186.c | 32 - arch/arm/mach-tegra/board2.c | 37 +- arch/arm/mach-tegra/cache.c | 2 + arch/arm/mach-tegra/cboot.c | 605 ++++++++++++++++++ arch/arm/mach-tegra/clock.c | 13 +- arch/arm/mach-tegra/cmd_enterrcm.c | 6 +- arch/arm/mach-tegra/cpu.c | 20 +- arch/arm/mach-tegra/emc.c | 2 +- arch/arm/mach-tegra/lowlevel_init.S | 39 -- arch/arm/mach-tegra/pmc.c | 92 +++ arch/arm/mach-tegra/powergate.c | 11 +- arch/arm/mach-tegra/tegra186/Makefile | 4 - arch/arm/mach-tegra/tegra186/nvtboot_board.c | 332 ---------- arch/arm/mach-tegra/tegra186/nvtboot_ll.S | 20 - arch/arm/mach-tegra/tegra186/nvtboot_mem.c | 172 ----- board/nvidia/p2371-2180/p2371-2180.c | 50 ++ board/nvidia/p2771-0000/p2771-0000.c | 53 +- configs/e2220-1170_defconfig | 2 +- configs/p2371-0000_defconfig | 2 +- configs/p2371-2180_defconfig | 3 +- configs/p2571_defconfig | 2 +- configs/p2771-0000-000_defconfig | 3 +- configs/p2771-0000-500_defconfig | 3 +- include/configs/tegra-common-post.h | 2 + include/linux/string.h | 1 + lib/string.c | 23 + 37 files changed, 1046 insertions(+), 701 deletions(-) create mode 100644 arch/arm/include/asm/arch-tegra/cboot.h rename arch/arm/include/asm/{arch-tegra20 => arch-tegra}/pmu.h (73%) delete mode 100644 arch/arm/include/asm/arch-tegra114/pmu.h delete mode 100644 arch/arm/include/asm/arch-tegra124/pmu.h delete mode 100644 arch/arm/include/asm/arch-tegra210/pmu.h delete mode 100644 arch/arm/include/asm/arch-tegra30/pmu.h delete mode 100644 arch/arm/mach-tegra/board186.c create mode 100644 arch/arm/mach-tegra/cboot.c delete mode 100644 arch/arm/mach-tegra/lowlevel_init.S create mode 100644 arch/arm/mach-tegra/pmc.c delete mode 100644 arch/arm/mach-tegra/tegra186/nvtboot_board.c delete mode 100644 arch/arm/mach-tegra/tegra186/nvtboot_ll.S delete mode 100644 arch/arm/mach-tegra/tegra186/nvtboot_mem.c -- 2.21.0

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