March 2019 - U-Boot

[U-Boot] [PATCH] ARM: rmobile: rcar-gen2: Activate bootm_size
by Marek Vasut 30 Mar '19

30 Mar '19

Commit d245059ff797 ("ARM: rmobile: rcar-gen3: Activate bootm_size") only fixed the superfluous CONFIG_SYS_BOOTMAPSZ for R-Car Gen3, even though it listed all affected boards. Apply the same fix to Gen2. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Fixes: d245059ff797 ("ARM: rmobile: rcar-gen3: Activate bootm_size") Cc: Eugeniu Rosca <erosca(a)de.adit-jv.com> --- include/configs/rcar-gen2-common.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index 9213d33e21..7f72ff2e11 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -38,7 +38,6 @@ #define CONFIG_SYS_MONITOR_BASE 0x00000000 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) /* ENV setting */ #define CONFIG_ENV_ADDR 0xC0000 -- 2.20.1

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[U-Boot] [PATCH v2 0/6] spl: full-featured heap cleanups
by Simon Goldschmidt 30 Mar '19

30 Mar '19

Some platforms cannot use simple malloc even in very early stages, e.g. when using FAT before DRAM is available. Such platforms currently often use non-Kconfig defines to initialize full malloc and rely on simple heap before that. This series makes some adjustments to ensure SPL behaves the same with simple or full malloc: when CONFIG_SPL_SYS_MALLOC_F_LEN is != 0, both heap types can be used (by changing CONFIG_SPL_SYS_MALLOC_SIMPLE), without manually supplying an address range for the full heap. Changes in v2: - make CONFIG_SPL_CLEAR_BSS_F depend on ARM for now - add CONFIG_SPL_CLEAR_BSS_F implementation for arm64 also Simon Goldschmidt (6): spl: add Kconfig option to clear bss early spl: arm: implement SPL_CLEAR_BSS_F dlmalloc: fix malloc range at end of ram dlmalloc: be compatible to tiny printf spl: support using full malloc with SYS_MALLOC_F_LEN arm: socfpga: a10: move SPL stack size to Kconfig arch/arm/lib/crt0.S | 22 ++++++++++++++++++++++ arch/arm/lib/crt0_64.S | 14 ++++++++++++++ common/dlmalloc.c | 6 +++++- common/spl/Kconfig | 12 ++++++++++++ common/spl/spl.c | 5 +++++ configs/socfpga_arria10_defconfig | 1 + include/configs/socfpga_common.h | 14 -------------- 7 files changed, 59 insertions(+), 15 deletions(-) -- 2.17.1

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[U-Boot] [PATCH 1/2] ARM: dts: rmobile: Activate I2C7 on Alt
by Marek Vasut 30 Mar '19

30 Mar '19

Activate I2C7 on Alt to allow access to the PMIC. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- arch/arm/dts/r8a7794-alt-u-boot.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/dts/r8a7794-alt-u-boot.dts b/arch/arm/dts/r8a7794-alt-u-boot.dts index 593a418c3b..14cd39297e 100644 --- a/arch/arm/dts/r8a7794-alt-u-boot.dts +++ b/arch/arm/dts/r8a7794-alt-u-boot.dts @@ -8,6 +8,11 @@ #include "r8a7794-alt.dts" #include "r8a7794-u-boot.dtsi" +&i2c7 { + status = "okay"; + clock-frequency = <100000>; +}; + &scif2 { u-boot,dm-pre-reloc; }; -- 2.20.1

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[U-Boot] [PATCH] ARM: rmobile: alt: Increase USB power-good delay
by Marek Vasut 30 Mar '19

30 Mar '19

Increase the USB power good delay on Alt, this is required with certain USB sticks, otherwise they might not be detected. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- include/configs/alt.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/configs/alt.h b/include/configs/alt.h index 3f7f379e06..3a515eef00 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -39,7 +39,8 @@ #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK #define CONFIG_EXTRA_ENV_SETTINGS \ - "bootm_size=0x10000000\0" + "bootm_size=0x10000000\0" \ + "usb_pgood_delay=2000\0" /* SPL support */ #define CONFIG_SPL_TEXT_BASE 0xe6300000 -- 2.20.1

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[U-Boot] [PATCH] net: sh_eth: Initialize PHY in probe() once
by Marek Vasut 30 Mar '19

30 Mar '19

Reset and initialize the PHY once in the probe() function rather than doing it over and over again is start() function. This requires us to keep the clock enabled while the driver is in use. This significantly reduces the time between transfers as the PHY doesn't have to restart autonegotiation between transfers, which takes forever. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Joe Hershberger <joe.hershberger(a)ni.com> --- drivers/net/sh_eth.c | 31 +++++++++++++++++-------------- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 2e1123c488..4646f2ba4e 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -769,19 +769,9 @@ static int sh_ether_start(struct udevice *dev) struct sh_eth_dev *eth = &priv->shdev; int ret; - ret = clk_enable(&priv->clk); - if (ret) - return ret; - ret = sh_eth_init_common(eth, pdata->enetaddr); if (ret) - goto err_clk; - - ret = sh_eth_phy_config(dev); - if (ret) { - printf(SHETHER_NAME ": phy config timeout\n"); - goto err_start; - } + return ret; ret = sh_eth_start_common(eth); if (ret) @@ -792,17 +782,17 @@ static int sh_ether_start(struct udevice *dev) err_start: sh_eth_tx_desc_free(eth); sh_eth_rx_desc_free(eth); -err_clk: - clk_disable(&priv->clk); return ret; } static void sh_ether_stop(struct udevice *dev) { struct sh_ether_priv *priv = dev_get_priv(dev); + struct sh_eth_dev *eth = &priv->shdev; + struct sh_eth_info *port_info = &eth->port_info[eth->port]; + phy_shutdown(port_info->phydev); sh_eth_stop(&priv->shdev); - clk_disable(&priv->clk); } static int sh_ether_probe(struct udevice *udev) @@ -853,8 +843,20 @@ static int sh_ether_probe(struct udevice *udev) eth->port_info[eth->port].iobase = (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port); + ret = clk_enable(&priv->clk); + if (ret) + goto err_mdio_register; + + ret = sh_eth_phy_config(udev); + if (ret) { + printf(SHETHER_NAME ": phy config timeout\n"); + goto err_phy_config; + } + return 0; +err_phy_config: + clk_disable(&priv->clk); err_mdio_register: mdio_free(mdiodev); return ret; @@ -866,6 +868,7 @@ static int sh_ether_remove(struct udevice *udev) struct sh_eth_dev *eth = &priv->shdev; struct sh_eth_info *port_info = &eth->port_info[eth->port]; + clk_disable(&priv->clk); free(port_info->phydev); mdio_unregister(priv->bus); mdio_free(priv->bus); -- 2.20.1

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[U-Boot] [PATCH 1/4] ARM: rmobile: alt: Remove R8A7794_ETHERNET_B
by Marek Vasut 30 Mar '19

30 Mar '19

The R8A7794_ETHERNET_B config option is unused and based on the description, this is a setting which should be fully done on a DT level instead. Remove this config option. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- board/renesas/alt/Kconfig | 9 --------- 1 file changed, 9 deletions(-) diff --git a/board/renesas/alt/Kconfig b/board/renesas/alt/Kconfig index 39d53c185b..957962de20 100644 --- a/board/renesas/alt/Kconfig +++ b/board/renesas/alt/Kconfig @@ -9,13 +9,4 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "alt" -config R8A7794_ETHERNET_B - bool "Use ethernet B function" - depends on TARGET_ALT - default n - help - ALT board can use default ethernet and etnernet B function. - This config set pin function of ethenet B. You also needt to change - DIP switch of board in order to use this function. - endif -- 2.20.1

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[U-Boot] [PATCH 01/14] gpio: bcm6345: switch to raw I/O functions
by Philippe Reynes 29 Mar '19

29 Mar '19

This driver is used on several big endian mips board. So we could use raw I/O function instead of forcing big endian access. Signed-off-by: Philippe Reynes <philippe.reynes(a)softathome.com> --- drivers/gpio/bcm6345_gpio.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpio/bcm6345_gpio.c b/drivers/gpio/bcm6345_gpio.c index d1f6cfa..71a978c 100644 --- a/drivers/gpio/bcm6345_gpio.c +++ b/drivers/gpio/bcm6345_gpio.c @@ -22,7 +22,7 @@ static int bcm6345_gpio_get_value(struct udevice *dev, unsigned offset) { struct bcm6345_gpio_priv *priv = dev_get_priv(dev); - return !!(readl_be(priv->reg_data) & BIT(offset)); + return !!(readl(priv->reg_data) & BIT(offset)); } static int bcm6345_gpio_set_value(struct udevice *dev, unsigned offset, @@ -31,9 +31,9 @@ static int bcm6345_gpio_set_value(struct udevice *dev, unsigned offset, struct bcm6345_gpio_priv *priv = dev_get_priv(dev); if (value) - setbits_be32(priv->reg_data, BIT(offset)); + setbits_32(priv->reg_data, BIT(offset)); else - clrbits_be32(priv->reg_data, BIT(offset)); + clrbits_32(priv->reg_data, BIT(offset)); return 0; } @@ -42,9 +42,9 @@ static int bcm6345_gpio_set_direction(void __iomem *dirout, unsigned offset, bool input) { if (input) - clrbits_be32(dirout, BIT(offset)); + clrbits_32(dirout, BIT(offset)); else - setbits_be32(dirout, BIT(offset)); + setbits_32(dirout, BIT(offset)); return 0; } @@ -70,7 +70,7 @@ static int bcm6345_gpio_get_function(struct udevice *dev, unsigned offset) { struct bcm6345_gpio_priv *priv = dev_get_priv(dev); - if (readl_be(priv->reg_dirout) & BIT(offset)) + if (readl(priv->reg_dirout) & BIT(offset)) return GPIOF_OUTPUT; else return GPIOF_INPUT; -- 2.7.4

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[U-Boot] [PATCH] sunxi: video: HDMI: Fix clock setup
by Jernej Skrabec 29 Mar '19

29 Mar '19

Currently, HDMI driver doesn't consider minimum and maximum allowed rate of pll3 (video PLL). It works most of the time, but not always. Consider monitor with resolution 1920x1200, which has pixel clock rate of 154 MHz. Current code would determine that pll3 rate has to be set to 154 MHz. However, minimum supported rate is 192 MHz. In this case video output just won't work. The reason why the driver is written in the way it is, is that at the time HDMI PHY and clock configuration wasn't fully understood. But now we have needed knowledge, so the issue can be fixed. With this fix, clock configuration routine uses full range (1-16) for clock divider instead of limited one (1, 2, 4, 11). It also considers minimum and maximum allowed rate for pll3. Fixes: 56009451d843 ("sunxi: video: Add A64/H3/H5 HDMI driver") Signed-off-by: Jernej Skrabec <jernej.skrabec(a)siol.net> --- Hi! Unfortunately, issue fixed with patch here has influence on Linux too. In Linux, minimum and maximum rate is considered only when changing rate. But because U-Boot already set PLL to "correct" value, Linux clock driver doesn't see the need to change it. I know that this is Linux driver issue but let's start at the source of the issue and fix it. It would be very nice if this can go in 2019.04 release. Best regards, Jernej drivers/video/sunxi/sunxi_dw_hdmi.c | 62 +++++++++++++++++------------ 1 file changed, 37 insertions(+), 25 deletions(-) diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c index 9dbea649a0..6fe1aa7ee4 100644 --- a/drivers/video/sunxi/sunxi_dw_hdmi.c +++ b/drivers/video/sunxi/sunxi_dw_hdmi.c @@ -132,7 +132,7 @@ static int sunxi_dw_hdmi_wait_for_hpd(void) return -1; } -static void sunxi_dw_hdmi_phy_set(uint clock) +static void sunxi_dw_hdmi_phy_set(uint clock, int phy_div) { struct sunxi_hdmi_phy * const phy = (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS); @@ -146,7 +146,7 @@ static void sunxi_dw_hdmi_phy_set(uint clock) switch (div) { case 1: writel(0x30dc5fc0, &phy->pll); - writel(0x800863C0, &phy->clk); + writel(0x800863C0 | (phy_div - 1), &phy->clk); mdelay(10); writel(0x00000001, &phy->unk3); setbits_le32(&phy->pll, BIT(25)); @@ -164,7 +164,7 @@ static void sunxi_dw_hdmi_phy_set(uint clock) break; case 2: writel(0x39dc5040, &phy->pll); - writel(0x80084381, &phy->clk); + writel(0x80084380 | (phy_div - 1), &phy->clk); mdelay(10); writel(0x00000001, &phy->unk3); setbits_le32(&phy->pll, BIT(25)); @@ -178,7 +178,7 @@ static void sunxi_dw_hdmi_phy_set(uint clock) break; case 4: writel(0x39dc5040, &phy->pll); - writel(0x80084343, &phy->clk); + writel(0x80084340 | (phy_div - 1), &phy->clk); mdelay(10); writel(0x00000001, &phy->unk3); setbits_le32(&phy->pll, BIT(25)); @@ -192,7 +192,7 @@ static void sunxi_dw_hdmi_phy_set(uint clock) break; case 11: writel(0x39dc5040, &phy->pll); - writel(0x8008430a, &phy->clk); + writel(0x80084300 | (phy_div - 1), &phy->clk); mdelay(10); writel(0x00000001, &phy->unk3); setbits_le32(&phy->pll, BIT(25)); @@ -207,36 +207,46 @@ static void sunxi_dw_hdmi_phy_set(uint clock) } } -static void sunxi_dw_hdmi_pll_set(uint clk_khz) +static void sunxi_dw_hdmi_pll_set(uint clk_khz, int *phy_div) { - int value, n, m, div = 0, diff; - int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF; - - div = sunxi_dw_hdmi_get_divider(clk_khz * 1000); + int value, n, m, div, diff; + int best_n = 0, best_m = 0, best_div = 0, best_diff = 0x0FFFFFFF; /* * Find the lowest divider resulting in a matching clock. If there * is no match, pick the closest lower clock, as monitors tend to * not sync to higher frequencies. */ - for (m = 1; m <= 16; m++) { - n = (m * div * clk_khz) / 24000; - - if ((n >= 1) && (n <= 128)) { - value = (24000 * n) / m / div; - diff = clk_khz - value; - if (diff < best_diff) { - best_diff = diff; - best_m = m; - best_n = n; + for (div = 1; div <= 16; div++) { + int target = clk_khz * div; + + if (target < 192000) + continue; + if (target > 912000) + continue; + + for (m = 1; m <= 16; m++) { + n = (m * target) / 24000; + + if (n >= 1 && n <= 128) { + value = (24000 * n) / m / div; + diff = clk_khz - value; + if (diff < best_diff) { + best_diff = diff; + best_m = m; + best_n = n; + best_div = div; + } } } } + *phy_div = best_div; + clock_set_pll3_factors(best_m, best_n); debug("dotclock: %dkHz = %dkHz: (24MHz * %d) / %d / %d\n", - clk_khz, (clock_get_pll3() / 1000) / div, - best_n, best_m, div); + clk_khz, (clock_get_pll3() / 1000) / best_div, + best_n, best_m, best_div); } static void sunxi_dw_hdmi_lcdc_init(int mux, const struct display_timing *edid, @@ -244,7 +254,7 @@ static void sunxi_dw_hdmi_lcdc_init(int mux, const struct display_timing *edid, { struct sunxi_ccm_reg * const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - int div = sunxi_dw_hdmi_get_divider(edid->pixelclock.typ); + int div = clock_get_pll3() / edid->pixelclock.typ; struct sunxi_lcdc_reg *lcdc; if (mux == 0) { @@ -276,8 +286,10 @@ static void sunxi_dw_hdmi_lcdc_init(int mux, const struct display_timing *edid, static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock) { - sunxi_dw_hdmi_pll_set(mpixelclock/1000); - sunxi_dw_hdmi_phy_set(mpixelclock); + int phy_div; + + sunxi_dw_hdmi_pll_set(mpixelclock / 1000, &phy_div); + sunxi_dw_hdmi_phy_set(mpixelclock, phy_div); return 0; } -- 2.21.0

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Re: [U-Boot] CONFIG_OF_EMBED
by Simon Glass 29 Mar '19

29 Mar '19

Hi, On Fri, 22 Mar 2019 at 05:37, Marek Vasut <marex(a)denx.de> wrote: > > On 3/21/19 5:37 PM, Dalon L Westergreen wrote: > > On Thu, 2019-03-21 at 16:48 +0100, Marek Vasut wrote: > >> On 3/21/19 3:33 PM, Dalon L Westergreen wrote: > >>> On Thu, 2019-03-21 at 03:30 +0100, Marek Vasut wrote: > >>>> On 3/20/19 9:24 PM, Dalon L Westergreen wrote: > >>>>> On Wed, 2019-03-20 at 19:37 +0100, Marek Vasut wrote: > >>>>>> On 3/20/19 6:28 PM, Dalon L Westergreen wrote: > >>>>>>> Hey Marek, > >>>>>> > >>>>>> Hi, > >>>>>> > >>>>>>> A while ago, when adding the hex output required for stratix10, I > >>>>>>> enabled > >>>>>>> CONFIG_OF_EMBED so that the spl elf included the dtb. This avoided > >>>>>>> the > >>>>>>> -- > >>>>>>> change-address option when using objcopy to convert the u-boot-spl- > >>>>>>> dtb.bin > >>>>>>> into > >>>>>>> a hex file with the correct address as required by the quartus > >>>>>>> tools. > >>>>>>> > >>>>>>> In any case, there is now a warning that CONFIG_OF_EMBED should only > >>>>>>> be > >>>>>>> used > >>>>>>> for > >>>>>>> development and debug. I am wondering how best to resolve this > >>>>>>> issue, > >>>>>>> should i > >>>>>>> revert back to using objcopy with the u-boot-spl-dtb.bin, is there a > >>>>>>> way > >>>>>>> to > >>>>>>> have > >>>>>>> CONFIG_OF_EMBED only apply to SPL? > >>>>>> > >>>>>> CONFIG_OF_SEPARATE is what you want. > >>>>> > >>>>> I dont think this is what i want exactly. I was thinking of this. > >>>>> From 82c1d1bc6092ce40f33a04f2bc7713b0143e30a5 Mon Sep 17 00:00:00 2001 > >>>>> From: Dalon Westergreen <dalon.westergreen(a)intel.com> > >>>>> Date: Wed, 20 Mar 2019 11:21:20 -0700 > >>>>> Subject: [PATCH 1/2] Makefile: Add target to generate hex output for > >>>>> combined > >>>>> spl and dtb > >>>>> > >>>>> Some architectures, Stratix10, require a hex formatted spl that combines > >>>>> the spl image and dtb. This adds a target to create said hex file with > >>>>> and offset of SPL_TEXT_BASE. I don't really follow this thread, but you should not use CONFIG_OF_EMBED. If there is a problem with setting up the image with CONFIG_OF_SEPARATE, we should discuss it. - Simon > >>>> > >>>> The CONFIG_OF_SEPARATE doesn't generate a combined image anymore ? Seems > >>>> like it does at least on the renesas platforms (cfr e.g. > >>>> stout_defconfig, where I use exactly that). > >>> > >>> It generates a combined binary, u-boot-spl-dtb.bin, as far as i know. > >>> The elf is not combined, so using objcopy on the elf results in a hex > >>> file without the dtb. Stratix 10 needs a combined hex file that starts > >>> at CONFIG_SPL_TEXT_BASE. This file is then combined by quartus with > >>> the fpga image. The SDM loads the spl image into the cpu's onchip ram > >>> and releases it from reset. > >>> > >>> So what i am trying to do is get a hex file generated that is appriopriate > >>> for the quartus tools. With CONFIG_OF_EMBED, this was easy, as you just > >>> run objcopy on the elf to create the hex output. With CONFIG_OF_SEPARATE > >>> you need the combined binary to do the same. hence, > >>> > >>> +OBJCOPYFLAGS_u-boot-spl-dtb.hex := -I binary -O ihex --change- > >>>>> address=$(CONFIG_SPL_TEXT_BASE) > >>>>> + > >>>>> +spl/u-boot-spl-dtb.hex: spl/u-boot-spl-dtb.bin FORCE > >>>>> + $(call if_changed,objcopy) > >> Aha, right. CCing Simon, maybe he has some better idea. > >> > >> Otherwise, let's add the custom target. Maybe we can add it to > >> arch/arm/mach-socfpga instead though. > > > > After a quick test to add the target to mach-socfpga instead of the root > > Makefile, it seems i would still need to modify the root Makefile to call > > the mach-socfpga makefile for the target in any case. If acceptable, i > > think it cleaner to just add the target to the root Makefile. > > I think that's fine. The root Makefile is growing like dough. that needs > to stop. > > -- > Best regards, > Marek Vasut

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[U-Boot] [U-Boot, V5, PATCH 1/3] mips: fix erros on registers macros of pll-ddr-config1-nfrac for QCA956X
by rosysong＠rosinson.com 29 Mar '19

29 Mar '19

From: Rosy Song <rosysong(a)rosinson.com> See details in chapter 8.6.2 and 8.6.4 (page 140-141) of qca9563 datasheet, NFRAC[17:0] So the mask of [17:5] is 0x1fff not 0x3fff. Signed-off-by: Rosy Song <rosysong(a)rosinson.com> Changes for v2-v3: - add more information for this commit Changes for v4-v5: - coding style cleanup --- arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h index 5d371bb582..3506ed1da4 100644 --- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h +++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h @@ -528,7 +528,7 @@ #define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0 #define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f #define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5 -#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x3fff +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x1fff #define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18 #define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff @@ -540,7 +540,7 @@ #define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0 #define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f #define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5 -#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x3fff +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x1fff #define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18 #define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff -- 2.17.1

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