March 2019 - U-Boot

[U-Boot] [PATCH 1/2] Makefile: Add target to generate hex output for combined spl and dtb
by Dalon Westergreen 02 Apr '19

02 Apr '19

From: Dalon Westergreen <dalon.westergreen(a)intel.com> Some architectures, Stratix10, require a hex formatted spl that combines the spl image and dtb. This adds a target to create said hex file with and offset of SPL_TEXT_BASE. Signed-off-by: Dalon Westergreen <dalon.westergreen(a)intel.com> --- Makefile | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Makefile b/Makefile index c52a33b403..ecba06ffce 100644 --- a/Makefile +++ b/Makefile @@ -1074,6 +1074,11 @@ OBJCOPYFLAGS_u-boot-spl.hex = $(OBJCOPYFLAGS_u-boot.hex) spl/u-boot-spl.hex: spl/u-boot-spl FORCE $(call if_changed,objcopy) +OBJCOPYFLAGS_u-boot-spl-dtb.hex := -I binary -O ihex --change-address=$(CONFIG_SPL_TEXT_BASE) + +spl/u-boot-spl-dtb.hex: spl/u-boot-spl-dtb.bin FORCE + $(call if_changed,objcopy) + binary_size_check: u-boot-nodtb.bin FORCE @file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \ map_size=$(shell cat u-boot.map | \ @@ -1643,6 +1648,10 @@ u-boot.lds: $(LDSCRIPT) prepare FORCE spl/u-boot-spl.bin: spl/u-boot-spl @: + +spl/u-boot-spl-dtb.bin: spl/u-boot-spl + @: + spl/u-boot-spl: tools prepare \ $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb) \ $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_TPL_OF_PLATDATA),dts/dt.dtb) -- 2.20.1

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[U-Boot] [PATCH] spl: fit: handle mmc read to sram case in rockchip SoCs
by Kever Yang 02 Apr '19

02 Apr '19

Rockchip fit image with atf may have firmware for sram, so the fit driver need to read data from mmc to sram, but Rockchip mmc controller does not support this data path, we have to read into ddr first and then copy it to sram. Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- common/spl/spl_fit.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index c9bfe0cc8a..5c5b58f69d 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -9,6 +9,7 @@ #include <fpga.h> #include <image.h> #include <linux/libfdt.h> +#include <malloc.h> #include <spl.h> #ifndef CONFIG_SYS_BOOTM_LEN @@ -215,6 +216,15 @@ static int spl_load_fit_image(struct spl_load_info *info, ulong sector, return -ENOENT; load_ptr = (load_addr + align_len) & ~align_len; +#if defined(CONFIG_ROCKCHIP_RK3399) || defined(CONFIG_ROCKCHIP_RK3368) + /* + * Rockchip SOC's mmc controller does not support read data + * from mmc to sram, we have to read to sdram first, and then + * copy to sram. + */ + if ((load_ptr & 0xffff0000) != CONFIG_SYS_SDRAM_BASE) + load_ptr = (ulong)memalign(ARCH_DMA_MINALIGN, len); +#endif length = len; overhead = get_aligned_image_overhead(info, offset); -- 2.20.1

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[U-Boot] [PATCH 1/3] imx8mq_evk: README: Need to copy bl31.bin to U-Boot source tree
by Fabio Estevam 02 Apr '19

02 Apr '19

After building ATF it is needed to copy the generated bl31.bin file to the U-Boot source tree. Make this step explicit in the instructions. Signed-off-by: Fabio Estevam <festevam(a)gmail.com> --- board/freescale/imx8mq_evk/README | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/freescale/imx8mq_evk/README b/board/freescale/imx8mq_evk/README index 2529f7da3d..bd5ee12722 100644 --- a/board/freescale/imx8mq_evk/README +++ b/board/freescale/imx8mq_evk/README @@ -9,13 +9,14 @@ Quick Start Get and Build the ARM Trusted firmware ==================== +Note: srctree is U-Boot source directory Get ATF from: https://source.codeaurora.org/external/imx/imx-atf branch: imx_4.14.62_1.0.0_beta $ make PLAT=imx8mq bl31 +$ cp build/imx8mq/release/bl31.bin $(srctree) Get the ddr and hdmi firmware ==================== -Note: srctree is U-Boot source directory $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.9.bin $ chmod +x firmware-imx-7.9.bin $ ./firmware-imx-7.9.bin -- 2.17.1

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[U-Boot] [PATCH v2] ARM: zynq: Add missing i2c get_rate for fixing i2c SPL
by Hannes Schmelzer 02 Apr '19

02 Apr '19

The commit 'f48ef0d81aa837a33020f8d61abb3929ba613774' did break I2C support because requesting the clock for the I2C ip-block isn't supported during SPL. To fixup this we add support requesting clocks for: - i2c0 - i2c1 Signed-off-by: Hannes Schmelzer <hannes.schmelzer(a)br-automation.com> --- Changes in v2: - reword commit headline - cosmetic changes drivers/clk/clk_zynq.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/clk_zynq.c b/drivers/clk/clk_zynq.c index 482f093..b09c37d 100644 --- a/drivers/clk/clk_zynq.c +++ b/drivers/clk/clk_zynq.c @@ -434,6 +434,8 @@ static ulong zynq_clk_get_rate(struct clk *clk) case lqspi_clk ... pcap_clk: case sdio0_clk ... spi1_clk: return zynq_clk_get_peripheral_rate(priv, id, 0); + case i2c0_aper_clk ... i2c1_aper_clk: + return zynq_clk_get_cpu_rate(priv, cpu_1x_clk); default: return -ENXIO; } -- 2.7.4

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[U-Boot] [PATCH 1/2] serial: add skipping init option
by Jun Nie 02 Apr '19

02 Apr '19

add skipping init option to avoid corrupt data in console if serial is already initilized when u-boot start its excution. Signed-off-by: Jun Nie <jun.nie(a)linaro.org> --- drivers/serial/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 887cd68..7aeaffb 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -459,6 +459,12 @@ config DEBUG_UART_NS16550_CHECK_ENABLED Note that this does not work for every ns16550-compatible UART and so has to be enabled carefully or you might notice lost characters. +config UART_SKIP_INIT + bool "Skip UART initialization" + help + Select this if the UART you want to use for output is already + initialized by the time U-Boot starts its execution. + config ALTERA_JTAG_UART bool "Altera JTAG UART support" depends on DM_SERIAL -- 2.7.4

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[U-Boot] saveenv corrupts QSPI flash with latest commit U-Boot 2019.04-rc4-00047-gcfb3e102c4
by Ashish Kumar 02 Apr '19

02 Apr '19

Hello Maintainers, With latest commit I see that saveenv command corrupts QSPI-flash, meaning if I read QSPI-flash at 0x0 offset RCW(reset configuration word) is erased after saveenv command was executed. This is tested on LS1088ARDB, but it should not be limited to LS1088ARDB rather it will valid for all LS Freescale ARM boards.( like LS1088, LS2080/LS2085, LS1012, LS1043, LS1046). Logs below: U-Boot 2019.04-rc4-00047-gcfb3e102c4 (Mar 25 2019 - 17:09:17 +0530) SoC: LS1088AE Rev1.0 (0x87030010) Clock Configuration: CPU0(A53):1600 MHz CPU1(A53):1600 MHz CPU2(A53):1600 MHz CPU3(A53):1600 MHz CPU4(A53):1600 MHz CPU5(A53):1600 MHz CPU6(A53):1600 MHz CPU7(A53):1600 MHz Bus: 700 MHz DDR: 2100 MT/s Reset Configuration Word (RCW): 00000000: 4000541c 00000040 00000000 00000000 00000010: 00000000 000a0000 00300000 00000000 00000020: 00a011a0 00002580 00000000 00000040 00000030: 0000005b 00000000 00002403 00000000 00000040: 00000000 00000000 00000000 00000000 00000050: 00000000 00000000 00000000 00000000 00000060: 00000000 00000000 00000011 000009e7 00000070: 44110000 00509555 I2C: ready VID: Core voltage after adjustment is at 1025 mV DRAM: Initializing DDR....using SPD Detected UDIMM 18ASF1G72AZ-2G3B1 Address hashing enabled. 7.9 GiB DDR 7.9 GiB (DDR4, 64-bit, CL=15, ECC on) DDR Chip-Select Interleaving Mode: CS0+CS1 PPA Firmware: Version LSDK-18.09 Using SERDES1 Protocol: 29 (0x1d) Using SERDES2 Protocol: 13 (0xd) NAND: 512 MiB MMC: FSL_SDHC: 0 Loading Environment from SPI Flash... SF: Detected s25fl512s with page size 256 Bytes, erase size 256 KiB, total 64 MiB *** Warning - bad CRC, using default environment EEPROM: NXID v1 In: serial Out: serial Err: serial Model: NXP Layerscape 1088a RDB Board Board: LS1088A-RDB, Board Arch: V1, Board version: C, boot from QSPI:1 CPLD: v1.8 SERDES1 Reference : Clock1 = 100MHz Clock2 = 156.25MHz SERDES2 Reference : Clock1 = 100MHz Clock2 = 100MHz Net: PHY reset timed out PCIe0: pcie@3400000 Root Complex: no link PCIe1: pcie@3500000 Root Complex: no link PCIe2: pcie@3600000 Root Complex: x1 gen1 e1000: 68:05:ca:16:8b:30 DPMAC1@xgmii [PRIME], DPMAC2@xgmii, DPMAC3@qsgmii, DPMAC4@qsgmii, DPMAC5@qsgmii, DPMAC6@qsgmii, DPMAC7@qsgmii, DPMAC8@qsgmii, DPMAC9@qsgmii, DPMAC10@qsgmii, e1000#0 Warning: e1000#0 MAC addresses don't match: Address in SROM is 68:05:ca:16:8b:30 Address in environment is 00:04:9f:04:79:f3 SF: Detected s25fl512s with page size 256 Bytes, erase size 256 KiB, total 64 MiB device 0 offset 0xa00000, size 0x100000 SF: 1048576 bytes @ 0xa00000 Read: OK device 0 offset 0xe00000, size 0x100000 SF: 1048576 bytes @ 0xe00000 Read: OK crc32+ fsl-mc: Booting Management Complex ... SUCCESS fsl-mc: Management Complex booted (version: 10.10.0, boot status: 0x1) Hit any key to stop autoboot: 0 => => => => => => => savee Saving Environment to SPI Flash... Erasing SPI flash...Writing to SPI flash...done OK => sf read a0000000 0 40000 device 0 offset 0x0, size 0x40000 SF: 262144 bytes @ 0x0 Read: OK => md a0000000 a0000000: ffffffff ffffffff ffffffff ffffffff ................ a0000010: ffffffff ffffffff ffffffff ffffffff ................ a0000020: ffffffff ffffffff ffffffff ffffffff ................ a0000030: ffffffff ffffffff ffffffff ffffffff ................ a0000040: ffffffff ffffffff ffffffff ffffffff ................ a0000050: ffffffff ffffffff ffffffff ffffffff ................ a0000060: ffffffff ffffffff ffffffff ffffffff ................ a0000070: ffffffff ffffffff ffffffff ffffffff ................ a0000080: ffffffff ffffffff ffffffff ffffffff ................ a0000090: ffffffff ffffffff ffffffff ffffffff ................ a00000a0: ffffffff ffffffff ffffffff ffffffff ................ a00000b0: ffffffff ffffffff ffffffff ffffffff ................ a00000c0: ffffffff ffffffff ffffffff ffffffff ................ a00000d0: ffffffff ffffffff ffffffff ffffffff ................ a00000e0: ffffffff ffffffff ffffffff ffffffff ................ a00000f0: ffffffff ffffffff ffffffff ffffffff ................ Regards Ashish

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[U-Boot] [PATCH] mmc: dw_mmc: Calculate timeout from transfer length
by Marek Vasut 02 Apr '19

02 Apr '19

The current 4-minute data transfer timeout is misleading and broken. Instead of such a long wait, calculate the timeout duration based on the length of the data transfer. The current formula is the transfer length in bits, divided by a multiplication of bus frequency in Hz, bus width, DDR mode and converted the mSec. The value is bounded from the bottom to 1000 mSec. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> Cc: Simon Glass <sjg(a)chromium.org> --- drivers/mmc/dw_mmc.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 93a836eac3..8278f1dacb 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -116,20 +116,29 @@ static int dwmci_fifo_ready(struct dwmci_host *host, u32 bit, u32 *len) static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data) { + struct mmc *mmc = host->mmc; int ret = 0; - u32 timeout = 240000; - u32 mask, size, i, len = 0; + u32 timeout, mask, size, i, len = 0; u32 *buf = NULL; ulong start = get_timer(0); u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1) * 2; - size = data->blocksize * data->blocks / 4; + size = data->blocksize * data->blocks; if (data->flags == MMC_DATA_READ) buf = (unsigned int *)data->dest; else buf = (unsigned int *)data->src; + timeout = size * 8 * 1000; /* counting in bits and msec */ + timeout *= 2; /* wait twice as long */ + timeout /= mmc->clock; + timeout /= mmc->bus_width; + timeout /= mmc->ddr_mode ? 2 : 1; + timeout = (timeout < 1000) ? 1000 : timeout; + + size /= 4; + for (;;) { mask = dwmci_readl(host, DWMCI_RINTSTS); /* Error during data transfer. */ -- 2.20.1

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[U-Boot] [PATCH] mmc: dw_mmc: Round up descriptor end to nearest multiple of cacheline size
by Marek Vasut 02 Apr '19

02 Apr '19

The driver currently calculates the end address of cache flush operation for the DMA descriptors by adding cacheline size to the start address of the last DMA descriptor. This is not safe, as the cacheline size may be, in some unlikely cases, smaller than the DMA descriptor size. Replace the addition with roundup() applied on the end address of the last DMA descriptor to round it up to the nearest cacheline size multiple. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> Cc: Simon Glass <sjg(a)chromium.org> --- drivers/mmc/dw_mmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 72570235cb..bec30b1479 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -74,15 +74,15 @@ static void dwmci_prepare_data(struct dwmci_host *host, dwmci_set_idma_desc(cur_idmac, flags, cnt, (ulong)bounce_buffer + (i * PAGE_SIZE)); + cur_idmac++; if (blk_cnt <= 8) break; blk_cnt -= 8; - cur_idmac++; i++; } while(1); data_end = (ulong)cur_idmac; - flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN); + flush_dcache_range(data_start, roundup(data_end, ARCH_DMA_MINALIGN)); ctrl = dwmci_readl(host, DWMCI_CTRL); ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN; -- 2.20.1

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[U-Boot] [PATCH 1/6] fdt: boot_get_fdt: remove redundant zeroing out
by Eugeniu Rosca 01 Apr '19

01 Apr '19

Paranoid programming [1] lies at the foundation of proper software development, but the repetitive zeroint-out of output arguments in the context of the same function rather clutters the code and inhibits further refactoring/optimization than is doing any good. In boot_get_fdt(), we already perform zero/NULL-initialization of *of_flat_tree and *of_size at the beginning of the function, so doing the same at function error-out is redundant/superfluous. Moreover, keeping the code unchanged might encourage the developers to update *of_flat_tree and *of_size during some interim computations, which is against the current design of boot_get_fdt(). Currently, writing useful data into these arguments happens just before successfully returning from boot_get_fdt() and it should better stay so. [1] https://blog.regehr.org/archives/1106 Signed-off-by: Eugeniu Rosca <erosca(a)de.adit-jv.com> --- common/image-fdt.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/common/image-fdt.c b/common/image-fdt.c index 01186aeac7a4..1817ce6bce30 100644 --- a/common/image-fdt.c +++ b/common/image-fdt.c @@ -489,8 +489,6 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch, no_fdt: ok_no_fdt = 1; error: - *of_flat_tree = NULL; - *of_size = 0; if (!select && ok_no_fdt) { debug("Continuing to boot without FDT\n"); return 0; -- 2.21.0

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[U-Boot] [PATCH] clk: sunxi: a10: Add CLK_AHB_GMAC
by Jagan Teki 01 Apr '19

01 Apr '19

CLK_AHB_GMAC was suppose to be part of previous commit "clk: sunxi: Implement A10 EMAC clocks" add it so-that we can get rid of sunxi_set_gate warning on boot message. Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- drivers/clk/sunxi/clk_a10.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c index 15ffe5ecb3..7a96d1708e 100644 --- a/drivers/clk/sunxi/clk_a10.c +++ b/drivers/clk/sunxi/clk_a10.c @@ -28,6 +28,8 @@ static struct ccu_clk_gate a10_gates[] = { [CLK_AHB_SPI2] = GATE(0x060, BIT(22)), [CLK_AHB_SPI3] = GATE(0x060, BIT(23)), + [CLK_AHB_GMAC] = GATE(0x064, BIT(17)), + [CLK_APB1_UART0] = GATE(0x06c, BIT(16)), [CLK_APB1_UART1] = GATE(0x06c, BIT(17)), [CLK_APB1_UART2] = GATE(0x06c, BIT(18)), -- 2.18.0.321.gffc6fa0e3

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