February 2019 - U-Boot

[U-Boot] [PATCH 1/2] mmc: Export {sd,mmc}_select_mode_and_width()
by Marek Vasut 06 Feb '19

06 Feb '19

Make {sd,mmc}_select_mode_and_width() functions available to drivers, so that they can call these functions to reconfigure SD/MMC mode if necessary. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> --- drivers/mmc/mmc.c | 8 ++------ drivers/mmc/mmc_private.h | 4 ++++ 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 84d157ff40..c7730c9233 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -23,10 +23,6 @@ static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage); static int mmc_power_cycle(struct mmc *mmc); -#if !CONFIG_IS_ENABLED(MMC_TINY) -static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps); -#endif - #if !CONFIG_IS_ENABLED(DM_MMC) #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) @@ -1643,7 +1639,7 @@ static const struct mode_width_tuning sd_modes_by_pref[] = { mwt++) \ if (caps & MMC_CAP(mwt->mode)) -static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps) +int sd_select_mode_and_width(struct mmc *mmc, uint card_caps) { int err; uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT}; @@ -1912,7 +1908,7 @@ static int mmc_select_hs400(struct mmc *mmc) ecbv++) \ if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap)) -static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps) +int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps) { int err; const struct mode_width_tuning *mwt; diff --git a/drivers/mmc/mmc_private.h b/drivers/mmc/mmc_private.h index f49b6eb573..7198baf4fd 100644 --- a/drivers/mmc/mmc_private.h +++ b/drivers/mmc/mmc_private.h @@ -18,6 +18,10 @@ extern int mmc_set_blocklen(struct mmc *mmc, int len); #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT void mmc_adapter_card_type_ident(void); #endif +#if !CONFIG_IS_ENABLED(MMC_TINY) +int sd_select_mode_and_width(struct mmc *mmc, uint card_caps); +int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps); +#endif #if CONFIG_IS_ENABLED(BLK) ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, -- 2.19.2

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[U-Boot] [PATCH] .gitignore: ignore patch rejects (*.rej) files
by Philipp Tomsich 06 Feb '19

06 Feb '19

As my last merge (and the successive follow-up patch) shows, *.rej files are not covered by our .gitignore. To protect against future accidental addition of *.rej artifacts, this adds a pattern for these to our .gitignore. Signed-off-by: Philipp Tomsich <philipp.tomsich(a)theobroma-systems.com> Series-Cc: michal.simek(a)xilinx.com Series-Cc: vigneshr(a)ti.com --- .gitignore | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.gitignore b/.gitignore index 8d18d6f..1ef876a 100644 --- a/.gitignore +++ b/.gitignore @@ -88,3 +88,6 @@ GTAGS *.orig *~ \#*# + +# patch rejects +*.rej \ No newline at end of file -- 2.1.4

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[U-Boot] [RFC 0/3] dm, efi: integrate efi_disk into DM
by AKASHI Takahiro 06 Feb '19

06 Feb '19

This patch set came from the past discussion[1] on my "removable device support" patch and is intended to be an attempt to integrate efi_disk (more precisely, EFI_BLOCK_IO_PROTOCOL-capable efi object) into u-boot's Driver Model as much seamlessly as possible [1] https://lists.denx.de/pipermail/u-boot/2019-January/354010.html Basic idea is * create UCLASS_PARTITION * enumerate all the partitions when a block device is probed * hook up a creation of UCLASS_BLK or UCLASS_PARTITION device to efi handler for efi_disk attributes to be properly set up Since this patch is a prototype (or POC, proof-of-concept), the aim here is to discuss further about how in a better shape we will be able to merge the two worlds. Example operation: (Two scsi disks, one with no partition, one with two partitions) U-Boot 2019.01-rc3-00024-ga81a6f87ad48 (Jan 29 2019 - 10:56:45 +0900) DRAM: 1 GiB In: pl011@9000000 Out: pl011@9000000 Err: pl011@9000000 Net: No ethernet found. Hit any key to stop autoboot: 0 => efi devices Device Device Path ================ ==================== 000000007ef01350 /VenHw(e61d73b9-a384-4acc-aeab-82e828f3628b) => scsi rescan Reset SCSI scanning bus for devices... Target spinup took 0 ms. Target spinup took 0 ms. SATA link 2 timeout. SATA link 3 timeout. SATA link 4 timeout. SATA link 5 timeout. AHCI 0001.0000 32 slots 6 ports 1.5 Gbps 0x3f impl SATA mode flags: 64bit ncq only Device 0: (0:0) Vendor: ATA Prod.: QEMU HARDDISK Rev: 2.5+ Type: Hard Disk Capacity: 16.0 MB = 0.0 GB (32768 x 512) Device 0: (1:0) Vendor: ATA Prod.: QEMU HARDDISK Rev: 2.5+ Type: Hard Disk Capacity: 256.0 MB = 0.2 GB (524288 x 512) => efi devices Device Device Path ================ ==================== 000000007ef01350 /VenHw(e61d73b9-a384-4acc-aeab-82e828f3628b) 000000007ef0b2c0 /VenHw(e61d73b9-a384-4acc-aeab-82e828f3628b)/Scsi(0,0) 000000007ef0b7b0 /VenHw(e61d73b9-a384-4acc-aeab-82e828f3628b)/Scsi(1,0) 000000007ef0c760 /VenHw(e61d73b9-a384-4acc-aeab-82e828f3628b)/Scsi(1,0)/HD(-1,MBR,0x086246ba,0x17ff56048,0x7eeeb770) 000000007ef0cb50 /VenHw(e61d73b9-a384-4acc-aeab-82e828f3628b)/Scsi(1,0)/HD(-1,MBR,0x086246ba,0x17ff56048,0x7eeeb770) => dm tree Class index Probed Driver Name ----------------------------------------------------------- root 0 [ + ] root_driver root_driver ... pci 0 [ + ] pci_generic_ecam |-- pcie@10000000 pci_generi 0 [ ] pci_generic_drv | |-- pci_0:0.0 virtio 32 [ ] virtio-pci.l | |-- virtio-pci.l#0 ahci 0 [ + ] ahci_pci | `-- ahci_pci scsi 0 [ + ] ahci_scsi | `-- ahci_scsi blk 0 [ ] scsi_blk | |-- ahci_scsi.id0lun0 blk 1 [ ] scsi_blk | `-- ahci_scsi.id1lun0 partition 0 [ ] blk_partition | |-- ahci_scsi.id1lun0:1 partition 1 [ ] blk_partition | `-- ahci_scsi.id1lun0:2 ... Thanks, -Takahiro Akashi AKASHI Takahiro (3): dm: blk: add UCLASS_PARTITION efi_loader: associate BLK/PARTITION device to efi_disk drivers: align block device drivers with DM-efi integration common/usb_storage.c | 27 ++++- drivers/block/blk-uclass.c | 61 ++++++++++ drivers/core/device.c | 3 + drivers/scsi/scsi.c | 22 ++++ include/blk.h | 24 ++++ include/dm/device.h | 4 + include/dm/uclass-id.h | 1 + lib/efi_driver/efi_block_device.c | 30 ++--- lib/efi_loader/efi_disk.c | 192 +++++++++++++++++++++--------- 9 files changed, 283 insertions(+), 81 deletions(-) -- 2.19.1

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[U-Boot] [PATCH 1/3] board: engicam: Add watchdog support on Engicam
by Shyam Saini 06 Feb '19

06 Feb '19

This patch adds watchdog support for engicam imx6 family of boards. Signed-off-by: Shyam Saini <shyam.saini(a)amarulasolutions.com> --- board/engicam/common/board.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/board/engicam/common/board.c b/board/engicam/common/board.c index 5dccb17cb271..7486f0ac2d9c 100644 --- a/board/engicam/common/board.c +++ b/board/engicam/common/board.c @@ -8,6 +8,7 @@ #include <common.h> #include <mmc.h> #include <asm/arch/sys_proto.h> +#include <watchdog.h> #include "board.h" @@ -88,6 +89,10 @@ int board_late_init(void) setenv_fdt_file(); +#ifdef CONFIG_HW_WATCHDOG + hw_watchdog_init(); +#endif + return 0; } -- 2.11.0

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[U-Boot] [RFC][PATCH] cmd: pxe: Display splashscreen from extlinux.conf input
by Patrice Chotard 05 Feb '19

05 Feb '19

The objective is to provide a simple way to retrieve a BMP file, and display it as splashscreen, from extlinux.conf file input. For this, we take example on https://www.syslinux.org/wiki/ index.php?title=Menu#The_advanced_menu_system and more particularly on MENU BACKGROUND chapter. For this, add "menu background" support in pxe command. As example, extlinux.conf content will look like: # Generic Distro Configuration file generated by OpenEmbedded menu title Select the boot mode TIMEOUT 20 menu background ../splash.bmp DEFAULT stm32mp157c-ev1-sdcard LABEL stm32mp157c-ev1-sdcard KERNEL /uImage FDT /stm32mp157c-ev1.dtb APPEND root=/dev/mmcblk0p6 rootwait rw earlyprintk console=ttySTM0,115200 Signed-off-by: Patrice Chotard <patrice.chotard(a)st.com> --- cmd/pxe.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/cmd/pxe.c b/cmd/pxe.c index 274555319ba8..e77770237cb1 100644 --- a/cmd/pxe.c +++ b/cmd/pxe.c @@ -8,11 +8,13 @@ #include <command.h> #include <malloc.h> #include <mapmem.h> +#include <lcd.h> #include <linux/string.h> #include <linux/ctype.h> #include <errno.h> #include <linux/list.h> #include <fs.h> +#include <splash.h> #include <asm/io.h> #include "menu.h" @@ -488,6 +490,7 @@ struct pxe_label { * * title - the name of the menu as given by a 'menu title' line. * default_label - the name of the default label, if any. + * bmp - the bmp file name which is displayed in background * timeout - time in tenths of a second to wait for a user key-press before * booting the default label. * prompt - if 0, don't prompt for a choice unless the timeout period is @@ -498,6 +501,7 @@ struct pxe_label { struct pxe_menu { char *title; char *default_label; + char *bmp; int timeout; int prompt; struct list_head labels; @@ -850,6 +854,7 @@ enum token_type { T_FDTDIR, T_ONTIMEOUT, T_IPAPPEND, + T_BACKGROUND, T_INVALID }; @@ -883,6 +888,7 @@ static const struct token keywords[] = { {"fdtdir", T_FDTDIR}, {"ontimeout", T_ONTIMEOUT,}, {"ipappend", T_IPAPPEND,}, + {"background", T_BACKGROUND,}, {NULL, T_INVALID} }; @@ -1160,6 +1166,10 @@ static int parse_menu(cmd_tbl_t *cmdtp, char **c, struct pxe_menu *cfg, nest_level + 1); break; + case T_BACKGROUND: + err = parse_sliteral(c, &cfg->bmp); + break; + default: printf("Ignoring malformed menu command: %.*s\n", (int)(*c - s), s); @@ -1574,6 +1584,20 @@ static void handle_pxe_menu(cmd_tbl_t *cmdtp, struct pxe_menu *cfg) struct menu *m; int err; +#ifdef CONFIG_CMD_BMP + /* display BMP if available */ + if (cfg->bmp) { + if (get_relfile(cmdtp, cfg->bmp, load_addr)) { + run_command("cls", 0); + bmp_display(load_addr, + BMP_ALIGN_CENTER, BMP_ALIGN_CENTER); + } else { + printf("Skipping background bmp %s for failure\n", + cfg->bmp); + } + } +#endif + m = pxe_menu_to_menu(cfg); if (!m) return; -- 1.9.1

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[U-Boot] [PATCH v2] video: Armada XP: Move driver to DM_VIDEO
by Stefan Roese 05 Feb '19

05 Feb '19

This patch moves the Armada XP video / LCD driver to DM_VIDEO. With this move, the legacy interface board_video_init() is removed from the theadorable board code (only user of this video driver). The support via DT will be added in a separate patch. This patch also enables DM_VIDEO for the theadorable board, as this is needed to not break git bisect'ability. Signed-off-by: Stefan Roese <sr(a)denx.de> Reviewed-by: Anatolij Gustschin <agust(a)denx.de> --- v2: - Add DM_VIDEO in theadorable_debug_defconfig in this patch arch/arm/mach-mvebu/include/mach/cpu.h | 12 - board/theadorable/theadorable.c | 16 -- configs/theadorable_debug_defconfig | 3 +- drivers/video/mvebu_lcd.c | 321 +++++++++++++++---------- 4 files changed, 193 insertions(+), 159 deletions(-) diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index 85d7dd1610..9e23043a48 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -158,18 +158,6 @@ int serdes_phy_config(void); */ int ddr3_init(void); -struct mvebu_lcd_info { - u32 fb_base; - int x_res; - int y_res; - int x_fp; /* frontporch */ - int y_fp; - int x_bp; /* backporch */ - int y_bp; -}; - -int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info); - /* * get_ref_clk * diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c index 1169d67746..acd46b0026 100644 --- a/board/theadorable/theadorable.c +++ b/board/theadorable/theadorable.c @@ -222,22 +222,6 @@ int board_eth_init(bd_t *bis) } #endif -int board_video_init(void) -{ - struct mvebu_lcd_info lcd_info; - - /* Reserved memory area via CONFIG_SYS_MEM_TOP_HIDE */ - lcd_info.fb_base = gd->ram_size; - lcd_info.x_res = 240; - lcd_info.x_fp = 1; - lcd_info.x_bp = 45; - lcd_info.y_res = 320; - lcd_info.y_fp = 1; - lcd_info.y_bp = 3; - - return mvebu_lcd_register_init(&lcd_info); -} - #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { diff --git a/configs/theadorable_debug_defconfig b/configs/theadorable_debug_defconfig index ac6dfd6844..a7d02e957a 100644 --- a/configs/theadorable_debug_defconfig +++ b/configs/theadorable_debug_defconfig @@ -71,6 +71,5 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y +CONFIG_DM_VIDEO=y CONFIG_VIDEO_MVEBU=y -CONFIG_VIDEO=y -# CONFIG_VIDEO_SW_CURSOR is not set diff --git a/drivers/video/mvebu_lcd.c b/drivers/video/mvebu_lcd.c index 5bf0d01faa..dc6254514a 100644 --- a/drivers/video/mvebu_lcd.c +++ b/drivers/video/mvebu_lcd.c @@ -6,74 +6,96 @@ */ #include <common.h> -#include <video_fb.h> +#include <dm.h> +#include <video.h> #include <linux/mbus.h> #include <asm/io.h> #include <asm/arch/cpu.h> #include <asm/arch/soc.h> -#define MVEBU_LCD_WIN_CONTROL(w) (MVEBU_LCD_BASE + 0xf000 + ((w) << 4)) -#define MVEBU_LCD_WIN_BASE(w) (MVEBU_LCD_BASE + 0xf004 + ((w) << 4)) -#define MVEBU_LCD_WIN_REMAP(w) (MVEBU_LCD_BASE + 0xf00c + ((w) << 4)) - -#define MVEBU_LCD_CFG_DMA_START_ADDR_0 (MVEBU_LCD_BASE + 0x00cc) -#define MVEBU_LCD_CFG_DMA_START_ADDR_1 (MVEBU_LCD_BASE + 0x00dc) - -#define MVEBU_LCD_CFG_GRA_START_ADDR0 (MVEBU_LCD_BASE + 0x00f4) -#define MVEBU_LCD_CFG_GRA_START_ADDR1 (MVEBU_LCD_BASE + 0x00f8) -#define MVEBU_LCD_CFG_GRA_PITCH (MVEBU_LCD_BASE + 0x00fc) -#define MVEBU_LCD_SPU_GRA_OVSA_HPXL_VLN (MVEBU_LCD_BASE + 0x0100) -#define MVEBU_LCD_SPU_GRA_HPXL_VLN (MVEBU_LCD_BASE + 0x0104) -#define MVEBU_LCD_SPU_GZM_HPXL_VLN (MVEBU_LCD_BASE + 0x0108) -#define MVEBU_LCD_SPU_HWC_OVSA_HPXL_VLN (MVEBU_LCD_BASE + 0x010c) -#define MVEBU_LCD_SPU_HWC_HPXL_VLN (MVEBU_LCD_BASE + 0x0110) -#define MVEBU_LCD_SPUT_V_H_TOTAL (MVEBU_LCD_BASE + 0x0114) -#define MVEBU_LCD_SPU_V_H_ACTIVE (MVEBU_LCD_BASE + 0x0118) -#define MVEBU_LCD_SPU_H_PORCH (MVEBU_LCD_BASE + 0x011c) -#define MVEBU_LCD_SPU_V_PORCH (MVEBU_LCD_BASE + 0x0120) -#define MVEBU_LCD_SPU_BLANKCOLOR (MVEBU_LCD_BASE + 0x0124) -#define MVEBU_LCD_SPU_ALPHA_COLOR1 (MVEBU_LCD_BASE + 0x0128) -#define MVEBU_LCD_SPU_ALPHA_COLOR2 (MVEBU_LCD_BASE + 0x012c) -#define MVEBU_LCD_SPU_COLORKEY_Y (MVEBU_LCD_BASE + 0x0130) -#define MVEBU_LCD_SPU_COLORKEY_U (MVEBU_LCD_BASE + 0x0134) -#define MVEBU_LCD_SPU_COLORKEY_V (MVEBU_LCD_BASE + 0x0138) -#define MVEBU_LCD_CFG_RDREG4F (MVEBU_LCD_BASE + 0x013c) -#define MVEBU_LCD_SPU_SPI_RXDATA (MVEBU_LCD_BASE + 0x0140) -#define MVEBU_LCD_SPU_ISA_RXDATA (MVEBU_LCD_BASE + 0x0144) -#define MVEBU_LCD_SPU_DBG_ISA (MVEBU_LCD_BASE + 0x0148) - -#define MVEBU_LCD_SPU_HWC_RDDAT (MVEBU_LCD_BASE + 0x0158) -#define MVEBU_LCD_SPU_GAMMA_RDDAT (MVEBU_LCD_BASE + 0x015c) -#define MVEBU_LCD_SPU_PALETTE_RDDAT (MVEBU_LCD_BASE + 0x0160) -#define MVEBU_LCD_SPU_IOPAD_IN (MVEBU_LCD_BASE + 0x0178) -#define MVEBU_LCD_FRAME_COUNT (MVEBU_LCD_BASE + 0x017c) -#define MVEBU_LCD_SPU_DMA_CTRL0 (MVEBU_LCD_BASE + 0x0190) -#define MVEBU_LCD_SPU_DMA_CTRL1 (MVEBU_LCD_BASE + 0x0194) -#define MVEBU_LCD_SPU_SRAM_CTRL (MVEBU_LCD_BASE + 0x0198) -#define MVEBU_LCD_SPU_SRAM_WRDAT (MVEBU_LCD_BASE + 0x019c) -#define MVEBU_LCD_SPU_SRAM_PARA0 (MVEBU_LCD_BASE + 0x01a0) -#define MVEBU_LCD_SPU_SRAM_PARA1 (MVEBU_LCD_BASE + 0x01a4) -#define MVEBU_LCD_CFG_SCLK_DIV (MVEBU_LCD_BASE + 0x01a8) -#define MVEBU_LCD_SPU_CONTRAST (MVEBU_LCD_BASE + 0x01ac) -#define MVEBU_LCD_SPU_SATURATION (MVEBU_LCD_BASE + 0x01b0) -#define MVEBU_LCD_SPU_CBSH_HUE (MVEBU_LCD_BASE + 0x01b4) -#define MVEBU_LCD_SPU_DUMB_CTRL (MVEBU_LCD_BASE + 0x01b8) -#define MVEBU_LCD_SPU_IOPAD_CONTROL (MVEBU_LCD_BASE + 0x01bc) -#define MVEBU_LCD_SPU_IRQ_ENA_2 (MVEBU_LCD_BASE + 0x01d8) -#define MVEBU_LCD_SPU_IRQ_ISR_2 (MVEBU_LCD_BASE + 0x01dc) -#define MVEBU_LCD_SPU_IRQ_ENA (MVEBU_LCD_BASE + 0x01c0) -#define MVEBU_LCD_SPU_IRQ_ISR (MVEBU_LCD_BASE + 0x01c4) -#define MVEBU_LCD_ADLL_CTRL (MVEBU_LCD_BASE + 0x01c8) -#define MVEBU_LCD_CLK_DIS (MVEBU_LCD_BASE + 0x01cc) -#define MVEBU_LCD_VGA_HVSYNC_DELAY (MVEBU_LCD_BASE + 0x01d4) -#define MVEBU_LCD_CLK_CFG_0 (MVEBU_LCD_BASE + 0xf0a0) -#define MVEBU_LCD_CLK_CFG_1 (MVEBU_LCD_BASE + 0xf0a4) -#define MVEBU_LCD_LVDS_CLK_CFG (MVEBU_LCD_BASE + 0xf0ac) +#define MVEBU_LCD_WIN_CONTROL(w) (0xf000 + ((w) << 4)) +#define MVEBU_LCD_WIN_BASE(w) (0xf004 + ((w) << 4)) +#define MVEBU_LCD_WIN_REMAP(w) (0xf00c + ((w) << 4)) + +#define MVEBU_LCD_CFG_DMA_START_ADDR_0 0x00cc +#define MVEBU_LCD_CFG_DMA_START_ADDR_1 0x00dc + +#define MVEBU_LCD_CFG_GRA_START_ADDR0 0x00f4 +#define MVEBU_LCD_CFG_GRA_START_ADDR1 0x00f8 +#define MVEBU_LCD_CFG_GRA_PITCH 0x00fc +#define MVEBU_LCD_SPU_GRA_OVSA_HPXL_VLN 0x0100 +#define MVEBU_LCD_SPU_GRA_HPXL_VLN 0x0104 +#define MVEBU_LCD_SPU_GZM_HPXL_VLN 0x0108 +#define MVEBU_LCD_SPU_HWC_OVSA_HPXL_VLN 0x010c +#define MVEBU_LCD_SPU_HWC_HPXL_VLN 0x0110 +#define MVEBU_LCD_SPUT_V_H_TOTAL 0x0114 +#define MVEBU_LCD_SPU_V_H_ACTIVE 0x0118 +#define MVEBU_LCD_SPU_H_PORCH 0x011c +#define MVEBU_LCD_SPU_V_PORCH 0x0120 +#define MVEBU_LCD_SPU_BLANKCOLOR 0x0124 +#define MVEBU_LCD_SPU_ALPHA_COLOR1 0x0128 +#define MVEBU_LCD_SPU_ALPHA_COLOR2 0x012c +#define MVEBU_LCD_SPU_COLORKEY_Y 0x0130 +#define MVEBU_LCD_SPU_COLORKEY_U 0x0134 +#define MVEBU_LCD_SPU_COLORKEY_V 0x0138 +#define MVEBU_LCD_CFG_RDREG4F 0x013c +#define MVEBU_LCD_SPU_SPI_RXDATA 0x0140 +#define MVEBU_LCD_SPU_ISA_RXDATA 0x0144 +#define MVEBU_LCD_SPU_DBG_ISA 0x0148 + +#define MVEBU_LCD_SPU_HWC_RDDAT 0x0158 +#define MVEBU_LCD_SPU_GAMMA_RDDAT 0x015c +#define MVEBU_LCD_SPU_PALETTE_RDDAT 0x0160 +#define MVEBU_LCD_SPU_IOPAD_IN 0x0178 +#define MVEBU_LCD_FRAME_COUNT 0x017c +#define MVEBU_LCD_SPU_DMA_CTRL0 0x0190 +#define MVEBU_LCD_SPU_DMA_CTRL1 0x0194 +#define MVEBU_LCD_SPU_SRAM_CTRL 0x0198 +#define MVEBU_LCD_SPU_SRAM_WRDAT 0x019c +#define MVEBU_LCD_SPU_SRAM_PARA0 0x01a0 +#define MVEBU_LCD_SPU_SRAM_PARA1 0x01a4 +#define MVEBU_LCD_CFG_SCLK_DIV 0x01a8 +#define MVEBU_LCD_SPU_CONTRAST 0x01ac +#define MVEBU_LCD_SPU_SATURATION 0x01b0 +#define MVEBU_LCD_SPU_CBSH_HUE 0x01b4 +#define MVEBU_LCD_SPU_DUMB_CTRL 0x01b8 +#define MVEBU_LCD_SPU_IOPAD_CONTROL 0x01bc +#define MVEBU_LCD_SPU_IRQ_ENA_2 0x01d8 +#define MVEBU_LCD_SPU_IRQ_ISR_2 0x01dc +#define MVEBU_LCD_SPU_IRQ_ENA 0x01c0 +#define MVEBU_LCD_SPU_IRQ_ISR 0x01c4 +#define MVEBU_LCD_ADLL_CTRL 0x01c8 +#define MVEBU_LCD_CLK_DIS 0x01cc +#define MVEBU_LCD_VGA_HVSYNC_DELAY 0x01d4 +#define MVEBU_LCD_CLK_CFG_0 0xf0a0 +#define MVEBU_LCD_CLK_CFG_1 0xf0a4 +#define MVEBU_LCD_LVDS_CLK_CFG 0xf0ac #define MVEBU_LVDS_PADS_REG (MVEBU_SYSTEM_REG_BASE + 0xf0) +enum { + /* Maximum LCD size we support */ + LCD_MAX_WIDTH = 640, + LCD_MAX_HEIGHT = 480, + LCD_MAX_LOG2_BPP = VIDEO_BPP16, +}; + +struct mvebu_lcd_info { + u32 fb_base; + int x_res; + int y_res; + int x_fp; + int y_fp; + int x_bp; + int y_bp; +}; + +struct mvebu_video_priv { + uintptr_t regs; +}; + /* Setup Mbus Bridge Windows for LCD */ -static void mvebu_lcd_conf_mbus_registers(void) +static void mvebu_lcd_conf_mbus_registers(uintptr_t regs) { const struct mbus_dram_target_info *dram; int i; @@ -82,9 +104,9 @@ static void mvebu_lcd_conf_mbus_registers(void) /* Disable windows, set size/base/remap to 0 */ for (i = 0; i < 6; i++) { - writel(0, MVEBU_LCD_WIN_CONTROL(i)); - writel(0, MVEBU_LCD_WIN_BASE(i)); - writel(0, MVEBU_LCD_WIN_REMAP(i)); + writel(0, regs + MVEBU_LCD_WIN_CONTROL(i)); + writel(0, regs + MVEBU_LCD_WIN_BASE(i)); + writel(0, regs + MVEBU_LCD_WIN_REMAP(i)); } /* Write LCD bridge window registers */ @@ -92,14 +114,15 @@ static void mvebu_lcd_conf_mbus_registers(void) const struct mbus_dram_window *cs = dram->cs + i; writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | (dram->mbus_dram_target_id << 4) | 1, - MVEBU_LCD_WIN_CONTROL(i)); + regs + MVEBU_LCD_WIN_CONTROL(i)); - writel(cs->base & 0xffff0000, MVEBU_LCD_WIN_BASE(i)); + writel(cs->base & 0xffff0000, regs + MVEBU_LCD_WIN_BASE(i)); } } /* Initialize LCD registers */ -int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info) +static void mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info, + uintptr_t regs) { /* Local variable for easier handling */ int x = lcd_info->x_res; @@ -107,7 +130,7 @@ int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info) u32 val; /* Setup Mbus Bridge Windows */ - mvebu_lcd_conf_mbus_registers(); + mvebu_lcd_conf_mbus_registers(regs); /* * Set LVDS Pads Control Register @@ -121,8 +144,8 @@ int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info) * end (currently 1GB-64MB but also may be 2GB-64MB). * See also the Window 0 settings! */ - writel(lcd_info->fb_base, MVEBU_LCD_CFG_GRA_START_ADDR0); - writel(lcd_info->fb_base, MVEBU_LCD_CFG_GRA_START_ADDR1); + writel(lcd_info->fb_base, regs + MVEBU_LCD_CFG_GRA_START_ADDR0); + writel(lcd_info->fb_base, regs + MVEBU_LCD_CFG_GRA_START_ADDR1); /* * Set the LCD_CFG_GRA_PITCH Register @@ -132,14 +155,14 @@ int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info) * Bits 15-00: Line Length in Bytes * 240*2 (for RGB1555)=480=0x1E0 */ - writel(0x80100000 + 2 * x, MVEBU_LCD_CFG_GRA_PITCH); + writel(0x80100000 + 2 * x, regs + MVEBU_LCD_CFG_GRA_PITCH); /* * Set the LCD_SPU_GRA_OVSA_HPXL_VLN Register * Bits 31-16: Vertical start of graphical overlay on screen * Bits 15-00: Horizontal start of graphical overlay on screen */ - writel(0x00000000, MVEBU_LCD_SPU_GRA_OVSA_HPXL_VLN); + writel(0x00000000, regs + MVEBU_LCD_SPU_GRA_OVSA_HPXL_VLN); /* * Set the LCD_SPU_GRA_HPXL_VLN Register @@ -147,7 +170,7 @@ int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info) * Bits 15-00: Horizontal size of graphical overlay 240=0xF0 * Values before zooming */ - writel((y << 16) | x, MVEBU_LCD_SPU_GRA_HPXL_VLN); + writel((y << 16) | x, regs + MVEBU_LCD_SPU_GRA_HPXL_VLN); /* * Set the LCD_SPU_GZM_HPXL_VLN Register @@ -155,21 +178,21 @@ int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info) * Bits 15-00: Horizontal size of graphical overlay 240=0xF0 * Values after zooming */ - writel((y << 16) | x, MVEBU_LCD_SPU_GZM_HPXL_VLN); + writel((y << 16) | x, regs + MVEBU_LCD_SPU_GZM_HPXL_VLN); /* * Set the LCD_SPU_HWC_OVSA_HPXL_VLN Register * Bits 31-16: Vertical position of HW Cursor 320=0x140 * Bits 15-00: Horizontal position of HW Cursor 240=0xF0 */ - writel((y << 16) | x, MVEBU_LCD_SPU_HWC_OVSA_HPXL_VLN); + writel((y << 16) | x, regs + MVEBU_LCD_SPU_HWC_OVSA_HPXL_VLN); /* * Set the LCD_SPU_HWC_OVSA_HPXL_VLN Register * Bits 31-16: Vertical size of HW Cursor * Bits 15-00: Horizontal size of HW Cursor */ - writel(0x00000000, MVEBU_LCD_SPU_HWC_HPXL_VLN); + writel(0x00000000, regs + MVEBU_LCD_SPU_HWC_HPXL_VLN); /* * Set the LCD_SPU_HWC_OVSA_HPXL_VLN Register @@ -191,14 +214,14 @@ int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info) */ val = ((y + lcd_info->y_fp + lcd_info->y_bp + 1) << 16) | (x + lcd_info->x_fp + lcd_info->x_bp + 1); - writel(val, MVEBU_LCD_SPUT_V_H_TOTAL); + writel(val, regs + MVEBU_LCD_SPUT_V_H_TOTAL); /* * Set the LCD_SPU_V_H_ACTIVE Register * Bits 31-16: Screen active vertical lines 320=0x140 * Bits 15-00: Screen active horizontakl pixels 240=0x00F0 */ - writel((y << 16) | x, MVEBU_LCD_SPU_V_H_ACTIVE); + writel((y << 16) | x, regs + MVEBU_LCD_SPU_V_H_ACTIVE); /* * Set the LCD_SPU_H_PORCH Register @@ -207,7 +230,8 @@ int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info) * Note: The terms "front" and "back" for the Marvell seem to be * exactly opposite to the display. */ - writel((lcd_info->x_fp << 16) | lcd_info->x_bp, MVEBU_LCD_SPU_H_PORCH); + writel((lcd_info->x_fp << 16) | lcd_info->x_bp, + regs + MVEBU_LCD_SPU_H_PORCH); /* * Set the LCD_SPU_V_PORCH Register @@ -216,14 +240,15 @@ int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info) * Note: The terms "front" and "back" for the Marvell seem to be exactly * opposite to the display. */ - writel((lcd_info->y_fp << 16) | lcd_info->y_bp, MVEBU_LCD_SPU_V_PORCH); + writel((lcd_info->y_fp << 16) | lcd_info->y_bp, + regs + MVEBU_LCD_SPU_V_PORCH); /* * Set the LCD_SPU_BLANKCOLOR Register * This should be black = 0 * For tests this is magenta=00FF00FF */ - writel(0x00FF00FF, MVEBU_LCD_SPU_BLANKCOLOR); + writel(0x00FF00FF, regs + MVEBU_LCD_SPU_BLANKCOLOR); /* * Registers in the range of 0x0128 to 0x012C are colors for the cursor @@ -240,7 +265,7 @@ int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info) * Bit 8: FIFO watermark for DMA: 0=disable * Bits 07-00: Empty 8B FIFO entries to trigger DMA, default=0x80 */ - writel(0x00000780, MVEBU_LCD_CFG_RDREG4F); + writel(0x00000780, regs + MVEBU_LCD_CFG_RDREG4F); /* * Set the LCD_SPU_DMACTRL 0 Register @@ -271,7 +296,7 @@ int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info) * Bit 01: Video YUV to RGB Conversion: 0=disable * Bit 00: Video Transfer: 0=disable */ - writel(0x88111100, MVEBU_LCD_SPU_DMA_CTRL0); + writel(0x88111100, regs + MVEBU_LCD_SPU_DMA_CTRL0); /* * Set the LCD_SPU_DMA_CTRL1 Register @@ -288,7 +313,7 @@ int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info) * Bits 15-08: Configure Alpha: 0x00. * Bits 07-00: Reserved. */ - writel(0x20010000, MVEBU_LCD_SPU_DMA_CTRL1); + writel(0x20010000, regs + MVEBU_LCD_SPU_DMA_CTRL1); /* * Set the LCD_SPU_SRAM_CTRL Register @@ -297,14 +322,14 @@ int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info) * Bits 11-08: SRAM address ID: 0=gamma_yr, 1=gammy_ug, 2=gamma_vb, * 3=palette, 15=cursor */ - writel(0x0000C000, MVEBU_LCD_SPU_SRAM_CTRL); + writel(0x0000C000, regs + MVEBU_LCD_SPU_SRAM_CTRL); /* * LCD_SPU_SRAM_WRDAT register: 019C * LCD_SPU_SRAM_PARA0 register: 01A0 * LCD_SPU_SRAM_PARA1 register: 01A4 - Cursor control/Power settings */ - writel(0x00000000, MVEBU_LCD_SPU_SRAM_PARA1); + writel(0x00000000, regs + MVEBU_LCD_SPU_SRAM_PARA1); /* Clock settings in the at 01A8 and in the range F0A0 see below */ @@ -314,21 +339,21 @@ int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info) * Bits 31-16: Brightness sign ext. 8-bit value +255 to -255: default=0 * Bits 15-00: Contrast sign ext. 8-bit value +255 to -255: default=0 */ - writel(0x00000000, MVEBU_LCD_SPU_CONTRAST); + writel(0x00000000, regs + MVEBU_LCD_SPU_CONTRAST); /* * Set LCD_SPU_SATURATION * Bits 31-16: Multiplier signed 4.12 fixed point value * Bits 15-00: Saturation signed 4.12 fixed point value */ - writel(0x10001000, MVEBU_LCD_SPU_SATURATION); + writel(0x10001000, regs + MVEBU_LCD_SPU_SATURATION); /* * Set LCD_SPU_HUE * Bits 31-16: Sine signed 2.14 fixed point value * Bits 15-00: Cosine signed 2.14 fixed point value */ - writel(0x00000000, MVEBU_LCD_SPU_CBSH_HUE); + writel(0x00000000, regs + MVEBU_LCD_SPU_CBSH_HUE); /* * Set LCD_SPU_DUMB_CTRL @@ -348,7 +373,7 @@ int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info) * Question: Do we have to disable Smart and Dumb LCD * and separately enable LVDS? */ - writel(0x6000080F, MVEBU_LCD_SPU_DUMB_CTRL); + writel(0x6000080F, regs + MVEBU_LCD_SPU_DUMB_CTRL); /* * Set LCD_SPU_IOPAD_CTRL @@ -366,17 +391,17 @@ int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info) * 128 Bytes burst * Bits 03-00: LCD pins: ??? 0=24-bit Dump panel ?? */ - writel(0x000000C0, MVEBU_LCD_SPU_IOPAD_CONTROL); + writel(0x000000C0, regs + MVEBU_LCD_SPU_IOPAD_CONTROL); /* * Set SUP_IRQ_ENA_2: Disable all interrupts */ - writel(0x00000000, MVEBU_LCD_SPU_IRQ_ENA_2); + writel(0x00000000, regs + MVEBU_LCD_SPU_IRQ_ENA_2); /* * Set SUP_IRQ_ENA: Disable all interrupts. */ - writel(0x00000000, MVEBU_LCD_SPU_IRQ_ENA); + writel(0x00000000, regs + MVEBU_LCD_SPU_IRQ_ENA); /* * Set up ADDL Control Register @@ -399,19 +424,19 @@ int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info) * Bits 05-00: Delay taps, 0x3F=Half Cycle, 0x00=No delay * Note: ADLL is used for a VGA interface with DAC - not used here */ - writel(0x00000000, MVEBU_LCD_ADLL_CTRL); + writel(0x00000000, regs + MVEBU_LCD_ADLL_CTRL); /* * Set the LCD_CLK_DIS Register: * Bits 3 and 4 must be 1 */ - writel(0x00000018, MVEBU_LCD_CLK_DIS); + writel(0x00000018, regs + MVEBU_LCD_CLK_DIS); /* * Set the LCD_VGA_HSYNC/VSYNC Delay Register: * Bits 03-00: Sets the delay for the HSYNC and VSYNC signals */ - writel(0x00000000, MVEBU_LCD_VGA_HVSYNC_DELAY); + writel(0x00000000, regs + MVEBU_LCD_VGA_HVSYNC_DELAY); /* * Clock registers @@ -423,12 +448,12 @@ int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info) /* * Disable PLL, see "LCD Clock Configuration 1 Register" below */ - writel(0x8FF40007, MVEBU_LCD_CLK_CFG_1); + writel(0x8FF40007, regs + MVEBU_LCD_CLK_CFG_1); /* * Powerdown, see "LCD Clock Configuration 0 Register" below */ - writel(0x94000174, MVEBU_LCD_CLK_CFG_0); + writel(0x94000174, regs + MVEBU_LCD_CLK_CFG_0); /* * Set the LCD_CFG_SCLK_DIV Register @@ -437,7 +462,7 @@ int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info) * Bits 15-01: Clock Divider: Bypass for LVDS=0x0001 * See page 475 in section 28.5. */ - writel(0x80000001, MVEBU_LCD_CFG_SCLK_DIV); + writel(0x80000001, regs + MVEBU_LCD_CFG_SCLK_DIV); /* * Set the LCD Clock Configuration 0 Register: @@ -452,7 +477,7 @@ int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info) * N=28=0x1C => 0x1B * Bits 03-00: R1_CTRL (for N=28 => 0x4) */ - writel(0x940021B4, MVEBU_LCD_CLK_CFG_0); + writel(0x940021B4, regs + MVEBU_LCD_CLK_CFG_0); /* * Set the LCD Clock Configuration 1 Register: @@ -465,7 +490,7 @@ int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info) * Bits 12-00: PLL Full Divider [Note: Assumed to be the Post-Divider * M' for LVDS=7!] */ - writel(0x8FF40007, MVEBU_LCD_CLK_CFG_1); + writel(0x8FF40007, regs + MVEBU_LCD_CLK_CFG_1); /* * Set the LVDS Clock Configuration Register: @@ -479,12 +504,12 @@ int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info) * Note: Bits 0 and must be verified with the help of the * Interface/display */ - writel(0xC0000201, MVEBU_LCD_LVDS_CLK_CFG); + writel(0xC0000201, regs + MVEBU_LCD_LVDS_CLK_CFG); /* * Power up PLL (Clock Config 0) */ - writel(0x140021B4, MVEBU_LCD_CLK_CFG_0); + writel(0x140021B4, regs + MVEBU_LCD_CLK_CFG_0); /* wait 10 ms */ mdelay(10); @@ -492,40 +517,78 @@ int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info) /* * Enable PLL (Clock Config 1) */ - writel(0x8FF60007, MVEBU_LCD_CLK_CFG_1); - - return 0; + writel(0x8FF60007, regs + MVEBU_LCD_CLK_CFG_1); } -int __weak board_video_init(void) +static int mvebu_video_probe(struct udevice *dev) { - return -1; -} + struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); + struct video_priv *uc_priv = dev_get_uclass_priv(dev); + struct mvebu_video_priv *priv = dev_get_priv(dev); + struct mvebu_lcd_info lcd_info; + struct display_timing timings; + u32 fb_start, fb_end; + int ret; + + priv->regs = dev_read_addr(dev); + if (priv->regs == FDT_ADDR_T_NONE) { + dev_err(dev, "failed to get LCD address\n"); + return -ENXIO; + } -void *video_hw_init(void) -{ - static GraphicDevice mvebufb; - GraphicDevice *pGD = &mvebufb; - u32 val; + ret = ofnode_decode_display_timing(dev_ofnode(dev), 0, &timings); + if (ret) { + dev_err(dev, "failed to get any display timings\n"); + return -EINVAL; + } - /* - * The board code needs to call mvebu_lcd_register_init() - * in its board_video_init() implementation, with the board - * specific parameters for its LCD. - */ - if (board_video_init() || !readl(MVEBU_LCD_CFG_GRA_START_ADDR0)) - return NULL; + /* Use DT timing (resolution) in internal info struct */ + lcd_info.fb_base = plat->base; + lcd_info.x_res = timings.hactive.typ; + lcd_info.x_fp = timings.hfront_porch.typ; + lcd_info.x_bp = timings.hback_porch.typ; + lcd_info.y_res = timings.vactive.typ; + lcd_info.y_fp = timings.vfront_porch.typ; + lcd_info.y_bp = timings.vback_porch.typ; + + /* Initialize the LCD controller */ + mvebu_lcd_register_init(&lcd_info, priv->regs); + + /* Enable dcache for the frame buffer */ + fb_start = plat->base & ~(MMU_SECTION_SIZE - 1); + fb_end = plat->base + plat->size; + fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT); + mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start, + DCACHE_WRITEBACK); + video_set_flush_dcache(dev, true); + + uc_priv->xsize = lcd_info.x_res; + uc_priv->ysize = lcd_info.y_res; + uc_priv->bpix = VIDEO_BPP16; /* Uses RGB555 format */ + + return 0; +} - /* Provide the necessary values for the U-Boot video IF */ - val = readl(MVEBU_LCD_SPU_V_H_ACTIVE); - pGD->winSizeY = val >> 16; - pGD->winSizeX = val & 0x0000ffff; - pGD->gdfBytesPP = 2; - pGD->gdfIndex = GDF_15BIT_555RGB; - pGD->frameAdrs = readl(MVEBU_LCD_CFG_GRA_START_ADDR0); +static int mvebu_video_bind(struct udevice *dev) +{ + struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); - debug("LCD: buffer at 0x%08x resolution %dx%d\n", pGD->frameAdrs, - pGD->winSizeX, pGD->winSizeY); + plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT * + (1 << LCD_MAX_LOG2_BPP) / 8; - return pGD; + return 0; } + +static const struct udevice_id mvebu_video_ids[] = { + { .compatible = "marvell,armada-xp-lcd" }, + { } +}; + +U_BOOT_DRIVER(mvebu_video) = { + .name = "mvebu_video", + .id = UCLASS_VIDEO, + .of_match = mvebu_video_ids, + .bind = mvebu_video_bind, + .probe = mvebu_video_probe, + .priv_auto_alloc_size = sizeof(struct mvebu_video_priv), +}; -- 2.20.1

2 7

[U-Boot] [PATCH v4] arm64: mvebu: Add basic support for uDPU board
by Vladimir Vid 05 Feb '19

05 Feb '19

This adds initial support for micro-DPU (uDPU) board which is based on Armada-3720 SoC. micro-DPU is the single-port FTTdp "distribution point unit" made by Methode Electronics which offers complete modularity with replaceable SFP modules both for uplink and downlink (G.hn over twisted-pair, G.hn over coax, 1G and 2.5G Ethernet over Cat-5e cable). On-board features: - 512 MiB DDR3 - 2 x 2.5G SFP via HSGMII SERDES interface to the A3720 SoC - USB 2.0 Type-C connector - 4GB eMMC - ETSI TS 101548 reverse powering via twisted pair (RJ45) or coax (F Type) Cc: Luka Perkov <luka.perkov(a)sartura.hr> Cc: Luis Torres <luis.torres(a)methode.com> Cc: Scott Roberts <scott.roberts(a)telus.com> Cc: Paul Arola <paul.arola(a)telus.com> Cc: Stefan Roese <sr(a)denx.de> Signed-off-by: Vladimir Vid <vladimir.vid(a)sartura.hr> --- v4 changes: - moved u-boot specific properties to armada-3720-uDPU-u-boot.dtsi - added additional 'u-boot,dm-pre-reloc' on sdhci1 (eMMC) --- arch/arm/dts/Makefile | 1 + arch/arm/dts/armada-3720-uDPU-u-boot.dtsi | 13 ++ arch/arm/dts/armada-3720-uDPU.dts | 200 ++++++++++++++++++++ board/Marvell/mvebu_armada-37xx/MAINTAINERS | 5 + configs/uDPU_defconfig | 94 +++++++++ 5 files changed, 313 insertions(+) create mode 100644 arch/arm/dts/armada-3720-uDPU-u-boot.dtsi create mode 100644 arch/arm/dts/armada-3720-uDPU.dts create mode 100644 configs/uDPU_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 5c3225bcbf..9e1e1ad8e9 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -95,6 +95,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-3720-db.dtb \ armada-3720-espressobin.dtb \ armada-3720-turris-mox.dtb \ + armada-3720-uDPU.dts \ armada-375-db.dtb \ armada-388-clearfog.dtb \ armada-388-gp.dtb \ diff --git a/arch/arm/dts/armada-3720-uDPU-u-boot.dtsi b/arch/arm/dts/armada-3720-uDPU-u-boot.dtsi new file mode 100644 index 0000000000..ef178bdc86 --- /dev/null +++ b/arch/arm/dts/armada-3720-uDPU-u-boot.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ + +&spi0 { + u-boot,dm-pre-reloc; + + spi-flash@0 { + u-boot,dm-pre-reloc; + }; +}; + +&sdhci1 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/armada-3720-uDPU.dts b/arch/arm/dts/armada-3720-uDPU.dts new file mode 100644 index 0000000000..683dac2a7c --- /dev/null +++ b/arch/arm/dts/armada-3720-uDPU.dts @@ -0,0 +1,200 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device tree for the uDPU board. + * Based on Marvell Armada 3720 development board (DB-88F3720-DDR3) + * Copyright (C) 2016 Marvell + * Copyright (C) 2018 Methode + * Copyright (C) 2018 Telus + * + * Vladimir Vid <vladimir.vid(a)sartura.hr> + */ + +/dts-v1/; + +#include "armada-37xx.dtsi" +#include "armada-3720-uDPU-u-boot.dtsi" + +/ { + model = "Methode uDPU Board"; + compatible = "methode,udpu"; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs = "console=ttyMV0,115200 earlycon=ar3700_uart,0xd0012000"; + }; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + spi0 = &spi0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0x20000000>; + }; + + mdio: mdio@32004 { + #address-cells = <1>; + #size-cells = <0>; + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + ethphy1: ethernet-phy@1 { + reg = <1>; + }; + }; + + scsi: scsi { + compatible = "marvell,mvebu-scsi"; + #address-cells = <1>; + #size-cells = <1>; + max-id = <1>; + max-lun = <1>; + status = "okay"; + }; + + i2c1: i2c@11080 { + compatible = "marvell,armada-3700-i2c", "simple-bus"; + reg = <0x0 0x11080 0x0 0x80>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + #address-cells = <2>; + #size-cells = <2>; + status = "okay"; + }; + + uart1: serial@12200 { + compatible = "marvell,armada-3700-uart-ext"; + reg = <0x0 0x12200 0x0 0x30>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; + #address-cells = <2>; + #size-cells = <2>; + }; + + vcc_sd_reg0: regulator@0 { + compatible = "regulator-gpio"; + regulator-name = "vcc_sd0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-type = "voltage"; + states = <1800000 0x1 + 3300000 0x0>; + gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>; + }; + + sfp_eth0: sfp-eth0 { + compatible = "sff,sfp"; + i2c-bus = <&i2c0>; + los-gpio = <&gpiosb 2 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&gpiosb 3 GPIO_ACTIVE_LOW>; + tx-disable-gpio = <&gpiosb 4 GPIO_ACTIVE_HIGH>; + tx-fault-gpio = <&gpiosb 5 GPIO_ACTIVE_HIGH>; + }; + + sfp_eth1: sfp-eth1 { + compatible = "sff,sfp"; + i2c-bus = <&i2c1>; + sfp,ethernet = <&eth1>; + los-gpio = <&gpiosb 7 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&gpiosb 8 GPIO_ACTIVE_LOW>; + tx-disable-gpio = <&gpiosb 9 GPIO_ACTIVE_HIGH>; + tx-fault-gpio = <&gpiosb 10 GPIO_ACTIVE_HIGH>; + }; +}; + +&comphy { + phy0 { + phy-type = <PHY_TYPE_SGMII1>; + phy-speed = <PHY_SPEED_1_25G>; + }; + phy1 { + phy-type = <PHY_TYPE_SGMII0>; + phy-speed = <PHY_SPEED_1_25G>; + }; + + phy2 { + phy-type = <PHY_TYPE_USB3_HOST1>; + phy-speed = <PHY_SPEED_5G>; + }; +}; + +&eth0 { + pinctrl-0 = <&pcie_pins>; + status = "okay"; + phy-mode = "sgmii"; + phy = <&ethphy0>; + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&eth1 { + status = "okay"; + phy-mode = "sgmii"; + phy = <&ethphy1>; + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "okay"; +}; + +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi_quad_pins>; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q1024a","n25q512a"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + m25p,fast-read; + + partition@0 { + label = "uboot"; + reg = <0 0x400000>; + }; + }; +}; + +&sdhci1 { + non-removable; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + bus-width = <4>; + vqmmc-supply = <&vcc_sd_reg0>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio_pins>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + mmccard: mmccard@0 { + compatible = "mmc-card"; + reg = <0>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; diff --git a/board/Marvell/mvebu_armada-37xx/MAINTAINERS b/board/Marvell/mvebu_armada-37xx/MAINTAINERS index 9b0afeef10..f2c0a582d7 100644 --- a/board/Marvell/mvebu_armada-37xx/MAINTAINERS +++ b/board/Marvell/mvebu_armada-37xx/MAINTAINERS @@ -9,3 +9,8 @@ ESPRESSOBin BOARD M: Konstantin Porotchkin <kostap(a)marvell.com> S: Maintained F: configs/mvebu_espressobin-88f3720_defconfig + +uDPU BOARD +M: Vladimir Vid <vladimir.vid(a)sartura.hr> +S: Maintained +F: configs/uDPU_defconfig diff --git a/configs/uDPU_defconfig b/configs/uDPU_defconfig new file mode 100644 index 0000000000..53f2b6e746 --- /dev/null +++ b/configs/uDPU_defconfig @@ -0,0 +1,94 @@ +CONFIG_ARM=y +CONFIG_ARCH_MVEBU=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_MVEBU_ARMADA_37XX=y +CONFIG_DEBUG_UART_BASE=0xd0012000 +CONFIG_DEBUG_UART_CLOCK=25804800 +CONFIG_SMBIOS_PRODUCT_NAME="uDPU" +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_FIT=y +CONFIG_SPI_BOOT=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_ARCH_EARLY_INIT_R=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_PROMPT="uDPU>> " +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_MVEBU_BUBT=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nor0=spi0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0:4m(uboot),-(rootfs)" +CONFIG_MAC_PARTITION=y +CONFIG_DEFAULT_DEVICE_TREE="armada-3720-uDPU" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_AHCI_MVEBU=y +CONFIG_CLK=y +CONFIG_CLK_MVEBU=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_I2C_GPIO=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_XENON=y +CONFIG_MTD=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHYLIB_10G=y +CONFIG_PHY_MARVELL=y +CONFIG_PHY_GIGE=y +CONFIG_E1000=y +CONFIG_MVNETA=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCI_AARDVARK=y +CONFIG_MVEBU_COMPHY_SUPPORT=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_ARMADA_37XX=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +# CONFIG_SPL_SERIAL_PRESENT is not set +CONFIG_DEBUG_MVEBU_A3700_UART=y +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_MVEBU_A3700_UART=y +CONFIG_MVEBU_A3700_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_LZO=y +CONFIG_SPL_LZO=y -- 2.19.0

2 2

[U-Boot] eMMC boot partition possible with an eMMC 4.2 controller ?
by Joakim Tjernlund 05 Feb '19

05 Feb '19

Trying to figure out if it will be possible to boot u-boot from an eMMC boot partition using an eMMC 4.2 controller(eMMC boot part. was introduced in 4.3) ? I know this might not be the best list to ask this but I have been unable to find this out using Google and I hope there is someone here that knows the answer. Jocke

1 0

[U-Boot] [PATCH 00/11] SiFive FU540 Support
by Anup Patel 05 Feb '19

05 Feb '19

This patchset adds SiFive Freedom Unleashed (FU540) support to RISC-V U-Boot. The patches are based upon latest RISC-V U-Boot tree (git://git.denx.de/u-boot-riscv.git) at commit id 91882c472d8c0aef4db699d3f2de55bf43d4ae4b All drivers namely: SiFive PRCI, SiFive Serial, and Cadance MACB Ethernet work fine on actual SiFive Unleashed board and QEMU sifive_u machine. Anup Patel (7): riscv: Rename cpu/qemu to cpu/generic riscv: Add asm/dma-mapping.h for DMA mappings riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systems net: macb: Fix clk API usage for RISC-V systems clk: Add SiFive FU540 PRCI clock driver clk: Add fixed-factor clock driver riscv: Add SiFive FU540 board support Atish Patra (4): net: macb: Fix GEM hardware detection drivers: serial_sifive: Fix baud rate calculation drivers: serial: serial_sifive: Skip baudrate config if no input clock cpu: Bind timer driver for boot hart arch/riscv/Kconfig | 6 +- arch/riscv/cpu/{qemu => generic}/Kconfig | 2 +- arch/riscv/cpu/{qemu => generic}/Makefile | 0 arch/riscv/cpu/{qemu => generic}/cpu.c | 0 arch/riscv/cpu/generic/dram.c | 39 ++ arch/riscv/cpu/qemu/dram.c | 17 - arch/riscv/include/asm/dma-mapping.h | 38 ++ board/emulation/qemu-riscv/Kconfig | 4 +- .../qemu-riscv => sifive/fu540}/Kconfig | 36 +- board/sifive/fu540/MAINTAINERS | 9 + board/sifive/fu540/Makefile | 5 + board/sifive/fu540/fu540.c | 17 + configs/sifive_fu540_defconfig | 11 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 5 +- drivers/clk/clk_fixed_factor.c | 74 +++ drivers/clk/sifive/Kconfig | 19 + drivers/clk/sifive/Makefile | 5 + .../clk/sifive/analogbits-wrpll-cln28hpc.h | 101 +++ drivers/clk/sifive/fu540-prci.c | 604 ++++++++++++++++++ drivers/clk/sifive/wrpll-cln28hpc.c | 390 +++++++++++ drivers/cpu/riscv_cpu.c | 7 +- drivers/net/macb.c | 6 +- drivers/serial/serial_sifive.c | 60 +- include/configs/sifive-fu540.h | 43 ++ include/dt-bindings/clk/sifive-fu540-prci.h | 29 + 26 files changed, 1467 insertions(+), 61 deletions(-) rename arch/riscv/cpu/{qemu => generic}/Kconfig (91%) rename arch/riscv/cpu/{qemu => generic}/Makefile (100%) rename arch/riscv/cpu/{qemu => generic}/cpu.c (100%) create mode 100644 arch/riscv/cpu/generic/dram.c delete mode 100644 arch/riscv/cpu/qemu/dram.c create mode 100644 arch/riscv/include/asm/dma-mapping.h copy board/{emulation/qemu-riscv => sifive/fu540}/Kconfig (57%) create mode 100644 board/sifive/fu540/MAINTAINERS create mode 100644 board/sifive/fu540/Makefile create mode 100644 board/sifive/fu540/fu540.c create mode 100644 configs/sifive_fu540_defconfig create mode 100644 drivers/clk/clk_fixed_factor.c create mode 100644 drivers/clk/sifive/Kconfig create mode 100644 drivers/clk/sifive/Makefile create mode 100644 drivers/clk/sifive/analogbits-wrpll-cln28hpc.h create mode 100644 drivers/clk/sifive/fu540-prci.c create mode 100644 drivers/clk/sifive/wrpll-cln28hpc.c create mode 100644 include/configs/sifive-fu540.h create mode 100644 include/dt-bindings/clk/sifive-fu540-prci.h -- 2.17.1

5 35

[U-Boot] [PATCH v2 0/9] Add common pinctrl driver support for rockchip
by David Wu 05 Feb '19

05 Feb '19

The common pinctrl driver for rockchip Socs, it depends the PINCTRL_FULL config. If use it, the default pinctrl setup from DTS could be configured at device probe. Changes in v2: - Remove px30, rk2928, rk3066*. - Split it to multiple files for the relevant per-SoC data structures. David Wu (9): rockchip: rk3399-evb: defconfig: Enable FDT for new pinctrl driver ARM: rockchip: rk3188: Remove the pinctrl setup and enable uart at SPL ARM: rockchip: Kconfig: Remove the SPL_PINCTRL for rk3188 ARM: rockchip: Remove the pinctrl request at rk3288-board-spl rk3288: chrome: defconfig: Enable FDT for new pinctrl driver pinctrl: rockchip: Add common rockchip pinctrl driver rockchip: defconfig: Clean the unused pinctrl config pinctrl: rockchip: Clean the unused rockchip pinctrl drivers ARM: dts: rk322x: Correct the uart2 default pin configuration arch/arm/dts/rk322x.dtsi | 11 +- arch/arm/mach-rockchip/Kconfig | 1 - arch/arm/mach-rockchip/rk3188-board-spl.c | 41 +- arch/arm/mach-rockchip/rk3288-board-spl.c | 79 -- configs/chromebit_mickey_defconfig | 4 - configs/chromebook_jerry_defconfig | 4 - configs/chromebook_minnie_defconfig | 4 - configs/evb-px5_defconfig | 1 - configs/evb-rk3128_defconfig | 1 - configs/evb-rk3229_defconfig | 1 - configs/evb-rk3288_defconfig | 2 - configs/evb-rk3399_defconfig | 2 - configs/evb-rv1108_defconfig | 1 - configs/fennec-rk3288_defconfig | 2 - configs/firefly-rk3288_defconfig | 2 - configs/firefly-rk3399_defconfig | 1 - configs/geekbox_defconfig | 1 - configs/kylin-rk3036_defconfig | 1 - configs/lion-rk3368_defconfig | 1 - configs/miqi-rk3288_defconfig | 2 - configs/phycore-rk3288_defconfig | 2 - configs/popmetal-rk3288_defconfig | 2 - configs/puma-rk3399_defconfig | 1 - configs/rock2_defconfig | 2 - configs/rock_defconfig | 1 - configs/sandbox_defconfig | 2 - configs/sandbox_flattree_defconfig | 2 - configs/sandbox_noblk_defconfig | 2 - configs/sheep-rk3368_defconfig | 1 - configs/tinker-rk3288_defconfig | 2 - configs/vyasa-rk3288_defconfig | 2 - drivers/pinctrl/Kconfig | 91 +- drivers/pinctrl/Makefile | 2 +- drivers/pinctrl/rockchip/Kconfig | 17 + drivers/pinctrl/rockchip/Makefile | 19 +- drivers/pinctrl/rockchip/pinctrl-rk3036.c | 65 ++ drivers/pinctrl/rockchip/pinctrl-rk3128.c | 155 +++ drivers/pinctrl/rockchip/pinctrl-rk3188.c | 82 ++ drivers/pinctrl/rockchip/pinctrl-rk322x.c | 215 ++++ drivers/pinctrl/rockchip/pinctrl-rk3288.c | 157 +++ drivers/pinctrl/rockchip/pinctrl-rk3328.c | 227 ++++ drivers/pinctrl/rockchip/pinctrl-rk3368.c | 116 ++ drivers/pinctrl/rockchip/pinctrl-rk3399.c | 193 ++++ .../pinctrl/rockchip/pinctrl-rockchip-core.c | 788 ++++++++++++++ drivers/pinctrl/rockchip/pinctrl-rockchip.h | 302 ++++++ drivers/pinctrl/rockchip/pinctrl-rv1108.c | 203 ++++ drivers/pinctrl/rockchip/pinctrl_rk3036.c | 671 ------------ drivers/pinctrl/rockchip/pinctrl_rk3128.c | 186 ---- drivers/pinctrl/rockchip/pinctrl_rk3188.c | 989 ------------------ drivers/pinctrl/rockchip/pinctrl_rk322x.c | 894 ---------------- drivers/pinctrl/rockchip/pinctrl_rk3288.c | 869 --------------- drivers/pinctrl/rockchip/pinctrl_rk3328.c | 705 ------------- drivers/pinctrl/rockchip/pinctrl_rk3368.c | 739 ------------- drivers/pinctrl/rockchip/pinctrl_rk3399.c | 503 --------- drivers/pinctrl/rockchip/pinctrl_rv1108.c | 580 ---------- 55 files changed, 2543 insertions(+), 6406 deletions(-) create mode 100644 drivers/pinctrl/rockchip/Kconfig create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3036.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3128.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3188.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk322x.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3288.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3328.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3368.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3399.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rockchip-core.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rockchip.h create mode 100644 drivers/pinctrl/rockchip/pinctrl-rv1108.c delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3036.c delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3128.c delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3188.c delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk322x.c delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3288.c delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3328.c delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3368.c delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3399.c delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rv1108.c -- 2.19.1

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