February 2019 - U-Boot

[U-Boot] [PATCH v2 0/7] arm/arm64: i2c platform cleanup
by Michal Simek 07 Feb '19

07 Feb '19

Hi, sending this v2 as follow up series based on https://lists.denx.de/pipermail/u-boot/2019-January/357172.html which converts all platform to DM_I2C and removes old driver. Thanks, Michal Changes in v2: - Extract Syzygy from Topic - Add eeprom to i2c - needs to be checked by Syzygy team if this is correct - Add dependency Michal Simek (7): ARM: zynq: Convert Syzygy to DM_I2C ARM: zynq: Convert dlc20 and zc70x board to DM_I2C ARM: zynq: Remove addresses for i2c controllers arm64: zynqmp: Switch all platfroms to DM_I2C arm64: zynqmp: Remove addresses for i2c controllers i2c: Remove ancient zynq_i2c driver xilinx: common: Remove !DM_i2C code for reading mac from eeprom README | 5 - arch/arm/dts/zynq-syzygy-hub.dts | 6 + arch/arm/dts/zynqmp-zcu102-revA.dts | 1 + arch/arm/dts/zynqmp-zcu104-revC.dts | 1 + arch/arm/dts/zynqmp-zcu106-revA.dts | 1 + arch/arm/dts/zynqmp-zcu111-revA.dts | 1 + arch/arm/mach-zynq/include/mach/hardware.h | 2 - arch/arm/mach-zynqmp/include/mach/hardware.h | 3 - board/xilinx/common/board.c | 19 -- configs/avnet_ultra96_rev1_defconfig | 6 +- configs/syzygy_hub_defconfig | 5 +- configs/xilinx_zynqmp_zcu100_revC_defconfig | 6 +- configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 12 +- configs/xilinx_zynqmp_zcu102_revA_defconfig | 13 +- configs/xilinx_zynqmp_zcu102_revB_defconfig | 13 +- configs/xilinx_zynqmp_zcu104_revA_defconfig | 11 +- configs/xilinx_zynqmp_zcu104_revC_defconfig | 11 +- configs/xilinx_zynqmp_zcu106_revA_defconfig | 12 +- configs/xilinx_zynqmp_zcu111_revA_defconfig | 12 +- configs/zynq_dlc20_rev1_0_defconfig | 9 +- configs/zynq_zc702_defconfig | 10 +- configs/zynq_zc706_defconfig | 10 +- configs/zynq_zybo_defconfig | 1 - drivers/i2c/Kconfig | 33 --- drivers/i2c/Makefile | 1 - drivers/i2c/zynq_i2c.c | 313 -------------------------- drivers/misc/Kconfig | 1 + include/configs/syzygy_hub.h | 4 - include/configs/xilinx_zynqmp.h | 5 - include/configs/xilinx_zynqmp_zcu100.h | 15 -- include/configs/xilinx_zynqmp_zcu102.h | 29 --- include/configs/xilinx_zynqmp_zcu104.h | 17 -- include/configs/xilinx_zynqmp_zcu104_revC.h | 3 - include/configs/xilinx_zynqmp_zcu106.h | 28 --- include/configs/xilinx_zynqmp_zcu111.h | 31 --- include/configs/zynq-common.h | 14 -- include/configs/zynq_zc70x.h | 16 -- 37 files changed, 90 insertions(+), 590 deletions(-) delete mode 100644 drivers/i2c/zynq_i2c.c delete mode 100644 include/configs/zynq_zc70x.h -- 1.9.1

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Re: [U-Boot] [PATCH v2 1/2] splash: Use splashfile instead of location->name
by Jonas Mark (BT-FIR/ENG1) 07 Feb '19

07 Feb '19

Hi Tomas, > >> So my initial question still stands, could existing implementation be > >> kept as fallback? > >> > >> + if (!splash_file) > >> + splash_file = location->name; > >> > >> location->name has worked fine for those cases, so it would be nice > >> location->to > >> keep that option intact. > > I think that the .name field of struct splash_location is actually > > intended to hold a human readable name for the storage itself. That > > the code so far uses the storage location name synonymously with the > > splash screen name is unfortunate. That's why we decided to fix this. > > I am convinced that the patch actually makes it easier for others to > > start reading splash screens from a FIT image. > > If I understand the original issue you had correctly, could it also have > been fixed by renaming splash node in FIT image? Yes, that's we actually started with. But once we started adding more files to that FIT image we saw the problem: Then we had files in the FIT image with "nice" names and one "ugly duckling". Now it is fixed. Patch 2/2 shows more things we fixed on the way and are now contributing. > > Why do I think so? Because the behavior is now consistent to what > > splash_load_fs() does. That is, if there is an environment variable > > "splashfile" the splash screen name is taken from there. Else, the > > fixed default name "splash.bmp" is used. > > Symmetry is nice, so ok. But still, it now rules out the possiblity to use the > splash name in the FIT without defining additional "splashfile" > to the env. This is not correct. In case you do not define "splashfile" in the environment the consistent (!) default name is "splash.bmp". Regards, Mark Building Technologies, Panel Software Fire (BT-FIR/ENG1) Bosch Sicherheitssysteme GmbH | Postfach 11 11 | 85626 Grasbrunn | GERMANY | www.boschsecurity.com Sitz: Stuttgart, Registergericht: Amtsgericht Stuttgart HRB 23118 Aufsichtsratsvorsitzender: Christian Fischer; Geschäftsführung: Tanja Rückert, Andreas Bartz, Thomas Quante, Bernhard Schuster

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[U-Boot] [PATCH] i2c: cdns: Covert to livetree function
by Michal Simek 07 Feb '19

07 Feb '19

Update cadence i2c driver to support livetree Similar changes were done by: "net: zynq_gem: convert to use livetree" (sha1: 26026e695afa794ac018a09e79a48120d322b60d) Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/i2c/i2c-cdns.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c index f2c4b2073c48..4330d28c2b0d 100644 --- a/drivers/i2c/i2c-cdns.c +++ b/drivers/i2c/i2c-cdns.c @@ -419,7 +419,7 @@ static int cdns_i2c_ofdata_to_platdata(struct udevice *dev) struct clk clk; int ret; - i2c_bus->regs = (struct cdns_i2c_regs *)devfdt_get_addr(dev); + i2c_bus->regs = (struct cdns_i2c_regs *)dev_read_addr(dev); if (!i2c_bus->regs) return -ENOMEM; -- 1.9.1

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[U-Boot] [PATCH 0/3] arm: Introduce writel/readl_relaxed accessors
by Andre Przywara 07 Feb '19

07 Feb '19

Admittedly this is the long way round to solve some nasty SPL code size problem, but it looked beneficial to others as well, so here we go: arch/arm/include/asm/io.h looks like it's been around since the dawn of time, and was more or less blindly copied from Linux. We don't use and don't need most of the definitions, and mainline Linux got rid of them anyway, so patch 1/3 cleans up this header file to just contain what we need in U-Boot. Patch 2/3 introduces readl/writel_relaxed accessors, which are cheaper, but more importantly save one (barrier) instruction per accessor. This helps to bring down code size, since especially DRAM controller inits in SPLs tend to do a lot of MMIO. Consequently patch 3/3 introduces them in the Allwinner H6 DRAM driver, which reduces the SPL size by a whopping 2KB, due to a twist: The AArch64 exception table needs to be 2KB aligned, but we don't do anything special about it the linker script. So depending on where the code before the vectors ends, we have potentially large padding: At the moment this last address is 0x1824 for the H6, so the vectors can only start at 0x2000. By reducing the code size before the vectors by just (at least) 9 instructions, the vectors start at 0x1800 and we save most of the padding. I understand that the proper solution is to fill the gap before the vectors with code instead of NOPs, but I couldn't find any obvious way doing this in the linker script. If anyone has any idea here, I am all ears. Cheers, Andre. Andre Przywara (3): arm: clean up asm/io.h arm: introduce _relaxed MMIO accessors sunxi: H6: use writel_relaxed for DRAM timing register accesses arch/arm/include/asm/io.h | 164 +++-------------------------------- arch/arm/mach-sunxi/dram_sun50i_h6.c | 79 +++++++++-------- 2 files changed, 54 insertions(+), 189 deletions(-) -- 2.14.5

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[U-Boot] [PATCH v4 0/3] Add MMD PHY helpers
by Carlo Caione 07 Feb '19

07 Feb '19

Introduce phy_(read|write)_mmd() generic 802.3 clause 45 register accessors for Clause 22 PHYs, using the indirect method. Allow this behaviour to be overriden by PHY drivers where necessary. Carlo Caione (3): net: phy: Add support for accessing MMD PHY registers net: phy: ti: use generic helpers to access MMD registers cmd: mdio: Add new parameter to access MMD PHY registers cmd/mdio.c | 52 ++++++++++++----- drivers/net/phy/phy.c | 4 ++ drivers/net/phy/ti.c | 130 ++++++++---------------------------------- include/phy.h | 52 +++++++++++++++++ 4 files changed, 118 insertions(+), 120 deletions(-) -- 2.19.1

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[U-Boot] [PATCH 3/3] mips: add ethernet support for qca953x referenced boards
by Rosy Song 06 Feb '19

06 Feb '19

Signed-off-by: Rosy Song <rosysong(a)rosinson.com> --- arch/mips/dts/ap143.dts | 5 +++++ arch/mips/dts/qca953x.dtsi | 31 +++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/arch/mips/dts/ap143.dts b/arch/mips/dts/ap143.dts index 6aedd87db9..2e23225f12 100644 --- a/arch/mips/dts/ap143.dts +++ b/arch/mips/dts/ap143.dts @@ -40,3 +40,8 @@ reg = <0>; }; }; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; +}; diff --git a/arch/mips/dts/qca953x.dtsi b/arch/mips/dts/qca953x.dtsi index ba29ea287e..90d34ddbbf 100644 --- a/arch/mips/dts/qca953x.dtsi +++ b/arch/mips/dts/qca953x.dtsi @@ -65,6 +65,37 @@ status = "disabled"; }; + + gmac0: eth0@0x19000000 { + compatible = "qca,ag953x-mac"; + reg = <0x19000000 0x200>; + phy = <&phy4>; + phy-mode = "rmii"; + + status = "disabled"; + }; + + gmac1: eth1@0x1a000000 { + compatible = "qca,ag953x-mac"; + reg = <0x1a000000 0x200>; + phy = <&phy0>; + phy-mode = "rgmii"; + + status = "disabled"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@0 { + reg = <0>; + phy-mode = "rmii"; + }; + phy4: ethernet-phy@4 { + reg = <4>; + phy-mode = "rmii"; + }; + }; + }; }; spi0: spi@1f000000 { -- 2.17.0

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[U-Boot] [PATCH 2/3] drivers: add ethernet support for qca953x in ag7xxx driver
by Rosy Song 06 Feb '19

06 Feb '19

Signed-off-by: Rosy Song <rosysong(a)rosinson.com> --- drivers/net/ag7xxx.c | 203 +++++++++++++++++++++++++++++++++++++++---- 1 file changed, 186 insertions(+), 17 deletions(-) diff --git a/drivers/net/ag7xxx.c b/drivers/net/ag7xxx.c index 8146c3170e..403eb64895 100644 --- a/drivers/net/ag7xxx.c +++ b/drivers/net/ag7xxx.c @@ -23,6 +23,7 @@ DECLARE_GLOBAL_DATA_PTR; enum ag7xxx_model { AG7XXX_MODEL_AG933X, AG7XXX_MODEL_AG934X, + AG7XXX_MODEL_AG953X }; /* MAC Configuration 1 */ @@ -99,8 +100,29 @@ enum ag7xxx_model { /* Rx Status */ #define AG7XXX_ETH_DMA_RX_STATUS 0x194 +/* Custom register at 0x1805002C */ +#define AG7XXX_ETH_XMII 0x2C +#define AG7XXX_ETH_XMII_TX_INVERT BIT(31) +#define AG7XXX_ETH_XMII_RX_DELAY_LSB 28 +#define AG7XXX_ETH_XMII_RX_DELAY_MASK 0x30000000 +#define AG7XXX_ETH_XMII_RX_DELAY_SET(x) \ + (((x) << AG7XXX_ETH_XMII_RX_DELAY_LSB) & AG7XXX_ETH_XMII_RX_DELAY_MASK) +#define AG7XXX_ETH_XMII_TX_DELAY_LSB 26 +#define AG7XXX_ETH_XMII_TX_DELAY_MASK 0x0c000000 +#define AG7XXX_ETH_XMII_TX_DELAY_SET(x) \ + (((x) << AG7XXX_ETH_XMII_TX_DELAY_LSB) & AG7XXX_ETH_XMII_TX_DELAY_MASK) +#define AG7XXX_ETH_XMII_GIGE BIT(25) + /* Custom register at 0x18070000 */ #define AG7XXX_GMAC_ETH_CFG 0x00 +#define AG7XXX_ETH_CFG_RXDV_DELAY_LSB 16 +#define AG7XXX_ETH_CFG_RXDV_DELAY_MASK 0x00030000 +#define AG7XXX_ETH_CFG_RXDV_DELAY_SET(x) \ + (((x) << AG7XXX_ETH_CFG_RXDV_DELAY_LSB) & AG7XXX_ETH_CFG_RXDV_DELAY_MASK) +#define AG7XXX_ETH_CFG_RXD_DELAY_LSB 14 +#define AG7XXX_ETH_CFG_RXD_DELAY_MASK 0x0000c000 +#define AG7XXX_ETH_CFG_RXD_DELAY_SET(x) \ + (((x) << AG7XXX_ETH_CFG_RXD_DELAY_LSB) & AG7XXX_ETH_CFG_RXD_DELAY_MASK) #define AG7XXX_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8) #define AG7XXX_ETH_CFG_SW_PHY_SWAP BIT(7) #define AG7XXX_ETH_CFG_SW_ONLY_MODE BIT(6) @@ -200,7 +222,8 @@ static int ag7xxx_switch_reg_read(struct mii_dev *bus, int reg, u32 *val) u16 rv = 0; int ret; - if (priv->model == AG7XXX_MODEL_AG933X) { + if (priv->model == AG7XXX_MODEL_AG933X || + priv->model == AG7XXX_MODEL_AG953X) { phy_addr = 0x1f; reg_addr = 0x10; } else if (priv->model == AG7XXX_MODEL_AG934X) { @@ -239,7 +262,8 @@ static int ag7xxx_switch_reg_write(struct mii_dev *bus, int reg, u32 val) u32 reg_temp; int ret; - if (priv->model == AG7XXX_MODEL_AG933X) { + if (priv->model == AG7XXX_MODEL_AG933X || + priv->model == AG7XXX_MODEL_AG953X) { phy_addr = 0x1f; reg_addr = 0x10; } else if (priv->model == AG7XXX_MODEL_AG934X) { @@ -598,10 +622,16 @@ static int ag7xxx_mii_setup(struct udevice *dev) return 0; } - if (priv->model == AG7XXX_MODEL_AG934X) { - writel(AG7XXX_ETH_MII_MGMT_CFG_RESET | 0x4, + if (priv->model == AG7XXX_MODEL_AG934X) + reg = 0x4; + else if (priv->model == AG7XXX_MODEL_AG953X) + reg = 0x2; + + if (priv->model == AG7XXX_MODEL_AG934X || + priv->model == AG7XXX_MODEL_AG953X) { + writel(AG7XXX_ETH_MII_MGMT_CFG_RESET | reg, priv->regs + AG7XXX_ETH_MII_MGMT_CFG); - writel(0x4, priv->regs + AG7XXX_ETH_MII_MGMT_CFG); + writel(reg, priv->regs + AG7XXX_ETH_MII_MGMT_CFG); return 0; } @@ -698,14 +728,125 @@ static int ag933x_phy_setup_lan(struct udevice *dev) return 0; } +static int ag953x_phy_setup_wan(struct udevice *dev) +{ + int ret; + u32 reg = 0; + struct ar7xxx_eth_priv *priv = dev_get_priv(dev); + + /* Set wan port connect to GE0 */ + ret = ag7xxx_switch_reg_read(priv->bus, 0x8, &reg); + if (ret) + return ret; + + ret = ag7xxx_switch_reg_write(priv->bus, 0x8, reg | BIT(28)); + if (ret) + return ret; + + /* Configure switch port 4 (GMAC0) */ + ret = ag7xxx_switch_write(priv->bus, 4, MII_BMCR, 0x9000); + if (ret) + return ret; + + return 0; +} + +static int ag953x_phy_setup_lan(struct udevice *dev) +{ + struct ar7xxx_eth_priv *priv = dev_get_priv(dev); + int i, ret; + u32 reg = 0; + + /* Reset the switch */ + ret = ag7xxx_switch_reg_read(priv->bus, 0, &reg); + if (ret) + return ret; + + ret = ag7xxx_switch_reg_write(priv->bus, 0, reg | BIT(31)); + if (ret) + return ret; + + do { + ret = ag7xxx_switch_reg_read(priv->bus, 0, &reg); + if (ret) + return ret; + } while (reg & BIT(31)); + + ret = ag7xxx_switch_reg_write(priv->bus, 0x100, 0x4e); + if (ret) + return ret; + + /* Set GMII mode */ + ret = ag7xxx_switch_reg_read(priv->bus, 0x4, &reg); + if (ret) + return ret; + + ret = ag7xxx_switch_reg_write(priv->bus, 0x4, reg | BIT(6)); + if (ret) + return ret; + + /* Configure switch ports 0...4 (GMAC1) */ + for (i = 0; i < 5; i++) { + ret = ag7xxx_switch_write(priv->bus, i, MII_BMCR, 0x9000); + if (ret) + return ret; + } + + for (i = 0; i < 5; i++) { + ret = ag7xxx_switch_reg_write(priv->bus, (i + 2) * 0x100, BIT(9)); + if (ret) + return ret; + } + + /* QM Control */ + ret = ag7xxx_switch_reg_write(priv->bus, 0x38, 0xc000050e); + if (ret) + return ret; + + /* Disable Atheros header */ + ret = ag7xxx_switch_reg_write(priv->bus, 0x104, 0x4004); + if (ret) + return ret; + + /* Tag priority mapping */ + ret = ag7xxx_switch_reg_write(priv->bus, 0x70, 0xfa50); + if (ret) + return ret; + + /* Enable ARP packets to the CPU */ + ret = ag7xxx_switch_reg_read(priv->bus, 0x5c, &reg); + if (ret) + return ret; + + ret = ag7xxx_switch_reg_write(priv->bus, 0x5c, reg | 0x100000); + if (ret) + return ret; + + /* Enable broadcast packets to the CPU */ + ret = ag7xxx_switch_reg_read(priv->bus, 0x2c, &reg); + if (ret) + return ret; + + ret = ag7xxx_switch_reg_write(priv->bus, 0x2c, reg | BIT(25) | BIT(26)); + if (ret) + return ret; + + return 0; +} + static int ag933x_phy_setup_reset_set(struct udevice *dev, int port) { struct ar7xxx_eth_priv *priv = dev_get_priv(dev); int ret; - ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_ADVERTISE, - ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | - ADVERTISE_PAUSE_ASYM); + if (priv->model == AG7XXX_MODEL_AG953X) { + ret = ag7xxx_switch_write(priv->bus, port, MII_ADVERTISE, + ADVERTISE_ALL); + } else { + ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_ADVERTISE, + ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | + ADVERTISE_PAUSE_ASYM); + } if (ret) return ret; @@ -716,6 +857,10 @@ static int ag933x_phy_setup_reset_set(struct udevice *dev, int port) return ret; } + if (priv->model == AG7XXX_MODEL_AG953X) + return ag7xxx_switch_write(priv->bus, port, MII_BMCR, + BMCR_ANENABLE | BMCR_RESET); + return ag7xxx_mdio_write(priv->bus, port, 0, MII_BMCR, BMCR_ANENABLE | BMCR_RESET); } @@ -724,13 +869,23 @@ static int ag933x_phy_setup_reset_fin(struct udevice *dev, int port) { struct ar7xxx_eth_priv *priv = dev_get_priv(dev); int ret; + u16 reg; - do { - ret = ag7xxx_mdio_read(priv->bus, port, 0, MII_BMCR); - if (ret < 0) - return ret; - mdelay(10); - } while (ret & BMCR_RESET); + if (priv->model == AG7XXX_MODEL_AG953X) { + do { + ret = ag7xxx_switch_read(priv->bus, port, MII_BMCR, &reg); + if (ret < 0) + return ret; + mdelay(10); + } while (reg & BMCR_RESET); + } else { + do { + ret = ag7xxx_mdio_read(priv->bus, port, 0, MII_BMCR); + if (ret < 0) + return ret; + mdelay(10); + } while (ret & BMCR_RESET); + } return 0; } @@ -739,10 +894,12 @@ static int ag933x_phy_setup_common(struct udevice *dev) { struct ar7xxx_eth_priv *priv = dev_get_priv(dev); int i, ret, phymax; + u16 reg; if (priv->model == AG7XXX_MODEL_AG933X) phymax = 4; - else if (priv->model == AG7XXX_MODEL_AG934X) + else if (priv->model == AG7XXX_MODEL_AG934X || + priv->model == AG7XXX_MODEL_AG953X) phymax = 5; else return -EINVAL; @@ -757,7 +914,10 @@ static int ag933x_phy_setup_common(struct udevice *dev) return ret; /* Read out link status */ - ret = ag7xxx_mdio_read(priv->bus, phymax, 0, MII_MIPSCR); + if (priv->model == AG7XXX_MODEL_AG953X) + ret = ag7xxx_switch_read(priv->bus, phymax, MII_MIPSCR, &reg); + else + ret = ag7xxx_mdio_read(priv->bus, phymax, 0, MII_MIPSCR); if (ret < 0) return ret; @@ -779,7 +939,10 @@ static int ag933x_phy_setup_common(struct udevice *dev) for (i = 0; i < phymax; i++) { /* Read out link status */ - ret = ag7xxx_mdio_read(priv->bus, i, 0, MII_MIPSCR); + if (priv->model == AG7XXX_MODEL_AG953X) + ret = ag7xxx_switch_read(priv->bus, i, MII_MIPSCR, &reg); + else + ret = ag7xxx_mdio_read(priv->bus, i, 0, MII_MIPSCR); if (ret < 0) return ret; } @@ -858,6 +1021,11 @@ static int ag7xxx_mac_probe(struct udevice *dev) ret = ag933x_phy_setup_wan(dev); else ret = ag933x_phy_setup_lan(dev); + } else if (priv->model == AG7XXX_MODEL_AG953X) { + if (priv->interface == PHY_INTERFACE_MODE_RMII) + ret = ag953x_phy_setup_wan(dev); + else + ret = ag953x_phy_setup_lan(dev); } else if (priv->model == AG7XXX_MODEL_AG934X) { ret = ag934x_phy_setup(dev); } else { @@ -997,6 +1165,7 @@ static int ag7xxx_eth_ofdata_to_platdata(struct udevice *dev) static const struct udevice_id ag7xxx_eth_ids[] = { { .compatible = "qca,ag933x-mac", .data = AG7XXX_MODEL_AG933X }, { .compatible = "qca,ag934x-mac", .data = AG7XXX_MODEL_AG934X }, + { .compatible = "qca,ag953x-mac", .data = AG7XXX_MODEL_AG953X }, { } }; -- 2.17.0

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[U-Boot] [PATCH 1/3] drivers: fix typo for pinctrl qca953x
by Rosy Song 06 Feb '19

06 Feb '19

Signed-off-by: Rosy Song <rosysong(a)rosinson.com> --- drivers/pinctrl/ath79/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/ath79/Makefile b/drivers/pinctrl/ath79/Makefile index 1daa2123a1..c7d1e44882 100644 --- a/drivers/pinctrl/ath79/Makefile +++ b/drivers/pinctrl/ath79/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+ obj-$(CONFIG_PINCTRL_AR933X) += pinctrl_ar933x.o -obj-$(CONFIG_PINCTRL_QCA953x) += pinctrl_qca953x.o +obj-$(CONFIG_PINCTRL_QCA953X) += pinctrl_qca953x.o -- 2.17.0

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[U-Boot] [PATCH v2 0/2] Load splash from FIT image (internal, external, offset)
by Mark Jonas 06 Feb '19

06 Feb '19

We store a splash screen in SPI-NOR. We chose to use a FIT image as a container because we want to - store more than just the splash screen in SPI-NOR, - do not create a bunch of MTD partitions, - do not waste storage space, and - avoid the overhead of a real file system. In general U-Boot already supports this. But there were some ripples we had to smooth out. The following patches resolve these. Changes since v1: - Document default name in README.splashprepare - Use ALIGN() macro Leo Ruan (2): splash: Use splashfile instead of location->name splash: Load internal and external data from FIT common/splash_source.c | 65 +++++++++++++++++++++++++++++++----------------- doc/README.splashprepare | 9 ++++--- 2 files changed, 48 insertions(+), 26 deletions(-) -- 2.7.4

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Re: [U-Boot] [PATCH v2 1/2] splash: Use splashfile instead of location->name
by Jonas Mark (BT-FIR/ENG1) 06 Feb '19

06 Feb '19

Hi Tomas, > > I conclude that no upstream board is actually affected. They would only > be affecte if they would use SPLASH_STORAGE_FIT. > > You are right, indeed upstream boards should be ok. However, some > other non upstream boards I know of would be affected. > > So my initial question still stands, could existing implementation be kept > as fallback? > > + if (!splash_file) > + splash_file = location->name; > > location->name has worked fine for those cases, so it would be nice to > keep that option intact. I think that the .name field of struct splash_location is actually intended to hold a human readable name for the storage itself. That the code so far uses the storage location name synonymously with the splash screen name is unfortunate. That's why we decided to fix this. I am convinced that the patch actually makes it easier for others to start reading splash screens from a FIT image. Why do I think so? Because the behavior is now consistent to what splash_load_fs() does. That is, if there is an environment variable "splashfile" the splash screen name is taken from there. Else, the fixed default name "splash.bmp" is used. Regards, Mark Building Technologies, Panel Software Fire (BT-FIR/ENG1) Bosch Sicherheitssysteme GmbH | Postfach 11 11 | 85626 Grasbrunn | GERMANY | www.boschsecurity.com Sitz: Stuttgart, Registergericht: Amtsgericht Stuttgart HRB 23118 Aufsichtsratsvorsitzender: Christian Fischer; Geschäftsführung: Tanja Rückert, Andreas Bartz, Thomas Quante, Bernhard Schuster

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