November 2019 - U-Boot

[U-Boot] [PATCH] ARM: da850-evm: Disable SYS_MMCSD_RAW_MODE_USE_SECTOR
by Adam Ford 05 Dec '19

05 Dec '19

The da850-evm doesn't have the boot pins configured in a way to make MMC/SD booting an option, and MMC/SD support is not enabled in SPL. Therefore, there is no need to support raw mode mmc/sd support in SPL. This patch disables CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig index 4ff08e7d44..ed4a8609af 100644 --- a/configs/da850evm_defconfig +++ b/configs/da850evm_defconfig @@ -23,6 +23,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SEPARATE_BSS=y +# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000 CONFIG_HUSH_PARSER=y diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig index b1f11deab8..b4e9f25bfe 100644 --- a/configs/da850evm_nand_defconfig +++ b/configs/da850evm_nand_defconfig @@ -21,6 +21,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SEPARATE_BSS=y +# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000 -- 2.20.1

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[U-Boot] [PATCH] ARM: omapl138_lcdk: Shrink code size by building with Thumb
by Adam Ford 05 Dec '19

05 Dec '19

SPL has limited available resources, and the performance between ARM and Thumb isn't that significant. This patch builds using Thumb instruction set to reduce the code size by nearly 6K. Original: text data bss dec hex filename 26526 4004 1376 31906 7ca2 spl/u-boot-spl Thumb: text data bss dec hex filename 20232 4004 1376 25612 640c spl/u-boot-spl Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig index 9821df9884..16287a4ac2 100644 --- a/configs/omapl138_lcdk_defconfig +++ b/configs/omapl138_lcdk_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_DAVINCI=y CONFIG_SYS_TEXT_BASE=0xc1080000 CONFIG_TARGET_OMAPL138_LCDK=y -- 2.20.1

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[U-Boot] [PATCH v2 1/1] net: avoid address-of-packed-member error
by Heinrich Schuchardt 05 Dec '19

05 Dec '19

sandbox_defconfig does not compile using GCC 9.2.1: net/net.c: In function ‘net_process_received_packet’: net/net.c:1288:23: error: taking address of packed member of ‘struct ip_udp_hdr’ may result in an unaligned pointer value [-Werror=address-of-packed-member] 1288 | sumptr = (ushort *)&(ip->udp_src); | ^~~~~~~~~~~~~~ Avoid the error by using a u8 pointer instead of an u16 pointer and in-lining ntohs(). Simplify the checksumming of the last message byte. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- v2: reword commit message add a comment simplify checksumming of last byte --- net/net.c | 20 +++++++------------- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/net/net.c b/net/net.c index ded86e7456..bcb9d5f07e 100644 --- a/net/net.c +++ b/net/net.c @@ -1274,7 +1274,7 @@ void net_process_received_packet(uchar *in_packet, int len) #ifdef CONFIG_UDP_CHECKSUM if (ip->udp_xsum != 0) { ulong xsum; - ushort *sumptr; + u8 *sumptr; ushort sumlen; xsum = ip->ip_p; @@ -1285,22 +1285,16 @@ void net_process_received_packet(uchar *in_packet, int len) xsum += (ntohl(ip->ip_dst.s_addr) >> 0) & 0x0000ffff; sumlen = ntohs(ip->udp_len); - sumptr = (ushort *)&(ip->udp_src); + sumptr = (u8 *)&ip->udp_src; while (sumlen > 1) { - ushort sumdata; - - sumdata = *sumptr++; - xsum += ntohs(sumdata); + /* inlined ntohs() to avoid alignment errors */ + xsum += (sumptr[0] << 8) + sumptr[1]; + sumptr += 2; sumlen -= 2; } - if (sumlen > 0) { - ushort sumdata; - - sumdata = *(unsigned char *)sumptr; - sumdata = (sumdata << 8) & 0xff00; - xsum += sumdata; - } + if (sumlen > 0) + xsum += (sumptr[0] << 8) + sumptr[0]; while ((xsum >> 16) != 0) { xsum = (xsum & 0x0000ffff) + ((xsum >> 16) & 0x0000ffff); -- 2.24.0.rc1

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[U-Boot] [PATCH] sun8i: h3: Support H3 variant of Orange Pi Zero Plus 2
by Diego Rondini 05 Dec '19

05 Dec '19

Orangepi Zero Plus 2 is an open-source single-board computer, available in two Allwinner SOC variants, H3 and H5. We add support for H3 variant here, as the H5 is already supported. H3 Orangepi Zero Plus 2 has: - Quad-core Cortex-A7 - 512MB DDR3 - microSD slot and 8GB eMMC - Debug TTL UART - HDMI - Wifi + BT - OTG + power supply Signed-off-by: Diego Rondini <diego.rondini(a)kynetics.com> --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts | 139 ++++++++++++++++++ board/sunxi/MAINTAINERS | 5 + configs/orangepi_zero_plus2_h3_defconfig | 19 +++ 4 files changed, 165 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts create mode 100644 configs/orangepi_zero_plus2_h3_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 251d32ca62..5c7b8cfcc9 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -513,7 +513,8 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \ sun8i-h3-orangepi-pc.dtb \ sun8i-h3-orangepi-pc-plus.dtb \ sun8i-h3-orangepi-plus.dtb \ - sun8i-h3-orangepi-plus2e.dtb + sun8i-h3-orangepi-plus2e.dtb \ + sun8i-h3-orangepi-zero-plus2.dtb dtb-$(CONFIG_MACH_SUN8I_R40) += \ sun8i-r40-bananapi-m2-ultra.dtb \ sun8i-v40-bananapi-m2-berry.dtb diff --git a/arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts b/arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts new file mode 100644 index 0000000000..f2f7b7a925 --- /dev/null +++ b/arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts @@ -0,0 +1,139 @@ +/* + * Copyright (C) 2017 Jagan Teki <jteki(a)openedev.com> + * Copyright (C) 2018 Diego Rondini <diego.rondini(a)kynetics.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "sun8i-h3.dtsi" + +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "OrangePi Zero Plus2 H3"; + compatible = "xunlong,orangepi-zero-plus2-h3", "allwinner,sun8i-h3"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */ + post-power-on-delay-ms = <200>; + }; +}; + +&de { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&mmc0 { + vmmc-supply = <&reg_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <&reg_vcc3v3>; + vqmmc-supply = <&reg_vcc3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&r_pio>; + interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */ + interrupt-names = "host-wake"; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <&reg_vcc3v3>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index a2adf89b5d..4a89bb0e7b 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -405,6 +405,11 @@ M: Jagan Teki <jagan(a)amarulasolutions.com> S: Maintained F: configs/orangepi_zero_plus2_defconfig +ORANGEPI ZERO PLUS 2 H3 BOARD +M: Diego Rondini <diego.rondini(a)kynetics.com> +S: Maintained +F: configs/orangepi_zero_plus2_h3_defconfig + ORANGEPI PC 2 BOARD M: Andre Przywara <andre.przywara(a)arm.com> S: Maintained diff --git a/configs/orangepi_zero_plus2_h3_defconfig b/configs/orangepi_zero_plus2_h3_defconfig new file mode 100644 index 0000000000..3000a97e73 --- /dev/null +++ b/configs/orangepi_zero_plus2_h3_defconfig @@ -0,0 +1,19 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL=y +CONFIG_MACH_SUN8I_H3=y +CONFIG_DRAM_CLK=672 +# CONFIG_DRAM_ODT_EN is not set +CONFIG_MMC0_CD_PIN="PH13" +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y +# CONFIG_CMD_FLASH is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-zero-plus2" +CONFIG_SUN8I_EMAC=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y +CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y -- 2.21.0

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[U-Boot] [PATCH 1/3] net: gmac_rockchip: Add support for rk3308
by David Wu 05 Dec '19

05 Dec '19

Add the glue code to allow the rk3308 variant of the Rockchip gmac to provide network functionality. Signed-off-by: David Wu <david.wu(a)rock-chips.com> --- drivers/net/gmac_rockchip.c | 65 +++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index d2c52b4c46..e152faf083 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -17,6 +17,7 @@ #include <asm/arch-rockchip/grf_px30.h> #include <asm/arch-rockchip/grf_rk322x.h> #include <asm/arch-rockchip/grf_rk3288.h> +#include <asm/arch-rk3308/grf_rk3308.h> #include <asm/arch-rockchip/grf_rk3328.h> #include <asm/arch-rockchip/grf_rk3368.h> #include <asm/arch-rockchip/grf_rk3399.h> @@ -173,6 +174,47 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv) return 0; } +static int rk3308_gmac_fix_mac_speed(struct dw_eth_dev *priv) +{ + struct rk3308_grf *grf; + struct clk clk_speed; + int speed, ret; + enum { + RK3308_GMAC_SPEED_SHIFT = 0x0, + RK3308_GMAC_SPEED_MASK = BIT(0), + RK3308_GMAC_SPEED_10M = 0, + RK3308_GMAC_SPEED_100M = BIT(0), + }; + + ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", + &clk_speed); + if (ret) + return ret; + + switch (priv->phydev->speed) { + case 10: + speed = RK3308_GMAC_SPEED_10M; + ret = clk_set_rate(&clk_speed, 2500000); + if (ret) + return ret; + break; + case 100: + speed = RK3308_GMAC_SPEED_100M; + ret = clk_set_rate(&clk_speed, 25000000); + if (ret) + return ret; + break; + default: + debug("Unknown phy speed: %d\n", priv->phydev->speed); + return -EINVAL; + } + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(&grf->mac_con0, RK3308_GMAC_SPEED_MASK, speed); + + return 0; +} + static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv) { struct rk3328_grf_regs *grf; @@ -377,6 +419,22 @@ static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT); } +static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) +{ + struct rk3308_grf *grf; + enum { + RK3308_GMAC_PHY_INTF_SEL_SHIFT = 2, + RK3308_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 2), + RK3308_GMAC_PHY_INTF_SEL_RMII = BIT(4), + }; + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + + rk_clrsetreg(&grf->mac_con0, + RK3308_GMAC_PHY_INTF_SEL_MASK, + RK3308_GMAC_PHY_INTF_SEL_RMII); +} + static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) { struct rk3328_grf_regs *grf; @@ -646,6 +704,11 @@ const struct rk_gmac_ops rk3288_gmac_ops = { .set_to_rgmii = rk3288_gmac_set_to_rgmii, }; +const struct rk_gmac_ops rk3308_gmac_ops = { + .fix_mac_speed = rk3308_gmac_fix_mac_speed, + .set_to_rmii = rk3308_gmac_set_to_rmii, +}; + const struct rk_gmac_ops rk3328_gmac_ops = { .fix_mac_speed = rk3328_gmac_fix_mac_speed, .set_to_rgmii = rk3328_gmac_set_to_rgmii, @@ -673,6 +736,8 @@ static const struct udevice_id rockchip_gmac_ids[] = { .data = (ulong)&rk3228_gmac_ops }, { .compatible = "rockchip,rk3288-gmac", .data = (ulong)&rk3288_gmac_ops }, + { .compatible = "rockchip,rk3308-mac", + .data = (ulong)&rk3308_gmac_ops }, { .compatible = "rockchip,rk3328-gmac", .data = (ulong)&rk3328_gmac_ops }, { .compatible = "rockchip,rk3368-gmac", -- 2.19.1

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[U-Boot] [PATCH v2] Prevented possible null dereference.
by Niv Shetrit 05 Dec '19

05 Dec '19

Signed-off-by: Niv Shetrit <niv.shetrit(a)altair-semi.com> --- common/cli_hush.c | 73 ++++++++++++++++++++++++----------------------- 1 file changed, 38 insertions(+), 35 deletions(-) diff --git a/common/cli_hush.c b/common/cli_hush.c index 8f86e4aa4a..c14302c3ad 100644 --- a/common/cli_hush.c +++ b/common/cli_hush.c @@ -3539,41 +3539,44 @@ static char *insert_var_value_sub(char *inp, int tag_subst) } inp = ++p; /* find the ending marker */ - p = strchr(inp, SPECIAL_VAR_SYMBOL); - *p = '\0'; - /* look up the value to substitute */ - if ((p1 = lookup_param(inp))) { - if (tag_subst) - len = res_str_len + strlen(p1) + 2; - else - len = res_str_len + strlen(p1); - res_str = xrealloc(res_str, (1 + len)); - if (tag_subst) { - /* - * copy the variable value to the result - * string - */ - strcpy((res_str + res_str_len + 1), p1); - - /* - * mark the replaced text to be accepted as - * is - */ - res_str[res_str_len] = SUBSTED_VAR_SYMBOL; - res_str[res_str_len + 1 + strlen(p1)] = - SUBSTED_VAR_SYMBOL; - } else - /* - * copy the variable value to the result - * string - */ - strcpy((res_str + res_str_len), p1); - - res_str_len = len; - } - *p = SPECIAL_VAR_SYMBOL; - inp = ++p; - done = 1; + p = strchr(inp, SPECIAL_VAR_SYMBOL) + if (p != NULL) { + *p = '\0'; + /* look up the value to substitute */ + p1 = lookup_param(inp) + if (p1 != NULL) { + if (tag_subst) + len = res_str_len + strlen(p1) + 2; + else + len = res_str_len + strlen(p1); + res_str = xrealloc(res_str, (1 + len)); + if (tag_subst) { + /* + * copy the variable value to the + * result string + */ + strcpy((res_str + res_str_len + 1), p1); + + /* + * mark the replaced text to be + * accepted as is + */ + res_str[res_str_len] = SUBSTED_VAR_SYMBOL; + res_str[res_str_len + 1 + strlen(p1)] = + SUBSTED_VAR_SYMBOL; + } else + /* + * copy the variable value to the result + * string + */ + strcpy((res_str + res_str_len), p1); + + res_str_len = len; + } + *p = SPECIAL_VAR_SYMBOL; + inp = ++p; + done = 1; + } } if (done) { res_str = xrealloc(res_str, (1 + res_str_len + strlen(inp))); -- 2.17.1

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[U-Boot] Load Debian/Fedora via EFI
by Michal Simek 05 Dec '19

05 Dec '19

Hi, I tried to boot latest debian and fedora rootfs via distro boot and getting errors. I have tried to run just one command and it is failing. ZynqMP> bootefi bootmgr ${fdtcontroladdr} BootOrder not defined EFI boot manager: Cannot load any image How to define BootOrder? Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs

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[U-Boot] [PATCH v2 0/8] am57xx: Implement Android 10 boot flow
by Sam Protsenko 05 Dec '19

05 Dec '19

Android 10 brings a lot of new requirements for bootloaders: [1]. This patch series attempts to implement such a boot process on BeagleBoard X15 platform. Some common code is added too, which can be reused later for other platforms. This patch series denends on next (still not merged) patches: 1. libavb: Update libavb to current AOSP master [2] 2. libavb: Fix build warnings after updating the lib [3] 3. cmd: avb: Support A/B slots [4] 4. cmd: avb: Fix requested partitions list [5] Changes in v2: - add the unit test for new functionality ('bootimg' command, dtb/dtbo fields in Android Boot Image) - add "bootimg set_addr" sub-command - provide mem mappings so that 'bootimg' command works in sandbox (needed for tests to work correctly) - rebase on top of most recent master - re-sync am57x defconfigs with "make savedefconfig" [1] https://source.android.com/devices/bootloader [2] https://patchwork.ozlabs.org/patch/1147825/ [3] https://patchwork.ozlabs.org/patch/1147826/ [4] https://patchwork.ozlabs.org/patch/1144646/ [5] https://patchwork.ozlabs.org/patch/1147731/ Sam Protsenko (8): image: android: Add functions for handling dtb field image: android: Add routine to get dtbo params cmd: bootimg: Add bootimg command test/py: android: Add test for bootimg configs: am57xx_evm: Enable Android commands env: ti: boot: Respect slot_suffix in AVB commands env: ti: boot: Boot Android with dynamic partitions arm: ti: boot: Use correct dtb and dtbo on Android boot cmd/Kconfig | 8 + cmd/Makefile | 1 + cmd/bootimg.c | 210 ++++++++++++++++ common/Makefile | 2 +- common/image-android.c | 276 +++++++++++++++++++++ configs/am57xx_evm_defconfig | 10 +- configs/am57xx_hs_evm_defconfig | 6 + configs/am57xx_hs_evm_usb_defconfig | 6 + configs/sandbox_defconfig | 1 + include/configs/ti_armv7_common.h | 7 + include/environment/ti/boot.h | 145 ++++++----- include/image.h | 6 + test/py/tests/test_android/test_bootimg.py | 157 ++++++++++++ 13 files changed, 767 insertions(+), 68 deletions(-) create mode 100644 cmd/bootimg.c create mode 100644 test/py/tests/test_android/test_bootimg.py -- 2.23.0

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[U-Boot] [PATCHv2 1/2] PCI: layerscape: Add Support for ls2088 PCIe EP mode
by Xiaowei Bao 05 Dec '19

05 Dec '19

From: Xiaowei Bao <xiaowei.bao(a)nxp.com> Signed-off-by: hongbo.wang <hongbo.wang(a)nxp.com> Signed-off-by: Minghuan Lian <Minghuan.Lian(a)nxp.com> Signed-off-by: Xiaowei Bao <xiaowei.bao(a)nxp.com> --- v2: - Add the NXP copyright and make the function readability. drivers/pci/pcie_layerscape.c | 117 +++++++++++++++++++++++++++-------------- drivers/pci/pcie_layerscape.h | 19 +++++-- 2 files changed, 91 insertions(+), 45 deletions(-) diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index db1375a..8f5ebda 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2017 NXP + * Copyright 2017, 2019 NXP * Copyright 2014-2015 Freescale Semiconductor, Inc. * Layerscape PCIe driver */ @@ -105,13 +105,14 @@ static void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type, } /* Use bar match mode and MEM type as default */ -static void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, int idx, - int bar, u64 phys) +static void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, int idx, + int bar, u64 phys) { dbi_writel(pcie, PCIE_ATU_REGION_INBOUND | idx, PCIE_ATU_VIEWPORT); dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_TARGET); dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_TARGET); - dbi_writel(pcie, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1); + dbi_writel(pcie, PCIE_ATU_TYPE_MEM | PCIE_CTRL1_FUNC_NUM(pf), + PCIE_ATU_CR1); dbi_writel(pcie, PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE | PCIE_ATU_BAR_NUM(bar), PCIE_ATU_CR2); } @@ -341,50 +342,61 @@ static void ls_pcie_setup_ctrl(struct ls_pcie *pcie) ls_pcie_disable_bars(pcie); } -static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie) +static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie, u32 pf) { - u64 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE; + pci_size_t atu_size = CONFIG_SYS_PCI_MEMORY_SIZE; + u64 phys = 0; + phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + pf * SZ_2M; + + phys = ALIGN(phys, PCIE_BAR0_SIZE); /* ATU 0 : INBOUND : map BAR0 */ - ls_pcie_atu_inbound_set(pcie, 0, 0, phys); + ls_pcie_atu_inbound_set(pcie, pf, 0 + pf * BAR_NUM, 0, phys); /* ATU 1 : INBOUND : map BAR1 */ - phys += PCIE_BAR1_SIZE; - ls_pcie_atu_inbound_set(pcie, 1, 1, phys); + phys = ALIGN(phys + PCIE_BAR0_SIZE, PCIE_BAR1_SIZE); + ls_pcie_atu_inbound_set(pcie, pf, 1 + pf * BAR_NUM, 1, phys); /* ATU 2 : INBOUND : map BAR2 */ - phys += PCIE_BAR2_SIZE; - ls_pcie_atu_inbound_set(pcie, 2, 2, phys); - /* ATU 3 : INBOUND : map BAR4 */ - phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR4_SIZE; - ls_pcie_atu_inbound_set(pcie, 3, 4, phys); + phys = ALIGN(phys + PCIE_BAR1_SIZE, PCIE_BAR2_SIZE); + ls_pcie_atu_inbound_set(pcie, pf, 2 + pf * BAR_NUM, 2, phys); + /* ATU 3 : INBOUND : map BAR2 */ + phys = ALIGN(phys + PCIE_BAR2_SIZE, PCIE_BAR2_SIZE); + ls_pcie_atu_inbound_set(pcie, pf, 3 + pf * BAR_NUM, 4, phys); /* ATU 0 : OUTBOUND : map MEM */ - ls_pcie_atu_outbound_set(pcie, 0, - PCIE_ATU_TYPE_MEM, - pcie->cfg_res.start, - 0, - CONFIG_SYS_PCI_MEMORY_SIZE); + ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0, + PCIE_ATU_TYPE_MEM, (u64)pcie->cfg_res.start, + 0, atu_size); + + /* ATU 1 : OUTBOUND : map MEM */ + ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1, + PCIE_ATU_TYPE_MEM, (u64)pcie->cfg_res.start + + atu_size, atu_size, atu_size); } /* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */ static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size) { + u32 mask; + /* The least inbound window is 4KiB */ - if (size < 4 * 1024) - return; + if (size < SZ_4K) + mask = 0; + else + mask = size - 1; switch (bar) { case 0: - writel(size - 1, bar_base + PCI_BASE_ADDRESS_0); + writel(mask, bar_base + PCI_BASE_ADDRESS_0); break; case 1: - writel(size - 1, bar_base + PCI_BASE_ADDRESS_1); + writel(mask, bar_base + PCI_BASE_ADDRESS_1); break; case 2: - writel(size - 1, bar_base + PCI_BASE_ADDRESS_2); + writel(mask, bar_base + PCI_BASE_ADDRESS_2); writel(0, bar_base + PCI_BASE_ADDRESS_3); break; case 4: - writel(size - 1, bar_base + PCI_BASE_ADDRESS_4); + writel(mask, bar_base + PCI_BASE_ADDRESS_4); writel(0, bar_base + PCI_BASE_ADDRESS_5); break; default: @@ -394,13 +406,28 @@ static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size) static void ls_pcie_ep_setup_bars(void *bar_base) { - /* BAR0 - 32bit - 4K configuration */ + /* BAR0 - 32bit - configuration */ + ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE); + /* BAR1 - 32bit - MSIX*/ + ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE); + /* BAR2 - 64bit - MEM descriptor */ + ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE); + /* BAR4 - 64bit - MEM*/ + ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE); +} + +static void ls_pcie_ep_setup_vf_bars(void *bar_base) +{ + /* VF BAR0 MASK register at offset 0x19c*/ + bar_base += PCIE_SRIOV_VFBAR0 - PCI_BASE_ADDRESS_0; + + /* VF-BAR0 - 32bit - configuration */ ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE); - /* BAR1 - 32bit - 8K MSIX*/ + /* VF-BAR1 - 32bit - MSIX*/ ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE); - /* BAR2 - 64bit - 4K MEM desciptor */ + /* VF-BAR2 - 64bit - MEM descriptor */ ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE); - /* BAR4 - 64bit - 1M MEM*/ + /* VF-BAR4 - 64bit - MEM*/ ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE); } @@ -412,25 +439,33 @@ static void ls_pcie_ep_enable_cfg(struct ls_pcie *pcie) static void ls_pcie_setup_ep(struct ls_pcie *pcie) { u32 sriov; + u32 pf, vf; + void *bar_base = NULL; sriov = readl(pcie->dbi + PCIE_SRIOV); if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV) { - int pf, vf; - + pcie->sriov_flag = 1; for (pf = 0; pf < PCIE_PF_NUM; pf++) { - for (vf = 0; vf <= PCIE_VF_NUM; vf++) { - ctrl_writel(pcie, PCIE_LCTRL0_VAL(pf, vf), - PCIE_PF_VF_CTRL); - - ls_pcie_ep_setup_bars(pcie->dbi); - ls_pcie_ep_setup_atu(pcie); + if (pcie->cfg2_flag) { + for (vf = 0; vf <= PCIE_VF_NUM; vf++) { + ctrl_writel(pcie, + PCIE_LCTRL0_VAL(pf, vf), + PCIE_PF_VF_CTRL); + } } + bar_base = pcie->dbi + + PCIE_MASK_OFFSET(pcie->cfg2_flag, pf); + ls_pcie_ep_setup_bars(bar_base); + ls_pcie_ep_setup_vf_bars(bar_base); + + ls_pcie_ep_setup_atu(pcie, pf); } - /* Disable CFG2 */ - ctrl_writel(pcie, 0, PCIE_PF_VF_CTRL); + + if (pcie->cfg2_flag) /* Disable CFG2 */ + ctrl_writel(pcie, 0, PCIE_PF_VF_CTRL); } else { ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE); - ls_pcie_ep_setup_atu(pcie); + ls_pcie_ep_setup_atu(pcie, 0); } ls_pcie_ep_enable_cfg(pcie); @@ -502,6 +537,7 @@ static int ls_pcie_probe(struct udevice *dev) * for LS2088A series SoCs */ svr = get_svr(); + pcie->cfg2_flag = 1; svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE; if (svr == SVR_LS2088A || svr == SVR_LS2084A || svr == SVR_LS2048A || svr == SVR_LS2044A || @@ -511,6 +547,7 @@ static int ls_pcie_probe(struct udevice *dev) LS2088A_PCIE_PHYS_SIZE * pcie->idx; pcie->cfg_res.end = pcie->cfg_res.start + cfg_size; pcie->ctrl = pcie->lut + 0x40000; + pcie->cfg2_flag = 0; } pcie->cfg0 = map_physmem(pcie->cfg_res.start, diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h index ddfbba6..eb910ba 100644 --- a/drivers/pci/pcie_layerscape.h +++ b/drivers/pci/pcie_layerscape.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017 NXP + * Copyright 2017, 2019 NXP * Copyright 2014-2015 Freescale Semiconductor, Inc. * Layerscape PCIe driver */ @@ -9,6 +9,7 @@ #define _PCIE_LAYERSCAPE_H_ #include <pci.h> #include <dm.h> +#include <linux/sizes.h> #ifndef CONFIG_SYS_PCI_MEMORY_BUS #define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE @@ -85,11 +86,17 @@ #define PCIE_PF_NUM 2 #define PCIE_VF_NUM 64 +#define BAR_NUM 4 -#define PCIE_BAR0_SIZE (4 * 1024) /* 4K */ -#define PCIE_BAR1_SIZE (8 * 1024) /* 8K for MSIX */ -#define PCIE_BAR2_SIZE (4 * 1024) /* 4K */ -#define PCIE_BAR4_SIZE (1 * 1024 * 1024) /* 1M */ +#define PCIE_BAR0_SIZE SZ_4K /* 4K */ +#define PCIE_BAR1_SIZE SZ_8K /* 8K for MSIX */ +#define PCIE_BAR2_SIZE SZ_4K /* 4K */ +#define PCIE_BAR4_SIZE SZ_1M /* 1M */ + +#define PCIE_SRIOV_VFBAR0 0x19C +#define PCIE_CTRL1_FUNC_NUM(pf) (pf << 20) + +#define PCIE_MASK_OFFSET(flag, pf) ((flag) ? 0 : (0x1000 + 0x20000 * (pf))) /* LUT registers */ #define PCIE_LUT_UDR(n) (0x800 + (n) * 8) @@ -144,6 +151,8 @@ struct ls_pcie { bool big_endian; bool enabled; int next_lut_index; + uint sriov_flag; + uint cfg2_flag; int mode; }; -- 1.7.1

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[U-Boot] [PATCH v6 0/3] End of the MTD makefile cleanup
by Miquel Raynal 05 Dec '19

05 Dec '19

As rightfully pointed by Jagan, I should have dropped the dependency of cmd/sf.c and cmd/nand.c on mtd_uboot.c in patch 24/26 of the "MTD defconfigs/Kconfigs/Makefiles heavy cleanup" v5 series. Instead of sending the 40 patches again, here are only the last three patches with: * patch 1 (24/26) being corrected as per Jagan's comment * patch 2 (25/26) is untouched * patch 3 (26/26) is almost untouched but I had to resolve a conflict due to patch 1. Thanks, Miquèl Miquel Raynal (3): cmd: nand/sf: isolate legacy code cmd: make MTD commands depend on MTD mtd: Makefile: deep cleanup Makefile | 5 -- cmd/Kconfig | 10 ++-- cmd/Makefile | 3 ++ cmd/legacy-mtd-utils.c | 99 +++++++++++++++++++++++++++++++++++++++ cmd/legacy-mtd-utils.h | 14 ++++++ cmd/nand.c | 2 + cmd/sf.c | 2 + drivers/Makefile | 7 +-- drivers/mtd/Makefile | 50 ++++++++++++++------ drivers/mtd/mtd_uboot.c | 94 ------------------------------------- drivers/mtd/nand/Makefile | 5 ++ include/linux/mtd/mtd.h | 6 --- 12 files changed, 169 insertions(+), 128 deletions(-) create mode 100644 cmd/legacy-mtd-utils.c create mode 100644 cmd/legacy-mtd-utils.h -- 2.20.1

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