November 2019 - U-Boot

[U-Boot] [PATCH 0/9] phy: atheros: cleanup and device tree bindings
by Michael Walle 09 Dec '19

09 Dec '19

This series cleans up the Atheros PHY AR803x PHY driver and adds a device tree binding for the most commonly used PHY settings like clock output. If you're a board maintainer you're getting this mail because you probably use an AR803x PHY on your board. Please have a look at your board specific code and see if you can use the device tree bindings instead. Let me know, if something is missing. Michael Walle (9): phy: atheros: introduce debug read and write functions phy: atheros: move delay config to common function phy: atheros: ar8035: remove extra delay config phy: atheros: ar8035: use phy_{read|write}_mmd() phy: atheros: don't overwrite debug register values phy: atheros: fix delay configuration phy: atheros: Add device tree bindings and config phy: atheros: ar8035: remove static clock config phy: atheros: consolidate {ar8031|ar8035}_config() doc/device-tree-bindings/net/phy/atheros.txt | 22 ++ drivers/net/phy/atheros.c | 262 +++++++++++++++---- 2 files changed, 240 insertions(+), 44 deletions(-) create mode 100644 doc/device-tree-bindings/net/phy/atheros.txt Cc: Joe Hershberger <joe.hershberger(a)ni.com> Cc: Fabio Estevam <fabio.estevam(a)nxp.com> Cc: Adam Ford <aford173(a)gmail.com> Cc: Otavio Salvador <otavio(a)ossystems.com.br> Cc: Ian Ray <ian.ray(a)ge.com> Cc: Jason Liu <jason.hui.liu(a)nxp.com> Cc: Ye Li <ye.li(a)nxp.com> Cc: Uri Mashiach <uri.mashiach(a)compulab.co.il> Cc: Nikita Kiryanov <nikita(a)compulab.co.il> Cc: Lukasz Majewski <lukma(a)denx.de> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Vanessa Maegima <vanessa.maegima(a)nxp.com> Cc: Eric Bénard <eric(a)eukrea.com> -- 2.20.1

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[U-Boot] amlogic a96 mini
by Belisko Marek 09 Dec '19

09 Dec '19

Hi, I'm trying to run mainline u-boot on amlogic a96mini device but before I try to flash it does anybody have an idea if it will work on mainline. As I have limited number of devices and I know that after flashing I can brick the board so would like to ask if anybody have experience with this device and running mainline. Thanks and BR, marek -- as simple and primitive as possible ------------------------------------------------- Marek Belisko - OPEN-NANDRA Freelance Developer Ruska Nova Ves 219 | Presov, 08005 Slovak Republic Tel: +421 915 052 184 skype: marekwhite twitter: #opennandra web: http://open-nandra.com

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[U-Boot] imx8m: fix rom version check to unbreak some B0 chips
by Patrick Wildt 09 Dec '19

09 Dec '19

Recently the version check was improved to be able to determine that we're running on SoC revision 2.1. A check for B0 was tightened so that it now must equal 0x20 instead of being bigger than 0x20. On some B0 chips the value returned is 0x1020 instead of 0x20. This means even though it's B0, the check will fail and code relying on the correct chip revision will make wrong decisions. There is no documentation of those bits, but it seems that NXP always uses a byte to encode the revision. Thus remove the upper bits to fix the regression. Signed-off-by: Patrick Wildt <patrick(a)blueri.se> diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 9a203e4736..4d42368057 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -216,6 +216,7 @@ u32 get_cpu_rev(void) readl((void __iomem *)ROM_VERSION_A0); if (rom_version != CHIP_REV_1_0) { rom_version = readl((void __iomem *)ROM_VERSION_B0); + rom_version &= 0xff; if (rom_version == CHIP_REV_2_0) reg = CHIP_REV_2_0; }

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[U-Boot] [PATCH v3 00/16] import x509/pkcs7 parsers from linux
by AKASHI Takahiro 09 Dec '19

09 Dec '19

# This patch set is a prerequisite for UEFI secure boot. # This patch set should be merged first prior to my rsa extension patch # due to some dependency. Asn1 parsers of x509 certificates and pkcs7 messages are required to implement image authentication and variable authentication as part of UEFI secure boot feature. As we discussed before in the thread[1], most people insisted that we should re-use corresponding source code from Linux repository for this purpose. Here is my attempt to import all the necessary files from Linux; Those will eventually be part of UEFI secure boot implementation, but I'd like to get early feedback from other peoples before submitting the whole patchset so that they will be better formatted for merging. My approach here is * files from the latest Linux * modify files as little as possible * mark/protect unavoidable changes with "#if(n)def __UBOOT__" so that future fixes/differences in Linux repository will easily be applied to U-Boot. Known issues: * checkpatch.pl Checkpatch.pl will complain with a bunch of warnings/errors but I intentionally left them unchanged for the sake of better maintainability I said above. -Takahiro Akashi [1] https://lists.denx.de/pipermail/u-boot/2019-April/366423.html Changes in v3 (Nov 13, 2019) * rebased to v2020.01-rc * improve function description of kmemdup() (patch#1) * remove test/lib/Kconfig (patch#16) * declare variables in unit test as static (patch#16) Changes in v2 (Oct 25, 2019) * revise commit messages, describing what files are modified or not. * move kmemdump() in ubifs.c to linux_compat.c for general use (patch#1) * add patch#2 * move date.c to lib/ for general use (patch#3) * implement mktime64() with rtc_mktime() (patch#4) * move asn1_compiler.c to tools/ (patch#7) * change CONFIG_BUILD_ASN1 to CONFIG_ASN1_COMPILER (patch#7) * add clean rule to asn1_compiler-generated files to clean targets (patch#8) * change CONFIG_ASN1 to CONFIG_ASN1_DECODER (patch#9) * add README for asn1 compiler/decoder (patch#10) * move build_oid_registry to scripts/ (patch#11) * shuffle an order of patches (patch#13,#14,#15) * add a new config CONFIG_RSA_PUBLIC_KEY_PARSER so that it can be * modify Kconfig dependency (patch#13,#14,#15) compiled in independently (patch#13) * add unit test (patch#16,#17) Changes in v1 (Oct 11, 2019) from RFC * change the kernel code base from v5.0 to v5.3 * add preparatory patches (#1, #2 and #3) * comment off x509_check_for_self_signed() which is not useful for UEFI secure boot (patch#9) * improve usages of "#if(n)def __UBOOT__* to minimize differences between U-Boot and linux kernel AKASHI Takahiro (16): linux_compat: move kmemdup() from ubifs.c to linux_compat.c rtc.h: add struct udevice declaration rtc: move date.c from drivers/rtc/ to lib/ lib: add mktime64() for linux compatibility include: kernel.h: include printk.h linux/time.h: include vsprintf.h cmd: add asn1_compiler Makefile: add build script for asn1 parsers lib: add asn1 decoder doc: add README for asn1 compiler and decoder lib: add oid registry utility lib: crypto: add public key utility lib: crypto: add rsa public key parser lib: crypto: add x509 parser lib: crypto: add pkcs7 message parser test: add asn1 unit test Makefile | 1 + cmd/Kconfig | 1 + doc/README.asn1 | 40 + drivers/rtc/Kconfig | 1 + drivers/rtc/Makefile | 1 - fs/ubifs/ubifs.c | 19 +- include/crypto/internal/rsa.h | 57 + include/crypto/pkcs7.h | 47 + include/crypto/public_key.h | 90 ++ include/keys/asymmetric-type.h | 88 ++ include/linux/asn1.h | 65 ++ include/linux/asn1_ber_bytecode.h | 89 ++ include/linux/asn1_decoder.h | 20 + include/linux/kernel.h | 2 +- include/linux/oid_registry.h | 117 +++ include/linux/time.h | 11 + include/rtc.h | 2 + lib/Kconfig | 17 + lib/Makefile | 20 + lib/asn1_decoder.c | 527 ++++++++++ lib/crypto/Kconfig | 52 + lib/crypto/Makefile | 49 + lib/crypto/asymmetric_type.c | 668 ++++++++++++ lib/crypto/pkcs7.asn1 | 135 +++ lib/crypto/pkcs7_parser.c | 693 +++++++++++++ lib/crypto/pkcs7_parser.h | 65 ++ lib/crypto/public_key.c | 376 +++++++ lib/crypto/rsa_helper.c | 198 ++++ lib/crypto/rsapubkey.asn1 | 4 + lib/crypto/x509.asn1 | 60 ++ lib/crypto/x509_akid.asn1 | 35 + lib/crypto/x509_cert_parser.c | 697 +++++++++++++ lib/crypto/x509_parser.h | 57 + lib/crypto/x509_public_key.c | 292 ++++++ {drivers/rtc => lib}/date.c | 23 +- lib/linux_compat.c | 19 + lib/oid_registry.c | 179 ++++ scripts/Makefile.build | 4 +- scripts/build_OID_registry | 203 ++++ test/Kconfig | 18 +- test/lib/Makefile | 1 + test/lib/asn1.c | 392 +++++++ tools/Makefile | 3 + tools/asn1_compiler.c | 1611 +++++++++++++++++++++++++++++ 44 files changed, 7024 insertions(+), 25 deletions(-) create mode 100644 doc/README.asn1 create mode 100644 include/crypto/internal/rsa.h create mode 100644 include/crypto/pkcs7.h create mode 100644 include/crypto/public_key.h create mode 100644 include/keys/asymmetric-type.h create mode 100644 include/linux/asn1.h create mode 100644 include/linux/asn1_ber_bytecode.h create mode 100644 include/linux/asn1_decoder.h create mode 100644 include/linux/oid_registry.h create mode 100644 lib/asn1_decoder.c create mode 100644 lib/crypto/Kconfig create mode 100644 lib/crypto/Makefile create mode 100644 lib/crypto/asymmetric_type.c create mode 100644 lib/crypto/pkcs7.asn1 create mode 100644 lib/crypto/pkcs7_parser.c create mode 100644 lib/crypto/pkcs7_parser.h create mode 100644 lib/crypto/public_key.c create mode 100644 lib/crypto/rsa_helper.c create mode 100644 lib/crypto/rsapubkey.asn1 create mode 100644 lib/crypto/x509.asn1 create mode 100644 lib/crypto/x509_akid.asn1 create mode 100644 lib/crypto/x509_cert_parser.c create mode 100644 lib/crypto/x509_parser.h create mode 100644 lib/crypto/x509_public_key.c rename {drivers/rtc => lib}/date.c (81%) create mode 100644 lib/oid_registry.c create mode 100755 scripts/build_OID_registry create mode 100644 test/lib/asn1.c create mode 100644 tools/asn1_compiler.c -- 2.21.0

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[U-Boot] [PATCH v3 0/6] cmd: remove NET and CMD_NET dependency for CMD_PXE
by Patrice Chotard 06 Dec '19

06 Dec '19

It allows to use sysboot command on board which have no NET support. Currently, sysboot command can't be used if CMD_NET and NET flags are not set, while sysboot allows to load extlinux.conf file from local filesystem, so it doesn't need to depend of CMD_NET and NET flags. - Move from_env() from pxe.c to nvedit.c. - As sysboot and pxe commands are sharing piece of code, put this common code into a new file pxe_utils.c. - Extract sysboot command's code outside pxe.c and create a new sysboot.c file. - Fix some checkpatch issues. Patrice Chotard (6): cmd: Migrate from_env() from pxe.c to nvedit.c cmd: Prepare sysboot command independence cmd: sysboot: Create a sysboot command dedicated file cmd: pxe_utils: Fix checkpatch WARNING/CHECK cmd: sysboot: Fix checkpatch WARNING/CHECK cmd: pxe: Fix checkpatch WARNING/CHECK Kconfig | 1 + cmd/Kconfig | 6 + cmd/Makefile | 3 +- cmd/nvedit.c | 17 + cmd/pxe.c | 1730 ++--------------------------------------------- cmd/pxe_utils.c | 1413 ++++++++++++++++++++++++++++++++++++++ cmd/pxe_utils.h | 90 +++ cmd/sysboot.c | 134 ++++ include/env.h | 10 + 9 files changed, 1726 insertions(+), 1678 deletions(-) create mode 100644 cmd/pxe_utils.c create mode 100644 cmd/pxe_utils.h create mode 100644 cmd/sysboot.c -- 2.17.1

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[U-Boot] Maximum size of u-boot.imx for TBS2910 board
by Heinrich Schuchardt 06 Dec '19

06 Dec '19

Hello Soeren, when trying to add support for function key support in the USB keyboard driver u-boot.imx for the TBS2910 surpassed the maximum size for u-boot.imx. https://travis-ci.org/marex/u-boot-usb/builds/614059004 Do you remember why on the TBS2910 board this size is limited to 0x5fc00? Other i.MX6 boards like the Wandboard allow a much larger u-boot.imx. The limit is defined here: include/configs/tbs2910.h:80: #define CONFIG_BOARD_SIZE_LIMIT 392192 /* (CONFIG_ENV_OFFSET - 1024) */ Could the value CONFIG_ENV_OFFSET=0x60000 be enlarged? Many i.MX6 defconfigs use CONFIG_ENV_OFFSET=0xC0000. Best regards Heinrich

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[U-Boot] [PATCH] clk: imx: imx8mm: Fix the first root clock in imx8mm_ahb_sels[]
by Schrempf Frieder 06 Dec '19

06 Dec '19

From: Frieder Schrempf <frieder.schrempf(a)kontron.de> The 24MHz oscillator clock is referenced by "clock-osc-24m" and not "osc_24m". Signed-off-by: Frieder Schrempf <frieder.schrempf(a)kontron.de> --- drivers/clk/imx/clk-imx8mm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 091b092bbb..a05dac7c7a 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -74,7 +74,7 @@ static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", }; static const char *imx8mm_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", }; -static const char *imx8mm_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m", +static const char *imx8mm_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", }; static const char *imx8mm_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m", -- 2.17.1

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[U-Boot] [PATCH v5 000/101] x86: Add initial support for apollolake
by Simon Glass 06 Dec '19

06 Dec '19

Apollo Lake is an Intel SoC generation aimed at relatively low-end embedded systems. It was released in 2016 but has become more popular recently with some embedded boards using it. This series adds support for Apollo Lake. As an example it adds an implementation of chromebook_coral (a large range of Chromebooks released in 2017). The series provides enough support to boot to a prompt. with LCD display, storage, USB, EC and keyboard. Since this is the first time U-Boot has used FSP2 there is quite a bit of refactoring needed. This series is available at u-boot-dm/coral-working Changes in v5: - Add ACPI base address and size - Add L2 cache flush function - Add L2 cache flush functoin - Add a new patch to move qemu CPU fixup function into its own file - Add a way to obtain the port ID for a device - Add function to obtain ACPI gpio number - Add gpio-controller to GPIO nodes - Allocate the FSP-S data instead of using the stack - Change SPL as well - Comment out GPIOs in the fsp_s node since we don't use them yet - Correct CPU ACPI IDs - Correct build error in chromebook_samus_tpl - Drop SAFETY_MARGIN - Enable SMP - Fix FST typo - Fix build errors on some PowerPC boards - Group U-Boot and device tree into a section - Rename APOLLOLAKE_USB2_PORT_MAX - Use a define for ACPI base address Changes in v4: - Add a LOG_CATEGORY for silicon init - Add a binding file - Add a comment about the speed logic in __dw_i2c_set_bus_speed() - Add a comment for enable_bios_reset_cpl() - Add a comment in the commit message about why has_max_speed is added - Add a patch to explain of-platdata and header files - Add an extra comment to apl_uart_init() - Add comments about MRC-cache records being the same size - Add comments for exported functions - Add comments to functions - Add more documentation for pci_ofplat_get_devfn() - Add new patch to allow designware I2C driver to work in SPL - Add new patch to drop static data in designware i2c driver - Add new patch to make mrccache_update() static - Add new patch to move early-timer init later - Add support for updating power state - Add u-boot,skip-auto-config-until-reloc property to PCI - Adjust - Adjust condition for binding children - Adjust the comment for struct dw_i2c_speed_config - Allow pinctrl nodes to have subnodes (i.e. GPIO nodes) - Avoid needing to know internals of pinctrl in this driver - Change apollolake to apl - Change the behaviour to be a device-tree option - Detect zero mmio address - Disable SPL_DM_GPIO on omap35_logic to avoid a build error - Drop 'if (0)' call to deep_magic_nexgen_probe() and use #ifndef instead - Drop GPIO_NUM_PAD_CFG_REGS - Drop TCO_BASE_ADDRESS - Drop change to message about a missing uclass - Drop duplicate VBT file CONFIG - Drop duplicate commit 'Create a new sandbox_pci_read_bar() function' - Drop empty operations struct since p2sb does not need it - Drop incorrect coreboot reference from header file - Drop itss uclass change in Makefile (now in previous patch) - Drop itss uclass in Makefile - Drop pmic_pm8916 driver name and use a sandbox name instead - Drop sandbox defconfig change now that p2sb change is correct - Drop the whole interrupt file for TPL - Drop unrelated change metioned by Heiko - Drop unwanted debug printf("bad\n") - Enable HAVE_VBT for FSP2 also - Enable HAVE_X86_FIT - Enable INTEL_GPIO - Enable IRQ for sandbox64 too to avoid build error - Enable option for slimbootloader, coreboot, efi - Expand commit message to better explain the need to checksum functions - Explain the 'twisty headers' comment - Explain why FSP-M cannot be shown - Fix 'enabled' typo - Fix 'what' typo - Fix FSP_M reference to refer to FSP_S in commit message - Fix Makefile copyright message - Fix alpha order in Kconfig - Fix comment for exec_sync_hwseq_xfer() - Fix comment on fsp_silicon_init() - Fix incorrect mask check in pmc_gpe_init() - Fix indentation nit - Fix up license header - Fix various code-style problems - Mention that the return value is pci_dev_t - Move code to pinctrl driver - Move this to intel_common - Name this P-Unit instead of power unit, in the commit message - New GPIO driver binding - One last desperate attempt to try to explain the purpose of this commit - Rename arch_fsp_s_preinit() to arch_fsps_preinit() - Rename get_coreboot_fsp() and add comments - Rename new file to designware_i2c_pci.c - Rename option to HAVE_SYS_TEXT_BASE - Rename pci_x86_ofplat_get_devfn() to pci_ofplat_get_devfn() - Reverse the sense of the CONFIG option - Set up LPC pads early - Split out GPIO code from the pinctrl driver - Split out into a separate patch - Split out mmio changes into a separate patch - Switch over to use pinctrl for pad init/config - Tidy up header guards - Tidy up mixed case in FSP code - Tidy up the header file a little - Update SPI flash protection only in SPL - Update commit message to indicate that CPU-identity bug is fixed - Update documentation with more detailed memory map - Update the commit message to be clearer, fix 'correct' typo - Update the message to mention the preprocessed file, not un-preprocessed - Use 'Apollo Lake' - Use BIT() macro a bit more - Use BIT() macro bit more - Use CONFIG_INTEL_CAR_CQOS to control car2.S inclusion - Use car_init_ret to return - Use existing VBT Kconfig option - Use hex for size values also - Use hyphen for device-tree properties - Use lower-case pinctrl in arch_cpu_init_dm() - Use pci_ofplat_get_devfn() - Use post_code() calls consistent with car.S - Use priv->pch instead of dev->parent - Use tabs instead of spaces - Use the new pci_ofplat_get_devfn() function - apollolake -> Apollo Lake - use GENMASK() for VTBAR_MASK Changes in v3: - Ad FSP-S support - Add CONFIG_TPL_X86_ASSUME_CPUID to reduce code size - Add Chrome OS EC support - Add FSP-S and VBT also - Add MMC, video, USB configs - Add SPL condition to the option - Add VBT signature - Add a driver for APL SPI for TPL (using of-platdata) - Add a proper SPI node and make the SPI flash node a child - Add a proper implementation of fsp_notify - Add a weak function to avoid errors on other platforms - Add an APL_SPI_FLASH_BOOT option to enable non-mmap boot - Add an extra size parameter to the find_next_mrc_cache() function - Add an fsp: tag - Add bootstage support - Add bootstage timing for memory-mapped reads - Add bootstage timing for reading vbt - Add fsp_locate_fsp to locate an fsp component - Add fspm_done() hook - Add fspm_done() hook to handle FSP-S wierdness (it breaks SPI flash) - Add help to CONFIG_FIT and don't make it 'default y' - Add more documentation - Add snapshot/restore for IRQs - Add spi alias in device tree - Add structures for FSP-S also - Add support for FSP-S component and VBT - Add support for of-platdata for TPL - Add the missing header file - Add two more defines for the CPU driver - Add two more operations to IRQ - Add various minor tidy-ups - Adjust fast_spi_cache_bios_region() to avoid using SPI driver - Change Fast-SPI driver into a helper file used by ICH SPI - Change the sandbox test from ITSS to IRQ - Convert code to use hex increased of decimal - Disable the bootcommand since it does nothing useful on coral - Don't allow BOOT_FROM_FAST_SPI_FLASH with FSP-S - Don't enable SPI flash in TPL by default - Don't imply SPI flash either - Don't include write() and erase() in TPL - Drop 'a4' comment for register offset - Drop CONFIG_SPL_NET_SUPPORT - Drop VBT as we already have it elsewhere - Drop calls to x86_cpu_init_f(), x86_cpu_reinit_f() - Drop dead code - Drop patch '86: timer: Reduce timer code size in TPL on Intel CPUs' - Drop patch 'dm: core: Don't include ofnode functions with of-platdata' - Drop patch 'spi: sandbox: Add a test driver for sandbox SPI flash' - Drop patch 'spl: Allow SPL/TPL to use of-platdata without libfdt' - Drop patch 'x86: apollolake: Add definitions for the Intel Fast SPI interface' - Drop patch 'x86: timer: Set up the timer in timer_early_get_count()' - Drop struct fsp_usp_header as it is now in the API file - Drop unnecessary #else part of CONFIG_HAVE_MICROCODE - Drop unneeded Kconfig file - Drop unused code in lpc_configure_pads() - Enable video and USB3 - Expand comments for BOOT_FROM_FAST_SPI_FLASH - Fix build error when debug UART is disabled - Fix build errors in sandbox_spl, etc - Fix mixed case in GPIO defines - Fix the incorrect value of CPU_ADDR_BITS - Fix value of LPC_BC_LE - Init the p2sb before the northbridge since the latter so it can use GPIOs - Merge in patch "x86: Add support for booting from Fast SPI" - Move an additional error handling fix from a future patch - Move line related to variable-cache into the next patch - Move location of fast_spi.h header file - Move mtrr_add_request() call into this patch - Move mtrr_add_request() call to next patch - Move pad programming into the hostbridge to reduce TPL device-tree size - Move the function to a common file instead of duplicating it - Move the mrccache_get_region() change into this patch - Move write_pirq_routing_table() to avoid 64-bit build error - Only supress the 'MAC address from ROM' warning on sandbox - Reduce amount of early-pad data in TPL - Rename X86_HAS_FIT to HAVE_X86_FIT - Rename power-mgr uclass to acpi-pmc - Reorder file so that write() and erase() are together - Rework how pads configuration is defined in TPL and SPL - Rewrite commit message - Set boot_loader_tolum_size to 0 - Set the environment variables at runtime to avoid other warnings - Shorten log_msg_ret() calls since the function name is always printed - Simplify types for fsp_locate_fsp() - Support TPL without CONFIG_TPL_SPI_SUPPORT - Support TPL without CONFIG_TPL_SPI_SUPPORT (reduces code size) - Support bootstage timing - Switch mmap to use SPI instead of SPI flash - Tidy up Makefile rules to reduce duplication - Tidy up the pad settings in the device tree - Update commit message to explain why HAVE_FIT woudl be confusing - Update device type to pci_dev_t - Update example error message to better show the intended purpose - Update mrccache livetree patch to just convert to livetree - Update the 'fsp' command for FSP2, instead of disabling it - Use a macro for is-power-of-two - Use a zero-based tsc timer - Use pci_get_devfn() - Use the IRQ uclass instead of ITSS - Use the IRQ uclass instead of creating a new ITSS uclass - Use the LPSS code from a separate file Changes in v2: - Change 'queensbay' to 'baytrail' in help - Drop probe() function - Fix 'proides' typo - Fix the Kconfig condition to avoid build errors on snow - Implement set_spi_protect() - Use SPI mmap() instead of SPI flash Simon Glass (101): binman: Add a library to access binman entries dm: gpio: Allow control of GPIO uclass in SPL dm: core: Fix offset_to_ofnode() with invalid offset dm: pci: Allow delaying auto-config until after relocation dm: pci: Move pci_get_devfn() into a common file net: Move the checksum functions to lib/ i2c: designware: Tidy up PCI support i2c: designware: Avoid using static data i2c: designware: Support use in SPL x86: spi: Add helper functions for Intel Fast SPI fdt: Show the preprocessed .dts file on error board_r: Move early-timer init later RFC: sandbox: net: Suppress the MAC-address warnings Revert "RFC: sandbox: net: Suppress the MAC-address warnings" x86: timer: use a timer base of 0 x86: timer: Reduce timer code size in TPL on Intel CPUs x86: Drop unnecessary cpu code for TPL x86: Drop unnecessary interrupt code for TPL x86: power: Add an ACPI PMC uclass x86: sandbox: Add a PMC emulator and test x86: power: Add a 'pmc' command pci: Add support for p2sb uclass sandbox: Disable mmio by default in tests sandbox: Add PCI driver and test for p2sb x86: Move UCLASS_IRQ into a separate file sandbox: Add a test for IRQ x86: Define the SPL image start x86: Reduce mrccache record alignment size x86: Correct mrccache find_next_mrc_cache() calculation x86: Adjust mrccache_get_region() to use livetree x86: Adjust mrccache_get_region() to support get_mmap() x86: Add a new global_data member for the cache record x86: Tidy up error handling in mrccache_save() x86: Update mrccache to support multiple caches x86: Add mrccache support for a 'variable' cache x86: Don't export mrccache_update() x86: Move fsp_prepare_mrc_cache() to fsp1 directory x86: Set the DRAM banks to reflect real location x86: Set up the MTRR for SDRAM x86: Don't imply libfdt or SPI flash in TPL x86: Allow removal of standard PCH drivers x86: Allow interrupt to happen once x86: fsp: Make graphics support common to FSP1/2 x86: fsp: Correct wrong header inlude in fsp_support.c x86: fsp: Add FSP2 base support x86: fsp: Set up an MTRR for the graphics frame buffer x86: fsp: Add a new arch_fsp_init_r() hook x86: fsp: Allow remembering the location of FSP-S x86: fsp: Make the notify API call common x86: Don't include the BIOS emulator in TPL x86: Add an option to include a FIT x86: Add support for newer CAR schemes x86: Disable microcode section for FSP2 x86: Update the fsp command for FSP2 x86: Update .dtsi file for FSP2 x86: Add an option to control the position of U-Boot x86: Add an option to control the position of SPL x86: Add an fdtmap and image-header x86: Don't repeat microcode in U-Boot if not needed x86: Separate out U-Boot and device tree in ROM image x86: Make MSR_PKG_POWER_SKU common spi: Correct operations check in dm_spi_xfer() x86: spi: Don't enable SPI_FLASH_BAR by default spi: ich: Move init function just above probe() spi: ich: Move the protection/lockdown code into a function spi: ich: Convert to livetree spi: ich: Fix header order spi: ich: Various small tidy-ups spi: ich: Add mmio_base to struct ich_spi_platdata dm: doc: Add a note about of-platdata and header files spi: ich: Correct max-size bug in ich_spi_adjust_size() spi: ich: Support of-platdata for fast-spi spi: ich: Support hardware sequencing spi: ich: Add support for get_mmap() method spi: ich: Add TPL support spi: ich: Add Apollo Lake support mtd: spi: Export spi_flash_std_probe() x86: Enable pinctrl in SPL and TPL x86: Add low-power subsystem (lpss) support x86: Add a generic Intel pinctrl driver x86: Add a generic Intel GPIO driver x86: Move qemu CPU fixup function into its own file x86: apl: Add basic IO addresses x86: apl: Add PMC driver x86: apl: Add UART driver x86: apl: Add pinctrl driver i2c: designware: Add Apollo Lake support x86: apl: Add systemagent driver x86: apl: Add hostbridge driver x86: apl: Add ITSS driver x86: apl: Add LPC driver x86: apl: Add PCH driver x86: apl: Add PUNIT driver x86: apl: Add SPL loaders x86: apl: Add a CPU driver x86: apl: Add SPL/TPL init x86: apl: Add P2SB driver x86: apl: Add Kconfig and Makefile x86: apl: Add FSP structures x86: apl: Add FSP support x86: Add chromebook_coral Kconfig | 9 +- arch/Kconfig | 9 +- arch/arm/include/asm/omap_gpio.h | 2 +- arch/arm/mach-at91/include/mach/at91sam9260.h | 2 +- arch/arm/mach-davinci/include/mach/gpio.h | 2 +- arch/arm/mach-omap2/am33xx/board.c | 4 +- arch/arm/mach-omap2/omap3/board.c | 2 +- arch/arm/mach-omap2/omap5/hwinit.c | 2 +- arch/sandbox/cpu/state.c | 1 + arch/sandbox/dts/sandbox.dtsi | 14 + arch/sandbox/dts/test.dts | 31 + arch/sandbox/include/asm/test.h | 2 + arch/x86/Kconfig | 93 +- arch/x86/cpu/Makefile | 4 +- arch/x86/cpu/apollolake/Kconfig | 87 ++ arch/x86/cpu/apollolake/Makefile | 27 + arch/x86/cpu/apollolake/cpu.c | 51 ++ arch/x86/cpu/apollolake/cpu_common.c | 17 + arch/x86/cpu/apollolake/cpu_spl.c | 274 ++++++ arch/x86/cpu/apollolake/fsp_m.c | 210 +++++ arch/x86/cpu/apollolake/fsp_s.c | 667 ++++++++++++++ arch/x86/cpu/apollolake/hostbridge.c | 179 ++++ arch/x86/cpu/apollolake/itss.c | 214 +++++ arch/x86/cpu/apollolake/lpc.c | 141 +++ arch/x86/cpu/apollolake/p2sb.c | 167 ++++ arch/x86/cpu/apollolake/pch.c | 36 + arch/x86/cpu/apollolake/pmc.c | 216 +++++ arch/x86/cpu/apollolake/punit.c | 121 +++ arch/x86/cpu/apollolake/spl.c | 197 +++++ arch/x86/cpu/apollolake/systemagent.c | 19 + arch/x86/cpu/apollolake/uart.c | 141 +++ arch/x86/cpu/broadwell/sdram.c | 8 +- arch/x86/cpu/coreboot/Kconfig | 1 + arch/x86/cpu/cpu.c | 4 + arch/x86/cpu/i386/Makefile | 2 + arch/x86/cpu/i386/cpu.c | 41 +- arch/x86/cpu/intel_common/Makefile | 10 + arch/x86/cpu/intel_common/car2.S | 448 ++++++++++ arch/x86/cpu/intel_common/car2_uninit.S | 87 ++ arch/x86/cpu/intel_common/fast_spi.c | 73 ++ arch/x86/cpu/intel_common/lpss.c | 44 + arch/x86/cpu/irq.c | 13 - arch/x86/cpu/ivybridge/sdram.c | 8 +- arch/x86/cpu/mp_init.c | 73 +- arch/x86/cpu/qfw_cpu.c | 75 ++ arch/x86/cpu/quark/dram.c | 8 +- arch/x86/cpu/slimbootloader/Kconfig | 1 + arch/x86/cpu/u-boot-spl.lds | 5 +- arch/x86/dts/Makefile | 1 + arch/x86/dts/chromebook_coral.dts | 831 ++++++++++++++++++ arch/x86/dts/u-boot.dtsi | 89 +- arch/x86/include/asm/arch-apollolake/cpu.h | 26 + .../asm/arch-apollolake/fsp/fsp_configs.h | 14 + .../asm/arch-apollolake/fsp/fsp_m_upd.h | 123 +++ .../asm/arch-apollolake/fsp/fsp_s_upd.h | 292 ++++++ .../include/asm/arch-apollolake/fsp/fsp_vpd.h | 11 + arch/x86/include/asm/arch-apollolake/gpio.h | 490 +++++++++++ arch/x86/include/asm/arch-apollolake/iomap.h | 29 + arch/x86/include/asm/arch-apollolake/itss.h | 43 + arch/x86/include/asm/arch-apollolake/lpc.h | 82 ++ arch/x86/include/asm/arch-apollolake/pch.h | 9 + arch/x86/include/asm/arch-apollolake/pm.h | 19 + .../include/asm/arch-apollolake/systemagent.h | 37 + arch/x86/include/asm/arch-apollolake/uart.h | 20 + arch/x86/include/asm/arch-broadwell/cpu.h | 1 - .../include/asm/arch-ivybridge/model_206ax.h | 1 - arch/x86/include/asm/fast_spi.h | 68 ++ arch/x86/include/asm/fsp/fsp_api.h | 24 + arch/x86/include/asm/fsp/fsp_support.h | 7 - arch/x86/include/asm/fsp1/fsp_api.h | 21 +- arch/x86/include/asm/fsp2/fsp_api.h | 63 ++ arch/x86/include/asm/fsp2/fsp_internal.h | 97 ++ arch/x86/include/asm/global_data.h | 25 +- arch/x86/include/asm/intel_pinctrl.h | 306 +++++++ arch/x86/include/asm/intel_pinctrl_defs.h | 386 ++++++++ arch/x86/include/asm/lpss.h | 36 + arch/x86/include/asm/mrccache.h | 29 +- arch/x86/include/asm/msr-index.h | 10 +- arch/x86/include/asm/processor.h | 12 +- arch/x86/include/asm/spl.h | 1 + arch/x86/lib/Makefile | 2 + arch/x86/lib/fsp/Makefile | 3 + arch/x86/lib/fsp/fsp_common.c | 20 - arch/x86/lib/fsp/fsp_dram.c | 35 +- arch/x86/lib/{fsp1 => fsp}/fsp_graphics.c | 6 +- arch/x86/lib/fsp/fsp_support.c | 2 +- arch/x86/lib/fsp1/Makefile | 1 - arch/x86/lib/fsp1/fsp_common.c | 20 + arch/x86/lib/fsp1/fsp_dram.c | 8 +- arch/x86/lib/fsp2/Makefile | 10 + arch/x86/lib/fsp2/fsp_common.c | 13 + arch/x86/lib/fsp2/fsp_dram.c | 77 ++ arch/x86/lib/fsp2/fsp_init.c | 174 ++++ arch/x86/lib/fsp2/fsp_meminit.c | 97 ++ arch/x86/lib/fsp2/fsp_silicon_init.c | 54 ++ arch/x86/lib/fsp2/fsp_support.c | 131 +++ arch/x86/lib/mrccache.c | 204 +++-- arch/x86/lib/pirq_routing.c | 10 + board/freescale/imx8qm_mek/imx8qm_mek.c | 2 +- board/freescale/imx8qxp_mek/imx8qxp_mek.c | 2 +- board/gateworks/gw_ventana/Kconfig | 3 + board/google/Kconfig | 15 + board/google/chromebook_coral/Kconfig | 43 + board/google/chromebook_coral/MAINTAINERS | 6 + board/google/chromebook_coral/Makefile | 5 + board/google/chromebook_coral/coral.c | 18 + board/toradex/apalis-imx8/apalis-imx8.c | 2 +- cmd/Kconfig | 8 + cmd/Makefile | 1 + cmd/pmc.c | 81 ++ cmd/x86/fsp.c | 65 +- common/board_r.c | 32 +- configs/chromebook_coral_defconfig | 102 +++ configs/chromebook_samus_tpl_defconfig | 3 + configs/omap35_logic_defconfig | 1 + configs/qemu-x86_64_defconfig | 1 + configs/sandbox64_defconfig | 3 + configs/sandbox_defconfig | 2 + configs/sandbox_flattree_defconfig | 4 + configs/sandbox_spl_defconfig | 4 + configs/tools-only_defconfig | 2 + doc/board/google/chromebook_coral.rst | 241 +++++ .../gpio/intel,apl-gpio.txt | 55 ++ doc/device-tree-bindings/pci/x86-pci.txt | 24 + .../pinctrl/intel,apl-pinctrl.txt | 39 + doc/driver-model/of-plat.rst | 6 + drivers/Makefile | 1 + drivers/core/util.c | 20 + drivers/gpio/Kconfig | 31 + drivers/gpio/Makefile | 5 +- drivers/gpio/at91_gpio.c | 6 +- drivers/gpio/atmel_pio4.c | 2 +- drivers/gpio/da8xx_gpio.c | 7 +- drivers/gpio/da8xx_gpio.h | 2 +- drivers/gpio/intel_gpio.c | 161 ++++ drivers/gpio/mxc_gpio.c | 4 +- drivers/gpio/mxs_gpio.c | 4 +- drivers/gpio/omap_gpio.c | 6 +- drivers/gpio/sunxi_gpio.c | 8 +- drivers/i2c/Makefile | 3 + drivers/i2c/designware_i2c.c | 106 +-- drivers/i2c/designware_i2c.h | 35 + drivers/i2c/designware_i2c_pci.c | 144 +++ drivers/i2c/i2c-uclass.c | 6 +- drivers/i2c/muxes/pca954x.c | 4 +- drivers/misc/Kconfig | 42 + drivers/misc/Makefile | 5 + drivers/misc/irq-uclass.c | 53 ++ drivers/misc/irq_sandbox.c | 55 ++ drivers/misc/p2sb-uclass.c | 216 +++++ drivers/misc/p2sb_emul.c | 272 ++++++ drivers/misc/p2sb_sandbox.c | 40 + drivers/misc/sandbox_adder.c | 60 ++ drivers/mmc/fsl_esdhc_imx.c | 13 +- drivers/mmc/omap_hsmmc.c | 2 +- drivers/mtd/spi/sf_probe.c | 2 +- drivers/net/designware.c | 10 +- drivers/net/designware.h | 4 +- drivers/net/fec_mxc.c | 6 +- drivers/net/fec_mxc.h | 2 +- drivers/net/mvneta.c | 4 +- drivers/net/mvpp2.c | 8 +- drivers/net/sun8i_emac.c | 12 +- drivers/pch/Kconfig | 18 + drivers/pch/Makefile | 4 +- drivers/pci/pci-aardvark.c | 4 +- drivers/pci/pci-uclass.c | 31 +- drivers/pci/pcie_dw_mvebu.c | 4 +- drivers/pinctrl/Kconfig | 23 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/intel/Kconfig | 24 + drivers/pinctrl/intel/Makefile | 6 + drivers/pinctrl/intel/pinctrl.c | 635 +++++++++++++ drivers/pinctrl/intel/pinctrl_apl.c | 192 ++++ drivers/power/Kconfig | 2 + drivers/power/acpi_pmc/Kconfig | 34 + drivers/power/acpi_pmc/Makefile | 6 + drivers/power/acpi_pmc/acpi-pmc-uclass.c | 244 +++++ drivers/power/acpi_pmc/pmc_emul.c | 246 ++++++ drivers/power/acpi_pmc/sandbox.c | 97 ++ drivers/spi/Kconfig | 1 - drivers/spi/atmel_spi.c | 10 +- drivers/spi/designware_spi.c | 4 +- drivers/spi/ich.c | 528 ++++++++--- drivers/spi/ich.h | 46 +- drivers/spi/spi-uclass.c | 5 +- drivers/timer/Kconfig | 23 + drivers/timer/tsc_timer.c | 10 +- drivers/tpm/tpm2_tis_spi.c | 2 +- include/binman.h | 45 + include/bootstage.h | 3 + include/config_uncmd_spl.h | 1 - include/configs/at91-sama5_common.h | 5 +- include/configs/chromebook_coral.h | 32 + include/configs/gw_ventana.h | 1 - include/configs/mx6ul_14x14_evk.h | 1 + include/dm/ofnode.h | 2 +- include/dm/pci.h | 43 + include/dm/uclass-id.h | 2 + include/init.h | 11 + include/irq.h | 88 ++ include/p2sb.h | 135 +++ include/pci.h | 21 +- include/power/acpi_pmc.h | 185 ++++ include/qfw.h | 8 + include/spi.h | 2 +- include/spi_flash.h | 12 + lib/Kconfig | 10 + lib/Makefile | 3 +- lib/binman.c | 48 + lib/efi/Kconfig | 1 + lib/net_utils.c | 48 + net/Makefile | 1 - net/checksum.c | 59 -- scripts/Makefile.lib | 4 +- scripts/Makefile.uncmd_spl | 1 - test/dm/Makefile | 3 + test/dm/irq.c | 32 + test/dm/p2sb.c | 28 + test/dm/pmc.c | 33 + 220 files changed, 12406 insertions(+), 705 deletions(-) create mode 100644 arch/x86/cpu/apollolake/Kconfig create mode 100644 arch/x86/cpu/apollolake/Makefile create mode 100644 arch/x86/cpu/apollolake/cpu.c create mode 100644 arch/x86/cpu/apollolake/cpu_common.c create mode 100644 arch/x86/cpu/apollolake/cpu_spl.c create mode 100644 arch/x86/cpu/apollolake/fsp_m.c create mode 100644 arch/x86/cpu/apollolake/fsp_s.c create mode 100644 arch/x86/cpu/apollolake/hostbridge.c create mode 100644 arch/x86/cpu/apollolake/itss.c create mode 100644 arch/x86/cpu/apollolake/lpc.c create mode 100644 arch/x86/cpu/apollolake/p2sb.c create mode 100644 arch/x86/cpu/apollolake/pch.c create mode 100644 arch/x86/cpu/apollolake/pmc.c create mode 100644 arch/x86/cpu/apollolake/punit.c create mode 100644 arch/x86/cpu/apollolake/spl.c create mode 100644 arch/x86/cpu/apollolake/systemagent.c create mode 100644 arch/x86/cpu/apollolake/uart.c create mode 100644 arch/x86/cpu/intel_common/car2.S create mode 100644 arch/x86/cpu/intel_common/car2_uninit.S create mode 100644 arch/x86/cpu/intel_common/fast_spi.c create mode 100644 arch/x86/cpu/intel_common/lpss.c create mode 100644 arch/x86/cpu/qfw_cpu.c create mode 100644 arch/x86/dts/chromebook_coral.dts create mode 100644 arch/x86/include/asm/arch-apollolake/cpu.h create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_configs.h create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_vpd.h create mode 100644 arch/x86/include/asm/arch-apollolake/gpio.h create mode 100644 arch/x86/include/asm/arch-apollolake/iomap.h create mode 100644 arch/x86/include/asm/arch-apollolake/itss.h create mode 100644 arch/x86/include/asm/arch-apollolake/lpc.h create mode 100644 arch/x86/include/asm/arch-apollolake/pch.h create mode 100644 arch/x86/include/asm/arch-apollolake/pm.h create mode 100644 arch/x86/include/asm/arch-apollolake/systemagent.h create mode 100644 arch/x86/include/asm/arch-apollolake/uart.h create mode 100644 arch/x86/include/asm/fast_spi.h create mode 100644 arch/x86/include/asm/fsp/fsp_api.h create mode 100644 arch/x86/include/asm/fsp2/fsp_api.h create mode 100644 arch/x86/include/asm/fsp2/fsp_internal.h create mode 100644 arch/x86/include/asm/intel_pinctrl.h create mode 100644 arch/x86/include/asm/intel_pinctrl_defs.h create mode 100644 arch/x86/include/asm/lpss.h rename arch/x86/lib/{fsp1 => fsp}/fsp_graphics.c (95%) create mode 100644 arch/x86/lib/fsp2/Makefile create mode 100644 arch/x86/lib/fsp2/fsp_common.c create mode 100644 arch/x86/lib/fsp2/fsp_dram.c create mode 100644 arch/x86/lib/fsp2/fsp_init.c create mode 100644 arch/x86/lib/fsp2/fsp_meminit.c create mode 100644 arch/x86/lib/fsp2/fsp_silicon_init.c create mode 100644 arch/x86/lib/fsp2/fsp_support.c create mode 100644 board/google/chromebook_coral/Kconfig create mode 100644 board/google/chromebook_coral/MAINTAINERS create mode 100644 board/google/chromebook_coral/Makefile create mode 100644 board/google/chromebook_coral/coral.c create mode 100644 cmd/pmc.c create mode 100644 configs/chromebook_coral_defconfig create mode 100644 doc/board/google/chromebook_coral.rst create mode 100644 doc/device-tree-bindings/gpio/intel,apl-gpio.txt create mode 100644 doc/device-tree-bindings/pci/x86-pci.txt create mode 100644 doc/device-tree-bindings/pinctrl/intel,apl-pinctrl.txt create mode 100644 drivers/gpio/intel_gpio.c create mode 100644 drivers/i2c/designware_i2c_pci.c create mode 100644 drivers/misc/irq-uclass.c create mode 100644 drivers/misc/irq_sandbox.c create mode 100644 drivers/misc/p2sb-uclass.c create mode 100644 drivers/misc/p2sb_emul.c create mode 100644 drivers/misc/p2sb_sandbox.c create mode 100644 drivers/misc/sandbox_adder.c create mode 100644 drivers/pinctrl/intel/Kconfig create mode 100644 drivers/pinctrl/intel/Makefile create mode 100644 drivers/pinctrl/intel/pinctrl.c create mode 100644 drivers/pinctrl/intel/pinctrl_apl.c create mode 100644 drivers/power/acpi_pmc/Kconfig create mode 100644 drivers/power/acpi_pmc/Makefile create mode 100644 drivers/power/acpi_pmc/acpi-pmc-uclass.c create mode 100644 drivers/power/acpi_pmc/pmc_emul.c create mode 100644 drivers/power/acpi_pmc/sandbox.c create mode 100644 include/binman.h create mode 100644 include/configs/chromebook_coral.h create mode 100644 include/dm/pci.h create mode 100644 include/irq.h create mode 100644 include/p2sb.h create mode 100644 include/power/acpi_pmc.h create mode 100644 lib/binman.c delete mode 100644 net/checksum.c create mode 100644 test/dm/irq.c create mode 100644 test/dm/p2sb.c create mode 100644 test/dm/pmc.c -- 2.24.0.432.g9d3f5f5b63-goog

3 195

[U-Boot] [PATCH] drivers: optee: rpmb: fix returning CID to TEE
by Jorge Ramirez-Ortiz 05 Dec '19

05 Dec '19

The mmc CID value is one of the input parameters used to provision the RPMB key. The trusted execution environment expects this value to be specified in big endian format. Before this fix, on little endian systems, the value returned by the linux kernel mmc driver differed from the one returned by u-boot. This meant that if linux provisioned the RPMB key, u-boot would not have access to the partition (and the other way around). Signed-off-by: Jorge Ramirez-Ortiz <jorge(a)foundries.io> --- drivers/tee/optee/rpmb.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/tee/optee/rpmb.c b/drivers/tee/optee/rpmb.c index 955155b3f8..cf1ce77e6e 100644 --- a/drivers/tee/optee/rpmb.c +++ b/drivers/tee/optee/rpmb.c @@ -98,6 +98,7 @@ static struct mmc *get_mmc(struct optee_private *priv, int dev_id) static u32 rpmb_get_dev_info(u16 dev_id, struct rpmb_dev_info *info) { struct mmc *mmc = find_mmc_device(dev_id); + int i; if (!mmc) return TEE_ERROR_ITEM_NOT_FOUND; @@ -105,7 +106,9 @@ static u32 rpmb_get_dev_info(u16 dev_id, struct rpmb_dev_info *info) if (!mmc->ext_csd) return TEE_ERROR_GENERIC; - memcpy(info->cid, mmc->cid, sizeof(info->cid)); + for (i = 0; i < ARRAY_SIZE(mmc->cid); i++) + ((u32 *) info->cid)[i] = cpu_to_be32(mmc->cid[i]); + info->rel_wr_sec_c = mmc->ext_csd[222]; info->rpmb_size_mult = mmc->ext_csd[168]; info->ret_code = RPMB_CMD_GET_DEV_INFO_RET_OK; -- 2.17.1

3 2

[U-Boot] [PATCH] test/py: test_fs: add tests for creating/deleting many files
by AKASHI Takahiro 05 Dec '19

05 Dec '19

# This is actually a resent patch of # [1] https://lists.denx.de/pipermail/u-boot/2019-May/369170.html Two test cases are added under test_fs_ext: test case 10: for root directory test case 11: for non-root directory Those will verify a behavior fixed by the commits related to root directory ("fs: fat: allocate a new cluster for root directory of fat32" and "fs: fat: flush a directory cluster properly"), and focus on handling long-file-name directory entries under a directory. Signed-off-by: AKASHI Takahiro <takahiro.akashi(a)linaro.org> --- test/py/tests/test_fs/test_ext.py | 84 +++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/test/py/tests/test_fs/test_ext.py b/test/py/tests/test_fs/test_ext.py index 2c47738b8df2..6b7fc4870177 100644 --- a/test/py/tests/test_fs/test_ext.py +++ b/test/py/tests/test_fs/test_ext.py @@ -233,3 +233,87 @@ class TestFsExt(object): % (fs_type, ADDR, MIN_FILE)]) assert('Unable to write "/dir1' in ''.join(output)) assert_fs_integrity(fs_type, fs_img) + + def test_fs_ext10(self, u_boot_console, fs_obj_ext): + """ + 'Test Case 10 - create/delete as many directories under root directory + as amount of directory entries goes beyond one cluster size)' + """ + fs_type,fs_img,md5val = fs_obj_ext + with u_boot_console.log.section('Test Case 10 - create/delete (many)'): + # Test Case 10a - Create many files + # Please note that the size of directory entry is 32 bytes. + # So one typical cluster may holds 64 (2048/32) entries. + output = u_boot_console.run_command( + 'host bind 0 %s' % fs_img) + + for i in range(0, 66): + output = u_boot_console.run_command( + '%swrite host 0:0 %x /FILE0123456789_%02x 100' + % (fs_type, ADDR, i)) + output = u_boot_console.run_command('%sls host 0:0 /' % fs_type) + assert('FILE0123456789_00' in output) + assert('FILE0123456789_41' in output) + + # Test Case 10b - Delete many files + for i in range(0, 66): + output = u_boot_console.run_command( + '%srm host 0:0 /FILE0123456789_%02x' + % (fs_type, i)) + output = u_boot_console.run_command('%sls host 0:0 /' % fs_type) + assert(not 'FILE0123456789_00' in output) + assert(not 'FILE0123456789_41' in output) + + # Test Case 10c - Create many files again + # Please note no.64 and 65 are intentionally re-created + for i in range(64, 128): + output = u_boot_console.run_command( + '%swrite host 0:0 %x /FILE0123456789_%02x 100' + % (fs_type, ADDR, i)) + output = u_boot_console.run_command('%sls host 0:0 /' % fs_type) + assert('FILE0123456789_40' in output) + assert('FILE0123456789_79' in output) + + assert_fs_integrity(fs_type, fs_img) + + def test_fs_ext11(self, u_boot_console, fs_obj_ext): + """ + 'Test Case 11 - create/delete as many directories under non-root + directory as amount of directory entries goes beyond one cluster size)' + """ + fs_type,fs_img,md5val = fs_obj_ext + with u_boot_console.log.section('Test Case 11 - create/delete (many)'): + # Test Case 11a - Create many files + # Please note that the size of directory entry is 32 bytes. + # So one typical cluster may holds 64 (2048/32) entries. + output = u_boot_console.run_command( + 'host bind 0 %s' % fs_img) + + for i in range(0, 66): + output = u_boot_console.run_command( + '%swrite host 0:0 %x /dir1/FILE0123456789_%02x 100' + % (fs_type, ADDR, i)) + output = u_boot_console.run_command('%sls host 0:0 /dir1' % fs_type) + assert('FILE0123456789_00' in output) + assert('FILE0123456789_41' in output) + + # Test Case 11b - Delete many files + for i in range(0, 66): + output = u_boot_console.run_command( + '%srm host 0:0 /dir1/FILE0123456789_%02x' + % (fs_type, i)) + output = u_boot_console.run_command('%sls host 0:0 /dir1' % fs_type) + assert(not 'FILE0123456789_00' in output) + assert(not 'FILE0123456789_41' in output) + + # Test Case 11c - Create many files again + # Please note no.64 and 65 are intentionally re-created + for i in range(64, 128): + output = u_boot_console.run_command( + '%swrite host 0:0 %x /dir1/FILE0123456789_%02x 100' + % (fs_type, ADDR, i)) + output = u_boot_console.run_command('%sls host 0:0 /dir1' % fs_type) + assert('FILE0123456789_40' in output) + assert('FILE0123456789_79' in output) + + assert_fs_integrity(fs_type, fs_img) -- 2.24.0

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