January 2019 - U-Boot

[U-Boot] [PATCH] mtd: nand: let the raw NAND devices be compiled upon selection
by Miquel Raynal 08 Apr '19

08 Apr '19

Today way is to rely on CMD_NAND to be selected and from the root Makefile compile what is in drivers/mtd/nand/raw. While this will work most of the time with decent configurations, it is better to also compile this subsystem upon simple request in the configuration. Otherwise, a user not selecting CMD_NAND but selecting NAND and any of the controller drivers will not see their build. Fix this weird situation by adding a single line in the nand/ directory Kconfig file. Signed-off-by: Miquel Raynal <miquel.raynal(a)bootlin.com> --- drivers/mtd/nand/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index a358bc680e..2c33447995 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -2,4 +2,5 @@ nandcore-objs := core.o bbt.o obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o +obj-$(CONFIG_NAND) += raw/ obj-$(CONFIG_MTD_SPI_NAND) += spi/ -- 2.17.1

3 7

[U-Boot] [PATCH 0/7] android: Implement A/B boot process
by Ruslan Trofymenko 08 Apr '19

08 Apr '19

This patch series adds support for Android A/B boot process [1]. Main steps of A/B boot process are: - A/B metadata integrity check - looking for the current slot (where the system should be booting from) - getting the name of the current boot partition (boot_a or boot_b) and loading the corresponding Android boot image - getting the name of the current system partition (system_a or system_b) and passing of its full name via kernel command line (like 'root=/dev/mmcblk1p11') - passing current slot via kernel command line (like 'androidboot.slot_suffix=_a') and via A/B metadata (e.g. via misc partition) - A/B metadata processing: setting the boot success flag for current slot, handling the retry counter, etc A/B metadata is organized according to Android reference [2] and stored on 'misc' partition. On the first A/B boot process, when 'misc' partition doesn't contain required data, default A/B metadata will be created and stored in 'misc' partition. In the end of the Android boot, 'update_verifier' and 'update_engine' services are processing the A/B metadata through the Boot Control HAL. To confirm the boot was successful using current slot, "boot success" flag must be set on Android side. To enable Android A/B support in U-Boot: 1. Set the following config options: CONFIG_ANDROID_AB=y CONFIG_CMD_ANDROID_AB_SELECT=y 2. Change the disk layout so that it has sloted boot partitions. E.g. instead of 'boot' and 'system' partitions there should be 'boot_a', 'boot_b', 'system_a' and 'system_b' partitions. To be able to actually test this patch series, the A/B features must be implemented and enabled in Android as well (see [1] for details). Documentation and corresponding test for A/B boot is present here. The last patch in this series integrates A/B boot support on AM57xx based boards (though it's not enabled by default). Future users of A/B boot feature can use it as a reference. This series is a part of previous submission [3] by Alex Deymo. It contains only A/B feature that was stripped out from there with some modifications for using with "bootm" command preferred in upstream. [1] https://source.android.com/devices/tech/ota/ab/ab_implement [2] bootable/recovery/bootloader_message/include/bootloader_message/bootloader_message.h [3] https://lists.denx.de/pipermail/u-boot/2017-April/285841.html Ruslan Trofymenko (7): cmd: part: Add 'number' sub-command disk: part: Extend API to get partition info common: Implement A/B metadata cmd: Add 'android_ab_select' command test/py: Add base test case for A/B updates doc: android: Add simple guide for A/B updates env: am57xx: Implement A/B boot process cmd/Kconfig | 11 ++ cmd/Makefile | 1 + cmd/android_ab_select.c | 53 +++++++ cmd/part.c | 16 +- common/Kconfig | 10 ++ common/Makefile | 1 + common/android_ab.c | 278 +++++++++++++++++++++++++++++++++++ configs/sandbox_defconfig | 2 + disk/part.c | 68 +++++++++ doc/README.android-ab | 67 +++++++++ include/android_ab.h | 34 +++++ include/android_bootloader_message.h | 164 +++++++++++++++++++++ include/environment/ti/boot.h | 44 +++++- include/part.h | 21 +++ test/py/tests/test_ab.py | 74 ++++++++++ 15 files changed, 839 insertions(+), 5 deletions(-) create mode 100644 cmd/android_ab_select.c create mode 100644 common/android_ab.c create mode 100644 doc/README.android-ab create mode 100644 include/android_ab.h create mode 100644 include/android_bootloader_message.h create mode 100644 test/py/tests/test_ab.py -- 2.7.4

6 20

[U-Boot] [PATCH v2 1/2] x86: TunnelCreek: switch P state to the highest freq
by Christian Gmeiner 04 Apr '19

04 Apr '19

Fixes performance related issue when running vxWorks 5/7 images. The overall memory performance (L1, L2 cache and ram) was measured with Bandwidth [0]. Without this patch we get following numbers: - sequential 128-bit reads: ~5.2 GB/s - sequential 128-bit copy: ~2.1 GB/s - random 32-bit writes: ~1.2 GB/s With this patch patch we get the following numbers: - sequential 128-bit reads: ~18.0 GB/s - sequential 128-bit copy: ~9.5 GB/s - random 32-bit writes: ~5.0 GB/s [0] https://zsmith.co/bandwidth.html v1 -> v2: - incorporate feedback from Bin Meng Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> --- arch/x86/cpu/queensbay/Makefile | 2 +- arch/x86/cpu/queensbay/cpu.c | 58 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+), 1 deletion(-) create mode 100644 arch/x86/cpu/queensbay/cpu.c diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile index c0681995bd..3dd23465d4 100644 --- a/arch/x86/cpu/queensbay/Makefile +++ b/arch/x86/cpu/queensbay/Makefile @@ -5,4 +5,4 @@ # obj-y += fsp_configs.o irq.o -obj-y += tnc.o +obj-y += tnc.o cpu.o diff --git a/arch/x86/cpu/queensbay/cpu.c b/arch/x86/cpu/queensbay/cpu.c new file mode 100644 index 0000000000..805a94cc27 --- /dev/null +++ b/arch/x86/cpu/queensbay/cpu.c @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2018, Bachmann electronic GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <cpu.h> +#include <dm.h> +#include <asm/cpu.h> +#include <asm/cpu_x86.h> +#include <asm/msr.h> + +static void set_max_freq(void) +{ + msr_t msr; + + /* Enable enhanced speed step */ + msr = msr_read(MSR_IA32_MISC_ENABLES); + msr.lo |= (1 << 16); + msr_write(MSR_IA32_MISC_ENABLES, msr); + + /* Set new performance state */ + msr = msr_read(MSR_IA32_PERF_CTL); + msr.lo = 0x101f; + msr_write(MSR_IA32_PERF_CTL, msr); +} + +static int cpu_x86_tunnelcreek_probe(struct udevice *dev) +{ + if (!ll_boot_init()) + return 0; + debug("Init TunnelCreek core\n"); + + /* Set core to max frequency ratio */ + set_max_freq(); + + return 0; +} + +static const struct cpu_ops cpu_x86_tunnelcreek_ops = { + .get_desc = cpu_x86_get_desc, + .get_count = cpu_x86_get_count, +}; + +static const struct udevice_id cpu_x86_tunnelcreek_ids[] = { + { .compatible = "intel,tunnelcreek-cpu" }, + { } +}; + +U_BOOT_DRIVER(cpu_x86_tunnelcreek_drv) = { + .name = "cpu_x86_tunnelcreek", + .id = UCLASS_CPU, + .of_match = cpu_x86_tunnelcreek_ids, + .bind = cpu_x86_bind, + .probe = cpu_x86_tunnelcreek_probe, + .ops = &cpu_x86_tunnelcreek_ops, +}; -- 2.14.3

3 10

[U-Boot] [PATCH] board: rockchip: rk3399: add Rockpro64 board support
by Akash Gajjar 04 Apr '19

04 Apr '19

Rockpro64 is rk3399 based board from pine64.org. add initial board support for Rockpro64. complete board support will be added later in upcoming patchsets. Signed-off-by: Akash Gajjar <akash(a)openedev.com> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-rockpro64.dts | 519 +++++++ arch/arm/dts/rk3399-sdram-lpddr4-1600.dtsi | 1535 ++++++++++++++++++++ arch/arm/mach-rockchip/rk3399/Kconfig | 10 + board/rockchip/rockpro64/Kconfig | 15 + board/rockchip/rockpro64/MAINTAINERS | 6 + board/rockchip/rockpro64/Makefile | 7 + board/rockchip/rockpro64/rockpro64.c | 94 ++ configs/rockpro64-rk3399_defconfig | 78 + include/configs/rockpro64.h | 15 + 10 files changed, 2280 insertions(+) create mode 100644 arch/arm/dts/rk3399-rockpro64.dts create mode 100644 arch/arm/dts/rk3399-sdram-lpddr4-1600.dtsi create mode 100644 board/rockchip/rockpro64/Kconfig create mode 100644 board/rockchip/rockpro64/MAINTAINERS create mode 100644 board/rockchip/rockpro64/Makefile create mode 100644 board/rockchip/rockpro64/rockpro64.c create mode 100644 configs/rockpro64-rk3399_defconfig create mode 100644 include/configs/rockpro64.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d36447d18d..8a84cf55a3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3399-puma-ddr1333.dtb \ rk3399-puma-ddr1600.dtb \ rk3399-puma-ddr1866.dtb \ + rk3399-rockpro64.dtb \ rv1108-evb.dtb dtb-$(CONFIG_ARCH_MESON) += \ meson-gxbb-nanopi-k2.dtb \ diff --git a/arch/arm/dts/rk3399-rockpro64.dts b/arch/arm/dts/rk3399-rockpro64.dts new file mode 100644 index 0000000000..8497a1124b --- /dev/null +++ b/arch/arm/dts/rk3399-rockpro64.dts @@ -0,0 +1,519 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2018 Akash Gajjar <akash(a)openedev.com> + */ + +/dts-v1/; +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3399.dtsi" +#include "rk3399-sdram-lpddr4-1600.dtsi" + +/ { + model = "Pine64 Rockpro64-RK3399 Board"; + compatible = "pine64,rockpro64", "rockchip,rk3399"; + + chosen { + stdout-path = &uart2; + u-boot,spl-boot-order = &sdhci, &sdmmc; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <430000>; + regulator-max-microvolt = <1400000>; + regulator-init-microvolt = <950000>; + }; + + vccadc_ref: vccadc-ref { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x33>; + rx_delay = <0x45>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + vcc10-supply = <&vcc3v3_sys>; + vcc11-supply = <&vcc3v3_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc1v8_pmu>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-name = "vcc1v8_dvp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v0_tp: LDO_REG2 { + regulator-name = "vcc3v0_tp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmu: LDO_REG3 { + regulator-name = "vcc1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sd: LDO_REG4 { + regulator-name = "vcc_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-name = "vcca3v0_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-name = "vcca1v8_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <0>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c3 { + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c4 { + i2c-scl-rising-time-ns = <600>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; +}; + +&i2s0 { + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + #sound-dai-cells = <0>; + status = "okay"; +}; + +&i2s1 { + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; + status = "okay"; +}; + +&i2s2 { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&io_domains { + status = "okay"; + + bt656-supply = <&vcc1v8_dvp>; + audio-supply = <&vcca1v8_codec>; + sdmmc-supply = <&vcc_sd>; + gpio1830-supply = <&vcc_3v0>; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc_3v0>; + status = "okay"; +}; + +&pinctrl { + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + vsel1_gpio: vsel1-gpio { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_gpio: vsel2-gpio { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vccadc_ref>; + status = "okay"; +}; + +&sdmmc { + u-boot,dm-pre-reloc; + bus-width = <4>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + keep-power-in-suspend; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3399-sdram-lpddr4-1600.dtsi b/arch/arm/dts/rk3399-sdram-lpddr4-1600.dtsi new file mode 100644 index 0000000000..fa26e1cf01 --- /dev/null +++ b/arch/arm/dts/rk3399-sdram-lpddr4-1600.dtsi @@ -0,0 +1,1535 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2018 Akash Gajjar <akash(a)openedev.com> + */ + +&dmc { + rockchip,sdram-params = < + 0x2 + 0xa + 0x3 + 0x2 + 0x2 + 0x0 + 0xf + 0xf + 1 + 0x80191519 + 0x14040808 + 0x00000002 + 0x00006226 + 0x0000004c + 0x00000000 + 0x2 + 0xa + 0x3 + 0x2 + 0x2 + 0x0 + 0xf + 0xf + 1 + 0x80191519 + 0x14040808 + 0x00000002 + 0x00006226 + 0x0000004c + 0x00000000 + 800 + 6 + 2 + 13 + 1 + 0x00000700 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000050 + 0x00027100 + 0x00000320 + 0x00001f40 + 0x00000050 + 0x00027100 + 0x00000320 + 0x00001f40 + 0x00000050 + 0x00027100 + 0x00000320 + 0x01001f40 + 0x00000000 + 0x00000101 + 0x00020100 + 0x000000a0 + 0x00000190 + 0x00000000 + 0x06180000 + 0x00061800 + 0x04000618 + 0x33080004 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+ 0x00000000 + >; +}; diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 415466a49b..84e9d34800 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -28,6 +28,15 @@ config TARGET_PUMA_RK3399 * HDMI, eDP, MIPI-DSI, MIPI-DSI/CSI and MIPI-CSI * SPI, I2C, I2S, UART, GPIO, ... +config TARGET_ROCKPRO64_RK3399 + bool "RK3399 Rockpro64" + help + The Rockpro64 is a RK3399 based board from pine64.org. + Rockpro64 has a LPDDR4 (2GB and 4GB variant), PCIex4, HDMI, MIPI-DSI, + MIPI-CSI, eDP, CSI parallel, SPI, I2C, I2S, UART, USB2.0, USB3.0, USB + Type C, es8316 codec, SPDIF out, SD, eMMC and WiFI module support on + board. + endchoice config SYS_SOC @@ -37,6 +46,7 @@ config SYS_MALLOC_F_LEN default 0x0800 source "board/rockchip/evb_rk3399/Kconfig" +source "board/rockchip/rockpro64/Kconfig" source "board/theobroma-systems/puma_rk3399/Kconfig" endif diff --git a/board/rockchip/rockpro64/Kconfig b/board/rockchip/rockpro64/Kconfig new file mode 100644 index 0000000000..9cc2a8c382 --- /dev/null +++ b/board/rockchip/rockpro64/Kconfig @@ -0,0 +1,15 @@ +if TARGET_ROCKPRO64_RK3399 + +config SYS_BOARD + default "rockpro64" + +config SYS_VENDOR + default "rockchip" + +config SYS_CONFIG_NAME + default "rockpro64" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/rockchip/rockpro64/MAINTAINERS b/board/rockchip/rockpro64/MAINTAINERS new file mode 100644 index 0000000000..66dccf67ec --- /dev/null +++ b/board/rockchip/rockpro64/MAINTAINERS @@ -0,0 +1,6 @@ +ROCKPRO64-RK3399 +M: Akash Gajjar <akash(a)openedev.com> +S: Maintained +F: board/rockchip/rockpro64 +F: include/configs/rockpro64.h +F: configs/rockpro64-rk3399_defconfig diff --git a/board/rockchip/rockpro64/Makefile b/board/rockchip/rockpro64/Makefile new file mode 100644 index 0000000000..3bbb808b59 --- /dev/null +++ b/board/rockchip/rockpro64/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2018 Akash Gajjar <akash(a)openedev.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += rockpro64.o diff --git a/board/rockchip/rockpro64/rockpro64.c b/board/rockchip/rockpro64/rockpro64.c new file mode 100644 index 0000000000..74c7a56bd5 --- /dev/null +++ b/board/rockchip/rockpro64/rockpro64.c @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2018 Akash Gajjar <akash(a)openedev.com> + */ + +#include <common.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <dm/uclass-internal.h> +#include <asm/arch/periph.h> +#include <power/regulator.h> +#include <spl.h> + +int board_init(void) +{ + struct udevice *pinctrl, *regulator; + int ret; + + /* + * The PWM do not have decicated interrupt number in dts and can + * not get periph_id by pinctrl framework, so let's init them here. + * The PWM2 and PWM3 are for pwm regulater. + */ + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); + if (ret) { + debug("%s: Cannot find pinctrl device\n", __func__); + goto out; + } + + /* Enable pwm0 for panel backlight */ + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM0); + if (ret) { + debug("%s PWM0 pinctrl init fail! (ret=%d)\n", __func__, ret); + goto out; + } + + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM2); + if (ret) { + debug("%s PWM2 pinctrl init fail!\n", __func__); + goto out; + } + + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM3); + if (ret) { + debug("%s PWM3 pinctrl init fail!\n", __func__); + goto out; + } + + ret = regulators_enable_boot_on(false); + if (ret) + debug("%s: Cannot enable boot on regulator\n", __func__); + + ret = regulator_get_by_platname("vcc5v0_host", &regulator); + if (ret) { + debug("%s vcc5v0_host init fail! ret %d\n", __func__, ret); + goto out; + } + + ret = regulator_set_enable(regulator, true); + if (ret) { + debug("%s vcc5v0-host-en set fail!\n", __func__); + goto out; + } + +out: + return 0; +} + +void spl_board_init(void) +{ + struct udevice *pinctrl; + int ret; + + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); + if (ret) { + debug("%s: Cannot find pinctrl device\n", __func__); + goto err; + } + + /* Enable debug UART */ + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); + if (ret) { + debug("%s: Failed to set up console UART\n", __func__); + goto err; + } + + preloader_console_init(); + return; +err: + printf("%s: Error %d\n", __func__, ret); + + /* No way to report error here */ + hang(); +} diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig new file mode 100644 index 0000000000..88422f2db4 --- /dev/null +++ b/configs/rockpro64-rk3399_defconfig @@ -0,0 +1,78 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_ROCKPRO64_RK3399=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_ROCKCHIP_RK3399=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_ERRNO_STR=y diff --git a/include/configs/rockpro64.h b/include/configs/rockpro64.h new file mode 100644 index 0000000000..1a7e850c94 --- /dev/null +++ b/include/configs/rockpro64.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2018 Akash Gajjar <akash(a)openedev.com> + */ + +#ifndef __ROCKPRO64_RK3399_H +#define __ROCKPRO64_RK3399_H + +#include <configs/rk3399_common.h> + +#define CONFIG_SYS_MMC_ENV_DEV 1 + +#define SDRAM_BANK_SIZE (2UL << 30) + +#endif -- 2.17.1

8 10

[U-Boot] [PATCH] ARM: imx6q_logic: Correct phy fixup for broken ethernet
by Adam Ford 03 Apr '19

03 Apr '19

The Ethernet has been broken for some time. This patch unifies this board with a few others that use a similar approach to enabling phy. This fixes ar8031 Ethernet controller so it works. Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/board/logicpd/imx6/imx6logic.c b/board/logicpd/imx6/imx6logic.c index cda76a8084..eb4849117d 100644 --- a/board/logicpd/imx6/imx6logic.c +++ b/board/logicpd/imx6/imx6logic.c @@ -60,57 +60,6 @@ static iomux_v3_cfg_t const uart3_pads[] = { MX6_PAD_EIM_EB3__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), }; -#ifndef CONFIG_SPL_BUILD -static void fixup_enet_clock(void) -{ - struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - struct gpio_desc nint; - struct gpio_desc reset; - int ret; - - /* Set Ref Clock to 50 MHz */ - enable_fec_anatop_clock(0, ENET_50MHZ); - - /* Set GPIO_16 as ENET_REF_CLK_OUT */ - setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); - - /* Request GPIO Pins to reset Ethernet with new clock */ - ret = dm_gpio_lookup_name("GPIO4_7", &nint); - if (ret) { - printf("Unable to lookup GPIO4_7\n"); - return; - } - - ret = dm_gpio_request(&nint, "eth0_nInt"); - if (ret) { - printf("Unable to request eth0_nInt\n"); - return; - } - - /* Ensure nINT is input or PHY won't startup */ - dm_gpio_set_dir_flags(&nint, GPIOD_IS_IN); - - ret = dm_gpio_lookup_name("GPIO4_9", &reset); - if (ret) { - printf("Unable to lookup GPIO4_9\n"); - return; - } - - ret = dm_gpio_request(&reset, "eth0_reset"); - if (ret) { - printf("Unable to request eth0_reset\n"); - return; - } - - /* Reset LAN8710A PHY */ - dm_gpio_set_dir_flags(&reset, GPIOD_IS_OUT); - dm_gpio_set_value(&reset, 0); - udelay(150); - dm_gpio_set_value(&reset, 1); - mdelay(50); -} -#endif - static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); @@ -141,8 +90,33 @@ static void setup_nand_pins(void) imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads)); } +static int ar8031_phy_fixup(struct phy_device *phydev) +{ + unsigned short val; + + /* To enable AR8031 output a 125MHz clk from CLK_25M */ + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); + + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); + val &= 0xffe3; + val |= 0x18; + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); + + /* introduce tx clock delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); + val |= 0x0100; + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); + + return 0; +} + int board_phy_config(struct phy_device *phydev) { + ar8031_phy_fixup(phydev); + if (phydev->drv->config) phydev->drv->config(phydev); @@ -160,9 +134,6 @@ int overwrite_console(void) int board_early_init_f(void) { -#ifndef CONFIG_SPL_BUILD - fixup_enet_clock(); -#endif setup_iomux_uart(); setup_nand_pins(); return 0; -- 2.17.1

3 3

[U-Boot] [PATCH 1/2] tools/imx8m_image.sh: remove bashism
by Baruch Siach 01 Apr '19

01 Apr '19

Use a single '=' to test string equality for compatibility with non-bash shells. Otherwise, if /bin/sh is dash, build fails: ./tools/imx8m_image.sh: 15: [: signed_hdmi_imx8m.bin: unexpected operator ./tools/imx8m_image.sh: 15: [: signed_hdmi_imx8m.bin: unexpected operator ./tools/imx8m_image.sh: 15: [: spl/u-boot-spl-ddr.bin: unexpected operator ./tools/imx8m_image.sh: 15: [: spl/u-boot-spl-ddr.bin: unexpected operator WARNING './spl/u-boot-spl-ddr.bin' not found, resulting binary is not-functional Signed-off-by: Baruch Siach <baruch(a)tkos.co.il> --- tools/imx8m_image.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/imx8m_image.sh b/tools/imx8m_image.sh index 6346fb64d8c5..ec0881a12812 100755 --- a/tools/imx8m_image.sh +++ b/tools/imx8m_image.sh @@ -12,7 +12,7 @@ blobs=`awk '/^SIGNED_HDMI/ {print $2} /^LOADER/ {print $2} /^SECOND_LOADER/ {pri for f in $blobs; do tmp=$srctree/$f - if [ $f == "spl/u-boot-spl-ddr.bin" ] || [ $f == "u-boot.itb" ]; then + if [ $f = "spl/u-boot-spl-ddr.bin" ] || [ $f = "u-boot.itb" ]; then continue fi @@ -28,7 +28,7 @@ for f in $blobs; do sed -in "s;$f;$tmp;" $file done -if [ $post_process == 1 ]; then +if [ $post_process = 1 ]; then if [ -f $srctree/lpddr4_pmu_train_1d_imem.bin ]; then objcopy -I binary -O binary --pad-to 0x8000 --gap-fill=0x0 $srctree/lpddr4_pmu_train_1d_imem.bin lpddr4_pmu_train_1d_imem_pad.bin objcopy -I binary -O binary --pad-to 0x4000 --gap-fill=0x0 $srctree/lpddr4_pmu_train_1d_dmem.bin lpddr4_pmu_train_1d_dmem_pad.bin -- 2.19.2

7 13

[U-Boot] [PATCH 00/11] sound: Add sound support for Nyan
by Simon Glass 31 Mar '19

31 Mar '19

This series adds sound support for Nyan. It allows simple beeps to be generated in U-Boot. This requires the addition of an I2S driver, an audio hub driver and a sound driver to pull things together. An existing audio codec (MAX98090) is used. Simon Glass (11): misc: Allow child devices sound: samsung: Fix 'regiter' typo sound: i2s: Tidy up a few comments sound: Allow audio codecs to be used by other SoCs tegra: Correct tegra124 clock name tegra: Add a delay in clock_start_periph_pll() tegra: sound: Add an audio hub driver tegra: sound: Add an I2S driver sound: tegra: Add a sound driver tegra: nyan-big: Enable sound tegra: nyan: Add a README arch/arm/include/asm/arch-tegra/tegra_ahub.h | 475 +++++++++++++++++++ arch/arm/include/asm/arch-tegra/tegra_i2s.h | 206 ++++++++ arch/arm/mach-tegra/clock.c | 1 + arch/arm/mach-tegra/tegra124/clock.c | 2 +- board/nvidia/nyan-big/README | 18 + board/nvidia/nyan-big/nyan-big.c | 2 +- configs/nyan-big_defconfig | 8 +- drivers/misc/misc-uclass.c | 1 + drivers/sound/Kconfig | 17 +- drivers/sound/Makefile | 1 + drivers/sound/max98088.c | 7 - drivers/sound/max98090.c | 7 - drivers/sound/max98095.c | 7 - drivers/sound/maxim_codec.c | 3 - drivers/sound/samsung-i2s.c | 16 +- drivers/sound/samsung_sound.c | 4 + drivers/sound/tegra_ahub.c | 256 ++++++++++ drivers/sound/tegra_i2s.c | 124 +++++ drivers/sound/tegra_i2s_priv.h | 29 ++ drivers/sound/tegra_sound.c | 100 ++++ include/i2s.h | 11 +- 21 files changed, 1246 insertions(+), 49 deletions(-) create mode 100644 arch/arm/include/asm/arch-tegra/tegra_ahub.h create mode 100644 arch/arm/include/asm/arch-tegra/tegra_i2s.h create mode 100644 board/nvidia/nyan-big/README create mode 100644 drivers/sound/tegra_ahub.c create mode 100644 drivers/sound/tegra_i2s.c create mode 100644 drivers/sound/tegra_i2s_priv.h create mode 100644 drivers/sound/tegra_sound.c -- 2.20.1.415.g653613c723-goog

4 21

[U-Boot] [PATCH V4 1/2] mmc: add HS400 support
by Peng Fan 29 Mar '19

29 Mar '19

Add HS400 support. Selecting HS400 needs first select HS200 according to spec, so use a dedicated function for HS400. Add HS400 related macros. Remove the restriction of only using the low 6 bits of EXT_CSD_CARD_TYPE, using all the 8 bits. Signed-off-by: Peng Fan <peng.fan(a)nxp.com> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> Cc: Jean-Jacques Hiblot <jjhiblot(a)ti.com> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Kishon Vijay Abraham I <kishon(a)ti.com> Cc: Faiz Abbas <faiz_abbas(a)ti.com> Cc: Marek Vasut <marex(a)denx.de> --- V4: Add SPL_MMC_HS400_SUPPORT Kconfig entry typo fix, HS199->HS200 in commit log. V3: Simplify code add error msg V2: remove 4bits support from HS400, as HS400 does not support 4bits per spec. drivers/mmc/Kconfig | 13 +++++ drivers/mmc/mmc.c | 137 +++++++++++++++++++++++++++++++++++++++++----------- include/mmc.h | 11 +++++ 3 files changed, 134 insertions(+), 27 deletions(-) diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 377b1c4b3b..1616022b91 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -111,6 +111,19 @@ config SPL_MMC_UHS_SUPPORT cards. The IO voltage must be switchable from 3.3v to 1.8v. The bus frequency can go up to 208MHz (SDR104) +config MMC_HS400_SUPPORT + bool "enable HS400 support" + select MMC_HS200_SUPPORT + help + The HS400 mode is support by some eMMC. The bus frequency is up to + 200MHz. This mode requires tuning the IO. + +config SPL_MMC_HS400_SUPPORT + bool "enable HS400 support in SPL" + help + The HS400 mode is support by some eMMC. The bus frequency is up to + 200MHz. This mode requires tuning the IO. + config MMC_HS200_SUPPORT bool "enable HS200 support" help diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index ad429f49c9..585951cd78 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -147,6 +147,7 @@ const char *mmc_mode_name(enum bus_mode mode) [MMC_HS_52] = "MMC High Speed (52MHz)", [MMC_DDR_52] = "MMC DDR52 (52MHz)", [MMC_HS_200] = "HS200 (200MHz)", + [MMC_HS_400] = "HS400 (200MHz)", }; if (mode >= MMC_MODES_END) @@ -171,6 +172,7 @@ static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode) [UHS_DDR50] = 50000000, [UHS_SDR104] = 208000000, [MMC_HS_200] = 200000000, + [MMC_HS_400] = 200000000, }; if (mode == MMC_LEGACY) @@ -769,6 +771,11 @@ static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode) case MMC_HS_200: speed_bits = EXT_CSD_TIMING_HS200; break; +#endif +#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) + case MMC_HS_400: + speed_bits = EXT_CSD_TIMING_HS400; + break; #endif case MMC_LEGACY: speed_bits = EXT_CSD_TIMING_LEGACY; @@ -816,7 +823,7 @@ static int mmc_get_capabilities(struct mmc *mmc) mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT; - cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0x3f; + cardtype = ext_csd[EXT_CSD_CARD_TYPE]; mmc->cardtype = cardtype; #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) @@ -824,6 +831,12 @@ static int mmc_get_capabilities(struct mmc *mmc) EXT_CSD_CARD_TYPE_HS200_1_8V)) { mmc->card_caps |= MMC_MODE_HS200; } +#endif +#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) + if (cardtype & (EXT_CSD_CARD_TYPE_HS400_1_2V | + EXT_CSD_CARD_TYPE_HS400_1_8V)) { + mmc->card_caps |= MMC_MODE_HS400; + } #endif if (cardtype & EXT_CSD_CARD_TYPE_52) { if (cardtype & EXT_CSD_CARD_TYPE_DDR_52) @@ -1734,10 +1747,13 @@ static int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode, u32 card_mask = 0; switch (mode) { + case MMC_HS_400: case MMC_HS_200: - if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS200_1_8V) + if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_8V | + EXT_CSD_CARD_TYPE_HS400_1_8V)) card_mask |= MMC_SIGNAL_VOLTAGE_180; - if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS200_1_2V) + if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V | + EXT_CSD_CARD_TYPE_HS400_1_2V)) card_mask |= MMC_SIGNAL_VOLTAGE_120; break; case MMC_DDR_52: @@ -1773,6 +1789,13 @@ static inline int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode, #endif static const struct mode_width_tuning mmc_modes_by_pref[] = { +#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) + { + .mode = MMC_HS_400, + .widths = MMC_MODE_8BIT, + .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200 + }, +#endif #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) { .mode = MMC_HS_200, @@ -1816,6 +1839,54 @@ static const struct ext_csd_bus_width { {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1}, }; +#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) +static int mmc_select_hs400(struct mmc *mmc) +{ + int err; + + /* Set timing to HS200 for tuning */ + err = mmc_set_card_speed(mmc, MMC_HS_200); + if (err) + return err; + + /* configure the bus mode (host) */ + mmc_select_mode(mmc, MMC_HS_200); + mmc_set_clock(mmc, mmc->tran_speed, false); + + /* execute tuning if needed */ + err = mmc_execute_tuning(mmc, MMC_CMD_SEND_TUNING_BLOCK_HS200); + if (err) { + debug("tuning failed\n"); + return err; + } + + /* Set back to HS */ + mmc_set_card_speed(mmc, MMC_HS); + mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false); + + err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH, + EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG); + if (err) + return err; + + err = mmc_set_card_speed(mmc, MMC_HS_400); + if (err) + return err; + + mmc_select_mode(mmc, MMC_HS_400); + err = mmc_set_clock(mmc, mmc->tran_speed, false); + if (err) + return err; + + return 0; +} +#else +static int mmc_select_hs400(struct mmc *mmc) +{ + return -ENOTSUPP; +} +#endif + #define for_each_supported_width(caps, ddr, ecbv) \ for (ecbv = ext_csd_bus_width;\ ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\ @@ -1869,37 +1940,49 @@ static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps) goto error; mmc_set_bus_width(mmc, bus_width(ecbw->cap)); - /* configure the bus speed (card) */ - err = mmc_set_card_speed(mmc, mwt->mode); - if (err) - goto error; - - /* - * configure the bus width AND the ddr mode (card) - * The host side will be taken care of in the next step - */ - if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) { - err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, - EXT_CSD_BUS_WIDTH, - ecbw->ext_csd_bits); + if (mwt->mode == MMC_HS_400) { + err = mmc_select_hs400(mmc); + if (err) { + printf("Select HS400 failed %d\n", err); + goto error; + } + } else { + /* configure the bus speed (card) */ + err = mmc_set_card_speed(mmc, mwt->mode); if (err) goto error; - } - /* configure the bus mode (host) */ - mmc_select_mode(mmc, mwt->mode); - mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE); + /* + * configure the bus width AND the ddr mode + * (card). The host side will be taken care + * of in the next step + */ + if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) { + err = mmc_switch(mmc, + EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_BUS_WIDTH, + ecbw->ext_csd_bits); + if (err) + goto error; + } + + /* configure the bus mode (host) */ + mmc_select_mode(mmc, mwt->mode); + mmc_set_clock(mmc, mmc->tran_speed, + MMC_CLK_ENABLE); #ifdef MMC_SUPPORTS_TUNING - /* execute tuning if needed */ - if (mwt->tuning) { - err = mmc_execute_tuning(mmc, mwt->tuning); - if (err) { - pr_debug("tuning failed\n"); - goto error; + /* execute tuning if needed */ + if (mwt->tuning) { + err = mmc_execute_tuning(mmc, + mwt->tuning); + if (err) { + pr_debug("tuning failed\n"); + goto error; + } } - } #endif + } /* do a transfer to check the configuration */ err = mmc_read_and_compare_ext_csd(mmc); diff --git a/include/mmc.h b/include/mmc.h index df4255b828..9b9cbedadc 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -64,6 +64,7 @@ #define MMC_MODE_HS_52MHz MMC_CAP(MMC_HS_52) #define MMC_MODE_DDR_52MHz MMC_CAP(MMC_DDR_52) #define MMC_MODE_HS200 MMC_CAP(MMC_HS_200) +#define MMC_MODE_HS400 MMC_CAP(MMC_HS_400) #define MMC_MODE_8BIT BIT(30) #define MMC_MODE_4BIT BIT(29) @@ -248,6 +249,10 @@ static inline bool mmc_is_tuning_cmd(uint cmdidx) /* SDR mode @1.2V I/O */ #define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \ EXT_CSD_CARD_TYPE_HS200_1_2V) +#define EXT_CSD_CARD_TYPE_HS400_1_8V BIT(6) +#define EXT_CSD_CARD_TYPE_HS400_1_2V BIT(7) +#define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \ + EXT_CSD_CARD_TYPE_HS400_1_2V) #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ @@ -259,6 +264,7 @@ static inline bool mmc_is_tuning_cmd(uint cmdidx) #define EXT_CSD_TIMING_LEGACY 0 /* no high speed */ #define EXT_CSD_TIMING_HS 1 /* HS */ #define EXT_CSD_TIMING_HS200 2 /* HS200 */ +#define EXT_CSD_TIMING_HS400 3 /* HS400 */ #define EXT_CSD_BOOT_ACK_ENABLE (1 << 6) #define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3) @@ -519,6 +525,7 @@ enum bus_mode { UHS_DDR50, UHS_SDR104, MMC_HS_200, + MMC_HS_400, MMC_MODES_END }; @@ -532,6 +539,10 @@ static inline bool mmc_is_mode_ddr(enum bus_mode mode) #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) else if (mode == UHS_DDR50) return true; +#endif +#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) + else if (mode == MMC_HS_400) + return true; #endif else return false; -- 2.14.1

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[U-Boot] [PATCH 0/5] Use Android DT image format for TI boards
by Sam Protsenko 29 Mar '19

29 Mar '19

Android documentation recommends using new image format for storing dtb and dtbo files: [1]. Using that format, we can pack several dtb files to dtb.img, and also pack several dtbo files to dtbo.img. Then those images should be flashed to eMMC partitions, called "dtb" and "dtbo" respectively. This patch series introduces support for mentioned Android DT image format, adds "dtimg" command to deal with that image format from U-Boot shell, and provides new Android boot scheme to TI boards (AM57x and DRA7 boards). So with this patch series we will have next procedure for Android boot: 1. Read next images from eMMC partitions to RAM: - boot.img - dtb.img - dtbo.img 2. Take addresses of desired dtb/dtbo files from that images (for current board) 3. Apply dtbo overlays to main dtb, if needed 4. Boot the kernel from Android boot image, using resulting dtb It was tested on X15 and AM57x EVM boards. [1] https://source.android.com/devices/architecture/dto/partitions Sam Protsenko (5): common: Add support for Android DT image cmd: Add dtimg command arm: ti: boot: Extract PARTS_DEFAULT to boot.h arm: ti: boot: Add dtbo partition for Android boot arm: ti: boot: Implement Android boot using DT image format board/ti/common/Kconfig | 1 + cmd/Kconfig | 8 ++ cmd/Makefile | 1 + cmd/dtimg.c | 142 ++++++++++++++++++++++++++++++ common/Makefile | 4 + common/image-android-dt.c | 134 ++++++++++++++++++++++++++++ configs/am57xx_evm_defconfig | 1 + configs/am57xx_hs_evm_defconfig | 1 + configs/dra7xx_evm_defconfig | 1 + configs/dra7xx_hs_evm_defconfig | 1 + include/configs/am57xx_evm.h | 25 ------ include/configs/cl-som-am57x.h | 2 + include/configs/cm_t54.h | 2 + include/configs/dra7xx_evm.h | 25 ------ include/configs/ti_armv7_common.h | 1 + include/dt_table.h | 46 ++++++++++ include/environment/ti/boot.h | 68 ++++++++++++-- include/image-android-dt.h | 18 ++++ 18 files changed, 422 insertions(+), 59 deletions(-) create mode 100644 cmd/dtimg.c create mode 100644 common/image-android-dt.c create mode 100644 include/dt_table.h create mode 100644 include/image-android-dt.h -- 2.17.0

4 21

[U-Boot] [PATCH 00/36] rockchip: clean up board file for rockchip SoCs
by Kever Yang 29 Mar '19

29 Mar '19

This patch set is to clean code for board related file, after this patch set, all the Rockchip SoCs will share the same tpl/spl/board file and very similar boot flow. tpl.c: target for init DDR sdram, only internal sram available, prefer tpl to be as simple as possible and then back to backrom; spl.c: target for load U-Boot and Trust(option) image and boot into next stage, init DDR sdram if no tpl exist; board.c: use for U-Boot proper for all Rockchip SoCs. We prefer to reduce boot flow option like RETURN_TO_BROM in SPL/TPL, and will enable trust(ATF or OPTEE) support for all SoCs with TrustZone, will share scripts for link and firmware package. Only rk3399 is using spl+Trust/U-Boot and all other SoCs should go to tpl+spl_Trust/U-Boot mode now. Kever Yang (36): rockchip: rk3288: move configure_l2ctlr back to rk3288 rockchip: add common MACRO to enable sys arch timer rockchip: enable SYS_NS16550 for all SoCs by default rockchip: defconfig: remove CONFIG_SYS_NS16550 rockchip: add STIMER_BASE for all SoCs rockchip: add IRAM_START_ADDR for all SoCs rockchip: rk3328: add BOOT_MODE_REG for rk3328 rockchip: rk322x: remove use rockchip timer as sys timer rockchip: rk322x: sdram: use common udelay instead of rockchip_udelay rockchip: rk322x: prepare to use common board file rockchip: defconfig enable sysreset for rk3229 spl rockchip: rk3036: sdram: use udelay instead of rockchip_udelay rockchip: rk3036: remove sys timer rockchip: rk3036: prepare to use commong board file rockchip: declare sdram_init() in common header rockchip: sdram-common: add api to pass dram info to trust os rockchip: sdram_common: add common dram_init_banksize rockchip: rk3188: remove rockchip timer as sys timer rockchip: rk3188: prepare to use common board file rockchip: rk3128: remove rockchip timer as systimer rockchip: rk3128: prepare use common board file rockchip: dts: rk3288: update spl-boot-order rockchip: rk3288: remove rockchip timer for sys timer armv8: add timer_get_boot_us() for generic timer rockchip: rk3288: prepare to use common board file rockchip: rk1108: remove rockchip timer for sys timer rockchip: rv1108: prepare to use common board file rockchip: rk3328: prepare to use common board file rockchip: rk3368: prepare to use common board file rockchip: lion-rk3368: remove rockchip timer rockchip: rk3399: prepare to use common board file rockchip: remove rk_timer rockchip: dts: rk3399-firefly: enable uart2 in spl rockchip: spl-boot-order: do not enable with OF_PLATDATA rockchip: declear boot_devices in bootrom.h rockchip: add common board file for rockchip platform arch/arm/Kconfig | 1 + arch/arm/cpu/armv8/generic_timer.c | 6 + arch/arm/dts/rk3288-phycore-rdk.dts | 6 +- arch/arm/dts/rk3288-veyron.dtsi | 6 +- arch/arm/dts/rk3399-firefly.dts | 1 + arch/arm/include/asm/arch-rockchip/bootrom.h | 2 + arch/arm/include/asm/arch-rockchip/sdram_common.h | 4 + arch/arm/include/asm/arch-rockchip/sys_proto.h | 25 +- arch/arm/mach-rockchip/Kconfig | 38 ++- arch/arm/mach-rockchip/Makefile | 23 +- arch/arm/mach-rockchip/{rk3128-board.c => board.c} | 93 +++--- arch/arm/mach-rockchip/rk3036-board.c | 104 ------- arch/arm/mach-rockchip/rk3036/Makefile | 2 +- .../{rk3036-board-spl.c => rk3036/rk3036.c} | 41 +-- arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 33 +- arch/arm/mach-rockchip/rk3188-board-spl.c | 226 -------------- arch/arm/mach-rockchip/rk3188-board.c | 82 ----- arch/arm/mach-rockchip/rk3188/Makefile | 1 + arch/arm/mach-rockchip/rk3188/rk3188.c | 23 ++ arch/arm/mach-rockchip/rk322x-board.c | 155 ---------- arch/arm/mach-rockchip/rk322x/Makefile | 2 +- .../{rk322x-board-spl.c => rk322x/rk322x.c} | 86 ++---- arch/arm/mach-rockchip/rk3288-board-spl.c | 304 ------------------ arch/arm/mach-rockchip/rk3288-board-tpl.c | 84 ----- arch/arm/mach-rockchip/rk3288-board.c | 338 --------------------- arch/arm/mach-rockchip/rk3288/rk3288.c | 328 +++++++++++++++++++- arch/arm/mach-rockchip/rk3328/rk3328.c | 59 +++- arch/arm/mach-rockchip/rk3368-board-spl.c | 73 ----- arch/arm/mach-rockchip/rk3368-board-tpl.c | 157 ---------- arch/arm/mach-rockchip/rk3368/rk3368.c | 116 ++++++- arch/arm/mach-rockchip/rk3399-board-spl.c | 179 ----------- arch/arm/mach-rockchip/rk3399-board.c | 14 - arch/arm/mach-rockchip/rk3399/rk3399.c | 86 +++++- arch/arm/mach-rockchip/rk_timer.c | 48 --- arch/arm/mach-rockchip/rv1108/rv1108.c | 8 - arch/arm/mach-rockchip/sdram_common.c | 84 ++++- arch/arm/mach-rockchip/spl-boot-order.c | 2 +- arch/arm/mach-rockchip/spl.c | 195 ++++++++++++ arch/arm/mach-rockchip/tpl.c | 111 +++++++ board/chipspark/popmetal_rk3288/popmetal-rk3288.c | 9 +- board/geekbuying/geekbox/geekbox.c | 5 - board/mqmaker/miqi_rk3288/miqi-rk3288.c | 7 - board/phytec/phycore_rk3288/phycore-rk3288.c | 45 ++- board/rockchip/evb_px5/evb-px5.c | 5 - board/rockchip/evb_rk3288/evb-rk3288.c | 7 - .../rockchip/evb_rk3288_rk1608/evb-rk3288-rk1608.c | 8 + board/rockchip/evb_rk3328/evb-rk3328.c | 66 ---- board/rockchip/evb_rk3399/evb-rk3399.c | 56 ++-- board/rockchip/evb_rv1108/evb_rv1108.c | 6 - board/rockchip/fennec_rk3288/fennec-rk3288.c | 7 - board/rockchip/sheep_rk3368/sheep_rk3368.c | 5 - board/rockchip/tinker_rk3288/tinker-rk3288.c | 2 +- board/theobroma-systems/lion_rk3368/lion_rk3368.c | 8 - board/theobroma-systems/puma_rk3399/puma-rk3399.c | 17 +- configs/evb-rk3128_defconfig | 1 - configs/evb-rk3229_defconfig | 2 +- configs/evb-rk3288_defconfig | 1 - configs/evb-rk3328_defconfig | 1 - configs/evb-rk3399_defconfig | 1 - configs/fennec-rk3288_defconfig | 1 - configs/firefly-rk3288_defconfig | 1 - configs/firefly-rk3399_defconfig | 1 - configs/lion-rk3368_defconfig | 4 - configs/miqi-rk3288_defconfig | 1 - configs/phycore-rk3288_defconfig | 1 - configs/popmetal-rk3288_defconfig | 1 - configs/puma-rk3399_defconfig | 1 - configs/tinker-rk3288_defconfig | 1 - configs/vyasa-rk3288_defconfig | 1 - drivers/ram/rockchip/sdram_rk322x.c | 29 +- include/configs/rk3036_common.h | 7 - include/configs/rk3128_common.h | 6 - include/configs/rk3188_common.h | 5 - include/configs/rk322x_common.h | 4 - include/configs/rk3288_common.h | 6 - include/configs/rk3328_common.h | 2 - include/configs/rk3368_common.h | 4 - include/configs/rk3399_common.h | 4 - include/configs/rockchip-common.h | 6 + include/configs/rv1108_common.h | 8 - 80 files changed, 1248 insertions(+), 2251 deletions(-) rename arch/arm/mach-rockchip/{rk3128-board.c => board.c} (63%) delete mode 100644 arch/arm/mach-rockchip/rk3036-board.c rename arch/arm/mach-rockchip/{rk3036-board-spl.c => rk3036/rk3036.c} (50%) delete mode 100644 arch/arm/mach-rockchip/rk3188-board-spl.c delete mode 100644 arch/arm/mach-rockchip/rk3188-board.c create mode 100644 arch/arm/mach-rockchip/rk3188/rk3188.c delete mode 100644 arch/arm/mach-rockchip/rk322x-board.c rename arch/arm/mach-rockchip/{rk322x-board-spl.c => rk322x/rk322x.c} (51%) delete mode 100644 arch/arm/mach-rockchip/rk3288-board-spl.c delete mode 100644 arch/arm/mach-rockchip/rk3288-board-tpl.c delete mode 100644 arch/arm/mach-rockchip/rk3288-board.c delete mode 100644 arch/arm/mach-rockchip/rk3368-board-spl.c delete mode 100644 arch/arm/mach-rockchip/rk3368-board-tpl.c delete mode 100644 arch/arm/mach-rockchip/rk3399-board-spl.c delete mode 100644 arch/arm/mach-rockchip/rk3399-board.c delete mode 100644 arch/arm/mach-rockchip/rk_timer.c create mode 100644 arch/arm/mach-rockchip/spl.c create mode 100644 arch/arm/mach-rockchip/tpl.c create mode 100644 board/rockchip/evb_rk3288_rk1608/evb-rk3288-rk1608.c -- 1.9.1

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