January 2019 - U-Boot

[U-Boot] [PATCH v4 01/12] m68k: add basic set of devicetrees
by Angelo Dureghello 11 Mar '19

11 Mar '19

This patch adds a basic group of devicetrees, one for each cpu family, including actually just uart and dspi devices, since these are the drivers supporting devicetree (support added in this patch-set). Acked-by: Jagan Teki <jagan(a)amarulasolutions.com> Signed-off-by: Angelo Dureghello <angelo(a)sysam.it> --- Changes for v2: - add mcf54xx.dtsi and mcf537x.dtsi Changes for v3: - none Changes for v4: - none --- arch/m68k/dts/mcf5208.dtsi | 36 ++++++++ arch/m68k/dts/mcf5227x.dtsi | 48 ++++++++++ arch/m68k/dts/mcf523x.dtsi | 44 ++++++++++ arch/m68k/dts/mcf5249.dtsi | 38 ++++++++ arch/m68k/dts/mcf5253.dtsi | 44 ++++++++++ arch/m68k/dts/mcf5271.dtsi | 44 ++++++++++ arch/m68k/dts/mcf5272.dtsi | 38 ++++++++ arch/m68k/dts/mcf5275.dtsi | 44 ++++++++++ arch/m68k/dts/mcf5282.dtsi | 44 ++++++++++ arch/m68k/dts/mcf5301x.dtsi | 48 ++++++++++ arch/m68k/dts/mcf5307.dtsi | 39 +++++++++ arch/m68k/dts/mcf5329.dtsi | 36 ++++++++ arch/m68k/dts/mcf537x.dtsi | 36 ++++++++ arch/m68k/dts/mcf5441x.dtsi | 87 +++++++++++++++++++ arch/m68k/dts/mcf5445x.dtsi | 48 ++++++++++ arch/m68k/dts/mcf54xx.dtsi | 40 +++++++++ doc/device-tree-bindings/serial/mcf-uart.txt | 19 ++++ doc/device-tree-bindings/spi/spi-mcf-dspi.txt | 30 +++++++ 18 files changed, 763 insertions(+) create mode 100644 arch/m68k/dts/mcf5208.dtsi create mode 100644 arch/m68k/dts/mcf5227x.dtsi create mode 100644 arch/m68k/dts/mcf523x.dtsi create mode 100644 arch/m68k/dts/mcf5249.dtsi create mode 100644 arch/m68k/dts/mcf5253.dtsi create mode 100644 arch/m68k/dts/mcf5271.dtsi create mode 100644 arch/m68k/dts/mcf5272.dtsi create mode 100644 arch/m68k/dts/mcf5275.dtsi create mode 100644 arch/m68k/dts/mcf5282.dtsi create mode 100644 arch/m68k/dts/mcf5301x.dtsi create mode 100644 arch/m68k/dts/mcf5307.dtsi create mode 100644 arch/m68k/dts/mcf5329.dtsi create mode 100644 arch/m68k/dts/mcf537x.dtsi create mode 100644 arch/m68k/dts/mcf5441x.dtsi create mode 100644 arch/m68k/dts/mcf5445x.dtsi create mode 100644 arch/m68k/dts/mcf54xx.dtsi create mode 100644 doc/device-tree-bindings/serial/mcf-uart.txt create mode 100644 doc/device-tree-bindings/spi/spi-mcf-dspi.txt diff --git a/arch/m68k/dts/mcf5208.dtsi b/arch/m68k/dts/mcf5208.dtsi new file mode 100644 index 0000000000..558d8bf41a --- /dev/null +++ b/arch/m68k/dts/mcf5208.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo(a)sysam.it> + */ + +/ { + compatible = "fsl,mcf5208"; + + aliases { + serial0 = &uart0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + uart0: uart@fc060000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc060000 0x40>; + status = "disabled"; + }; + + uart1: uart@fc064000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc064000 0x40>; + status = "disabled"; + }; + + uart2: uart@fc068000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc068000 0x40>; + status = "disabled"; + }; + }; +}; diff --git a/arch/m68k/dts/mcf5227x.dtsi b/arch/m68k/dts/mcf5227x.dtsi new file mode 100644 index 0000000000..8c95edddb6 --- /dev/null +++ b/arch/m68k/dts/mcf5227x.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo(a)sysam.it> + */ + +/ { + compatible = "fsl,mcf5227x"; + + aliases { + serial0 = &uart0; + spi0 = &dspi0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + uart0: uart@fc060000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc060000 0x40>; + status = "disabled"; + }; + + uart1: uart@fc064000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc064000 0x40>; + status = "disabled"; + }; + + uart2: uart@fc068000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc068000 0x40>; + status = "disabled"; + }; + + dspi0: dspi@fc05c000 { + compatible = "fsl,mcf-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfc05c000 0x100>; + spi-max-frequency = <50000000>; + num-cs = <4>; + spi-mode = <0>; + status = "disabled"; + }; + }; +}; diff --git a/arch/m68k/dts/mcf523x.dtsi b/arch/m68k/dts/mcf523x.dtsi new file mode 100644 index 0000000000..9e79d472ec --- /dev/null +++ b/arch/m68k/dts/mcf523x.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo(a)sysam.it> + */ + +/ { + compatible = "fsl,mcf523x"; + + aliases { + serial0 = &uart0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ipsbar: ipsbar@4000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x40000000 0x40000000>; + reg = <0x40000000 0x40000000>; + + uart0: uart@200 { + compatible = "fsl,mcf-uart"; + reg = <0x200 0x40>; + status = "disabled"; + }; + + uart1: uart@240 { + compatible = "fsl,mcf-uart"; + reg = <0x240 0x40>; + status = "disabled"; + }; + + uart2: uart@280 { + compatible = "fsl,mcf-uart"; + reg = <0x280 0x40>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/m68k/dts/mcf5249.dtsi b/arch/m68k/dts/mcf5249.dtsi new file mode 100644 index 0000000000..248b3dc68b --- /dev/null +++ b/arch/m68k/dts/mcf5249.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo(a)sysam.it> + */ + +/ { + compatible = "fsl,mcf5249"; + + aliases { + serial0 = &uart0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + mbar: mbar@10000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x10000000 0x10000>; + reg = <0x10000000 0x10000>; + + uart0: uart@1c0 { + compatible = "fsl,mcf-uart"; + reg = <0x1c0 0x40>; + status = "disabled"; + }; + + uart1: uart@200 { + compatible = "fsl,mcf-uart"; + reg = <0x200 0x40>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/m68k/dts/mcf5253.dtsi b/arch/m68k/dts/mcf5253.dtsi new file mode 100644 index 0000000000..3bde2d6202 --- /dev/null +++ b/arch/m68k/dts/mcf5253.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo(a)sysam.it> + */ + +/ { + compatible = "fsl,mcf5253"; + + aliases { + serial0 = &uart0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + mbar: mbar@10000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x10000000 0x10000>; + reg = <0x10000000 0x10000>; + + uart0: uart@1c0 { + compatible = "fsl,mcf-uart"; + reg = <0x1c0 0x40>; + status = "disabled"; + }; + + uart1: uart@200 { + compatible = "fsl,mcf-uart"; + reg = <0x200 0x40>; + status = "disabled"; + }; + + uart3: uart@c00 { + compatible = "fsl,mcf-uart"; + reg = <0xc00 0x40>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/m68k/dts/mcf5271.dtsi b/arch/m68k/dts/mcf5271.dtsi new file mode 100644 index 0000000000..29355528d0 --- /dev/null +++ b/arch/m68k/dts/mcf5271.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo(a)sysam.it> + */ + +/ { + compatible = "fsl,mcf5271"; + + aliases { + serial0 = &uart0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ipsbar: ipsbar@4000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x40000000 0x40000000>; + reg = <0x40000000 0x40000000>; + + uart0: uart@200 { + compatible = "fsl,mcf-uart"; + reg = <0x200 0x40>; + status = "disabled"; + }; + + uart1: uart@240 { + compatible = "fsl,mcf-uart"; + reg = <0x240 0x40>; + status = "disabled"; + }; + + uart2: uart@280 { + compatible = "fsl,mcf-uart"; + reg = <0x280 0x40>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/m68k/dts/mcf5272.dtsi b/arch/m68k/dts/mcf5272.dtsi new file mode 100644 index 0000000000..a56117728b --- /dev/null +++ b/arch/m68k/dts/mcf5272.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo(a)sysam.it> + */ + +/ { + compatible = "fsl,mcf5272"; + + aliases { + serial0 = &uart0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + mbar: mbar@10000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x10000000 0x10000>; + reg = <0x10000000 0x10000>; + + uart0: uart@100 { + compatible = "fsl,mcf-uart"; + reg = <0x100 0x40>; + status = "disabled"; + }; + + uart1: uart@140 { + compatible = "fsl,mcf-uart"; + reg = <0x140 0x40>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/m68k/dts/mcf5275.dtsi b/arch/m68k/dts/mcf5275.dtsi new file mode 100644 index 0000000000..b375609d4a --- /dev/null +++ b/arch/m68k/dts/mcf5275.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo(a)sysam.it> + */ + +/ { + compatible = "fsl,mcf5275"; + + aliases { + serial0 = &uart0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ipsbar: ipsbar@4000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x40000000 0x40000000>; + reg = <0x40000000 0x40000000>; + + uart0: uart@200 { + compatible = "fsl,mcf-uart"; + reg = <0x200 0x40>; + status = "disabled"; + }; + + uart1: uart@240 { + compatible = "fsl,mcf-uart"; + reg = <0x240 0x40>; + status = "disabled"; + }; + + uart2: uart@280 { + compatible = "fsl,mcf-uart"; + reg = <0x280 0x40>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/m68k/dts/mcf5282.dtsi b/arch/m68k/dts/mcf5282.dtsi new file mode 100644 index 0000000000..3ad1be7bb5 --- /dev/null +++ b/arch/m68k/dts/mcf5282.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo(a)sysam.it> + */ + +/ { + compatible = "fsl,mcf5282"; + + aliases { + serial0 = &uart0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ipsbar: ipsbar@4000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x40000000 0x40000000>; + reg = <0x40000000 0x40000000>; + + uart0: uart@200 { + compatible = "fsl,mcf-uart"; + reg = <0x200 0x40>; + status = "disabled"; + }; + + uart1: uart@240 { + compatible = "fsl,mcf-uart"; + reg = <0x240 0x40>; + status = "disabled"; + }; + + uart2: uart@280 { + compatible = "fsl,mcf-uart"; + reg = <0x280 0x40>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/m68k/dts/mcf5301x.dtsi b/arch/m68k/dts/mcf5301x.dtsi new file mode 100644 index 0000000000..0891e4dfd5 --- /dev/null +++ b/arch/m68k/dts/mcf5301x.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo(a)sysam.it> + */ + +/ { + compatible = "fsl,mcf5301x"; + + aliases { + serial0 = &uart0; + spi0 = &dspi0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + uart0: uart@fc060000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc060000 0x40>; + status = "disabled"; + }; + + uart1: uart@fc064000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc064000 0x40>; + status = "disabled"; + }; + + uart2: uart@fc068000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc068000 0x40>; + status = "disabled"; + }; + + dspi0: dspi@fc05c000 { + compatible = "fsl,mcf-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfc05c000 0x100>; + spi-max-frequency = <50000000>; + num-cs = <4>; + spi-mode = <0>; + status = "disabled"; + }; + }; +}; diff --git a/arch/m68k/dts/mcf5307.dtsi b/arch/m68k/dts/mcf5307.dtsi new file mode 100644 index 0000000000..e199cf9991 --- /dev/null +++ b/arch/m68k/dts/mcf5307.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo(a)sysam.it> + */ + +/ { + compatible = "fsl,mcf5307"; + + aliases { + serial0 = &uart0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + /* MBAR */ + mbar: mbar@10000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x10000000 0x10000>; + reg = <0x10000000 0x10000>; + + uart0: uart@1c0 { + compatible = "fsl,mcf-uart"; + reg = <0x1c0 0x40>; + status = "disabled"; + }; + + uart1: uart@200 { + compatible = "fsl,mcf-uart"; + reg = <0x200 0x40>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/m68k/dts/mcf5329.dtsi b/arch/m68k/dts/mcf5329.dtsi new file mode 100644 index 0000000000..aeaa6430af --- /dev/null +++ b/arch/m68k/dts/mcf5329.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo(a)sysam.it> + */ + +/ { + compatible = "fsl,mcf5329"; + + aliases { + serial0 = &uart0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + uart0: uart@fc060000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc060000 0x40>; + status = "disabled"; + }; + + uart1: uart@fc064000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc064000 0x40>; + status = "disabled"; + }; + + uart2: uart@fc068000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc068000 0x40>; + status = "disabled"; + }; + }; +}; diff --git a/arch/m68k/dts/mcf537x.dtsi b/arch/m68k/dts/mcf537x.dtsi new file mode 100644 index 0000000000..aeaa6430af --- /dev/null +++ b/arch/m68k/dts/mcf537x.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo(a)sysam.it> + */ + +/ { + compatible = "fsl,mcf5329"; + + aliases { + serial0 = &uart0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + uart0: uart@fc060000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc060000 0x40>; + status = "disabled"; + }; + + uart1: uart@fc064000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc064000 0x40>; + status = "disabled"; + }; + + uart2: uart@fc068000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc068000 0x40>; + status = "disabled"; + }; + }; +}; diff --git a/arch/m68k/dts/mcf5441x.dtsi b/arch/m68k/dts/mcf5441x.dtsi new file mode 100644 index 0000000000..71b392adc3 --- /dev/null +++ b/arch/m68k/dts/mcf5441x.dtsi @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo(a)sysam.it> + */ + +/ { + compatible = "fsl,mcf5441x"; + + aliases { + serial0 = &uart0; + spi0 = &dspi0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + uart0: uart@fc060000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc060000 0x40>; + status = "disabled"; + }; + + uart1: uart@fc064000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc064000 0x40>; + status = "disabled"; + }; + + uart2: uart@fc068000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc068000 0x40>; + status = "disabled"; + }; + + uart3: uart@fc06c000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc06c000 0x40>; + status = "disabled"; + }; + + dspi0: dspi@fc05c000 { + compatible = "fsl,mcf-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfc05c000 0x100>; + spi-max-frequency = <50000000>; + num-cs = <4>; + spi-mode = <0>; + status = "disabled"; + }; + + dspi1: dspi@fc03c000 { + compatible = "fsl,mcf-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfc03c000 0x100>; + spi-max-frequency = <50000000>; + num-cs = <4>; + spi-mode = <0>; + status = "disabled"; + }; + + dspi2: dspi@ec038000 { + compatible = "fsl,mcf-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xec038000 0x100>; + spi-max-frequency = <50000000>; + num-cs = <4>; + spi-mode = <0>; + status = "disabled"; + }; + + dspi3: dspi@ec03c000 { + compatible = "fsl,mcf-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xec03c00 0x100>; + spi-max-frequency = <50000000>; + num-cs = <4>; + spi-mode = <0>; + status = "disabled"; + }; + }; +}; diff --git a/arch/m68k/dts/mcf5445x.dtsi b/arch/m68k/dts/mcf5445x.dtsi new file mode 100644 index 0000000000..ccbee29a6c --- /dev/null +++ b/arch/m68k/dts/mcf5445x.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo(a)sysam.it> + */ + +/ { + compatible = "fsl,mcf5445x"; + + aliases { + serial0 = &uart0; + spi0 = &dspi0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + uart0: uart@fc060000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc060000 0x40>; + status = "disabled"; + }; + + uart1: uart@fc064000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc064000 0x40>; + status = "disabled"; + }; + + uart2: uart@fc068000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc068000 0x40>; + status = "disabled"; + }; + + dspi0: dspi@fc05c000 { + compatible = "fsl,mcf-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfc05c000 0x100>; + spi-max-frequency = <50000000>; + num-cs = <4>; + spi-mode = <0>; + status = "disabled"; + }; + }; +}; diff --git a/arch/m68k/dts/mcf54xx.dtsi b/arch/m68k/dts/mcf54xx.dtsi new file mode 100644 index 0000000000..537bb424f3 --- /dev/null +++ b/arch/m68k/dts/mcf54xx.dtsi @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo(a)sysam.it> + */ + +/ { + compatible = "fsl,mcf54x5"; + + aliases { + /* TO DO, clarify on serial, this SoC seems to have SPC and + * no UARTS. + */ + spi0 = &dspi0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + mbar: mbar@80000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x80000000 0x10000>; + reg = <0x80000000 0x10000>; + + dspi0: dspi@8a00 { + compatible = "fsl,mcf-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x8a00 0x100>; + spi-max-frequency = <50000000>; + num-cs = <4>; + spi-mode = <0>; + status = "disabled"; + }; + }; + }; +}; diff --git a/doc/device-tree-bindings/serial/mcf-uart.txt b/doc/device-tree-bindings/serial/mcf-uart.txt new file mode 100644 index 0000000000..d73f764c01 --- /dev/null +++ b/doc/device-tree-bindings/serial/mcf-uart.txt @@ -0,0 +1,19 @@ +Freescale ColdFire UART + +Required properties: +- compatible : should be "fsl,mcf-uart" +- reg: start address and size of the registers + +Example: + +soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + uart0: uart@fc060000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc060000 0x40>; + status = "disabled"; + }; +}; diff --git a/doc/device-tree-bindings/spi/spi-mcf-dspi.txt b/doc/device-tree-bindings/spi/spi-mcf-dspi.txt new file mode 100644 index 0000000000..860eb8ac85 --- /dev/null +++ b/doc/device-tree-bindings/spi/spi-mcf-dspi.txt @@ -0,0 +1,30 @@ +Freescale ColdFire DSPI controller + +Required properties: +- compatible : "fsl,mcf-dspi" +- #address-cells: <1>, as required by generic SPI binding +- #size-cells: <0>, also as required by generic SPI binding +- reg : offset and length of the register set for the device + +Optional properties: +- spi-max-frequency : max supported spi frequency +- num-cs : the number of the chipselect signals +- spi-mode: spi motorola mode, 0 to 3 +- ctar-params: CTAR0 to 7 register configuration, as an array + of 8 integer fields for each register, where each register + is defined as: <fmsz, pcssck, pasc, pdt, cssck, asc, dt, br>. + +Example: + +dspi0: dspi@fc05c000 { + compatible = "fsl,mcf-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfc05c000 0x100>; + spi-max-frequency = <50000000>; + num-cs = <4>; + spi-mode = <0>; + ctar-fields = <7, 0, 0, 0, 0, 0, 1, 6>, + <7, 0, 0, 0, 0, 0, 1, 6>, + <7, 0, 0, 0, 0, 0, 1, 6>; +}; -- 2.19.1

2 14

[U-Boot] rk3399 sdram data training read gate is looping forever
by Jagan Teki 11 Mar '19

11 Mar '19

Hi, I'm trying to bring-up rk3399 SBC with 1GB DDR3 933MHZ capable, and observed an sdram_init issue where data_training_rg transfer is looping forever. The denali_pi[80], and denali_pi[74] seems to be proper values while setting up the particular ranks. Can anyone encounter similar issue? let me know for any inputs. Log: U-Boot SPL board init uclass_find_device_by_seq: 0 -1 uclass_find_device_by_seq: 0 0 - -1 -1 'root_driver' - not found syscon: rockchip_rk3399_pmugrf 4 syscon: rockchip_rk3399_pmusgrf 5 syscon: rockchip_rk3399_cic 6 syscon: rockchip_rk3399_grf 1 uclass_find_device_by_seq: 0 -1 uclass_find_device_by_seq: 0 0 - -1 -1 'rockchip_rk3399_pmugrf' - -1 -1 'rockchip_rk3399_pmusgrf' - -1 -1 'rockchip_rk3399_cic' - -1 -1 'rockchip_rk3399_grf' - not found uclass_find_device_by_seq: 0 -1 uclass_find_device_by_seq: 0 0 - -1 -1 'rockchip_rk3399_pmugrf' - -1 0 'rockchip_rk3399_pmusgrf' - found uclass_find_device_by_seq: 0 1 - -1 -1 'rockchip_rk3399_pmugrf' - -1 0 'rockchip_rk3399_pmusgrf' - -1 -1 'rockchip_rk3399_cic' - -1 -1 'rockchip_rk3399_grf' - not found uclass_find_device_by_seq: 0 -1 uclass_find_device_by_seq: 0 0 - -1 -1 'rockchip_rk3399_pinctrl' - not found uclass_find_device_by_seq: 0 -1 uclass_find_device_by_seq: 0 0 - -1 -1 'rockchip_rk3399_pmugrf' - -1 0 'rockchip_rk3399_pmusgrf' - found uclass_find_device_by_seq: 0 1 - -1 -1 'rockchip_rk3399_pmugrf' - -1 0 'rockchip_rk3399_pmusgrf' - -1 -1 'rockchip_rk3399_cic' - -1 1 'rockchip_rk3399_grf' - found uclass_find_device_by_seq: 0 2 - -1 -1 'rockchip_rk3399_pmugrf' - -1 0 'rockchip_rk3399_pmusgrf' - -1 -1 'rockchip_rk3399_cic' - -1 1 'rockchip_rk3399_grf' - not found rk3399_pinctrl_probe: grf=ff770000, pmugrf=ff320000 uclass_find_device_by_seq: 0 -1 uclass_find_device_by_seq: 0 0 - -1 -1 'rockchip_rk3399_dmc' - not found uclass_find_device_by_seq: 0 -1 uclass_find_device_by_seq: 0 0 - -1 2 'rockchip_rk3399_pmugrf' - -1 0 'rockchip_rk3399_pmusgrf' - found uclass_find_device_by_seq: 0 1 - -1 2 'rockchip_rk3399_pmugrf' - -1 0 'rockchip_rk3399_pmusgrf' - -1 -1 'rockchip_rk3399_cic' - -1 1 'rockchip_rk3399_grf' - found uclass_find_device_by_seq: 0 2 - -1 2 'rockchip_rk3399_pmugrf' - found uclass_find_device_by_seq: 0 3 - -1 2 'rockchip_rk3399_pmugrf' - -1 0 'rockchip_rk3399_pmusgrf' - -1 -1 'rockchip_rk3399_cic' - -1 1 'rockchip_rk3399_grf' - not found uclass_find_device_by_seq: 0 -1 uclass_find_device_by_seq: 0 0 - -1 -1 'rockchip_rk3399_cru' - -1 -1 'rockchip_rk3399_pmucru' - not found uclass_find_device_by_seq: 0 -1 uclass_find_device_by_seq: 0 0 - -1 -1 'rockchip_rk3399_cru' - -1 0 'rockchip_rk3399_pmucru' - found uclass_find_device_by_seq: 0 1 - -1 -1 'rockchip_rk3399_cru' - -1 0 'rockchip_rk3399_pmucru' - not found PLL at ff760000: fbdiv=50, refdiv=1, postdiv1=2, postdiv2=1, vco=1200000 khz, output=600000 khz PLL at ff760020: fbdiv=50, refdiv=1, postdiv1=2, postdiv2=1, vco=1200000 khz, output=600000 khz PLL at ff760080: fbdiv=99, refdiv=2, postdiv1=2, postdiv2=1, vco=1188000 khz, output=594000 khz PLL at ff760060: fbdiv=64, refdiv=1, postdiv1=2, postdiv2=2, vco=1536000 khz, output=384000 khz con reg ffa80000 ffa80800 ffa82000 ffa84000 ffa88000 ffa88800 ffa8a000 ffa8c000 cru ff760000, cic ff620000, grf ff320000, sgrf ff330000, pmucru ff750000 clk_set_rate(clk=ff8ee498, rate=933000000) PLL at ff760040: fbdiv=116, refdiv=1, postdiv1=3, postdiv2=1, vco=2784000 khz, output=928000 khz Starting SDRAM initialization... freq 933, channnels 2 DRAM (pctl_cfg): phy locked after 1 ms pctl_cfg done! call data_training call data_training_wl data_training_wl while(1) data_training_wl while(1) call data_training_rg data_training_rg while(1) data_training_rg while(1) data_training_rg while(1) data_training_rg while(1) data_training_rg while(1) data_training_rg while(1) data_training_rg while(1) data_training_rg while(1)

2 2

[U-Boot] [PATCH v2 00/23] spl: Add features for passing info from SPL to U-Boot proper
by Simon Glass 10 Mar '19

10 Mar '19

At present we have no standard way of passing information from SPL to U-Boot. Such information may be the size of DRAM banks or some information about the reset state of the machine,for example. This series first adds a bloblist, which allows a list of 'blobs' to be created, each with a tag so that subsystems can store data and retrieve it later. Then it adds the SPL 'handoff' information, which uses bloblist. Various minor sandbox enhancements are provided to make this easier, or to support testing. Changes in v2: - Fix several typos - Add back a blank line, and put one in the new function too - Drop the wildcard in the .lds file as it is not needed Simon Glass (23): log: Correct definition of log_msg_ret() spl: Add support for logging in SPL and TPL Add core support for a bloblist to convey data from SPL spl: Set up the bloblist in SPL bloblist: Locate bloblist in U-Boot test: Add a simple test for bloblist Add bloblist documentation spl: Support hash, input, pch, pci, rtc, tpm in SPL spl: Add a define for SPL_TPL_PROMPT spl: Make SPL_DISABLE_BANNER_PRINT a positive option spl: Add a comment to spl_set_bd() spl: Print a message if we are unable to load an image sandbox: Add a memory map to the sandbox README test/py: Add a way to pass flags to sandbox sandbox: Add an option to display of-platdata in SPL sandbox: Drop the deprecated 'sb' command sandbox: Add a new 'sb' command sandbox: Allow puts() output before global_data is set up sandbox: Refactor code to create os_jump_to_file() sandbox: Use malloc() and free() from os layer sandbox: Filter arguments when starting U-Boot sandbox: Boot in U-Boot through the standard call spl: Add support for passing handoff info to U-Boot proper arch/Kconfig | 1 + arch/powerpc/include/asm/spl.h | 3 - arch/sandbox/cpu/eth-raw-os.c | 9 +- arch/sandbox/cpu/os.c | 115 +++++++++----- arch/sandbox/cpu/spl.c | 31 +++- arch/sandbox/cpu/start.c | 19 +++ arch/sandbox/cpu/u-boot-spl.lds | 2 +- arch/sandbox/include/asm/handoff.h | 18 +++ arch/sandbox/include/asm/state.h | 8 + board/sandbox/README.sandbox | 14 +- cmd/Makefile | 1 + cmd/host.c | 5 - cmd/sb.c | 65 ++++++++ common/Kconfig | 84 +++++++++- common/Makefile | 5 +- common/bloblist.c | 239 +++++++++++++++++++++++++++++ common/board_f.c | 49 ++++++ common/console.c | 7 + common/init/Makefile | 1 + common/init/handoff.c | 47 ++++++ common/spl/Kconfig | 95 +++++++++++- common/spl/spl.c | 142 +++++++++++++---- configs/sandbox_spl_defconfig | 1 + doc/README.bloblist | 82 ++++++++++ doc/README.trace | 2 +- drivers/Makefile | 11 +- include/asm-generic/global_data.h | 7 + include/bloblist.h | 195 +++++++++++++++++++++++ include/handoff.h | 36 +++++ include/log.h | 10 +- include/spl.h | 41 +++++ include/test/suites.h | 1 + test/Makefile | 1 + test/bloblist.c | 187 ++++++++++++++++++++++ test/cmd_ut.c | 3 + test/dm/sf.c | 2 +- test/py/tests/test_fit.py | 12 +- test/py/tests/test_handoff.py | 14 ++ test/py/tests/test_ofplatdata.py | 31 +++- test/py/tests/test_vboot.py | 2 +- test/py/u_boot_console_base.py | 2 +- test/py/u_boot_console_sandbox.py | 18 +++ test/run | 2 +- 43 files changed, 1510 insertions(+), 110 deletions(-) create mode 100644 arch/sandbox/include/asm/handoff.h create mode 100644 cmd/sb.c create mode 100644 common/bloblist.c create mode 100644 common/init/handoff.c create mode 100644 doc/README.bloblist create mode 100644 include/bloblist.h create mode 100644 include/handoff.h create mode 100644 test/bloblist.c create mode 100644 test/py/tests/test_handoff.py -- 2.19.0.605.g01d371f741-goog

5 47

[U-Boot] [RFC 0/9] Convert Pico-Pi i.MX7D to DM
by Joris Offouga 10 Mar '19

10 Mar '19

Hi all, Pinctrl, GPIO, I2C, MMC, ETH are converted. Convert PMIC is the same of warp7 but i have a some erros, si this log : U-Boot SPL 2019.01-00197-ga524e5d-dirty (Jan 20 2019 - 21:09:49 +0100) Trying to boot from USB SDP SDP: initialize... SDP: handle requests... Downloading file of size 556397 to 0x877fffc0... done Jumping to header at 0x877fffc0 Header Tag is not an IMX image U-Boot 2019.01-00197-ga524e5d-dirty (Jan 20 2019 - 21:09:49 +0100) CPU: Freescale i.MX7D rev1.2 1000 MHz (running at 792 MHz) CPU: Commercial temperature grade (0C to 95C) at 43C Reset cause: POR Model: TechNexion PICO-IMX7D Board and PI baseboard Board: i.MX7D PICOSOM DRAM: 512 MiB read error from device: 9df65458 register: 0x3! PMIC: PFUZE3000 DEV_ID=0x0 REV_ID=0xfffffffb read error from device: 9df65458 register: 0x69! write error to device: 9df65458 register: 0x23! write error to device: 9df65458 register: 0x31! write error to device: 9df65458 register: 0x21! write error to device: 9df65458 register: 0x2f! read error from device: 9df65458 register: 0x2e! write error to device: 9df65458 register: 0x2e! MMC: FSL_SDHC: 2, FSL_SDHC: 1, FSL_SDHC: 0 Loading Environment from MMC... OK In: serial@30a70000 Out: serial@30a70000 Err: serial@30a70000 Net: Warning: ethernet@30be0000 using MAC address from ROM eth0: ethernet@30be0000 Hit any key to stop autoboot: 0 USB is convert but update u-boot with dfu log a error : => dfu 0 mmc 0 Request would exceed designated area! #Deferred dfu_flush() failed!=> Thanks a advance for your help. Best Regards, Joris Offouga Joris Offouga (9): Arm: dts: imx7d-pico: Import Linux pico-pi dts Arm: imx7d-pico: Add DT file hooks pico-pi-imx7d: defconfig Enable DM gpio pinctrl and pinctrl_imx7 arm: imx7d-pico-pi: Convert to DM MMC initialization pico-pi-imx7d: defconfig: Switch to DM for I2C pico-imx7d-pico: defconfig: Switch to DM for UART pico-imx7d: Convert to DM PMIC arm: pico-pi-imx7d: Convert to DM USB pico-imx7d: Convert to DM Ethernet arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx7d-pico-pi.dts | 102 ++++++ arch/arm/dts/imx7d-pico.dtsi | 588 +++++++++++++++++++++++++++++++ board/technexion/pico-imx7d/pico-imx7d.c | 105 +----- configs/pico-pi-imx7d_defconfig | 17 +- include/configs/pico-imx7d.h | 11 - 6 files changed, 726 insertions(+), 100 deletions(-) create mode 100644 arch/arm/dts/imx7d-pico-pi.dts create mode 100644 arch/arm/dts/imx7d-pico.dtsi -- 2.7.4

4 26

[U-Boot] [RESEND PATCH 2/2] ARM: qemu-arm: enable USB boot in distro boot with UEFI
by AKASHI Takahiro 09 Mar '19

09 Mar '19

With this patch which adds a removable USB mass storage to a list of bootable devices, USB boot is supported in distro boot if UEFI is configured. Signed-off-by: AKASHI Takahiro <takahiro.akashi(a)linaro.org> --- include/configs/qemu-arm.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/qemu-arm.h b/include/configs/qemu-arm.h index fedc4662fa18..392839f7ad59 100644 --- a/include/configs/qemu-arm.h +++ b/include/configs/qemu-arm.h @@ -24,6 +24,7 @@ #define CONFIG_ENV_SIZE SZ_64K #define BOOT_TARGET_DEVICES(func) \ + func(USB, usb, 0) \ func(SCSI, scsi, 0) \ func(DHCP, dhcp, na) -- 2.19.1

4 3

[U-Boot] [PATCH 1/2] phy: rcar: Add R-Car Gen3 PHY driver
by Marek Vasut 08 Mar '19

08 Mar '19

Add a PHY driver for the R-Car Gen3 which allows configuring USB OTG PHY on Gen3 into host mode and toggles VBUS in case a dedicated regulator is present. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- drivers/phy/Kconfig | 8 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-rcar-gen3.c | 161 ++++++++++++++++++++++++++++++++++++ 3 files changed, 170 insertions(+) create mode 100644 drivers/phy/phy-rcar-gen3.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index bcc8e22795..14d82b93ed 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -118,6 +118,14 @@ config PHY_RCAR_GEN2 PHY connected to USBHS module, PCI EHCI module and USB3.0 module and allows configuring the module multiplexing. +config PHY_RCAR_GEN3 + tristate "Renesas R-Car Gen3 USB PHY" + depends on PHY && RCAR_GEN3 && CLK && DM_REGULATOR + default y if RCAR_GEN3 + help + Support for the Renesas R-Car Gen3 USB PHY. This driver operates the + PHY connected to EHCI USB module and controls USB OTG operation. + config PHY_STM32_USBPHYC tristate "STMicroelectronics STM32 SoC USB HS PHY driver" depends on PHY && ARCH_STM32MP diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 1e1e4ca11e..8030d599e7 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_PHY_SANDBOX) += sandbox-phy.o obj-$(CONFIG_$(SPL_)PIPE3_PHY) += ti-pipe3-phy.o obj-$(CONFIG_STI_USB_PHY) += sti_usb_phy.o obj-$(CONFIG_PHY_RCAR_GEN2) += phy-rcar-gen2.o +obj-$(CONFIG_PHY_RCAR_GEN3) += phy-rcar-gen3.o obj-$(CONFIG_PHY_STM32_USBPHYC) += phy-stm32-usbphyc.o obj-$(CONFIG_MESON_GXL_USB_PHY) += meson-gxl-usb2.o meson-gxl-usb3.o obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o diff --git a/drivers/phy/phy-rcar-gen3.c b/drivers/phy/phy-rcar-gen3.c new file mode 100644 index 0000000000..b662935626 --- /dev/null +++ b/drivers/phy/phy-rcar-gen3.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas RCar Gen3 USB PHY driver + * + * Copyright (C) 2018 Marek Vasut <marek.vasut(a)gmail.com> + */ + +#include <common.h> +#include <clk.h> +#include <div64.h> +#include <dm.h> +#include <fdtdec.h> +#include <generic-phy.h> +#include <reset.h> +#include <syscon.h> +#include <usb.h> +#include <asm/io.h> +#include <linux/bitops.h> +#include <power/regulator.h> + +/* USB2.0 Host registers (original offset is +0x200) */ +#define USB2_INT_ENABLE 0x000 +#define USB2_USBCTR 0x00c +#define USB2_SPD_RSM_TIMSET 0x10c +#define USB2_OC_TIMSET 0x110 +#define USB2_COMMCTRL 0x600 +#define USB2_OBINTSTA 0x604 +#define USB2_OBINTEN 0x608 +#define USB2_VBCTRL 0x60c +#define USB2_LINECTRL1 0x610 +#define USB2_ADPCTRL 0x630 + +/* USBCTR */ +#define USB2_USBCTR_PLL_RST BIT(1) + +/* SPD_RSM_TIMSET */ +#define USB2_SPD_RSM_TIMSET_INIT 0x014e029b + +/* OC_TIMSET */ +#define USB2_OC_TIMSET_INIT 0x000209ab + +/* COMMCTRL */ +#define USB2_COMMCTRL_OTG_PERI BIT(31) /* 1 = Peripheral mode */ + +/* LINECTRL1 */ +#define USB2_LINECTRL1_DP_RPD BIT(18) +#define USB2_LINECTRL1_DM_RPD BIT(16) + +/* ADPCTRL */ +#define USB2_ADPCTRL_DRVVBUS BIT(4) + +struct rcar_gen3_phy { + fdt_addr_t regs; + struct clk clk; + struct udevice *vbus_supply; +}; + +static int rcar_gen3_phy_phy_init(struct phy *phy) +{ + struct rcar_gen3_phy *priv = dev_get_priv(phy->dev); + + /* Initialize USB2 part */ + writel(0, priv->regs + USB2_INT_ENABLE); + writel(USB2_SPD_RSM_TIMSET_INIT, priv->regs + USB2_SPD_RSM_TIMSET); + writel(USB2_OC_TIMSET_INIT, priv->regs + USB2_OC_TIMSET); + + setbits_le32(priv->regs + USB2_LINECTRL1, + USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD); + + clrbits_le32(priv->regs + USB2_COMMCTRL, USB2_COMMCTRL_OTG_PERI); + + setbits_le32(priv->regs + USB2_ADPCTRL, USB2_ADPCTRL_DRVVBUS); + + return 0; +} + +static int rcar_gen3_phy_phy_power_on(struct phy *phy) +{ + struct rcar_gen3_phy *priv = dev_get_priv(phy->dev); + int ret; + + if (priv->vbus_supply) { + ret = regulator_set_enable(priv->vbus_supply, true); + if (ret) + return ret; + } + + setbits_le32(priv->regs + USB2_USBCTR, USB2_USBCTR_PLL_RST); + clrbits_le32(priv->regs + USB2_USBCTR, USB2_USBCTR_PLL_RST); + + return 0; +} + +static int rcar_gen3_phy_phy_power_off(struct phy *phy) +{ + struct rcar_gen3_phy *priv = dev_get_priv(phy->dev); + + if (!priv->vbus_supply) + return 0; + + return regulator_set_enable(priv->vbus_supply, false); +} + +static const struct phy_ops rcar_gen3_phy_phy_ops = { + .init = rcar_gen3_phy_phy_init, + .power_on = rcar_gen3_phy_phy_power_on, + .power_off = rcar_gen3_phy_phy_power_off, +}; + +static int rcar_gen3_phy_probe(struct udevice *dev) +{ + struct rcar_gen3_phy *priv = dev_get_priv(dev); + int ret; + + priv->regs = dev_read_addr(dev); + if (priv->regs == FDT_ADDR_T_NONE) + return -EINVAL; + + ret = device_get_supply_regulator(dev, "vbus-supply", + &priv->vbus_supply); + if (ret && ret != -ENOENT) { + pr_err("Failed to get PHY regulator\n"); + return ret; + } + + /* Enable clock */ + ret = clk_get_by_index(dev, 0, &priv->clk); + if (ret) + return ret; + + ret = clk_enable(&priv->clk); + if (ret) + return ret; + + return 0; +} + +static int rcar_gen3_phy_remove(struct udevice *dev) +{ + struct rcar_gen3_phy *priv = dev_get_priv(dev); + + clk_disable(&priv->clk); + clk_free(&priv->clk); + + return 0; +} + +static const struct udevice_id rcar_gen3_phy_of_match[] = { + { .compatible = "renesas,rcar-gen3-usb2-phy", }, + { }, +}; + +U_BOOT_DRIVER(rcar_gen3_phy) = { + .name = "rcar-gen3-phy", + .id = UCLASS_PHY, + .of_match = rcar_gen3_phy_of_match, + .ops = &rcar_gen3_phy_phy_ops, + .probe = rcar_gen3_phy_probe, + .remove = rcar_gen3_phy_remove, + .priv_auto_alloc_size = sizeof(struct rcar_gen3_phy), +}; -- 2.18.0

3 5

[U-Boot] [PATCH v10 00/10] Fix CVE-2018-18440 and CVE-2018-18439
by Simon Goldschmidt 06 Mar '19

06 Mar '19

This series fixes CVE-2018-18440 ("insufficient boundary checks in filesystem image load") by adding restrictions to the 'load' command and fixes CVE-2018-18439 ("insufficient boundary checks in network image boot") by adding restrictions to the tftp code. The functions from lmb.c are used to setup regions of allowed and reserved memory. Then, the file size to load is checked against these addresses and loading the file is aborted if it would overwrite reserved memory. The memory reservation code is reused from bootm/image. Changes in v10: - added acked-by and reviewed-by tags Changes in v9: - fixed compile error in patch 10/10 (in arch/arm/lib/bootm.c) Changes in v8: - fix address overflow in 'arch_lmb_reserve' for ARM Changes in v7: - add braces around if/else with macros accross more than one line - fix compiling without CONFIG_FIT - fix compiling without CONFIG_LMB Changes in v6: - fix size of allocated regions that need alignment padding - fix compiling without OF_CONTROL - fixed NULL pointer access in 'fdt_blob' passed to 'boot_fdt_add_mem_rsv_regions' Changes in v5: - added tests for lib/lmb.c - fixed bug in lmb.c when ram is at the end of 32-bit address range - fixed a bug in lmb_alloc_addr when resulting reserved ranges get combined Changes in v4: - fixed invalid 'if' statement without braces in boot_fdt_reserve_region - removed patch 7 ("net: remove CONFIG_MCAST_TFTP), adapted patch 8 Changes in v3: - No patch changes, but needed to resend since patman added too many cc addresses that gmail seemed to detect as spam :-( Changes in v2: - added code to reserve devicetree reserved-memory in lmb - added tftp fixes (patches 7 and 8) - fixed a bug in new function lmb_alloc_addr Simon Goldschmidt (10): test: add test for lib/lmb.c lmb: fix allocation at end of address range lib: lmb: reserving overlapping regions should fail fdt: parse "reserved-memory" for memory reservation lib: lmb: extend lmb for checks at load time fs: prevent overwriting reserved memory bootm: use new common function lmb_init_and_reserve lmb: remove unused extern declaration tftp: prevent overwriting reserved memory arm: bootm: fix sp detection at end of address range arch/arm/lib/bootm.c | 10 +- common/bootm.c | 8 +- common/image-fdt.c | 53 +++- fs/fs.c | 56 +++- include/lmb.h | 7 +- lib/Makefile | 1 + lib/lmb.c | 106 ++++++-- net/tftp.c | 73 +++++- test/lib/Makefile | 1 + test/lib/lmb.c | 601 +++++++++++++++++++++++++++++++++++++++++++ 10 files changed, 859 insertions(+), 57 deletions(-) create mode 100644 test/lib/lmb.c -- 2.17.1

6 38

[U-Boot] [PATCH] ARM: rmobile: Convert to bootm_size
by Marek Vasut 05 Mar '19

05 Mar '19

Convert all Renesas R-Car boards to bootm_size of 256 MiB and drop both fdt_high and initrd_high. This change implies that the FDT and initrd will always be copied into the first 256 MiB of RAM instead of being used in place, which can cause various kinds of inobvious problems. The simpler problems include FDT or initrd being overwritten or being used from unaligned addresses, especially on ARM64. The overhead of copying the FDT to aligned location is negligible and these problems go away, so the benefit is significant. Regarding alignment problems with fitImage. The alignment of DT properties is always 32 bits, which implies that the alignment of the "data" property in fitImage is also 32 bits. The /incbin/ syntax plays no role here. The kernel expects all elements, including DT and initrd, to be aligned to 64 bits on ARM64, thus using them in place may not be possible. Using the bootm_size assures correct alignment, again with negligible overhead. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> Cc: Tom Rini <trini(a)konsulko.com> --- include/configs/alt.h | 3 +-- include/configs/gose.h | 3 +-- include/configs/koelsch.h | 3 +-- include/configs/lager.h | 3 +-- include/configs/porter.h | 3 +-- include/configs/rcar-gen3-common.h | 3 +-- include/configs/silk.h | 3 +-- include/configs/stout.h | 3 +-- 8 files changed, 8 insertions(+), 16 deletions(-) diff --git a/include/configs/alt.h b/include/configs/alt.h index cc6a7bf638..3f7f379e06 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -39,8 +39,7 @@ #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK #define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" + "bootm_size=0x10000000\0" /* SPL support */ #define CONFIG_SPL_TEXT_BASE 0xe6300000 diff --git a/include/configs/gose.h b/include/configs/gose.h index 36ac88a20d..8f0e378488 100644 --- a/include/configs/gose.h +++ b/include/configs/gose.h @@ -35,8 +35,7 @@ #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK #define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" + "bootm_size=0x10000000\0" /* SPL support */ #define CONFIG_SPL_TEXT_BASE 0xe6300000 diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index ef26a144a9..33c8bd4149 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -35,8 +35,7 @@ #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK #define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" + "bootm_size=0x10000000\0" /* SPL support */ #define CONFIG_SPL_TEXT_BASE 0xe6300000 diff --git a/include/configs/lager.h b/include/configs/lager.h index 08498c6d81..89c5d01d3c 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -36,8 +36,7 @@ #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK #define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" + "bootm_size=0x10000000\0" /* SPL support */ #define CONFIG_SPL_TEXT_BASE 0xe6300000 diff --git a/include/configs/porter.h b/include/configs/porter.h index e56dc3f1ec..9950f80afd 100644 --- a/include/configs/porter.h +++ b/include/configs/porter.h @@ -40,8 +40,7 @@ #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK #define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" + "bootm_size=0x10000000\0" /* SPL support */ #define CONFIG_SPL_TEXT_BASE 0xe6300000 diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index 435d108628..6c2fa6a63c 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -59,8 +59,7 @@ #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) #define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" + "bootm_size=0x10000000\0" #define CONFIG_BOOTCOMMAND \ "tftp 0x48080000 Image; " \ diff --git a/include/configs/silk.h b/include/configs/silk.h index a94928bd16..112806c342 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -40,8 +40,7 @@ #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK #define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" + "bootm_size=0x10000000\0" /* SPL support */ #define CONFIG_SPL_TEXT_BASE 0xe6300000 diff --git a/include/configs/stout.h b/include/configs/stout.h index b72b565c33..93d980569c 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -44,8 +44,7 @@ #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK #define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" + "bootm_size=0x10000000\0" /* SPL support */ #define CONFIG_SPL_TEXT_BASE 0xe6300000 -- 2.18.0

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[U-Boot] [PATCH v3 0/6] net: phy: Allow disabling SmartEEE for Atheros PHYs
by Vladimir Oltean 05 Mar '19

05 Mar '19

The patchset adds support for disabling a PHY feature that may cause packet loss, and also cleans up the atheros.c driver a bit. As part of the cleanup, there are also some functional changes for the AR8035 in the RGMII internal delay area. Due to a mistake, RGMII Tx internal delay used to be implicitly always enabled. This is now corrected. Users of this driver may need to update their bindings to explicitly request the Tx internal delays back. Changes in v3: * Replaced all magic numbers with macros * Squashed "net: phy: ar803x: Use phy_read_mmd and phy_write_mmd functions" into new "net: phy: ar803x: Clarify the configuration of the CLK_25M output pin" patch * Fixed unconditional enabling of RGMII TxID for AR8035 Vladimir Oltean (6): net: phy: ar803x: Address packet drops at low traffic rate due to SmartEEE feature net: phy: ar803x: Make RGMII Tx delays actually configurable for AR8035 net: phy: ar803x: Use common functions for RGMII internal delays net: phy: ar803x: Explicitly disable RGMII delays net: phy: ar803x: Clarify the configuration of the CLK_25M output pin net: phy: ar803x: Clarify the intention of ar8021_config drivers/net/phy/Kconfig | 21 ++++++++ drivers/net/phy/atheros.c | 128 ++++++++++++++++++++++++++++++++-------------- 2 files changed, 111 insertions(+), 38 deletions(-) -- 2.7.4

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[U-Boot] [PATCH v2] net: phy: realtek: Introduce quirk to mark RXC not stoppable
by Carlo Caione 05 Mar '19

05 Mar '19

When EEE is supported by the PHY and the driver allows it, libphy in the kernel is configuring the PHY to stop receiving the xMII clock while it is signaling LPI. While this (usually) works fine in the kernel this is causing issues in U-Boot when rebooting from the linux kernel with this bit set (without having the possibility to reset the PHY) where the PHY suddenly stops working. A new quirk is introduced to unconditionally reset this bit. If the quirk is not enabled using the proper configuration symbol, the PHY state is not changed. Signed-off-by: Carlo Caione <ccaione(a)baylibre.com> Acked-by: Joe Hershberger <joe.hershberger(a)ni.com> --- drivers/net/phy/Kconfig | 20 ++++++++++++++++++++ drivers/net/phy/realtek.c | 19 +++++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 3dc0822d9c..631b52b1cf 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -202,6 +202,26 @@ config RTL8211X_PHY_FORCE_MASTER If unsure, say N. +config RTL8211F_PHY_FORCE_EEE_RXC_ON + bool "Ethernet PHY RTL8211F: do not stop receiving the xMII clock during LPI" + depends on PHY_REALTEK + default n + help + The IEEE 802.3az-2010 (EEE) standard provides a protocol to coordinate + transitions to/from a lower power consumption level (Low Power Idle + mode) based on link utilization. When no packets are being + transmitted, the system goes to Low Power Idle mode to save power. + + Under particular circumstances this setting can cause issues where + the PHY is unable to transmit or receive any packet when in LPI mode. + The problem is caused when the PHY is configured to stop receiving + the xMII clock while it is signaling LPI. For some PHYs the bit + configuring this behavior is set by the Linux kernel, causing the + issue in U-Boot on reboot if the PHY retains the register value. + + Default n, which means that the PHY state is not changed. To work + around the issues, change this setting to y. + config PHY_SMSC bool "Microchip(SMSC) Ethernet PHYs support" diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index b3e6578df9..fa11696fe2 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -12,6 +12,7 @@ #define PHY_RTL8211x_FORCE_MASTER BIT(1) #define PHY_RTL8211E_PINE64_GIGABIT_FIX BIT(2) +#define PHY_RTL8211F_FORCE_EEE_RXC_ON BIT(3) #define PHY_AUTONEGOTIATE_TIMEOUT 5000 @@ -75,6 +76,15 @@ static int rtl8211e_probe(struct phy_device *phydev) return 0; } +static int rtl8211f_probe(struct phy_device *phydev) +{ +#ifdef CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON + phydev->flags |= PHY_RTL8211F_FORCE_EEE_RXC_ON; +#endif + + return 0; +} + /* RealTek RTL8211x */ static int rtl8211x_config(struct phy_device *phydev) { @@ -124,6 +134,14 @@ static int rtl8211f_config(struct phy_device *phydev) { u16 reg; + if (phydev->flags & PHY_RTL8211F_FORCE_EEE_RXC_ON) { + unsigned int reg; + + reg = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1); + reg &= ~MDIO_PCS_CTRL1_CLKSTOP_EN; + phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, reg); + } + phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); phy_write(phydev, MDIO_DEVAD_NONE, @@ -333,6 +351,7 @@ static struct phy_driver RTL8211F_driver = { .uid = 0x1cc916, .mask = 0xffffff, .features = PHY_GBIT_FEATURES, + .probe = &rtl8211f_probe, .config = &rtl8211f_config, .startup = &rtl8211f_startup, .shutdown = &genphy_shutdown, -- 2.19.1

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